Method and apparatus for efficient reading of super merged arrays from higher resolution sensors

Abstract

This application relates to methods and apparatus for efficient readout of super binning arrays from higher resolution sensors. A pixel includes a photosensor configured to photo generate charge in response to incident light. A floating diffusion region is configured to receive charge photo generated by the photosensor. A transfer transistor is coupled between the floating diffusion region and the photosensor. A double floating diffusion (DFD) transistor is coupled to the floating diffusion region. A bin node is coupled to the DFD transistor. A floating diffusion region interconnect mesh is coupled to bin nodes of the pixel and a second pixel. The pixel and the second pixel are included in a pixel array. The DFD transistor is configured to, when activated, couple the bin node to the floating diffusion region to provide a binned readout during a readout operation of the pixel array, and the DFD transistor is configured to, when deactivated, not couple the bin node to the floating diffusion region to provide a full resolution readout.

Description

[0001] Cross-reference of related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 490,478, filed March 15, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure generally relates to image sensors, and specifically (but not exclusively) to complementary metal-oxide-semiconductor (CMOS) image sensors with pixel binning. Background Technology

[0004] Image sensors have become ubiquitous and are now widely used in digital cameras, cellular phones, security cameras, and medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, there is a desire to enhance their functionality, performance metrics, and the like in as many ways as possible, such as resolution, power consumption, dynamic range, etc., through device architecture design and image acquisition and processing.

[0005] A typical image sensor operates in response to incident image light from an external scene. The image sensor comprises an array of pixels having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate image charge upon absorption. The image charge generated by the pixel light can be measured as an analog output image signal on the bit lines, which varies with the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, which is read out as an analog image signal from the bit lines and converted into a digital value to provide information representing the external scene. Summary of the Invention

[0006] One aspect of this disclosure relates to a pixel comprising: a photodetector configured to generate a charge in response to incident light; a floating diffuser configured to receive the charge generated by the photodetector; a transfer transistor coupled between the floating diffuser and the photodetector; a dual floating diffuser (DFD) transistor coupled to the floating diffuser; a merging node coupled to the DFD transistor; and a floating diffuser interconnect grid coupled to the merging node of the pixel and a merging node of a second pixel, wherein the pixel and the second pixel are included in a plurality of pixels in a pixel array, wherein the DFD transistor is configured to couple the merging node to the floating diffuser when activated during a readout operation of the pixel array to provide a merged readout of the pixel and the second pixel, wherein the DFD transistor is configured not to couple the merging node to the floating diffuser when deactivated during the readout operation of the pixel array to provide a full-resolution readout of the pixel and the second pixel.

[0007] Another aspect of this disclosure relates to an imaging system comprising: a pixel array including a plurality of pixels arranged in rows and columns and a floating diffusion region interconnection grid coupled to the plurality of pixels, wherein each of the pixels includes: a photodetector configured to generate a photocharge in response to incident light; a floating diffusion region configured to receive the photocharge generated by the photodetector; a transfer transistor coupled between the floating diffusion region and the photodetector; a dual floating diffusion (DFD) transistor coupled to the floating diffusion region; and a merging node coupled to the DFD transistor; and a control circuitry system coupled to the pixel array to control the operation of the pixel array. and readout circuitry coupled to receive merged readout or full-resolution readout from the pixel array, wherein the floating diffusion region interconnect grid is coupled to the merged node of each of the pixels, wherein the DFD transistor of each of the pixels is configured to couple the merged node to the floating diffusion region when activated during a readout operation of the pixel array to provide the merged readout of the pixel array, and wherein the DFD transistor of each of the pixels is configured not to couple the merged node to the floating diffusion region when deactivated during the readout operation of the pixel array to provide the full-resolution readout of the pixel array. Attached Figure Description

[0008] The following description, with reference to the following figures, illustrates non-limiting and non-exhaustive embodiments of the present technology, wherein, unless otherwise specified, similar or analogous reference numerals throughout the text are used to refer to similar or analogous components. Additional details of the present technology are described in Appendix A.

[0009] Figure 1 This describes an example of an imaging system comprising a pixel array according to the teachings of this technology.

[0010] Figure 2 This illustrates an example of a schematic diagram of one of a plurality of pixel circuits contained in a pixel array, according to the teachings of this technique.

[0011] Figures 3A and 3B illustrate an example merging scheme for a pixel array according to the teachings of this technique, wherein 10x10 blocks of pixels are merged at the floating diffusion region by a corresponding floating diffusion region interconnecting grid within the 10x10 blocks of pixels.

[0012] Figure 4 The illustration shows an example timing diagram of improved readout time with reduced power consumption of a pixel array comprising 10x10 blocks of pixels according to the teachings of this technique, wherein the 10x10 blocks of pixels are merged at floating diffusion regions within the pixels contained in the 10x10 blocks of pixels.

[0013] Those skilled in the art will understand that the elements in the figures and Appendix A are illustrated for simplicity and clarity, and are not necessarily drawn to scale. For example, the dimensions of some elements in the figures and Appendix A may be exaggerated relative to other elements to aid in understanding various aspects of the art. Furthermore, common but easily understood elements or methods that are useful or necessary in commercially feasible embodiments are generally not depicted in the figures and Appendix A or described in detail below, in order to avoid unnecessarily obscuring the description of various aspects of the art. Detailed Implementation

[0014] This disclosure generally relates to image sensors. For example, several embodiments of the technology relate to CMOS image sensors contained in pixel arrays (e.g., a 640x640 pixel array, where ultra-low power 64x64 readouts of 10x10 blocks of pixels are implemented using pixel-level floating diffusion region super-merging). In the following description, specific details are set forth to provide a thorough understanding of aspects of the technology. However, those skilled in the art will recognize that the systems, apparatuses, and techniques described herein can be practiced without one or more of the specific details set forth herein or with other methods, components, materials, etc.

[0015] Throughout this specification, references to “example” or “implementation” mean that a particular feature, structure, or characteristic described in connection with an example or embodiment is included in at least one example or embodiment of the present technology. Therefore, the use of the phrases “for example,” “as an example,” or “implementation” herein does not necessarily refer to the same example or embodiment and is not necessarily limited to the specific example or embodiment discussed. Furthermore, the features, structures, or characteristics of the present technology described herein may be combined in any suitable manner to provide further examples or embodiments of the present technology.

[0016] For ease of description, spatial relative terms (e.g., “below,” “under,” “above,” “below,” “above,” “top,” “bottom,” “left,” “right,” “center,” “middle,” and the like) are used herein to describe the relationship of an element or feature relative to one or more other elements or features, as illustrated in the figures. It should be understood that, in addition to the orientations depicted in the figures, spatial relative terms are intended to cover different orientations of the device or system during use or operation. For example, if the device or system illustrated in the figures rotates, turns, or flips about a horizontal axis, then an element or feature described as “below,” “under,” or “below” one or more other elements or features may be oriented “above” one or more other elements or features. Therefore, the exemplary terms “below” or “below” are non-limiting and may cover both above and below orientations. Devices or systems may also be oriented in other ways as illustrated in the figures (e.g., rotated ninety degrees about a vertical axis or otherwise), and the spatial relative descriptive terms used herein shall be interpreted accordingly. In addition, it should be understood that when an element is referred to as being "between" two other elements, it may be the only element between the other two elements or there may be one or more intermediary elements.

[0017] Throughout this specification, several terms used in the field are employed. These terms have their general meanings in the field, unless specifically defined herein or indicated otherwise by the context in which they are used. It should be noted that element names and symbols (e.g., Si for silicon) are used interchangeably throughout this document; however, they have the same meaning.

[0018] A. Overview

[0019] As will be discussed, various examples of CMOS imaging systems with pixel arrays are disclosed. In these examples, ultra-low power merging of 64x64 readouts from 10x10 blocks of pixels from a 640x640 pixel array is implemented using pixel-level floating diffuser super-merging, where 10x10 pixels can be merged in the floating diffuser using a floating diffuser interconnect grid within the pixel array. A typical merging method for obtaining merged 64x64 pixels involves 10 rows of pixels vertically merged with source follower transistors and 10 columns of pixels horizontally merged. In these examples, each row reads out 64 10x10 pixels in parallel using a column analog-to-digital converter (ADC). For example, the typical frame time for reading 64 rows would therefore be 64*row time (e.g., 5 μs) or approximately 320 μs. The readout bandwidth is reduced by decreasing the data clock and allowing unused columns to be turned off.

[0020] However, the issue of reducing power consumption remains. Specifically, the data path is designed to accommodate higher resolutions, and the frame readout workcycle efficiency is reduced by only about 1 / 10x, because, for example, a total of 640 lines read is reduced to 64 merged line reads. Additionally, data transmission presents further challenges. Interfaces (e.g., the I3C data transfer interface) are not fast enough and therefore require a single-chip static random access memory (SRAM) to store data, impacting power and area. Furthermore, it should be understood that the Mobile Industry Processor Interface (MIPI) TX standard is not very efficient for data transmission at lower bandwidths.

[0021] In the examples described herein, super-merged pixel arrays are read out at high resolution with improved efficiency, thereby providing, for example, ultra-low power readout of 64 x 10 pixels per line time and / or ultra-low power readout of a 64 x 64 merged array of 10 x 10 blocks of pixels from a 640 x 640 pixel array. In various examples, super-merging is achieved by merging 10 x 10 pixels at a floating diffusion region using a floating diffusion region interconnect grid within the 10 x 10 blocks of pixels in the pixel array. In various examples, each 10 x 10 block of a pixel is coupled to an existing bit line using a dedicated source follower transistor and row select transistor coupled to a specific bit line of the corresponding 10 x 10 block of the pixel. In other examples, each 10 x 10 block of a pixel is coupled to an existing bit line using two or more source follower transistors and row select transistors coupled to a specific bit line of the corresponding 10 x 10 block of the pixel. Therefore, the eight vertical 10x10 blocks of a pixel can be read out simultaneously via their respective dedicated source follower transistors and row select transistors and / or via specific bit lines of the respective 10x10 pixel blocks. In various instances, this reduces the frame time from 64 line times in conventional methods (which require approximately 320 μs) to 64 / 8* line times (e.g., approximately 40 μs).

[0022] It should be understood that this technique can be implemented with pixels of other sizes and arrangements. For example, in some embodiments, the size of each block of pixels can be 4x4, 8x8, or another size. In some embodiments, the number of vertical blocks of pixels read simultaneously can be 4, 6, 10, or another number.

[0023] B. Image sensors with pixel binning of 10x10 blocks or full-resolution pixels and for reading image sensors Selected embodiments of the method

[0024] To illustrate, Figure 1 This is a block diagram of an example of an imaging system 100 configured according to various embodiments of the present technology. As shown, the imaging system 100 includes a pixel array 102, a readout circuitry system 106, functional logic 108, and a control circuitry system 110. The pixel array may consist of pixels arranged in rows (in... Figure 1Individually identified as rows R1 to Ry and rows (in Figure 1 Multiple pixels 104 (in which each is individually identified as column C1 to column Cx) Figure 1 The image is individually identified as a two-dimensional (2D) array of pixels P1 to Pn. Each pixel 104 is configured to acquire an image charge in response to incident light received from an external scene and to generate a corresponding analog image charge data signal based at least in part on the acquired image charge.

[0025] In various instances, it should be noted that pixel array 102 can be a 640x640 pixel array. In this instance, x = 640 and y = 640, such that... Figure 1 The rows in the table can be individually identified as rows R1 to R640, and Figure 1 The columns in the array can be individually identified as columns C1 to C640. In various instances, the pixels 104 in the pixel array 102 are also organized or arranged as 10x10 blocks of pixels 104. Thus, each 10x10 block of pixels 104 contains 100 pixels 104. Therefore, the first 10x10 block of pixels contains pixels in rows R1 to R10 and columns C1 to C10, and the second 10x10 block of pixels contains pixels in rows R11 to R20 and columns C1 to C10, and so on. Thus, the pixel array 102 is grouped into 64x64 blocks arranged or organized as 10x10 blocks of pixels 104.

[0026] After each pixel 104 has acquired image charge, the corresponding analog image charge data signal is read from the pixel array 102 along column bit line 112 and read into an analog-to-digital converter (ADC) 148, which is included in the readout circuitry system 106, as shown. As will be discussed in more detail below, in full-resolution mode, the full-resolution readout of each pixel 104 can be read from the pixel array 102 via bit line 112. In merged mode, the ultra-low power readout of a 10x10 block of pixels can be read from the pixel array 102 via bit line 112. In full-resolution mode, each pixel 104 is read through its corresponding source follower transistor, row select transistor, and bit line 112. In one example, in merged mode, each 10x10 block of pixels is read through the dedicated source follower transistor, row select transistor, and bit line 112 of the corresponding 10x10 block of the pixel. In another instance, when in merge mode, each 10x10 block of a pixel is read out through two or more source follower transistors and two or more row select transistors coupled to a specific bit line 112 of the corresponding 10x10 block of the pixel.

[0027] As mentioned, when the analog image charge data signal (i.e., a full-resolution signal from each pixel or a merged signal from a 10x10 block of pixels) is read into the readout circuitry 106, the analog image charge data signal can be converted into a digital value (digital representation) using the ADC 148. The digital representation of the analog image charge data signal can then be transferred from the readout circuitry 106 to the functional logic 108. In various instances, the data can be transferred via a data transfer interface, for example, according to the MIPI I3C data transfer interface specification or via other suitable data transfer interfaces. In some instances, the functional logic 108 is configured to simply store the digital representation as image data. In other instances, in addition to storing image data, the functional logic 108 can be configured to manipulate the image data (e.g., by applying post-image effects such as cropping, rotation, red-eye removal, brightness adjustment, contrast adjustment, etc.). The image data can be used to reproduce an image of an external scene (e.g., people, locations, objects, etc. within the external scene) from which light is received incident on pixels 104 of the pixel array 102.

[0028] As shown, control circuitry 110 is coupled to pixel array 102. In some embodiments, control circuitry 110 controls the operational characteristics of pixel array 102. For example, control circuitry 110 may generate appropriate transistor control gate signals (e.g., transfer gate signals, row selection signals RS0 / RS1, etc.) that can be used to: (a) control the transfer of signals from each of the pixels 104; or (b) control the transfer of merged signals from each 10x10 block of pixels.

[0029] Figure 2 This is a schematic circuit diagram of an example of pixel 204 according to the teachings of this technology. Pixel 204 can be... Figure 1 An instance of one of the pixels 104 of the pixel array 102 or an instance of another pixel according to the teachings of this technology, and the elements similarly named and numbered as described above are similarly coupled and functioned below.

[0030] As shown in the illustrated example, Figure 2 The pixel 204 shown includes a photoelectric sensor 216, a transfer transistor 218, a floating diffusion region 220, a dual floating diffusion region (DFD) transistor 221, a merge node 223, a floating diffusion region interconnect grid 225, a reset transistor 222, a source follower transistor 224, a row select transistor 226, and a bit line 212.

[0031] In the illustrated embodiment, photoelectric sensor 216 is a photodiode having an anode coupled to ground (e.g., ground, negative power supply rail, or another reference voltage) and a cathode coupled to transfer transistor 218. In other embodiments of the art, photoelectric sensor 216 may be another suitable type of photoelectric sensor or photodetector (e.g., metal-semiconductor-metal (MSM) photodetector, phototransistor, photoconductivity detector, or phototube). In operation, photoelectric sensor 216 is configured to generate image charge or photocurrent in response to incident light received from an external scene.

[0032] Transfer transistor 218 selectively couples photodetector 216 to floating diffusion region 220. Specifically, transfer transistor 218 includes a gate configured to receive transfer signal TX. When transfer signal TX is asserted on the gate of transfer transistor 218, transfer transistor 218 is activated to transfer photogenerated image charge from photodetector 216 to floating diffusion region 220.

[0033] DFD transistor 221 selectively couples the floating diffusion region 220 to the merging node 223, which in turn couples to the floating diffusion region interconnect grid 225, as shown. As will be discussed in more detail below, the floating diffusion region interconnect grid 225 is also coupled to the merging node 223 of all other similar pixels 204 in the corresponding 10x10 block of a pixel in the pixel array (e.g., pixel array 102). As shown, DFD transistor 221 includes a gate configured to receive the signal DFD. When the signal DFD applied to the gate of DFD transistor 221 is asserted, DFD transistor 221 is activated, which couples the floating diffusion region 220 to the merging node 223 and thus to the merging node 223 of all other similar pixels 204 in the corresponding 10x10 block of a pixel in the pixel array. Therefore, when the DFD transistor 221 is activated, the merging mode is enabled, causing the floating diffusion region 220 of pixel 204 to couple to the merging node 223. The merging node 223 is coupled to the corresponding merging node 223 through the floating diffusion region interconnect grid 225 and to the floating diffusion region 220 through the DFD transistors 221 of other similar pixels 204 contained in the corresponding 10x10 block of the pixel. Thus, when the corresponding DFD transistor 221 of pixel 204 contained in the corresponding 10x10 block of the pixel is activated, the pixels contained in the 10x10 block of the pixel are merged.

[0034] On the other hand, when the signal DFD applied to the gate of DFD transistor 221 is not asserted, DFD transistor 221 is deactivated, and floating diffusion region 220 is not coupled to merging node 223, and therefore not coupled to merging node 223 of other pixels contained in the 10x10 block of the pixel through floating diffusion region interconnect grid 225. Therefore, when DFD transistor 221 is deactivated, full-resolution mode is enabled so that each pixel 204 can be individually read out to the readout circuitry system to achieve full-resolution readout.

[0035] In the illustrated embodiment, reset transistor 222 selectively couples merging node 223 to pixel voltage supply PIXVD. More specifically, reset transistor 222 includes a gate configured to receive a reset signal RST. When the reset signal RST is asserted, reset transistor 222 is activated to couple merging node 223 to pixel voltage supply PIXVD. In various instances, when the reset signal RST applied to the gate of reset transistor 222 is asserted, the signal DFD applied to the gate of DFD transistor 221 can be asserted. When this occurs, DFD transistor 221 and reset transistor 222 are activated to couple floating diffusion region 220 to pixel voltage supply PIXVD, thereby resetting the voltage at floating diffusion region 220. In various instances, when the reset signal RST applied to the gate of reset transistor 222 is asserted and the signal DFD applied to the gate of DFD transistor 221 is simultaneously asserted, the transfer signal TX applied to the gate of transfer transistor 218 can be asserted. When this occurs, DFD transistor 221, reset transistor 222 and transfer transistor 218 are activated to couple floating diffusion region 220 and photoelectric sensor 216 to pixel voltage supply PIXVD, thereby resetting the voltage at floating diffusion region 220 and photoelectric sensor 216.

[0036] As shown in the illustrated example, the floating diffusion region 220 is further coupled to the gate of the source follower transistor 224. A row select transistor 226 is coupled to the source follower transistor 224 such that the source follower transistor 224 and the row select transistor 226 are coupled between the voltage supply AVDD and the bit line 212, as shown. In operation, the source follower transistor 224 is configured to convert the charge at the floating diffusion region 220 into an analog signal at the source of the source follower transistor 224. When the signal DFD applied to the gate of the DFD transistor 221 is asserted and the DFD transistor 221 is activated, all floating diffusion regions 220 in the corresponding 10x10 block of the pixel 204 are coupled together or merged through the floating diffusion region interconnect grid 225 in the corresponding 10x10 block of the pixel at the gate of the source follower transistor 224 and the activated DFD transistor 221, such that a merged analog signal is provided at the source of the source follower transistor 224 to achieve merged readout. When the signal DFD applied to the gate of DFD transistor 221 is not asserted and DFD transistor 221 is deactivated, the floating diffusion region 220 is not coupled to other floating diffusion regions 220 of other pixels 204 contained in the corresponding 10x10 block of the pixel. Therefore, the analog signal provided at the source of the source follower transistor 224 represents the charge at the floating diffusion region 220 of pixel 204 for full-resolution readout.

[0037] Row selection transistor 226 selectively couples the source of source follower transistor 224 to bit line 212. As will be discussed in more detail below, in various instances, the gate of row selection transistor 226 is coupled to receive either row selection signal RS0 or row selection signal RS1. When row selection signal RS0 or RS1 is asserted, row selection transistor 226 is activated to pass the analog signal received from source follower transistor 224 to the ADC in the readout circuitry (e.g., ADC 148 in readout circuitry 106). As will be discussed in more detail below, in various instances, if the gate of row selection transistor 226 is coupled to receive row selection signal RS1, DFD transistor 221 is deactivated, and the gates of the row selection transistors of other pixels 204 contained in the corresponding 10x10 block of the pixel are coupled to receive row selection signal RS0, then row selection signals RS0 and RS1 can be asserted for full-resolution readout of pixel 204 in full-resolution mode. On the other hand, as will be discussed in more detail below, in various instances, if the gate of the row selection transistor 226 is coupled to receive the row selection transistor RS1 and the DFD transistor is activated, then the row selection signal RS1 can be asserted to merge the readout of the pixel 204 contained in the corresponding 10x10 block of the pixel in merge mode.

[0038] For illustration, Figures 3A and 3B illustrate an example merging scheme for a pixel array 302 according to the teachings of this technology, wherein 10x10 blocks of pixels 304 are merged at the floating diffusion region by corresponding floating diffusion region interconnecting grids 325 within the 10x10 blocks of pixels 304. It should be understood that the example pixel array 302, pixels 304, bit line 312, and floating diffusion region interconnecting grids 325 depicted in Figures 3A and 3B can be the same as described above. Figures 1 to 2 Examples of pixel arrays 102, pixels 104, 204 and / or floating diffusion region interconnection grids 225 discussed herein, and elements similarly named and numbered as described above are similarly coupled and function below.

[0039] As shown in the example depicted in Figure 3A, the pixel array 302 is arranged or organized into 10x10 blocks of pixels 304. In various examples, the pixels 304 of the pixel array 302 are read out via bit lines 312. In the illustrated example, the top 10x10 block of a pixel is labeled 1, the next 10x10 block is labeled 2, ..., the eighth 10x10 block of a pixel is labeled 8, and so on. In various examples, the full-resolution readout of each pixel 304 can be read out via the corresponding bit line 312. Additionally, in various examples, the combined readout of each 10x10 block of a pixel can also be read out via the corresponding bit line. As discussed, the merged readout of the top 10x10 block of a pixel marked 1 is read through bit line 312 marked 1, the merged readout of the top 10x10 block of a pixel marked 2 is read through bit line 312 marked 2, ..., and the merged readout of the eighth 10x10 block of a pixel marked 8 is read through bit line 312 marked 8. In various instances, the ADC (e.g., Figure 1 The ADC 148 is coupled in parallel to line 312 and is thus coupled to receive the combined readout of all eight 10x10 blocks of pixels in parallel. In other words, the ADC is configured to simultaneously read out the combined signal in parallel from eight vertical 10x10 blocks of pixels labeled 1 to 8 in a combined mode, to achieve high-speed super-combining ultra-low-power readout of pixel array 302 according to the teachings of this technique. Thus, it should be understood that the frame time is significantly reduced, for example, to 64 / 8*line time (e.g., 40 μs) according to the teachings of this technique. Therefore, in a 640x640 pixel array, it should be understood that, according to the teachings of this technique, each row and column ADC simultaneously converts 512 combined pixels (“1” x 640 / 80 x 640 / 10). In various instances, the 512 pixels can be read sequentially from asynchronous static random access memory (ASRAM), ignoring pixel order for efficient data transfer from the sensor.

[0040] It should be noted that because the vertical 10x10 block of pixels illustrated in Figure 3A contains eight 10x10 blocks of pixels, rather than ten, bit lines 312 marked 9 and 10 are not used and are therefore de-energized in the depicted instance to increase power savings. However, it should be understood that if there were ten 10x10 blocks containing pixels, then bit lines 312 marked 9 and 10 could also be energized and used in the same way.

[0041] The example diagram depicted in Figure 3B provides a more detailed description of pixels 304, a portion of pixel array 302. Specifically, the portion of pixel array 302 depicted in Figure 3B illustrates the top two vertical 10x10 blocks of pixels 1 to 2 shown in Figure 3A. Specifically, the top 10x10 block of pixel 1 in Figure 3A comprises a first row of ten pixels 304AA, 304AB, ..., 304AJ, ... up to a tenth row of ten pixels containing pixels 304JA, 304JB, ..., 304JJ. Similarly, the next vertical 10x10 block of pixel 2 in Figure 3A comprises an eleventh row of ten pixels 304KA, 304KB, ..., 304KJ, ... up to a twentieth row of ten pixels containing pixels 304TA, 304TB, ..., 304TJ.

[0042] Continuing with the example depicted in Figure 3B, the row selection transistors of pixels 304AB to 304AJ in the first row are coupled to receive the first row selection signal R0. <n>Meanwhile, the row selection transistor of pixel 304AA in the first row is coupled to receive the second row selection signal R1. <n>The row selection transistors for pixels 304JB to 304JJ in the tenth row are coupled to receive the first row selection signal R0.<n+9> Meanwhile, the row selection transistor of pixel 304JA in the tenth row is coupled to receive the second row selection signal R1.<n+9> .

[0043] Similarly, the row selection transistors of pixels 304KA, 304KC (not shown for simplicity) to 304KJ in the eleventh row are coupled to receive the first row selection signal R0.<n+10> Meanwhile, the 304KB row selection transistor of the eleventh row is coupled to receive the second row selection signal R1.<n+10> The row selection transistors of pixels 304TA, 304TC (not shown for simplicity) to 304TJ in the twentieth row are coupled to receive the first row selection signal R0.<n+19> Meanwhile, the row selection transistor of the 304TB pixel in the twentieth row is coupled to receive the second row selection signal R1.<n+19> .

[0044] Continuing further with the example depicted in Figure 3B, the row selection transistors containing pixels 304AA, ... 304JA, ... 304KA, ... 304TA, ... in the first column shown are coupled to the label bl. <m>The bit line 312, and the row selection transistors of pixels 304AB, ... 304JB, ... 304KB, ... 304TB, ... contained in the second column shown, are coupled to the label bl.<m+1> The bit line is 312.

[0045] The example depicted in Figure 3B also illustrates a floating diffusion region interconnect mesh 325AA, which is coupled to the merge node of each of pixels 304AA to 304JJ contained in the first vertical 10x10 block labeled 1, as shown in Figure 3A. Similarly, a floating diffusion region interconnect mesh 325KA is coupled to the merge node of each of pixels 304KA to 304TJ contained in the second vertical 10x10 block labeled 2, as shown in Figure 3A.

[0046] As discussed above, in full-resolution mode operation, the DFD transistor in each of the pixels 304 is deactivated. Therefore, it should be understood that, according to the teachings of this technique, in full-resolution mode operation, both the first row selection signal RS0 and the second row selection signal RS1 can be used to control the row selection transistor of the pixel 304 to achieve full-resolution readout of all pixels 304 contained in the pixel array 302.

[0047] As discussed above, in the merge mode operation, the DFD transistor in each of pixel 304 is activated. Therefore, the floating diffusion regions of all pixels 304AA to 304JJ contained in the first vertical 10x10 block labeled 1 are coupled together or merged via the floating diffusion region interconnect grid 325AA. Similarly, the floating diffusion regions of all pixels 304KA to 304TJ contained in the second vertical 10x10 block labeled 2 are coupled together or merged via the floating diffusion region interconnect grid 325KA.

[0048] In one example, the merged readout of each 10x10 block of pixels can be read out via a separate bit line through a designated source follower transistor and a row select transistor. In one example, the merged signal of pixels 304AA to 304JJ contained in the first vertical 10x10 block of pixel 1 is read out via bit line 312bl. <m>Read out via a designated single source follower transistor and row select transistor for pixel 304JA. In this example, the second row select signal RS1<n+9> The specified row selection transistor for pixel 304JA is configured to activate to read out the merge signal. In this example, the first row selection signal RS0 and the other second row selection signal RS1... <n>To RS1<n+8> Unused. Similarly, the merged signal of pixels 304KA to 304TJ contained in the second vertical 10x10 block marked as pixel 2 is transmitted via bit line 312bl.<m+1> Readout via a single source follower transistor and row select transistor for a pixel 304TB. In this example, the second row select signal RS1<n+19> The specified row selection transistors of pixel 304TB are configured to activate to read out the merged signals. In this example, the first row selection signal RS0 and the other second row selection signal RS1...<n+10> To RS1<n+18> Unused. Because it utilizes a single or specified bit line 312bl. <m>312bl<m+1> The corresponding 10x10 blocks of pixels are read out, and it should be understood that, according to the teachings of this technique, the merged signals from the 10x10 blocks can be read out simultaneously to achieve high-speed super-merging ultra-low-power readout of the pixel array 302.

[0049] In another example, it should be understood that the merged readout of each 10x10 block of a pixel can be read out via two or more source follower transistors and row select transistors coupled to separate bit lines of each corresponding 10x10 block of the pixel. For example, the merged signal of pixels 304AA to 304JJ contained in the first vertical 10x10 block of the pixel marked 1 is transmitted via bit line 312bl. <m>Readout is achieved through two or more source follower transistors and row select transistors for pixels 304AA to 304JJ. In this example, the second row select signal RS1 <n>To RS1<n+9> Two or more of them are configured to activate the coupling bit line 312bl <m>The corresponding row selection transistors in the corresponding columns of pixels 304AA, ... 304JA. The first row selection signal RS0 is not used during merge mode readout. Similarly, the merge signal for pixels 304KA to 304TJ contained in the second vertical 10x10 block labeled 2 is transmitted via bit line 312bl.<m+1> Readout is achieved through two or more source follower transistors and row select transistors for pixels 304KA to 304TJ. In this example, the second row select signal RS1<n+10> To RS1<n+19> Two or more of them are configured to activate the coupling bit line 312bl<m+1> The corresponding row selection transistors in the corresponding columns of pixels 304KB, ... 304TB. The first row selection signal RS0 is not used during merge mode readout. This is because it utilizes a single or designated bit line 312bl. <m>312bl<m+1> ... and so on, to read out the corresponding 10x10 blocks of pixels. Therefore, it should be understood that, according to the teachings of this technology, the merged signals from the 10x10 blocks can be read out simultaneously to achieve high-speed super-merging ultra-low-power readout of the pixel array 302.

[0050] Figure 4 The illustration shows an example timing diagram 428 of an improved readout time with reduced power consumption of a pixel array comprising 10x10 blocks of pixels according to the teachings of this technology, wherein the 10x10 blocks of pixels are merged at floating diffusion regions within the pixels contained in the 10x10 blocks of pixels.

[0051] In the illustrated example, the trigger event (TRIG) in the frame synchronization (FSIN) input indicates the end of a sleep cycle as indicated for the sensor. After the sleep cycle ends, a readout cycle occurs in the sensor. The readout cycle consists of a period T. wake The wake-up cycle, followed by a cycle with period T precharge The precharge cycle, with a period T int The integral period, with period T xfr The transfer cycle, with a period T Read The read cycle and sleep cycle. As shown, the sleep cycle ends in response to another trigger event TRIG in the frame synchronization input.

[0052] The illustrated examples demonstrate that the readout cycle begins with an ADC cycle that overlaps with the MIPI cycle that ends the readout cycle. In the depicted examples, the ADC cycle of the readout cycle is extended, according to the teachings of this technique, to illustrate the difference between conventional merge readout and efficient super-merge ultra-low power readout for an example 640x640 pixel array. For example, in conventional merge readout, a typical merging method to obtain a merged 64x64 pixels involves 10 rows of pixels vertically merged with source follower transistors and 10 columns of pixels horizontally merged. In these conventional examples, for a 640x640 pixel array, 10x10 pixels are read out in parallel 64 times using an ADC. Figure 4 The examples described typically correspond to high-power, high-speed (HS) data transfer cycles and low-speed (LS) or low-power cycles that occur in each of the total 64 reads. For example, the typical frame time for 64 read lines would therefore be 64 * 5 μs, or approximately 320 μs.

[0053] Figure 4 The examples depicted also illustrate an improved, highly efficient, super-merging, ultra-low-power readout of a conventional 640x640 pixel array for comparison. As shown and described in the previous example where the merged readout of eight 10x10 blocks of pixels is performed simultaneously, only eight readouts are required. The examples also illustrate the high-speed (HS) data transfer cycle and the low-speed (LS) cycle that occurs in each of the total 8x readouts. It should be noted that the HS duration for each of the improved 8x readouts can be longer than the corresponding HS duration for each of the conventional 64x readouts, but the overall power consumption is still reduced. Therefore, according to the teachings of this technique, significant time savings and thus significant power savings are achieved. In various examples, in the case of simultaneous merged readout of 10x10 blocks as described above, the readout cycle time is significantly reduced by 64 / 8 or 8*line time (e.g., approximately 40 μs).

[0054] C. in conclusion

[0055] The above detailed description of embodiments of this technology is not intended to be exhaustive or to limit the technology to the precise forms disclosed above. Although specific embodiments and examples of this technology have been described above for illustrative purposes, those skilled in the art will recognize that various equivalent modifications are possible within the scope of this technology. For example, although the steps are presented in the given order above, alternative embodiments may perform the steps in a different order. Furthermore, the various embodiments described herein may also be combined to provide other embodiments.

[0056] As should be understood from the foregoing, specific embodiments of the present technology have been described herein for illustrative purposes, but well-known structures and functions have not been shown or described in detail so as not to unnecessarily obscure the description of the embodiments of the present technology. If any material incorporated herein by reference conflicts with this disclosure, this disclosure shall prevail. Singular or plural terms may be included, respectively, where the context permits. Furthermore, unless the word "or" is explicitly limited to a single item excluding other items in a list of two or more items, its use in this list shall be interpreted as including (a) any single item in the list, (b) all items in the list, or (c) any combination of items in the list. Additionally, as used herein, the phrase "and / or" in "A and / or B" means only A, only B, and both A and B. Furthermore, the use throughout the term "comprising," "including," "having," and "having" means including at least the stated features, such that no larger number of identical features and / or other features of additional types are excluded. Furthermore, as used herein, the phrases "based on," "depending on," "due to," and "in response to" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on" or the phrase "at least partially based on." Moreover, the terms "connected" and "coupled" are used interchangeably herein and refer to both direct and indirect connection or coupling. For example, where the context permits, element A being "connected" or "coupled" to element B may mean (i) A being directly "connected" or directly "coupled" to B and / or (ii) A being indirectly "connected" or indirectly "coupled" to B.

[0057] It should also be understood from the foregoing that various modifications can be made without departing from this disclosure or the present technology. For example, those skilled in the art will understand that the various components of the present technology can be further divided into sub-components, or the various components and functions of the present technology can be combined and integrated. Furthermore, certain aspects of the present technology described in the context of a particular embodiment may be combined or eliminated in other embodiments. Moreover, although advantages associated with certain embodiments of the present technology have been described in the context of said embodiments, other embodiments may also exhibit such advantages, and not all embodiments necessarily need to exhibit such advantages to fall within the scope of the present technology. Therefore, this disclosure and related technologies may cover other embodiments not explicitly shown or described herein.< / m> < / m> < / n> < / m> < / m> < / n> < / m> < / m> < / n> < / n>

Claims

1. A pixel comprising: A photoelectric sensor configured to generate a photoelectric charge in response to incident light; A floating diffusion region configured to receive the charge generated by the photoelectric sensor; A transfer transistor coupled between the floating diffusion region and the photoelectric sensor; A dual floating diffusion region DFD transistor, coupled to the floating diffusion region; A merging node, which is coupled to the DFD transistor; and A floating diffusion region interconnecting mesh, coupled to the merging node of the pixel and the merging node of the second pixel, wherein the pixel and the second pixel are contained in a plurality of pixels in a pixel array. The DFD transistor is configured to couple the merging node to the floating diffusion region when activated during a readout operation of the pixel array to provide merged readout of the pixel and the second pixel. The DFD transistor is configured to not couple the merge node to the floating diffusion region when deactivated during the readout operation on the pixel array, in order to provide full-resolution readout of the pixel and the second pixel.

2. The pixel according to claim 1, further comprising: A source follower transistor having a gate coupled to the floating diffusion region; and A row select transistor coupled to the source follower transistor, wherein the source follower transistor and the row select transistor are coupled between a voltage supply and a bit line.

3. The pixel of claim 2, wherein the row selection transistor is configured to be activated during the readout operation in response to one of a first row selection signal and a second row selection signal to provide the full-resolution readout of the pixel when the DFD transistor is deactivated.

4. The pixel of claim 2, wherein the row selection transistor is configured to be activated during the readout operation in response to a second row selection signal to provide the combined readout of the pixel and the second pixel when the DFD transistor is activated and the row selection transistor of the second pixel is deactivated.

5. The pixel of claim 2, wherein the row selection transistor of the second pixel is configured to be activated during the readout operation in response to a second row selection signal to provide the combined readout of the pixel and the second pixel when the DFD transistor is activated and the row selection transistor of the pixel is deactivated.

6. The pixel of claim 2, wherein the bit line is the first bit line of a plurality of bit lines, wherein the row selection transistor is configured to be activated in response to a second row selection signal during the readout operation to provide the combined readout of the pixel and the second pixel when the DFD transistor is activated, wherein the row selection transistor of the second pixel is coupled to the first bit line, wherein the row selection transistor of the second pixel is activated in response to the second row selection signal, wherein the row selection transistor of the third pixel is coupled to the second bit line of the plurality of bit lines, wherein the row selection transistor of the third pixel is deactivated in response to the first row selection signal.

7. The pixel of claim 1, wherein the plurality of pixels comprises 100 pixels contained in a 10x10 block of pixels in the pixel array, wherein the floating diffusion region interconnect mesh is coupled to a corresponding merge node contained in each of the plurality of pixels.

8. The pixel of claim 1, further comprising a reset transistor coupled between the pixel voltage supply and the merging node.

9. An imaging system comprising: A pixel array comprising a plurality of pixels arranged in rows and columns and a floating diffusion region interconnection grid coupled to the plurality of pixels, wherein each of the pixels comprises: A photoelectric sensor configured to generate a photoelectric charge in response to incident light; A floating diffusion region configured to receive the charge generated by the photoelectric sensor; A transfer transistor coupled between the floating diffusion region and the photoelectric sensor; A dual floating diffused DFD transistor coupled to the floating diffused region; and A merging node, which is coupled to the DFD transistor; A control circuit system coupled to the pixel array to control the operation of the pixel array; and Readout circuitry, coupled to receive merged or full-resolution readout from the pixel array. The floating diffusion region interconnect mesh is coupled to the merged node of each of the pixels. The DFD transistor of each of the pixels is configured to couple the merging node to the floating diffusion region when activated during a readout operation of the pixel array to provide the merging readout of the pixel array, and The DFD transistor of each of the pixels is configured to not couple the merge node to the floating diffusion region when deactivated during the readout operation of the pixel array to provide the full-resolution readout of the pixel array.

10. The imaging system of claim 9, further comprising functional logic coupled to the readout circuit for storing and processing digital representations of image charge values ​​from the pixel array.

11. The imaging system of claim 9, wherein each of the pixels further comprises: A source follower transistor having a gate coupled to the floating diffusion region; and Row selection transistor, which is coupled to the source follower transistor, The source follower transistor and the row selection transistor of each of the pixels are coupled between a voltage supply and one of a plurality of bit lines.

12. The imaging system of claim 11, wherein the row selection transistor of the pixel is configured to be activated during the readout operation in response to a first or second row selection signal to provide the full-resolution readout of the pixel array when the DFD transistor of each of the pixels is deactivated.

13. The imaging system of claim 11, wherein the row selection transistor of one of the pixels is configured to be activated in response to a second row selection signal during the readout operation to provide the combined readout of the pixel array when the DFD transistor of each of the pixels is activated and the row selection transistor of the remaining pixels is deactivated.

14. The imaging system of claim 11, wherein the row selection transistors of a second subset of the plurality of pixels are configured to be activated during the readout operation in response to a second row selection signal to provide the combined readout of the pixel array when the DFD transistor of each of the pixels is activated and the row selection transistors of the first subset of the plurality of pixels are deactivated.

15. The imaging system of claim 11, wherein a row selection transistor of a first pixel in the pixels is coupled to a first bit line of the plurality of bit lines, wherein the row selection transistor of the first pixel is configured to be activated in response to a second row selection signal during the readout operation to provide the merged readout of the pixel array when the DFD transistor of each of the pixels is activated, wherein a row selection transistor of a second pixel in the pixels is coupled to the first bit line, wherein the row selection transistor of the second pixel is activated in response to the second row selection signal, wherein a row selection transistor of a third pixel in the pixels is coupled to a second bit line of the plurality of bit lines, wherein the row selection transistor of the third pixel is deactivated in response to the first row selection signal.

16. The imaging system of claim 9, wherein the plurality of pixels comprises 100 pixels contained in a 10x10 block of pixels in the pixel array.

17. The imaging system of claim 9, wherein each of the pixels further comprises a reset transistor coupled between the pixel voltage supply and the merging node.

18. The imaging system according to claim 11, wherein: The plurality of pixels includes a first plurality of pixels. The pixel array further includes a second plurality of pixels. The row selection transistor of a subset of the first plurality of pixels is coupled to the first bit line of the plurality of bit lines and configured to be activated during the readout operation in response to a first row selection signal to provide a merged readout of the first plurality of pixels when the DFD transistor of each of the first plurality of pixels is activated, and The row selection transistor of the subset of the second plurality of pixels is coupled to a second bit line among the plurality of bit lines and configured to be activated during the readout operation in response to a second row selection signal to provide a combined readout of the second plurality of pixels when the DFD transistor of each of the second plurality of pixels is activated.

19. The imaging system of claim 18, wherein the readout circuit is coupled to the first and second bit lines and configured to simultaneously and in parallel receive the combined readout of the first plurality of pixels and the combined readout of the second plurality of pixels.

20. The imaging system of claim 18, wherein the row selection transistors of the subset of the first plurality of pixels are configured to be activated during the readout operation to provide a merged readout of the first plurality of pixels when the row selection transistors of the remaining pixels in the first plurality of pixels are deactivated, and wherein the row selection transistors of the subset of the second plurality of pixels are configured to be activated during the readout operation to provide a merged readout of the second plurality of pixels when the row selection transistors of the remaining pixels in the second plurality of pixels are deactivated.

Images