Micro LED structure and micro display panel

Abstract

A micro light emitting diode (LED) structure includes a mesa structure. The mesa structure further includes a first semiconductor layer having a first conductivity type, a light emitting layer formed on the first semiconductor layer, and a second semiconductor layer formed on the light emitting layer, the second semiconductor layer having a second conductivity type different from the first conductivity type. The second semiconductor layer further includes a semiconductor region and an ion implantation region formed around the semiconductor region, the ion implantation region having a higher electrical resistance than the semiconductor region.

Description

Technical Field

[0001] This disclosure relates generally to the field of light-emitting diode technology, and more specifically to a micro light-emitting diode (LED) structure and a micro display panel including said micro LED structure. Background Technology

[0002] Inorganic micro-light-emitting diodes (also known as “micro-LEDs” or “μ-LEDs”) are becoming increasingly important due to their use in a variety of applications, including self-emitting microdisplays, visible light communication, and optogenetics. μ-LEDs offer superior output performance compared to conventional LEDs due to better strain relaxation, improved light extraction efficiency, and more uniform current spreading. Compared to conventional LEDs, μ-LEDs are characterized by improved thermal effects, improved operation at higher current densities, better response rates, a wider operating temperature range, higher resolution, a wider color gamut, higher contrast, and lower power consumption.

[0003] μ-LEDs comprise a III-V group epitaxial layer for forming multiple mesa. In some μ-LED designs, spaces need to be formed between adjacent μ-LEDs to prevent carriers in the epitaxial layer from diffusing from one mesa to the next. The spaces formed between adjacent microLEDs can reduce the effective light-emitting area and decrease light extraction efficiency. Eliminating these spaces may increase the effective light-emitting area, but this will cause carriers in the epitaxial layer to diffuse laterally to adjacent mesa, thus reducing luminous efficiency. Furthermore, without the spaces between adjacent mesa, crosstalk will occur between adjacent μ-LEDs, leading to less reliable or inaccurate μ-LEDs.

[0004] Furthermore, in some μ-LED structures, small LED pixels with high current density are more likely to experience redshift, lower maximum efficiency, and uneven emission, typically caused by degraded current injection during manufacturing. Additionally, the peak external quantum efficiency (EQE) and internal quantum efficiency (IQE) of μ-LEDs decrease significantly with decreasing chip size. The reduction in EQE is caused by nonradiative recombination at improperly etched quantum well sidewalls. The reduction in IQE is caused by poor current injection and electron leakage current in μ-LEDs. Improving EQE and IQE requires optimizing the quantum well sidewall region to reduce current density. Summary of the Invention

[0005] According to this disclosure, a micro-LED structure is provided. The structure includes a mesa structure. The mesa structure further includes a first semiconductor layer having a first conductivity type, a light-emitting layer formed on the first semiconductor layer, and a second semiconductor layer formed on the light-emitting layer, the second semiconductor layer having a second conductivity type different from the first conductivity type. The second semiconductor layer further includes a semiconductor region and an ion-implanted region formed around the semiconductor region, the resistance of the ion-implanted region being higher than the resistance of the semiconductor region.

[0006] Furthermore, according to this disclosure, a microdisplay panel is provided. The microdisplay panel includes a microLED array. The microLED array includes a first microLED structure and an integrated circuit (IC) backplane formed beneath the first microLED structure. The first microLED structure is electrically coupled to the IC backplane. Attached Figure Description

[0007] Figure 1 This is a schematic cross-sectional view of a micro-LED structure according to an exemplary embodiment of this disclosure;

[0008] Figure 2 This is an exemplary embodiment of the present disclosure for manufacturing such as Figure 1 A flowchart illustrating the method for constructing the micro-LED structure is shown.

[0009] Figure 3 This is an illustrative representation of an exemplary embodiment according to this disclosure for implementing... Figure 2 A cross-sectional view of the steps of the method;

[0010] Figure 4 This is an illustrative representation of an exemplary embodiment according to this disclosure for implementing... Figure 2 A cross-sectional view of the steps of the method;

[0011] Figure 5 This is an illustrative representation of an exemplary embodiment according to this disclosure for implementing... Figure 2 A cross-sectional view of the steps of the method;

[0012] Figure 6 This is an illustrative representation of an exemplary embodiment according to this disclosure for implementing... Figure 2 A cross-sectional view of the steps of the method;

[0013] Figure 7 This is an illustrative representation of an exemplary embodiment according to this disclosure for implementing... Figure 2 A cross-sectional view of the steps of the method;

[0014] Figure 8This is an illustrative representation of an exemplary embodiment according to this disclosure for implementing... Figure 2 A cross-sectional view of the steps of the method;

[0015] Figure 9 This is an illustrative representation of an exemplary embodiment according to this disclosure for implementing... Figure 2 A cross-sectional view of the steps of the method;

[0016] Figure 10 This is an illustrative representation of an exemplary embodiment according to this disclosure for implementing... Figure 2 A cross-sectional view of the steps of the method;

[0017] Figure 11 This is an illustrative representation of an exemplary embodiment according to this disclosure for implementing... Figure 2 A cross-sectional view of the steps of the method;

[0018] Figure 12 This is an illustrative representation of an exemplary embodiment according to this disclosure for implementing... Figure 2 A cross-sectional view of the steps of the method;

[0019] Figure 13 This is a schematic cross-sectional view of at least a portion of an exemplary microdisplay panel according to an exemplary embodiment of this disclosure.

[0020] Figure 14 This is an illustrative representation of an exemplary embodiment according to this disclosure for implementing... Figure 13 A cross-sectional view of the steps of the method;

[0021] Figure 15 This is an illustrative representation of an exemplary embodiment according to this disclosure for implementing... Figure 13 A cross-sectional view of the steps of the method;

[0022] Figure 16 This is an illustrative representation of an exemplary embodiment according to this disclosure for implementing... Figure 13 A cross-sectional view of the steps of the method;

[0023] Figure 17 This is an illustrative representation of an exemplary embodiment according to this disclosure for implementing... Figure 13 A cross-sectional view of the steps of the method;

[0024] Figure 18 This is an illustrative representation of an exemplary embodiment according to this disclosure for implementing... Figure 13 A cross-sectional view of the steps of the method;

[0025] Figure 19This is an illustrative representation of an exemplary embodiment according to this disclosure for implementing... Figure 13 A cross-sectional view of the steps of the method;

[0026] Figure 20 This is an illustrative representation of an exemplary embodiment according to this disclosure for implementing... Figure 13 A cross-sectional view of the steps of the method;

[0027] Figure 21 This is an illustrative representation of an exemplary embodiment according to this disclosure for implementing... Figure 13 A cross-sectional view of the steps of the method;

[0028] Figure 22 This is an illustrative representation of an exemplary embodiment according to this disclosure for implementing... Figure 13 A cross-sectional view of the steps of the method;

[0029] Figure 23 This is an illustrative representation of an exemplary embodiment according to this disclosure for implementing... Figure 13 A cross-sectional view of the steps of the method;

[0030] Figure 24 This is an illustrative representation of an exemplary embodiment according to this disclosure for implementing... Figure 13 A cross-sectional view of the steps of the method;

[0031] Figure 25 This is an illustrative representation of an exemplary embodiment according to this disclosure for implementing... Figure 13 A cross-sectional view of the steps of the method;

[0032] Figure 26 This is an illustrative representation of an exemplary embodiment according to this disclosure for implementing... Figure 13 A cross-sectional view of the steps of the method;

[0033] Figure 27 This is an illustrative representation of an exemplary embodiment according to this disclosure for implementing... Figure 13 A cross-sectional view of the steps of the method;

[0034] Figure 28 This is an illustrative representation of an exemplary embodiment according to this disclosure for implementing... Figure 13 A cross-sectional view of the steps of the method; and

[0035] Figure 29 This is an illustrative representation of an exemplary embodiment according to this disclosure for implementing... Figure 13 A cross-sectional view of the steps of the method. Detailed Implementation

[0036] In the following description, embodiments consistent with this disclosure will be illustrated with reference to the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts.

[0037] As discussed above, existing micro-LEDs may suffer from problems such as redshift, low maximum efficiency, and uneven emission. To address these issues, an embodiment of the present invention provides a micro-LED structure. In conjunction with... Figure 1 In some consistent embodiments, the micro-LED structure includes a mesa structure 01, a top contact 02, a bottom contact 03, and a top conductive layer 04. The mesa structure 01 further includes a first-type semiconductor layer 101, a light-emitting layer 102, and a second-type semiconductor layer 103. The light-emitting layer 102 is formed on top of the first-type semiconductor layer 101. The second-type semiconductor layer 103 is located on top of the light-emitting layer 102. In some embodiments, the first type and the second type refer to different conductivity types. For example, the first type is P-type, and the second type is N-type. In another example, the first type is N-type, and the second type is P-type.

[0038] In some embodiments, the material of the first type semiconductor layer 101 includes at least one of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, and p-AlGaN. The material of the second type semiconductor layer 103 includes at least one of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-InGaN, and n-AlGaN. The light-emitting layer 102 is formed of a quantum well layer. The material of the quantum well layer includes at least one of GaAs, InGaN, AlGaN, AlInP, GaInP, and AlGaInP. In some further embodiments, the thickness of the first type semiconductor layer 101 is greater than the thickness of the second type semiconductor layer 103, and the thickness of the light-emitting layer 102 is less than the thickness of the first type semiconductor layer 101. In some embodiments, the thickness of the first type semiconductor layer 101 ranges from 700 nm to 2 μm, and the thickness of the second type semiconductor layer 103 ranges from 100 nm to 200 nm. In some implementations, the thickness of the quantum well layer is less than or equal to 30 nm. In some implementations, the quantum well layer comprises no more than three pairs of quantum wells.

[0039] In some embodiments, the first type semiconductor layer 101 includes one or more mirrors 1011. In some embodiments, the mirrors 1011 are formed on the bottom surface of the first type semiconductor layer 101. In some embodiments, the mirrors 1011 are formed inside the first type semiconductor layer 101. In some embodiments, the material of the mirrors 1011 is a mixture of dielectric and metallic materials. In some further embodiments, the dielectric material includes SiO2 or SiN. x Where "x" is a positive integer. In some embodiments, the metallic material includes Au or Ag. In some embodiments, a plurality of mirrors 1011 are formed horizontally, one after another, in different horizontal planes in the first type semiconductor layer 1011, thereby dividing the first type semiconductor layer 101 into multiple layers.

[0040] In some embodiments, a top contact 02 is formed on the top surface of the second type semiconductor layer 103. The conductivity type of the top contact 02 is the same as that of the second type semiconductor layer 103. For example, if the second type is N-type, then the top contact 02 is an N-type contact; or if the second type is P-type, then the top contact 02 is a P-type contact. In some embodiments, the top contact 02 is made of a metal or metal alloy including at least one of AuGe, AuGeNi, etc. The top contact 02 is used to form an ohmic contact between the top conductive layer 04 and the second type semiconductor layer 103, thereby optimizing the electrical properties of the microLED. In some embodiments, the diameter of the top contact 02 ranges from 20 nm to 50 nm, and the thickness of the top contact 02 ranges from 10 nm to 20 nm.

[0041] In some embodiments, the second type semiconductor layer 103 includes a second type semiconductor region 1031 and an ion-implanted region 1032. The second type semiconductor region 1031 is formed directly below the top contact 02. The ion-implanted region 1032 is formed around the second type semiconductor region 1031. In some embodiments, the resistance of the ion-implanted region 1032 is greater than the resistance of the second type semiconductor region 1031. The ion-implanted region 1032 is formed via an additional ion implantation process. In some embodiments, the center of the top contact 02 is aligned with the center of the second type semiconductor region 1031 along an axis perpendicular to the upper surface of the second type semiconductor region 1031. In some further embodiments, the diameter of the ion-implanted region 1032 is greater than or equal to the diameter of the top contact 02, and the diameter of the second semiconductor region 1031 is greater than or equal to the diameter of the top contact 02. In some embodiments, the diameter of the second semiconductor region 1031 is less than or equal to three times the diameter of the top contact 02. In some embodiments, the conductivity type of the ion implantation region 1032 is the same as that of the second type semiconductor region 1031. In some further embodiments, the ion implantation region 1032 includes at least one type of implanted ion. In some embodiments, the implanted ion is selected from one or more of the following ions: hydrogen, nitrogen, fluorine, oxygen, carbon, argon, phosphorus, boron, silicon, sulfur, arsenic, chlorine, and metal ions. The metal ion is selected from one or more of the following ions: zinc, copper, indium, aluminum, nickel, titanium, magnesium, chromium, gallium, tin, antimony, tellurium, tungsten, tantalum, germanium, molybdenum, and platinum. In some further embodiments, the diameter of the ion implantation region 1032 is larger than the diameter of the second semiconductor region 1031. In some embodiments, the diameter of the ion implantation region 1032 is more than twice that of the second semiconductor region 1031. Here, the diameter of the ion implantation region 1032 ranges from 100 nm to 1200 nm; and the diameter of the top contact O2 ranges from 20 nm to 50 nm. The thickness of the second type semiconductor region 1031 is greater than or equal to the thickness of the ion implantation region 1032. In some embodiments, the thickness of the second type semiconductor region 1031 ranges from 100 nm to 200 nm, and the thickness of the ion implantation region 1032 ranges from 100 nm to 150 nm.

[0042] Still referencing Figure 1 In some embodiments, the microLED structure further includes a top conductor layer 04 covering the top surface of the second type semiconductor layer 103 and the top contact 02. The top conductor layer 04 is transparent and conductive. In some embodiments, the top conductor layer 04 includes at least one of indium tin oxide (ITO) and fluorine-doped tin oxide (FTO).

[0043] In some embodiments, a bottom contact 03 is formed on the bottom surface of the first type semiconductor layer 101. The conductivity type of the bottom contact 03 is the same as that of the first type semiconductor layer 101. For example, if the first type semiconductor layer 101 is P-type, then the bottom contact 03 is also P-type. Similarly, if the first type semiconductor layer 101 is N-type, then the bottom contact 03 is also N-type. In some embodiments, light is emitted from the top surface of the mesa structure 01. For this purpose, the diameter of the bottom contact 03 is made larger than the diameter of the top contact 02, and the diameter of the top contact 02 is made as small as possible, such that the top contact 02 appears as a point on the top surface of the second type semiconductor layer 103. In some embodiments, the diameter of the bottom contact 03 is equal to or smaller than the diameter of the top contact 02. In some embodiments, the bottom contact 03 is configured to connect to a bottom electrode (such as a contact pad in an IC backplane). In some embodiments, the diameter of the bottom contact 03 ranges from 20 nm to 1 μm. In some embodiments, the diameter of the bottom contact 03 ranges from 800 nm to 1 μm. In some embodiments, the center of the bottom contact 03 is aligned with the center of the top contact 02 along an axis perpendicular to the upper surface of the second type semiconductor region 1031. In some embodiments, the centers of the bottom contact 03, the top contact 02, and the second type semiconductor region 1031 are all aligned along an axis perpendicular to the upper surface of the second type semiconductor region 1031. In some embodiments, the material of the bottom contact 03 comprises a transparent conductive material. In some further embodiments, the material of the bottom contact 03 comprises ITO or FTO. In some embodiments, the bottom contact 03 is opaque, and the material of the bottom contact is a conductive metal. In some embodiments, the material of the bottom contact comprises at least one of the following elements: Au, Zn, Be, Cr, Ni, Ti, Ag, and Pt.

[0044] Figure 2 This is a flowchart of a method for manufacturing a micro-LED structure consistent with the embodiments disclosed herein. Figures 3 to 12 This is a schematic illustration of what is used to implement Figure 2 A cross-sectional diagram of the steps of the method. Figures 3 to 12 Mirror 1011 is not shown in the image. Figure 1 (As shown in the image), the omission is for the purpose of better illustrating the manufacturing method. This omission should not limit or affect the scope of this disclosure. It is conceivable that the disclosed manufacturing method is not limited to... Figures 3 to 12 The specific micro-LED structure shown. In conjunction with... Figures 3 to 12 In some consistent implementations, methods for manufacturing the aforementioned microLED structures are described herein.

[0045] In Figure 3In some consistent embodiments, an epitaxial structure is provided. The epitaxial structure includes a first type semiconductor layer 101, a light-emitting layer 102, and a second type semiconductor layer 103. In some embodiments, the first type semiconductor layer 101, the light-emitting layer 102, and the second type semiconductor layer 103 are arranged in a top-to-bottom order. In some embodiments, the epitaxial structure can be formed on the substrate 00 using any epitaxial growth process known in the art.

[0046] In Figure 4 In some consistent embodiments, the mesa is formed by etching the epitaxial structure. The mesa is formed by sequentially etching a first type semiconductor layer 101, a light-emitting layer 102, and a second type semiconductor layer 103. In some embodiments, the sidewalls of the mesa are vertical or inclined relative to a horizontal plane (e.g., substrate 00). In some embodiments, the etching process includes a dry etching process. In some embodiments, the etching process includes a plasma etching process.

[0047] In Figure 5 In some consistent embodiments, the bottom contact 03 is deposited on the surface of the first type semiconductor layer 101. The bottom contact 03 is deposited using a chemical vapor deposition (CVD) or physical vapor deposition (PVD) process known in the art. In some further embodiments, a first patterned mask is provided to cover the entire surface of the mesa, wherein a portion of the top of the mesa is exposed during the deposition process. After deposition, the first patterned mask is removed by a chemical etching method.

[0048] In Figures 6 to 10 In some consistent implementations, the top contact 02 is deposited on the second type semiconductor layer 103 to form an ion implantation region 1032. Figure 6 In some consistent implementations, the mesa is inverted to form the mesa structure 01 before the top contact 02 is deposited, and the substrate 00 is removed from the mesa structure 01 by a separation process to expose the top of the mesa structure 01. Figure 6 In some consistent embodiments, the bottom of the second semiconductor layer 103 is positioned as the top surface of the second type of semiconductor layer 103. In conjunction with... Figure 7 In some consistent embodiments, during chemical vapor deposition or physical vapor deposition processes, the top contact 02 is deposited on the top surface of the second type semiconductor layer 103. Figure 7 In some consistent implementations, the area of ​​the top contact 02 is made as small as possible. More specifically, in conjunction with Figure 7 In some further implementations, the top contact 02 is a point.

[0049] In Figures 8 to 11 In some consistent implementations, the ion implantation region 1032 is formed via an ion implantation process. In conjunction with... Figure 8 In some consistent embodiments, a mask M is formed on the second type semiconductor layer 103. More specifically, in some embodiments, a predetermined second type semiconductor region and a predetermined ion implantation region are defined in the second type semiconductor layer 103. In some embodiments, the predetermined second type semiconductor region is below the top contact 02, and the predetermined ion implantation region surrounds the predetermined second type semiconductor region. More specifically, in conjunction with... Figure 7 In some consistent implementations, the predetermined second type semiconductor region is the region between the dashed lines, and the predetermined ion implantation region is the region outside the dashed lines. The predetermined second type semiconductor region is configured to form second type semiconductor region 1031, and the predetermined ion implantation region is configured to form ion implantation region 1032.

[0050] In Figure 9 In some consistent embodiments, the mask M is patterned to expose a predetermined ion implantation region. More specifically, the mask M is patterned using an etching process known in the art. After the etching process, the mask M over the predetermined second-type semiconductor region is retained, and the mask M over the predetermined ion implantation region is removed to expose the predetermined ion implantation region.

[0051] In Figure 10 In some consistent embodiments, ions are implanted into a predetermined ion implantation region. More specifically, in some embodiments, ions are implanted into a second type of semiconductor layer 103 to form an ion implantation region 1032. The ion implantation process is performed using ion implantation technology. Figure 10 In some consistent embodiments, the implanted ion is selected from one or more of hydrogen, nitrogen, fluorine, oxygen, carbon, argon, phosphorus, boron, silicon, sulfur, arsenic, chlorine, and metal ions. In some embodiments, the metal ion is selected from one or more of zinc, copper, indium, aluminum, nickel, titanium, magnesium, chromium, gallium, tin, antimony, tellurium, tungsten, tantalum, germanium, molybdenum, and platinum. More specifically, in some further embodiments, the implantation dose ranges from 10E12 to 10E16.

[0052] In some embodiments, an ion implantation process is performed after the deposition of the top contact 02. In some embodiments, an ion implantation process is performed before the deposition of the top contact 02 to form an ion implantation region 1032, and then the top contact 02 is deposited on a predetermined second type semiconductor region when another mask covers the ion implantation region 1032.

[0053] In Figure 11 In some consistent implementations, the mask M is removed from the mesa structure. In some implementations, the mask M is removed by chemical etching methods known in the art.

[0054] In Figure 12In some consistent embodiments, a top conductive layer 04 is formed on the mesa structure. More specifically, in some embodiments, the top conductive layer 04 is deposited on the second type semiconductor layer 103 and on the top and sidewalls of the top contact 02, covering the exposed top surfaces of the second semiconductor layer 103 and the top contact 02. The deposition of the top conductive layer 04 is performed using chemical vapor deposition methods known in the art.

[0055] In Figure 13 In some consistent embodiments, a microdisplay panel is provided. The microdisplay panel includes a microLED array and an IC backplane 05 formed beneath the microLED array. The microLED array includes a plurality of the aforementioned microLED structures. The microLED structures are electrically coupled or connected to the IC backplane 05. In some embodiments, the length of the entire microLED array does not exceed 5 cm. The length of the backplane is greater than the length of the microLED array. In some embodiments, the length of the backplane is no greater than 6 cm. The area of ​​the microLED array is the effective display area.

[0056] In some implementations, the microLED structure further includes a metal bonding structure. More specifically, the metal bonding structure includes a metal bonding layer or a connection hole. For example, as... Figure 13 As shown, the metal bonding structure is a connection hole 05, and the connection hole 05 is filled with bonding metal. The top side of the connection hole 05 is connected to the bottom contact 03, and the bottom side of the connection hole 05 is connected to the contact pad 09 on the surface of the IC backplane 06. In some embodiments, the top conductive layer 04 in the microdisplay panel covers the entire display panel.

[0057] Still referencing Figure 13 The microdisplay panel further includes a dielectric layer 08. The dielectric layer 08 is formed between adjacent mesa structures 01. The dielectric layer 08 is made of a non-conductive material, thereby electrically isolating adjacent microLEDs. In some embodiments, the dielectric layer material includes at least one of SiO2, Si3N4, Al2O3, AlN, HfO2, TiO2, and ZrO2. In some further embodiments, a reflective structure 07 is formed in the dielectric layer 08 between adjacent mesa structures 01 to avoid crosstalk. In some embodiments, the reflective structure 07 does not contact the mesa structure 01. In some embodiments, the top surface of the reflective structure 07 is aligned with the top surface of the mesa structure 01, and the bottom surface of the reflective structure 07 is aligned with the bottom surface of the mesa structure 01. The cross-sectional structure of the reflective structure 07 can be triangular, rectangular, trapezoidal, or any other shape. In some embodiments, ion implantation regions 1032 are formed in a second type semiconductor layer 103, and the space between adjacent mesa structures 01 can be formed as small as possible. In some implementations, the bottom of the reflective structure 07 extends downwards, below the bottom of the platform structure 01.

[0058] Figure 14 Is with Figure 13 A flowchart of a method for manufacturing a microdisplay panel, consistent with the illustrated implementation. Figures 15 to 29 This is a schematic illustration of what is used to implement Figure 14 A cross-sectional diagram of the steps of the method. Figures 15 to 29 Mirror 1011 is not shown in the image. Figure 13 (As shown in the image), the omission is for the purpose of better illustrating the manufacturing method. This omission should not limit or affect the scope of this disclosure. It is conceivable that the disclosed manufacturing method is not limited to... Figures 15 to 29 The specific micro-LED structure shown. In conjunction with... Figures 15 to 29 In some consistent embodiments, methods for manufacturing the aforementioned microdisplay panel are described herein.

[0059] In Figure 15 In some consistent embodiments, a substrate 00 with an epitaxial structure is provided. More specifically, the epitaxial structure includes a first type semiconductor layer 101, a light-emitting layer 102, and a second type semiconductor layer 103. In some embodiments, the first type semiconductor layer 101, the light-emitting layer 102, and the second type semiconductor layer 103 are arranged in a top-to-bottom order. In some embodiments, the epitaxial structure can be formed on the substrate 00 using any epitaxial growth process known in the art. In some further embodiments, the first type semiconductor layer 101 includes one or more mirrors 1011. The mirrors 1011 are formed on the surface of the first type semiconductor layer 101.

[0060] In Figure 16 In some consistent embodiments, multiple mesa are formed by etching an epitaxial structure. More specifically, the mesa is formed by sequentially etching a first type semiconductor layer 101, a light-emitting layer 102, and a second type semiconductor layer 103. The sidewalls of the mesa are vertical or inclined relative to a horizontal plane (e.g., substrate 00). In some embodiments, the etching process is a dry etching process. In some embodiments, the etching process is a plasma etching process.

[0061] In Figure 17 In some consistent embodiments, the bottom contact 03 is deposited on the surface of the mesa. More specifically, the bottom contact 03 is deposited via a chemical vapor deposition (CVD) process or a conventional physical vapor deposition (PEV) process. In some further embodiments, a first patterned mask is provided to cover the entire surface of the mesa, wherein a portion of the top of the mesa is exposed during the deposition process. In some embodiments, after the deposition process, the first patterned mask is removed by a chemical etching method, thereby forming the bottom contact on the first semiconductor layer 101.

[0062] In Figure 18In some consistent implementations, dielectric layer 08 is deposited on substrate 00. More specifically, dielectric layer 08 is deposited on the top and sidewalls of the mesa and on the bottom contact 03, such that dielectric layer 08 covers the mesa and the bottom contact 08.

[0063] In Figures 19 to 21 In some consistent implementations, interconnect vias are formed in dielectric layer 08. More specifically, in conjunction with... Figure 19 In some consistent embodiments, a hole 051 is first formed in the dielectric layer 08 by etching a dielectric layer 08 on each bottom contact 03 to expose the bottom contact 03. In some embodiments, one bottom contact 03 is coupled to one hole 051. Figure 20 In some consistent embodiments, the hole 051 is filled with bonding metal 05' to form the connection hole 05. More specifically, the bonding metal 05' is also deposited on the top surface of the dielectric layer 08. Figure 21 In some consistent embodiments, the top of the bonding metal 05' is polished to expose the top of the dielectric layer 08, and the connection hole 05 is formed by a planarization process. In some embodiments, the planarization process includes a chemical mechanical polishing process. In some embodiments, the top of the bonding metal 05' is above the dielectric layer 08.

[0064] In Figure 22 In some consistent embodiments, a bonding process is performed between the mesa structure 01 and the IC backplane 06, thereby removing the substrate 00. More specifically, the mesa is first positioned upside down to form the mesa structure 01. In some embodiments, the connection hole 05 is first aligned with the contact pad 09 on the IC backplane 06. In some further embodiments, the bonding metal in the connection hole 05 is bonded to the contact pad 09 on the surface of the IC backplane 06 via a metal bonding process. In some embodiments, the substrate 00 can be removed before or after the bonding process via a substrate separation process known in the art.

[0065] In Figures 23 to 25 In some consistent implementations, a top contact 02 is deposited on the mesa structure 01 to form an ion implantation region 1032. More specifically, in conjunction with Figure 23 Consistent implementation methods, such as Figure 22The bottom of the second semiconductor layer 103 shown is inverted as the top surface of the second type semiconductor layer 103 by inverting the mesa. In some further embodiments, the top contact 02 is deposited on the top surface of the second type semiconductor layer 103 via a chemical vapor deposition (CVD) or physical vapor deposition (PVD) process known in the art. In some embodiments, the area of ​​the top contact 02 is configured to be as small as possible. In some embodiments, the area of ​​the top contact 02 is formed as a dot. In some embodiments, a patterned mask is provided to cover the mesa structure 01 by exposing a portion of the surface of the second semiconductor layer 103. In some embodiments, the patterned mask is a patterned photoresist. In some further embodiments, material may be deposited on the surface of the second semiconductor layer 103 to form the top contact 02.

[0066] In some embodiments consistent with this disclosure, the ion implantation region 1032 is formed via an ion implantation process. More specifically, the ion implantation process is further described below.

[0067] In Figure 24 In some consistent embodiments, a mask M is formed on the second type semiconductor layer 103 to define a predetermined second type semiconductor region and a predetermined ion implantation region within the second type semiconductor layer 103. More specifically, in some embodiments, in each mesa structure 01, the predetermined second type semiconductor region is located below the top contact, such as... Figure 24 The area shown is between the dashed lines. In some embodiments, the predetermined ion implantation region surrounds a respective predetermined second-type semiconductor region, such as... Figure 24 The area outside the dashed line is shown. A preset second type semiconductor region is set to form the second type semiconductor region 1031, and a preset ion implantation region is set to form the ion implantation region 1032.

[0068] In Figure 25 In some consistent embodiments, the mask M is patterned to expose a predetermined ion implantation region. More specifically, in some embodiments, the mask M is patterned by an etching process. In some embodiments, after the etching process, the mask M over the predetermined second-type semiconductor region is retained, and the mask M over the predetermined ion implantation region is removed to expose the predetermined ion implantation region.

[0069] In Figure 26In some consistent embodiments, ions are implanted into a predetermined ion implantation region. More specifically, in some embodiments, ions are implanted into a second type semiconductor layer 103 to form an ion implantation region 1032. In some embodiments, the ion implantation process is performed using conventional ion implantation techniques known to those skilled in the art. In some embodiments, the implanted ions include at least one of the following ions: hydrogen, nitrogen, fluorine, oxygen, carbon, argon, phosphorus, boron, silicon, sulfur, arsenic, chlorine, and metal ions. In some further embodiments, the metal ions include at least one of zinc, copper, indium, aluminum, nickel, titanium, magnesium, chromium, gallium, tin, antimony, tellurium, tungsten, tantalum, germanium, molybdenum, and platinum. In some embodiments, the implantation dose ranges from 10E12 to 10E16.

[0070] In Figure 27 In some consistent embodiments, the mask M is removed via a chemical etching process known in the art. In some embodiments, an ion implantation process is performed after the deposition of the top contact 02. In some embodiments, an ion implantation process is first performed to form an ion implantation region 1032 before the deposition of the top contact 02, and then the top contact 02 is deposited on the second type semiconductor region 1031 when another mask covers the ion implantation region 1032.

[0071] In Figure 28 In some consistent embodiments, the reflective structure 07 is formed in the dielectric layer 08 and between adjacent mesa structures 01. In some embodiments, the reflective structure 07 is formed by etching trenches in the dielectric layer 08 between adjacent mesa structures 01 using a protective mask. In some embodiments, a protective mask is formed on the mesa structures 01 and the dielectric layer 08, exposing the trench areas to protect the mesa structures 01 from unwanted etching. In some embodiments, a reflective material is filled into the trenches to form the reflective structure 07 between adjacent mesa structures 01. More specifically, during the filling of the reflective material, another protective mask is formed on the mesa structures 01 and the dielectric layer 08, exposing the trenches. In some embodiments, after the aforementioned trenches are etched, the protective mask is etched to a certain thickness, and a portion of the protective mask is left during the filling of the reflective material to protect unwanted filling areas, thus eliminating the need for an additional protective mask. In some embodiments, ion implantation regions 1032 are formed in a second type semiconductor layer 103, and reflective structures 07 are formed between adjacent mesa structures 01, with the space between adjacent mesa structures 01 configured to be as small as possible. In some embodiments, the bottom of the reflective structure 07 extends downward below the bottom of the mesa structure 01.

[0072] In Figure 29In some consistent embodiments, a top conductive layer 04 is formed on the mesa structure 01 and the dielectric layer 08. More specifically, the top conductive layer 08 is deposited on the second type semiconductor layer 103, the top and sidewalls of the top contact 02, and the dielectric layer 08, covering the exposed top surfaces of the second semiconductor layer 103, the top contact 02, and the dielectric layer 08. The deposition of the top conductive layer 04 is performed using chemical vapor deposition methods known to those skilled in the art.

[0073] Other embodiments of the invention will be apparent to those skilled in the art in light of the description and practice of the invention disclosed herein. The description and examples are intended to be illustrative only, and the true scope and spirit of the invention are indicated by the following claims.

Claims

1. A miniature light-emitting diode (LED) structure, comprising: A mezzanine structure and a top conductive layer, wherein the mezzanine structure includes: A first semiconductor layer having a first conductivity type; A light-emitting layer formed on the first semiconductor layer; and A second semiconductor layer is formed on the light-emitting layer, the second semiconductor layer having a second conductivity type different from the first conductivity type; The second semiconductor layer further includes: Semiconductor region; and An ion-implanted region, surrounding only the semiconductor region, has a higher resistance than the semiconductor region. The ions used in the ion-implanted region are selected from one or more of the following: hydrogen, nitrogen, fluorine, oxygen, carbon, argon, phosphorus, boron, silicon, sulfur, arsenic, chlorine, and metal ions. The top conductive layer is formed on the ion implantation region and the semiconductor region, and is in contact with the ion implantation region. The thickness of the first semiconductor layer is greater than the thickness of the second semiconductor layer. The thickness of the semiconductor region is greater than or equal to the thickness of the ion-implanted region, the diameter of the semiconductor region is greater than or equal to the diameter of the top contact, and the diameter of the ion-implanted region is equal to or greater than the diameter of the semiconductor region. Wherein, the diameter of the semiconductor region is less than or equal to three times the diameter of the top contact, and the diameter of the ion implantation region is greater than twice that of the semiconductor region.

2. The micro light-emitting diode (LED) structure according to claim 1, further comprising: A top contact formed on the upper surface of the second semiconductor layer, the top contact having the second conductivity type; as well as A bottom contact is formed on the bottom surface of the first semiconductor layer, the bottom contact having the first conductivity type.

3. The micro light-emitting diode (LED) structure according to claim 2, wherein, The centers of the bottom contact, the top contact, and the semiconductor region are aligned along the same axis perpendicular to the upper surface of the second semiconductor layer, and The diameter of the ion implantation region is greater than or equal to the diameter of the top contact.

4. The micro light-emitting diode (LED) structure according to claim 1, wherein, The metal ion is selected from one or more of zinc, copper, indium, aluminum, nickel, titanium, magnesium, chromium, gallium, tin, antimony, tellurium, tungsten, tantalum, germanium, molybdenum, and platinum.

5. The micro light-emitting diode (LED) structure according to claim 1, wherein, The thickness of the first semiconductor layer ranges from 700 nm to 2 μm, and the thickness of the second semiconductor layer ranges from 100 nm to 200 nm.

6. The micro light-emitting diode (LED) structure according to claim 1, wherein: The thickness of the semiconductor region ranges from 100 nm to 200 nm. The thickness of the ion implantation region ranges from 100 nm to 150 nm. The diameter of the ion implantation region ranges from 100 nm to 1200 nm, and The diameter of the top contact ranges from 20 nm to 50 nm.

7. The micro light-emitting diode (LED) structure according to claim 1, wherein, The thickness of the light-emitting layer is less than the thickness of the first semiconductor layer.

8. The micro light-emitting diode (LED) structure according to claim 1, wherein, The light-emitting layer is formed by a quantum well layer located between the first semiconductor layer and the second semiconductor layer.

9. The micro light-emitting diode (LED) structure according to claim 8, wherein, The thickness of the quantum well layer is less than or equal to 30 nm.

10. The micro light-emitting diode (LED) structure according to claim 8, wherein, The quantum well layer comprises three or fewer pairs of quantum wells.

11. The micro light-emitting diode (LED) structure according to claim 2, further comprising: A top conductive layer is formed on the second semiconductor layer and the top contact.

12. The micro light-emitting diode (LED) structure according to claim 1, further comprising: A first reflector is formed on the bottom surface of the first semiconductor layer.

13. The micro light-emitting diode (LED) structure according to claim 12, further comprising: The second reflector is formed inside the first semiconductor layer.

14. A miniature display panel, comprising: A miniature light-emitting diode (LED) array, comprising: A first micro-light-emitting diode (LED) structure, wherein the first micro-light-emitting diode (LED) structure is the micro-light-emitting diode (LED) structure according to claim 1; and The integrated circuit (IC) backplane formed beneath the first micro-LED structure. The first micro light-emitting diode (LED) structure is electrically coupled to the backplane of the integrated circuit (IC).

15. The microdisplay panel according to claim 14, wherein, The first miniature light-emitting diode (LED) structure further includes: The bottom contacts formed on the bottom surface of the first semiconductor layer, and Metal bonding structure formed on the bottom surface of the bottom contact.

16. The microdisplay panel of claim 15, further comprising a top conductive layer formed on the second semiconductor layer and configured to cover the microdisplay panel. in, The metal bonding structure includes a connection hole or a metal bonding layer, a first side of the metal bonding structure is connected to the bottom contact, and a second side of the metal bonding structure is connected to the backplane of the integrated circuit (IC).

17. The microdisplay panel according to claim 15, further comprising: The second miniature light-emitting diode (LED) structure is... The micro light-emitting diode (LED) structure according to claim 1; and dielectric layer, The second micro-LED structure is located adjacent to the first micro-LED structure, and The dielectric layer is non-conductive and is formed between the mesa structures of the first and second micro-light-emitting diode (LED) structures.

18. The microdisplay panel according to claim 17, wherein, The dielectric layer is made of at least one of SiO2, Si3N4, Al2O3, AlN, HfO2, TiO2 and ZrO2.

19. The microdisplay panel of claim 17, further comprising a reflective structure formed in the dielectric layer and between the mesa structures of the first and second microlight-emitting diode (LED) structures, wherein, The reflective structure does not contact the platform structure.

20. The microdisplay panel according to claim 19, wherein, The reflective structure has: The top surface aligned with the top surface of the platform structure, and The bottom surface is aligned with the bottom surface of the platform structure.

Images