A Chip-based Synchronous Phase Measurement Method

Abstract

The present invention discloses a chip-based synchronous phasor measurement method, which belongs to the field of phasor measurement technology and includes the following steps: Step 1, collecting the power signal of the target chip, and decomposing the collected power signal into the superposition of several single-frequency signals from the frequency domain perspective according to different conditions of the power signal, including static offset and dynamic modulation; Step 2, designing a nonlinear FIR filter; Step 3, inputting the signal decomposed in Step 1 into the nonlinear FIR filter designed in Step 2 to extract and measure the chip signal. The present invention proposes a chip-based synchronous phasor measurement method, which extracts the positive frequency component of the fundamental signal in the passband through the designed nonlinear FIR filter, and simultaneously filters out the interference signals in the stopband, so as to more accurately extract and measure the chip signal.

Description

Technical Field

[0001] The invention belongs to the technical field of phasor measurement, and in particular relates to a chip-based synchronous phasor measurement method. Background Art

[0002] The existing measurement devices are large in size and high in cost, making it difficult to achieve full coverage of the distribution network: the distribution network has a wide coverage and extremely complex topology, and a large number of measurement devices can achieve comprehensive observability, adjustability, and controllability, which puts forward low-cost requirements for the devices. In order to reduce the measurement cost, the concept of algorithm chipization has been widely mentioned in the power system in recent years. Algorithm chipization refers to shaping and solidifying the algorithm on the FPGA chip, so as to achieve the purpose of reducing costs and facilitating chip production. This requires that the algorithm should not be too complex while having high accuracy. After a large number of distributed new energy sources are connected to the distribution network, its operating environment and operating mode are extremely complex. The harmonic and interharmonic content in the power signal is high, and it is often in various static and dynamic changes, such as frequency offset, signal modulation, frequency ramp, etc., which affect the measurement of the fundamental signal. Therefore, it is urgent to study a chip measurement algorithm suitable for the complex environment of the distribution network side to achieve effective monitoring of the distribution system.

[0003] In recent years, domestic and foreign scholars have conducted a lot of research on synchronized phasor measurement algorithms, which can be mainly divided into frequency domain algorithms based on discrete Fourier transform (DFT) and time domain algorithms based on Taylor-weighted least squares (TWLS) method.

[0004] 1) The traditional DFT algorithm has small sidelobe attenuation and serious spectrum leakage, and has poor suppression ability for interharmonics. When the frequency is offset, the suppression ability for harmonics is also poor. Therefore, the windowed DFT algorithm is used instead of the DFT algorithm. Commonly used window functions include Hanning window, Taylor window, flat-top window, etc. However, the above window coefficients have problems such as large passband attenuation and inability to effectively suppress the fundamental negative frequency component, resulting in poor measurement accuracy under static and dynamic conditions. Therefore, scholars at home and abroad have successively proposed improved methods such as interpolated DFT (IpDFT), enhanced interpolated DFT (e-IpDFT) and iterative interpolated DFT (i-IpDFT). Specifically, the IpDFT algorithm compensates for the fence loss caused by the main lobe of the DFT algorithm, and proposes a 3-cycle minimum sidelobe horizontal window suitable for the IpDFT algorithm, which improves the measurement accuracy when static interference is superimposed on the signal and frequency offset occurs, but the error is still large when amplitude and phase angle oscillation occurs. The e-IpDFT algorithm compensates for the spectrum interference caused by the fundamental negative frequency component through an iterative method, but the algorithm does not eliminate the interference of harmonic and interharmonic spectra on the fundamental frequency. i-IpDFT eliminates the influence of interference components on the fundamental phasor by reconstructing harmonic and interharmonic signals on the basis of e-IpDFT, but the actual signal is complex and it is difficult to accurately reconstruct the interference signal. At the same time, the dynamic accuracy of this method is poor and does not meet the test calibration requirements. Therefore, the above DFT-based algorithm is difficult to apply to the benchmark PMU.

[0005] 2) The essence of the time domain TWLS method is to use Taylor series to approximate the dynamically changing amplitude and phase angle, such as establishing a dynamic phasor model. However, in the actual distribution network system, there are many dynamic processes of the signal and it is easily interfered by harmonics / interharmonics, so the phasor model is difficult to determine. There are three main types of improvement methods: 1) The signal model includes harmonics and interharmonics, and the compressed sensing method is used to determine the position of harmonics and interharmonics in the frequency domain. However, the iterative process in the compressed sensing algorithm is computationally intensive and takes a long time to calculate, making it difficult to achieve real-time measurement of the distribution network; 2) A detector is used to identify static and dynamic signals. For static signals, a long time window is used to increase anti-interference ability, and for dynamic signals, a short time window is used to ensure dynamic performance. However, the trend of power electronics in distribution network systems is constantly increasing, and the harmonic / interharmonic content in the signal is high, so this method may fail; 3) After analysis, the second harmonic has the greatest impact on the phasor accuracy. Therefore, as long as the parameters of the second harmonic are estimated, the second harmonic signal is reconstructed and removed from the original signal, the anti-interference ability can be guaranteed. However, this method is difficult to effectively eliminate the interharmonic components within the second harmonic.

[0006] In summary, the current traditional synchronized phasor measurement method applied to the distribution network after a high proportion of new energy access will have the following problems: 1) poor dynamic performance; 2) inability to effectively filter out harmonics / interharmonics; 3) too long response time, etc. Therefore, it is urgent to design a chip-based synchronized phasor measurement method suitable for this scenario to provide a reliable data basis for the protection and control of the distribution network. Summary of the invention

[0007] The purpose of the present invention is to provide a chip-based synchronous phasor measurement method to solve the problems of poor dynamic performance, inability to effectively filter out harmonics / interharmonics and long response time in the prior art.

[0008] To achieve the above object, the present invention provides a chip-based synchronized phasor measurement method, comprising the following steps:

[0009] Step 1: Collect the power signal of the target chip, and decompose the collected power signal into the superposition of several single-frequency signals from the perspective of frequency domain according to different conditions of the power signal, including static offset and dynamic modulation;

[0010] Step 2: Design a nonlinear FIR filter;

[0011] Step 3, input the signal decomposed in step 1 into the nonlinear FIR filter designed in step 2 to extract and measure the chip signal.

[0012] Preferably, in step 1, in the case of dynamic modulation, the process of decomposing the collected power signal x(t) is as follows:

[0013] S11A, the collected power signal is expressed by amplitude modulation as follows:

[0014]

[0015] In the formula, λ1 is the modulation amplitude, f1 is the modulation frequency, and X m represents the amplitude, f0 represents the fundamental frequency, represents the initial phase angle;

[0016] S12A, decompose the amplitude modulated signal, the specific expression is as follows:

[0017]

[0018] In the formula, x1(t) represents the base frequency component, x2(t) represents the first interference component, and x3(t) represents the second interference component. The base frequency component and the interference component are decomposed into positive frequency component and negative frequency component according to the Euler formula. The specific expressions are as follows:

[0019]

[0020] S13A, reference fundamental steady-state signal and corresponding synchronization vector, the decomposed amplitude modulation signal is decomposed twice by Euler formula, and the specific expression is as follows:

[0021] The fundamental steady-state signal is expressed as:

[0022]

[0023] The corresponding synchronized phasor for:

[0024]

[0025] The result of the second decomposition is:

[0026]

[0027] Preferably, in step 1, in the case of static offset, the expression for decomposing the collected power signal x′(t) is as follows:

[0028] S11B, the collected power signal is expressed by amplitude modulation as follows:

[0029]

[0030] S12B. Decompose x'(t) according to Euler's formula. The specific expression is as follows:

[0031]

[0032] Preferably, the specific process of designing the nonlinear FIR filter in step 2 is as follows:

[0033] S21. Design nonlinear FIR filter parameters. Based on the nonlinear error mathematical model and the absolute value inequality, decompose the measurement error. The specific expression is as follows:

[0034] The mathematical model of nonlinear error is:

[0035] E(ω)=|E(δ1)+E(δ2)|≤E l

[0036] Where E(ω) is the filter measurement error, E l To measure the on-site error requirements, E(δ1) is the error caused by the passband gain δ1, and E(δ2) is the error caused by the stopband attenuation δ2;

[0037] According to the absolute value inequality, the specific expression for decomposing the measurement error is as follows:

[0038] E(ω)≤|E(δ1)|+|E(δ2)|≤E l

[0039] |E(δ1)|≤E lpass ,|E(δ2)|≤E lstop

[0040] In the formula, E lpass is the passband error limit, E lstop is the stopband error limit, and under static offset, E lpass +E lstop =E l / 4, dynamic modulation E lpass +E lstop =E l / 2;

[0041] According to the decomposed measurement error and mathematical derivation, the function model of passband gain δ1 and stopband attenuation δ2 is obtained. The specific expression is as follows:

[0042] The function model of the passband gain δ1 is:

[0043]

[0044] The function model of stopband attenuation δ2 is:

[0045]

[0046] Among them, AE lpass Indicates the passband amplitude error requirement, PE lpass Indicates the passband phase error requirement, FE lpass Represents the passband frequency error requirement, RFE lpass Indicates the passband frequency change rate error requirement, AE lstop Indicates the stopband amplitude error requirement, k i Indicates the ratio of the interference component amplitude to the fundamental component, f i Indicates the frequency of any interference component, PE lstop Indicates the stopband phase angle error requirement, FE lstop represents the stopband frequency error requirement, η i =2 π (f i -f0), RFE lstop Indicates the stopband frequency change rate error requirement, k a represents the amplitude of the amplitude modulated signal, f m represents the modulation frequency;

[0047] S22, solving the coefficient of filter stopband attenuation by a forward-backward iterative method;

[0048] S23, combining the parameters and coefficients designed in S21 and S22 to obtain a nonlinear FIR filter.

[0049] Preferably, in S22, the parameters of the filter stopband attenuation are solved by an iterative method of forward pushback, and the specific process is as follows:

[0050] S221. Assuming that in the initial design conditions, the influence of the phase function in the stopband attenuation is the same as that in the passband gain, the time scale is moved to eliminate the influence of the phase function in the stopband attenuation, and θ(f i )=0, the design condition at this time is specifically expressed as:

[0051]

[0052] Among them, δ 20 represents θ(f i )=0 when the stopband gain;

[0053] S222, design the nonlinear FIR filter coefficients based on the maximum error minimization criterion, and find the filter coefficient at the interference signal frequency f i The phase function θ0(f i ), the specific process of designing the nonlinear FIR filter coefficients is as follows:

[0054] Assume that the nonlinear phase FIR filter coefficient is h d (i), is a set of complex number series, then its frequency response H(ω,h) is:

[0055] H(ω,h)=e T (ω)h d (i)

[0056] in,

[0057] e T (ω)=[1,e -j1ω ,···,e -j(N-1)ω ]

[0058] h=[h(0),h(1),···,h(N-1)]

[0059] Approximate H(ω,h) to the ideal filter frequency response H d (ω), the error function is:

[0060] ε(ω)|=|H(ω,h)-H d (ω)|

[0061] At this time, the constraints on the filter coefficients are expressed as:

[0062]

[0063] In the formula, e T (ω) represents the phase function, [ω0-ω P,ω0+ω P ] represents the passband near the frequency center, t0 is the delay requirement for the algorithm, ||E(ω)|| represents the error norm, W(ω) represents the weighting coefficient, ε(ω) represents the error function, and ξ represents the accuracy requirement;

[0064] S223, the obtained phase function θ0(f i ) is substituted into the stopband attenuation function model, and the second stopband error mathematical model is calculated to obtain the new stopband attenuation δ 21 , repeat step S222 and get the new phase function θ1(f i ), forming an iterative process, until the passband error and stopband error of the designed nonlinear FIR filter meet the accuracy requirements and jump out of the loop.

[0065] Preferably, the specific expression for extracting and measuring the chip signal through the nonlinear FIR filter in step 3 is as follows:

[0066]

[0067] Where N is the filter order, z(k) is the time domain form of the phasor spectrum extracted after the signal is filtered by the FIR filter, h(i) represents the filter coefficient, and x(ki) represents the sampling value.

[0068] Therefore, the present invention adopts the above-mentioned chip-based synchronized phasor measurement method, which has the following beneficial effects:

[0069] (1) Based on the idea of ​​frequency band extraction, the complex signal is decomposed into the positive frequency component of the fundamental signal in the passband and the interference signal in the stopband, so that the positive frequency component of the fundamental signal in the passband can be extracted through the filter, while the interference signals in the stopband can be filtered out;

[0070] (2) The response time of the algorithm is reduced. A nonlinear FIR filter is used as the filter for signal extraction. Under the premise of controlling the filter group delay, an error function is constructed in the complex domain according to the maximum error minimization criterion. By continuously iteratively approximating the ideal filter parameters, the nonlinear FIR filter parameters within the error requirement range are obtained, so that the chip signal can be extracted and measured more accurately.

[0071] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] Figure 1 It is an overall flow chart of a chip-based synchronized phasor measurement method of the present invention;

[0073] Figure 2 This is a principle diagram of phasor measurement based on frequency band extraction according to an embodiment of the present invention;

[0074] Figure 3 This is a schematic diagram of the maximum error minimization criterion according to an embodiment of the present invention;

[0075] Figure 4 Graphs showing the amplitude-frequency characteristics and group delay of a low-delay FIR filter according to an embodiment of the present invention; wherein (a) is a graph showing the amplitude-frequency characteristics of a low-delay FIR filter, and (b) is a graph showing the group delay of a low-delay FIR filter;

[0076] Figure 5 Graphs showing the error in measuring the baseband signal according to an embodiment of the present invention; wherein (a) is a graph showing the total phasor error in measuring the baseband signal, and (b) is a graph showing the frequency error in measuring the baseband signal;

[0077] Figure 6 This is a framework diagram of a PMU device based on FPGA according to an embodiment of the present invention;

[0078] Figure 7 This is a diagram for verifying the algorithm experiment based on FPGA chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0079] The following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0080] See also Figure 1-7 , a chip-based synchronized phasor measurement method, comprising the following steps:

[0081] Step 1: Collect the power signal of the target chip, and decompose the collected power signal into the superposition of several single-frequency signals from the perspective of frequency domain according to different conditions of the power signal, including static offset and dynamic modulation;

[0082] In the case of dynamic modulation, the process of decomposing the collected power signal x(t) is as follows:

[0083] S11A, the collected power signal is expressed by amplitude modulation as follows:

[0084]

[0085] In the formula, λ1 is the modulation amplitude, f1 is the modulation frequency, and X m represents the amplitude, f0 represents the fundamental frequency, represents the initial phase angle;

[0086] S12A, decompose the amplitude modulated signal, the specific expression is as follows:

[0087]

[0088] In the formula, x1(t) represents the base frequency component, x2(t) represents the first interference component, and x3(t) represents the second interference component. The base frequency component and the interference component are decomposed into positive frequency component and negative frequency component according to the Euler formula. The specific expressions are as follows:

[0089]

[0090] S13A, reference fundamental steady-state signal and corresponding synchronization vector, the decomposed amplitude modulation signal is decomposed twice by Euler formula, and the specific expression is as follows:

[0091] The fundamental steady-state signal is expressed as:

[0092]

[0093] The corresponding synchronized phasor for:

[0094]

[0095] The result of the second decomposition is:

[0096]

[0097] In the case of static offset, the expression for decomposing the collected power signal x′(t) is as follows:

[0098] S11B, the collected power signal is expressed by amplitude modulation as follows:

[0099]

[0100] S12B. Decompose x'(t) according to Euler's formula. The specific expression is as follows:

[0101]

[0102] Step 2: Design a nonlinear FIR filter. The specific process is as follows:

[0103] S21. Design nonlinear FIR filter parameters. Based on the nonlinear error mathematical model and the absolute value inequality, decompose the measurement error. The specific expression is as follows:

[0104] The mathematical model of nonlinear error is:

[0105] E(ω)=|E(δ1)+E(δ2)|≤E l

[0106] Where E(ω) is the filter measurement error, E l To measure the on-site error requirements, E(δ1) is the error caused by the passband gain δ1, and E(δ2) is the error caused by the stopband attenuation δ2;

[0107] According to the absolute value inequality, the specific expression for decomposing the measurement error is as follows:

[0108] E(ω)≤|E(δ1)|+|E(δ2)|≤E l

[0109] |E(δ1)|≤E lpass ,|E(δ2)|≤E lstop

[0110] In the formula, E lpass is the passband error limit, E lstop is the stopband error limit. To facilitate subsequent analysis, it is assumed that the error caused by the passband and the stopband accounts for the same proportion of the total error. However, in actual applications, there are hardware errors and other reasons, which require a certain margin to be left when designing the algorithm, and E lpass With E lstop The sum of the error should be less than the total error limit. At the same time, the IEEE standard requires a higher accuracy for steady-state signals than for signals under dynamic conditions. Therefore, under static offset, E lpass +E lstop =E l / 4, E under dynamic modulation lpass +E lstop =E l / 2;

[0111] According to the decomposed measurement error and mathematical derivation, the function model of passband gain δ1 and stopband attenuation δ2 is obtained. The specific expression is as follows:

[0112] The function model of the passband gain δ1 is:

[0113]

[0114] The function model of stopband attenuation δ2 is:

[0115]

[0116] Among them, AE lpass Indicates the passband amplitude error requirement, PE lpass Indicates the passband phase error requirement, FE lpass Represents the passband frequency error requirement, RFE lpass Indicates the passband frequency change rate error requirement, AE lstopIndicates the stopband amplitude error requirement, k i Indicates the ratio of the interference component amplitude to the fundamental component, f i Indicates the frequency of any interference component, PE lstop Indicates the stopband phase angle error requirement, FE lstop represents the stopband frequency error requirement, η i =2 π (f i -f0), RFE lstop Indicates the stopband frequency change rate error requirement, k a represents the amplitude of the amplitude modulated signal, f m represents the modulation frequency;

[0117] S22. Solve the coefficient of filter stopband attenuation by an iterative method of forward and backward iteration. The specific process is as follows:

[0118] S221. Assuming that in the initial design conditions, the influence of the phase function in the stopband attenuation is the same as that in the passband gain, the time scale is moved to eliminate the influence of the phase function in the stopband attenuation, and θ(f i )=0, the design condition at this time is specifically expressed as:

[0119]

[0120] Among them, δ 20 represents θ(f i )=0 when the stopband gain;

[0121] S222, design the nonlinear FIR filter coefficients based on the maximum error minimization criterion, and calculate the filter coefficient at the interference signal frequency f i The phase function θ0(f i ), the specific process of designing the nonlinear FIR filter coefficients is as follows:

[0122] Assume that the nonlinear phase FIR filter coefficient is h d (i) is a set of complex number series, then its frequency response H(ω,h) is:

[0123] H(ω,h)=e T (ω)h d (i)

[0124] in,

[0125] e T (ω)=[1,e -j1ω ,···,e -j(N-1)ω ]

[0126] h=[h(0),h(1),···,h(N-1)]

[0127] Approximate H(ω,h) to the ideal filter frequency response H d (ω), the error function is:

[0128] ε(ω)|=|H(ω,h)-H d (ω)|

[0129] At this time, the constraints on the filter coefficients are expressed as:

[0130]

[0131] In the formula, e T (ω) represents the phase function, [ω0-ω P ,ω0+ω P ] represents the passband near the frequency center, t0 is the delay requirement for the algorithm, ||E(ω)|| represents the error norm, W(ω) represents the weighting coefficient, ε(ω) represents the error function, and ξ represents the accuracy requirement;

[0132] S223, the obtained phase function θ0(f i ) is substituted into the stopband attenuation function model, and the second stopband error mathematical model is calculated to obtain the new stopband attenuation δ 21 , repeat step S222 and get the new phase function θ1(f i ), forming an iterative process, until the passband error and stopband error of the designed nonlinear FIR filter meet the accuracy requirements and jump out of the loop.

[0133] S23, combining the parameters and coefficients designed in S21 and S22 to obtain a nonlinear FIR filter.

[0134] Step 3: Input the signal decomposed in step 1 into the nonlinear FIR filter designed in step 2 to extract and measure the chip signal. The specific expression is as follows:

[0135]

[0136] Where N is the filter order, z(k) is the time domain form of the phasor spectrum extracted after the signal is filtered by the FIR filter, h(i) represents the filter coefficient, and x(ki) represents the sampling value.

[0137] Example

[0138] According to IEEE standard IEC / IEEE 60255-118-1:2018, P-type PMU is mainly used for the protection and control of power grids, and its performance requirements are high accuracy under the premise of fast response. The application scenario of this article is a distribution network containing distributed renewable energy. Its algorithm requirements and measurement purposes are consistent with those of P-type PMU. Therefore, this invention is based on the measurement accuracy requirements of P-type PMU in the IEEE standard as a reference for algorithm design and performance indicators. Table 1 lists the P-type PMU test conditions specified by the IEEE standard:

[0139] Table 1 Static and dynamic test conditions

[0140]

[0141]

[0142] A synchronous phasor measurement design example using a nonlinear phase FIR filter is given. In the phasor measurement algorithm, the sampling rate f s =1kHz, F r =100Hz, the passband is 48~52Hz. The filter order is 81 (equivalent to the calculation window length of 4 cycles), and the passband delay design is based on the requirements of the IEEE standard for P-type PMU. The lag time for measuring data reporting is 2 / Fs, that is, 20ms. At this time, compared with the linear FIR filter, the 81-order filter delay should be 40ms, and the calculation delay requirement should be reduced by half. Using the design method proposed in the present invention, the amplitude-frequency response and group delay of the nonlinear FIR filter obtained are as follows: Figure 4 As shown, Figure 4 In Figure (a), the filter has a stopband gain of less than -100dB for the frequency band containing the fundamental negative frequency component, and a stopband gain of less than -60dB for other frequency bands. Figure 4 As shown in Figure (b), the group delay error of the filter is only 0.0311ms. The designed nonlinear FIR filter is used to measure the 50Hz baseband signal, and the total phasor error curve and frequency error curve are shown in Figure 2. Figure 5 As shown in Figure 2, when measuring the ideal baseband signal, the total phasor error is 2.87×10 -4 The frequency error is kept at 8×10- 7 In order to simulate the measurement in the actual environment, the test was carried out under static and dynamic conditions. The test results are shown in Table 2:

[0143] Table 2 The maximum TVE error and frequency and frequency change rate error of the proposed algorithm

[0144]

[0145] In the table, TVE (total vector error) represents the total phasor error, FE (frequency error) represents the frequency measurement error, and RFE (rate of change of frequency error) represents the frequency change rate error. The proposed method not only meets the standard requirements for calculating the delay, but also has an accuracy of about 2-4 orders of magnitude higher than the standard requirements, whether under dynamic conditions or when the signal contains complex harmonics and interharmonics. Therefore, the proposed method has good measurement performance.

[0146] In addition, in order to verify that the method proposed in the present invention can be applied to chip-based measurement devices, a distribution network-side chip-based PMU device framework based on FPGA chips was built. Figure 6 As shown in the figure, FPGA as the main control chip has both control and calculation functions. The FPGA control acquisition module ADC realizes the synchronous acquisition of voltage and current signals through analog filters, and converts the analog signal quantity into digital signal quantity; then it calculates according to the synchronous sampling value, and outputs the fundamental phasor amplitude, frequency, phase angle and other information with time stamp to the external collection unit in combination with the precise time signal provided by the synchronization module. Compared with the traditional distribution network side PMU, this device framework effectively reduces the size of the device, reduces the application of chips in the device, and reduces the cost of the device. At the same time, due to the characteristics of FPGA easy to tape out, the measurement algorithm can be shaped and solidified in the FPGA chip, simplifying the design process and providing a basis for the chipization of the algorithm in the future. The proposed algorithm is tested on the FPGA simulation platform, and the JTAG (Joint Test Action Group) mode of the FPGA chip is used to experimentally verify the internal algorithm of the chip. This mode is an international standard test protocol, which is mainly used for internal chip testing and online debugging of the system. And because FPGA is based on hardware design language and cannot process decimals, the data of the input signal and the filter coefficient are amplified respectively, and the amplification factor is related to the accuracy. In order to ensure the accuracy to four decimal places, the filter coefficient h(i) and the input data x(i) are amplified by 2 through normalization and amplification. 15 with 2 13 , get the integer h that the FPGA can process l (i) and x l (i), the specific expression is as follows:

[0147]

[0148] The designed nonlinear FIR filter coefficients are amplified by the above formula and used as the filter coefficients of the algorithm imported into the FPGA chip. The amplified sample values ​​are measured to obtain the amplitude of the fundamental wave phasor, such as Figure 7As shown, since FPGA is not suitable for processing inverse trigonometric transformation operations, MATLAB is used to process the real and imaginary parts of the phasor output by FPGA to obtain the phasor phase angle, and further obtain the frequency and frequency change rate. The fundamental wave phasor measurement results are shown in Table 3 below:

[0149] Table 3. Fundamental phasor amplitude, phase angle, frequency and frequency change rate measured based on FPGA experimental platform

[0150]

[0151] The measured amplitude was restored to 57.7317, with an error of 2.8×10 -4 %. It can be seen that in the FPGA simulation environment, although the accuracy of the algorithm can still meet the IEEE standard requirements, it is slightly lower than the simulation test. This is related to the rounding of coefficients and input data during the amplification and calculation process, but the algorithm can still meet the measurement accuracy requirements.

[0152] The measurement algorithm in the FPGA is tested under static and dynamic conditions, and the measurement results are shown in Table 4 below:

[0153] Table 4 Accuracy test under static and dynamic conditions based on FPGA experimental platform

[0154]

[0155] After static and dynamic tests, it can be seen that although the experimental results of the measurement algorithm in the FPGA chip are lower than the simulation results, they can still meet the standard requirements, and the measurement accuracy is more than one order of magnitude higher than the IEEE's accuracy requirements for Class P PMU. From this test, it can be seen that the chip-based measurement method proposed in the present invention has high measurement accuracy when measuring on the FPGA chip, which can meet the measurement requirements and verify the feasibility of the device framework and measurement algorithm.

[0156] Therefore, the present invention adopts the above-mentioned chip-based synchronous phasor measurement method, and based on the idea of ​​frequency band extraction, decomposes the complex signal into the positive frequency component of the fundamental signal located in the passband and the interference signal located in the stopband, so as to facilitate the extraction of the positive frequency component of the fundamental signal in the passband through the filter, and filter out the interference signals in the stopband at the same time. In addition, a nonlinear FIR filter is used as the signal extraction filter. Under the premise of controlling the filter group delay, an error function is constructed in the complex domain according to the maximum error minimization criterion. By continuously iteratively approximating the ideal filter parameters, the nonlinear FIR filter parameters within the error requirement range are obtained, so that the chip signal can be extracted and measured more accurately.

[0157] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that they can still modify or replace the technical solution of the present invention with equivalents, and these modifications or equivalent replacements cannot cause the modified technical solution to deviate from the spirit and scope of the technical solution of the present invention.

Claims

1. A chip-based synchronized phasor measurement method, characterized in that: The following steps are involved: Step 1: Collect the power signal of the target chip, and decompose the collected power signal into the superposition of several single-frequency signals from the perspective of frequency domain according to different conditions of the power signal, including static offset and dynamic modulation; Step 2: Design a nonlinear FIR filter; Step 3, inputting the signal decomposed in step 1 into the nonlinear FIR filter designed in step 2 to extract and measure the chip signal; The specific process of designing the nonlinear FIR filter in step 2 is as follows: S21. Design nonlinear FIR filter parameters. Based on the nonlinear error mathematical model and the absolute value inequality, decompose the measurement error. The specific expression is as follows: The mathematical model of nonlinear error is: In the formula, is the filter measurement error, To measure the on-site error requirements, The passband gain The error caused by The stopband attenuation The error caused by According to the absolute value inequality, the specific expression for decomposing the measurement error is as follows: In the formula, is the passband error limit, is the stopband error limit, and under static offset, , under dynamic modulation ; According to the decomposed measurement error and mathematical derivation, the passband gain is obtained Stopband attenuation The function model is as follows: Passband gain The function model is: Stopband Attenuation The function model is: in, represents the passband amplitude error requirement, represents the passband phase angle error requirement, represents the passband frequency error requirement, It represents the passband frequency change rate error requirement, represents the stopband amplitude error requirement, It indicates the ratio of the interference component amplitude to the fundamental component. represents the frequency of any interference component, represents the stopband phase angle error requirement, represents the stopband frequency error requirement, , It represents the error requirement of the stopband frequency change rate, represents the amplitude of the amplitude modulated signal, represents the modulation frequency; S22, solving the coefficient of filter stopband attenuation by a forward-backward iterative method; S23, combining the parameters and coefficients designed in S21 and S22 to obtain a nonlinear FIR filter.

2. A chip-based synchronized phasor measurement method according to claim 1, characterized in that: In step 1, under dynamic modulation, the collected power signal The decomposition process is as follows: S11A, the collected power signal is expressed by amplitude modulation as follows: In the formula, is the modulation amplitude, is the modulation frequency, represents the amplitude, represents the fundamental frequency, represents the initial phase angle; S12A, decompose the amplitude modulated signal, the specific expression is as follows: In the formula, represents the fundamental frequency component, represents the first interference component, represents the second interference component, wherein both the base frequency component and the interference component are decomposed into positive frequency component and negative frequency component according to the Euler formula. The specific expression is as follows: S13A, reference fundamental steady-state signal and corresponding synchronization vector, the decomposed amplitude modulation signal is decomposed twice by Euler formula, and the specific expression is as follows: The fundamental steady-state signal is expressed as: The corresponding synchronized phasor for: The result of the second decomposition is: 。 3. A chip-based synchronized phasor measurement method according to claim 2, characterized in that: In step 1, in the case of static offset, the collected power signal The decomposed expression is as follows: S11B, the collected power signal is expressed by amplitude modulation as follows: S12B, according to Euler's formula Decompose it, the specific expression is as follows: 。 4. A chip-based synchronized phasor measurement method according to claim 3, characterized in that: In S22, the parameters of the filter stopband attenuation are solved by the forward and backward iterative method. The specific process is as follows: S221. Assuming that in the initial design conditions, the influence of the phase function in the stopband attenuation is the same as the passband gain, the time scale is moved to eliminate the influence of the phase function in the stopband attenuation, let , the design conditions at this time are specifically expressed as: in, express The stopband gain when S222, design the nonlinear FIR filter coefficients based on the maximum error minimization criterion, and find the filter at the interference signal frequency The phase function at , the specific process of designing nonlinear FIR filter coefficients is as follows: Assume that the nonlinear phase FIR filter coefficients are (i) is a set of complex numbers, then its frequency response is for: in, Will Approximate ideal filter frequency response , and the error function is: At this time, the constraints on the filter coefficients are expressed as: In the formula, represents the phase function, [ , ] represents the passband near the frequency center, is the delay requirement for the algorithm, represents the error norm, represents the weighting coefficient, represents the error function, Table accuracy requirements; S223, the obtained phase function Substitute it into the stopband attenuation function model, perform a second calculation of the stopband error mathematical model, and obtain the new stopband attenuation , repeat step S222 to get the new phase function , forming an iterative process until the passband error and stopband error of the designed nonlinear FIR filter meet the accuracy requirements and jump out of the loop.

5. A chip-based synchronized phasor measurement method according to claim 4, characterized in that: The specific expression for extracting and measuring the chip signal through the nonlinear FIR filter in step 3 is as follows: Where N is the filter order, z(k) is the time domain form of the phasor spectrum extracted after the signal is filtered by the FIR filter, represents the filter coefficients, Indicates the sample value.

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