Data consolidation method and storage device

Abstract

The present application provides a data consolidation method and a storage device. The method comprises: configuring a cache physical unit in a memory module; performing a host write operation to store data from a host system; determining whether the available capacity of the cache physical unit is less than a preset capacity; if the available capacity of the cache physical unit is less than the preset capacity, monitoring the data write performance of the host write operation; adjusting a threshold value according to the data write performance, the threshold value representing a threshold condition for triggering a target data consolidation; and if the target data consolidation is triggered, synchronously performing a data consolidation operation on the memory module during the host write operation to move valid data in the memory module to release idle physical units. Thus, the operation stability of the storage device can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to a storage technology field, and in particular, to a data consolidation method and a storage device. BACKGROUND

[0002] In order to improve the data processing capability of the storage device, the storage space can be optimized by performing data consolidation operations such as garbage collection (GC), so as to achieve the purpose of improving the performance and / or response speed of the storage device.

[0003] Generally, garbage collection can be divided into background garbage collection (i.e. garbage collection performed when the storage device is in an idle state) and foreground garbage collection (i.e. garbage collection performed when the storage device is in a busy state). Compared with background garbage collection, foreground garbage collection is often performed synchronously with host write operations, and in practice, its trigger condition is often set to start when an emergency event (such as almost all free blocks in the storage device being used up) is encountered. At this time, almost all free blocks in the storage device are used up, and even if foreground garbage collection is started to force garbage collection, it will still cause the efficiency of host write operations to further decrease.

[0004] Therefore, there is an urgent need for a data consolidation method to solve the above problems. SUMMARY

[0005] The present application provides a data consolidation method and a storage device, which can improve the above problems.

[0006] An embodiment of the present application provides a data consolidation method for a storage device, wherein the storage device comprises a memory module, and the data consolidation method comprises: configuring a cache entity unit in the memory module; performing a host write operation to store data from a host system; determining whether an available capacity of the cache entity unit is less than a preset capacity; if the available capacity is less than the preset capacity, monitoring a data write efficiency of the host write operation; adjusting a threshold value according to the data write efficiency, wherein the threshold value is used to represent a threshold condition for triggering a target data consolidation; and if the target data consolidation is triggered, synchronously performing a data consolidation operation on the memory module during the execution of the host write operation, wherein the data consolidation operation is used to move valid data in the memory module to release free entity units.

[0007] Embodiments of the present application also provide a storage device including a connection interface, a memory module, and a memory controller. The connection interface is configured to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory controller is configured to: configure a cache physical unit in the memory module; perform a host write operation to store data from the host system; determine whether an available capacity of the cache physical unit is less than a preset capacity; if the available capacity is less than the preset capacity, monitor a data write performance of the host write operation; adjust a threshold value according to the data write performance, wherein the threshold value is used to represent a threshold condition for triggering a target data compaction; and if the target data compaction is triggered, synchronize a data compaction operation performed on the memory module during the host write operation, wherein the data compaction operation is used to move valid data in the memory module to release idle physical units.

[0008] Based on the above, after the available capacity of the cache physical unit in the memory module is less than the preset capacity, the data write performance of the host write operation can be monitored, and the threshold value used to represent the threshold condition for triggering the target data compaction can be adjusted according to the data write performance. In this way, the target data compaction can be started early to release new idle physical units gradually without affecting the data write performance of the host write operation as much as possible before triggering an emergency event (e.g., the idle physical units in the memory module are almost exhausted). In this way, the problem of a significant decrease in the performance of the host write operation that is commonly encountered after the storage device is used for a period of time can be improved, and the operation stability of the storage device can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present application;

[0010] Figure 2 is a schematic diagram of a memory controller according to an embodiment of the present application;

[0011] Figure 3 is a schematic diagram of a management memory module according to an embodiment of the present application;

[0012] Figure 4 is a schematic diagram of adjusting a threshold value according to an embodiment of the present application;

[0013] Figure 5 is a schematic diagram of a host write performance in a case where data compaction is not triggered early according to an embodiment of the present application;

[0014] Figure 6is a graph showing host write performance in the case of early triggering data consolidation according to an embodiment of the present application;

[0015] Figure 7 is a flowchart showing a data consolidation method according to an embodiment of the present application. DETAILED DESCRIPTION

[0016] Reference will now be made in detail embodiments of the application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0017] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present application. Please refer to Figure 1 , the data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game console, a server, or a computer installed in a specific carrier (e.g., a vehicle), and the type of the host system 11 is not limited thereto. In addition, the storage device 12 can include a solid state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0018] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 can support embedded Multi-Media Card (eMMC), Universal Flash Storage (UFS), Peripheral Component Interconnect Express (PCI Express), Non-Volatile Memory Express (NVM express), Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), or other types of connection interface standards. Therefore, the storage device 12 can communicate (e.g., exchange signals, instructions, and / or data) with the host system 11 via the connection interface 121.

[0019] The memory module 122 is used to store data. For example, the memory module 122 can include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module can include one or more arrays of memory cells. A memory cell in an array of memory cells stores data in the form of a voltage, also referred to as a threshold voltage. For example, the memory module 122 can include a Single Level Cell (SLC) NAND-type flash memory module, a Multi Level Cell (MLC) NAND-type flash memory module, a Triple Level Cell (TLC) NAND-type flash memory module, a Quad Level Cell (QLC) NAND-type flash memory module, and / or other memory modules having the same or similar characteristics.

[0020] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be considered as a control core of the storage device 12 and is used to control the storage device 12. For example, the memory controller 123 can be used to control or manage the overall or partial operation of the storage device 12. For example, the memory controller 123 can include a Central Processing Unit (CPU), or other programmable general purpose or special purpose microprocessors, Digital Signal Processors (DSPs), programmable controllers, Application Specific Integrated Circuits (ASICs), Programmable Logic Devices (PLDs), or other similar devices, or a combination of such devices. In an embodiment, the memory controller 123 can include a flash memory controller.

[0021] The memory controller 123 can send a command sequence to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write command sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read command sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase command sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can send other types of command sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, and the present invention is not limited thereto. The memory module 122 can receive the command sequence from the memory controller 123 and access the memory cells within the memory module 122 according to the command sequence.

[0022] Figure 2 FIG is a schematic diagram of a memory controller according to an embodiment of the present invention. Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0023] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 can be used to control or manage all or part of the operation of the memory controller 123. For example, the memory control circuit 23 can communicate with the host system 11 via the host interface 21 and access the memory module 122 via the memory interface 22. For example, the memory control circuit 23 may include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is equivalent to the description of the memory controller 123.

[0024] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122. In one embodiment, the memory controller 123 may also include various other types of circuit modules (e.g., power management circuits), and the present invention is not limited thereto.

[0025] Figure 3 FIG is a schematic diagram of a management memory module according to an embodiment of the present invention. Figures 1 to 3The memory module 122 includes a plurality of physical units 301(1)-301(D). Each physical unit includes a plurality of memory cells and is used to store data non-volatilely.

[0026] In an embodiment, one physical unit can include one or more physical erase units. One physical erase unit can include a plurality of physical program units. One physical program unit can include a plurality of physical sectors. For example, a data capacity of one physical sector can be 512 Bytes (B), and one physical program unit can include 8 physical sectors. However, the data capacity of one physical sector and / or the total number of physical sectors included in one physical program unit can be adjusted according to practical requirements, which are not limited in the present application. In an embodiment, one physical program unit can be regarded as one physical page. For example, a data capacity of one physical program unit can be 4 kilobytes (4 KB), which is not limited in the present application.

[0027] In an embodiment, one physical program unit is the minimum unit of synchronously writing data in the memory module 122. For example, when a program operation (also referred to as a write operation or a data write operation) is performed on one physical program unit to write data to the physical program unit, a plurality of memory cells in the physical program unit can be programmed synchronously to store corresponding data. For example, when one physical program unit is programmed, a write voltage can be applied to the physical program unit to change a threshold voltage of at least some memory cells in the physical program unit. The threshold voltage of each memory cell can reflect the bit data stored in the memory cell.

[0028] In an embodiment, a plurality of physical program units in one physical erase unit can be erased synchronously. For example, when an erase operation is performed on one physical erase unit, an erase voltage can be applied to a plurality of physical program units in the physical erase unit to change a threshold voltage of at least some memory cells in the physical program units. By performing the erase operation on one physical erase unit, data stored in the physical erase unit can be cleared.

[0029] In an embodiment, the memory control circuit 23 can logically associate the physical units 301(1)-301(A) to a data area (also referred to as a first type of data area or a cache area) 31 and associate the physical units 301(A+1)-301(B) to a data area (also referred to as a second type of data area) 32. The physical units 301(1)-301(A) in the data area 31 and the physical units 301(A+1)-301(B) in the data area 32 all store data (also referred to as user data) from the host system 11. For example, any physical unit in the data areas 31 and 32 can store valid data and / or invalid data.

[0030] In one embodiment, the memory control circuit 23 can logically associate the physical units 301(B+1)~301(C) and 301(C+1)~301(D) in the spare area 33. For example, the physical units 301(B+1)~301(C) and 301(C+1)~301(D) in the spare area 33 do not store data (e.g., valid data).

[0031] In one embodiment, if a physical unit does not store valid data, the physical unit can be associated with the spare area 33. In addition, a physical unit in the spare area 33 can be erased to clear the data in the physical unit. In one embodiment, a physical unit in the spare area 33 is also referred to as a spare physical unit. In one embodiment, the spare area 33 is also referred to as a free pool.

[0032] In one embodiment, the memory control circuit 23 can configure the physical units 301(B+1)~301(C) as a first type of physical units (also referred to as cache physical units). In one embodiment, the memory control circuit 23 can configure the physical units 301(C+1)~301(D) as a second type of physical units.

[0033] In one embodiment, the speed at which the memory control circuit 23 accesses the first type of physical units (e.g., the speed at which the memory control circuit 23 reads data from the first type of physical units and / or the speed at which the memory control circuit 23 writes data to the first type of physical units) is higher than the speed at which the memory control circuit 23 accesses the second type of physical units (e.g., the speed at which the memory control circuit 23 reads data from the second type of physical units and / or the speed at which the memory control circuit 23 writes data to the second type of physical units).

[0034] In one embodiment, the memory control circuit 23 can program the first type of physical units based on a programming mode (also referred to as a first programming mode) to store data in the first type of physical units. In one embodiment, the memory control circuit 23 can program the second type of physical units based on another programming mode (also referred to as a second programming mode) to store data in the second type of physical units. The first programming mode is different from the second programming mode.

[0035] In one embodiment, the first programming mode can include an SLC mode or a pseudo SLC (pSLC) mode. In one embodiment, the second programming mode can include an MLC, TLC, or QLC mode. It should be noted that the first programming mode and the second programming mode can be set or adjusted according to practical needs, and the present application is not limited thereto.

[0036] In one embodiment, one storage unit in the first type of physical unit can store k bits. In one embodiment, one storage unit in the second type of physical unit can store p bits, and k is less than p. For example, if k is "1", p can be "2", "3", "4", or other integer greater than "1". Alternatively, if k is "2", p can be "3", "4", or other integer greater than "2". The present application does not limit the values of k and p.

[0037] In one embodiment, when data is to be stored, the memory control circuit 23 can select one or more physical units from the free area 33 and instruct the memory module 122 to store the data into the selected physical units. In particular, if the selected physical unit belongs to the first type of physical unit (e.g., one of the physical units 301(B+1) ~ 301(C)), the physical unit can be associated to the data area 31 after the data is stored into the physical unit. However, if the selected physical unit belongs to the second type of physical unit (e.g., one of the physical units 301(C+1) ~ 301(D)), the physical unit can be associated to the data area 32 after the data is stored into the physical unit. In other words, the first type of physical unit (i.e., the physical units 301(1) ~ 301(A) and 301(B+1) ~ 301(C)) can be alternately used between the data area 31 and the free area 33, while the second type of physical unit (i.e., the physical units 301(A+1) ~ 301(B) and 301(C+1) ~ 301(D)) can be alternately used between the data area 32 and the free area 33.

[0038] In one embodiment, the memory control circuit 23 can configure the plurality of logical units 302(1) ~ 302(E) to map the physical units (i.e., the physical units 301(1) ~ 301(A) and 301(A+1) ~ 301(B)) in the data areas 31 and 32. For example, one logical unit can correspond to one logical block address (LBA) or other logical management unit. One logical unit can map to one or more physical units in the data areas 31 and / or 32.

[0039] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the physical unit currently stores valid data. Otherwise, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that the physical unit currently does not store any valid data.

[0040] In one embodiment, the memory control circuit 23 can record the mapping relationship between the logical units and the physical units in a logical-to-physical mapping table. In one embodiment, the memory control circuit 23 can instruct the memory module 122 to perform data read, write or erase operations according to the information in the logical-to-physical mapping table.

[0041] In one embodiment, the memory control circuit 23 can obtain an instruction from the host system 11. For example, the instruction includes a write instruction. The write instruction can instruct to store certain data. In one embodiment, the memory control circuit 23 can perform a write operation (also referred to as a host write operation) according to the instruction to store data from the host system 11. For example, in the host write operation, the memory control circuit 23 can send a sequence of write instructions to the memory module 122 to instruct the memory module 122 to store certain data to certain physical units.

[0042] In one embodiment, in the host write operation, the memory control circuit 23 can instruct the memory module 122 to store data from the host system 11 to the first type of physical units (e.g. the physical units 301(B+1)~301(C) in the memory module 122) first. In this way, the data write efficiency of the host write operation can be improved. However, if the first type of physical units is exhausted (e.g. all the physical units 301(B+1)~301(C) in the memory module 122 are associated to the data area 31), the memory control circuit 23 can instruct the memory module 122 to store data from the host system 11 to the second type of physical units (e.g. the physical units 301C+1)~301(D) in the memory module 122) instead. In this way, although the data write efficiency of the host write operation can be reduced, the normal execution of the host write operation can still be maintained. Figure 3 Figure 3 Figure 3

[0043] In one embodiment, the memory control circuit 23 can determine whether the available capacity of the cache physical units (i.e. the first type of physical units) is less than a preset capacity. For example, the available capacity of the cache physical units refers to the total capacity of the physical units 301(B+1)~301(C) in the current free area 33. In one embodiment, the available capacity of the cache physical units can also be represented by the total number of the physical units 301(B+1)~301(C) in the current free area 33. For example, the total number of the physical units 301(B+1)~301(C) in the current free area 33 can be positively correlated to the available capacity of the cache physical units. That is, if the total number of the physical units 301(B+1)~301(C) in the current free area 33 is more, it indicates that the available capacity of the cache physical units is more.

[0044] ​​​In one embodiment, the memory control circuit 23 can determine whether the cache physical unit has been exhausted (i.e., whether the available capacity of the cache physical unit is zero). If the cache physical unit has been exhausted (i.e., the available capacity of the cache physical unit is zero), the memory control circuit 23 can determine that the available capacity of the cache physical unit is less than the preset capacity. Alternatively, if the cache physical unit has not been exhausted (i.e., the available capacity of the cache physical unit is not zero), the memory control circuit 23 can determine that the available capacity of the cache physical unit is not less than the preset capacity.

[0045] In one embodiment, if the available capacity of the cache physical unit is less than the preset capacity (e.g., the cache physical unit has been exhausted), the memory control circuit 23 can start monitoring the data write performance of the host write operation. For example, the data write performance of the host write operation can reflect the current speed of the storage device 12 for writing data from the host system 11. This writing speed can be represented by how much data is stored to the storage device 12 per unit time.

[0046] It can be seen that, by the method proposed in the above embodiment, first, the usage of the cache physical unit is monitored to determine whether the current cache physical unit is exhausted, and then, according to the determination result, it is determined whether the data write performance of the host write operation needs to be monitored. In this way, the problem of wasting system resources caused by directly monitoring the data write performance of the host every time data is written can be avoided.

[0047] In one embodiment, the memory control circuit 23 can monitor the status of the instruction queue in the buffer memory 24 and evaluate the data write performance of the host write operation according to the detection result. For example, the instruction queue can be used to buffer at least one instruction (e.g., a write instruction) from the host system 11.

[0048] In one embodiment, the status of the instruction queue can reflect the depth of the instruction queue. For example, the depth of the instruction queue can be positively correlated with the total number of instructions currently buffered in the instruction queue. In one embodiment, the memory control circuit 23 can evaluate the data write performance of the host write operation according to the depth of the instruction queue. For example, the depth of the instruction queue can be positively correlated with the data write performance of the host write operation. That is, if the depth of the instruction queue is deeper, it means that there are more instructions from the host system 11 waiting to be executed at present. If there are more instructions from the host system 11 waiting to be executed, it means that the data write performance of the host write operation is higher.

[0049] It should be noted that the present application does not limit the specific implementation of obtaining the data write performance of the host write operation. For example, in one embodiment, the memory control circuit 23 can also evaluate the data write performance of the host write operation by monitoring the data transmission status of the connection interface 121, etc.

[0050] In one embodiment, if the available capacity of the cache entity unit is detected to be less than the preset capacity, the memory control circuit 23 can adjust (e.g., increase or decrease) a threshold value according to the data write performance of the monitored host write operation. In particular, the threshold value can be used to trigger a target data compaction. For example, the target data compaction includes foreground data compaction (also referred to as foreground data compaction). In one embodiment, the threshold value can be used to represent a threshold condition for triggering the target data compaction.

[0051] In one embodiment, the memory control circuit 23 can not adjust the threshold value until the available capacity of the cache entity unit is less than the preset capacity. Thus, the memory control circuit 23 can not monitor the data write performance of the host write operation until the available capacity of the cache entity unit is less than the preset capacity, so as to save system resources.

[0052] In one embodiment, the memory control circuit 23 can continuously monitor whether the total number of free entity units (i.e., entity units in the free area 33) in the memory module 122 is less than the threshold value. If the total number of free entity units in the memory module 122 is less than the threshold value, the memory control circuit 23 can trigger the target data compaction. If the total number of free entity units in the memory module 122 is not less than (e.g., greater than or equal to) the threshold value, the memory control circuit 23 can not trigger the target data compaction.

[0053] In one embodiment, after the target data compaction is triggered, the memory control circuit 23 can perform a data compaction operation on the memory module 122 synchronously during the execution of the host write operation. The data compaction operation is used to move valid data in the memory module 122 to release (new) free entity units. For example, the data compaction operation includes a garbage collection (GC) operation.

[0054] In one embodiment, the target data compaction is not equal to a background data compaction. For example, the target data compaction refers to the data compaction operation performed by the memory control circuit 23 on the memory module 122 synchronously during the execution of the host write operation. In one embodiment, the target data compaction is performed synchronously with the host write operation, so the target data compaction can occupy the bandwidth of the host write operation, thereby affecting the data write performance of the host write operation. In one embodiment, the target data compaction is performed when the storage device 12 is busy.

[0055] On the other hand, the background data consolidation refers to a data consolidation operation performed by the memory control circuit 23 on the memory module 122 during the period when the host write operation is not performed. In one embodiment, the background data consolidation is performed when the storage device 12 is not busy (i.e., is idle) compared to the target data consolidation. Therefore, the background data consolidation does not occupy the bandwidth of the host write operation and does not affect the data write performance of the host write operation.

[0056] As can be seen, the method proposed by the above embodiment determines whether to perform the data consolidation operation at the same time as the host write operation based on the state of the storage device. In this way, the release of the physical units can be performed while avoiding affecting the data write performance.

[0057] In one embodiment, in the data consolidation operation (e.g., the GC operation), the memory control circuit 23 can select at least one physical unit from the data area 31 and / or 32 (e.g., the physical units 301(1)~301(B)) as a source physical unit and select at least one physical unit from the idle area 32 (e.g., the physical units 301(B+1)~301(D)) as a target physical unit. The memory control circuit 23 can collect valid data from the source physical unit and store the collected valid data into the target physical unit (i.e., move the valid data from the source physical unit to the target physical unit). If all the valid data in a source physical unit has been moved to the target physical unit, the memory control circuit 23 can associate this source physical unit to the idle area 33.

[0058] Therefore, the aforementioned operation of associating at least one physical unit to the idle area 33, which is also called releasing (new) idle physical units, can gradually increase the total number of physical units (i.e., idle physical units) in the idle area 33. By synchronously performing the data consolidation operation (i.e., the target data consolidation) on the memory module 122 during the host write operation, new idle physical units can be continuously replenished during the period when the host write operation consumes the idle physical units, thereby avoiding the exhaustion of the idle physical units.

[0059] In one embodiment, in the data consolidation operation, the memory control circuit 23 can preferentially select the physical units in the idle area 33 (i.e., the cache physical units) as the source physical units. After the valid data in a cache physical unit is completely moved to the target physical unit, this cache physical unit can be re-associated to the idle area 33 to become one of the physical units 301(B+1)~301(C).

[0060] Therefore, the physical units (i.e., the cache physical units) in the idle area 33 that are dedicated to store the data written by the host write operation can be continuously replenished, thereby improving the data write performance of the host write operation.

[0061] In one embodiment, by adjusting (e.g., increasing) the threshold, target data consolidation can be triggered in advance during a host write operation. By triggering target data consolidation in advance, physical units in the idle area 33 dedicated to storing data written by the host write operation (i.e., cache physical units) can be replenished in advance (i.e., freeing up idle physical units belonging to the cache physical units begins in advance) during the host write operation.

[0062] Therefore, during the execution of the host write operation, although the cache physical units in the idle area 33 (i.e., the physical units 301(B+1)-301(C)) are continuously consumed, the cache physical units in the idle area 33 (i.e., the physical units 301(B+1)-301(C)) can also be continuously replenished, thereby slowing down the consumption rate of the cache physical units in the idle area 33 (i.e., the physical units 301(B+1)-301(C)).

[0063] In one embodiment, the memory control circuit 23 can determine whether the data write efficiency of the monitored host write operation is lower than the preset efficiency. In one embodiment, if the data write efficiency of the monitored host write operation is lower than the preset efficiency, the memory control circuit 23 can adjust the critical value from a certain critical value (also referred to as the first critical value) to another critical value (also referred to as the second critical value). The second critical value is different from the first critical value. For example, the second critical value may be greater than the first critical value. Alternatively, in one embodiment, if the data write efficiency of the monitored host write operation is not lower than (for example, higher than or equal to) the preset efficiency, the memory control circuit 23 can maintain the critical value at the first critical value. It should be noted that the setting of the preset efficiency can be set based on data statistical analysis of the write efficiency of the host write operation in practice, or can be set based on relevant parameters of the storage device, which is not specifically limited here.

[0064] In one embodiment, the memory control circuit 23 may use a numerical value (also referred to as a first performance evaluation value) to represent the data writing performance of the host write operation. For example, the first performance evaluation value may be positively correlated with the data writing performance of the host write operation. That is, a larger first performance evaluation value indicates a higher data writing performance of the host write operation.

[0065] In one embodiment, the memory control circuit 23 may compare the first performance evaluation value with a preset value. For example, the preset value may represent the preset performance. The preset value may be positively correlated with the preset performance. That is, a larger preset value indicates a higher preset performance.

[0066] In one embodiment, if the comparison result of the first performance evaluation value and the preset value indicates that the first performance evaluation value is less than the preset value, the memory control circuit 23 can determine that the data write performance of the host write operation is lower than the preset performance. However, if the comparison result of the first performance evaluation value and the preset value indicates that the first performance evaluation value is not less than (e.g., greater than or equal to) the preset value, the memory control circuit 23 can determine that the data write performance of the host write operation is not lower than the preset performance.

[0067] In one embodiment, the memory control circuit 23 can determine whether the host write operation currently being executed is a host low-speed write or a host high-speed write according to the comparison result of the data write performance of the monitored host write operation and the preset performance. For example, if the data write performance of the host write operation is lower than the preset performance, the memory control circuit 23 can determine that the host write operation currently being executed is a host low-speed write. Alternatively, if the data write performance of the host write operation is not lower than the preset performance, the memory control circuit 23 can determine that the host write operation currently being executed is a host high-speed write.

[0068] In one embodiment, if the host write operation currently being executed is determined to be a host low-speed write, the memory control circuit 23 can adjust (e.g., increase) the threshold value from the first threshold value to the second threshold value. However, in one embodiment, if the host write operation currently being executed is determined to be a host high-speed write, the memory control circuit 23 can maintain the threshold value at the first threshold value or revert the threshold value from the second threshold value to the first threshold value.

[0069] In one embodiment, if the host write operation currently being executed is a host low-speed write (i.e., the data write performance of the host write operation is lower than the preset performance), it indicates that at this time, even if the host write operation and the data compaction operation are executed synchronously, the impact on the data write performance of the host write operation experienced by the host system 11 can be almost negligible. Therefore, in one embodiment, by increasing the threshold value (e.g., increasing the threshold value to the second threshold value) when the host system 11 executes a host low-speed write to trigger the target data compaction in advance, the release (i.e., replenishment) of idle physical units (especially, idle physical units belonging to the cache physical units) can be started in advance without almost affecting the data write performance of the host write operation. In this way, it helps to maintain or even improve the data write performance of the host write operation.

[0070] On the other hand, in one embodiment, if the host write operation currently being executed is a host high-speed write (i.e., the data write performance of the host write operation is not lower than a predetermined performance), it indicates that if the host write operation and the data consolidation operation are executed synchronously, the host system 11 can experience a significant decrease in the data write performance of the host write operation (because part of the bandwidth is occupied by the data consolidation operation). Therefore, in one embodiment, by lowering or reverting the threshold value (e.g., reverting the threshold value from the second threshold value to the first threshold value) to close or cancel the early triggering of the target data consolidation when the host system 11 is executing a host high-speed write, the data write performance of the host write operation can be prevented from being affected.

[0071] In one embodiment, the memory control circuit 23 can evaluate the execution performance of the data consolidation operation before or after triggering the target data consolidation. The memory control circuit 23 can adjust the threshold value according to the execution performance of the data consolidation operation.

[0072] In one embodiment, according to the execution performance of the data consolidation operation, the memory control circuit 23 can determine an adjustment parameter value. For example, the adjustment parameter value can be inversely related to the execution performance of the data consolidation operation. That is, the higher the evaluated execution performance of the data consolidation operation, the smaller the adjustment parameter value can be. According to the adjustment parameter value, the memory control circuit 23 can adjust the threshold value from the first threshold value to the second threshold value. For example, the adjustment parameter value can be positively related to the difference between the first threshold value and the second threshold value. That is, the larger the adjustment parameter value, the larger the difference between the first threshold value and the second threshold value can be.

[0073] Figure 4 is a schematic diagram of adjusting the threshold value according to an embodiment of the present application. Please refer to Figure 4 In one embodiment, assuming that the host write operation currently being executed is a host low-speed write, the memory control circuit 23 can set the threshold value for triggering the target data consolidation as the threshold value THR(l) (i.e., the first threshold value).

[0074] In one embodiment, if the host write operation currently being executed is a host high-speed write, the memory control circuit 23 can adjust (e.g., increase) the threshold value for triggering the target data consolidation as the threshold value THR(2) (i.e., the second threshold value). For example, the difference ΔP between the threshold values THR(l) and THR(2) is positively related to the adjustment parameter value. The difference ΔP can be inversely related to the execution performance of the data consolidation operation.

[0075] In one embodiment, the memory control circuit 23 can add the difference value ΔP to the threshold value THR(l) to obtain a threshold value THR(2). In one embodiment, the memory control circuit 23 can subtract the difference value ΔP from the threshold value THR(2) to obtain the threshold value THR(l).

[0076] In one embodiment, the performance of the data consolidation operation can be reflected by the number N of free physical units released per unit time during the execution of the data consolidation operation. For example, the value of N can be positively correlated to the performance of the data consolidation operation. That is, the larger the value of N, the more free physical units released per unit time during the execution of the data consolidation operation (equivalent to the higher the performance of the data consolidation operation).

[0077] In one embodiment, the memory control circuit 23 can obtain the storage status of the valid data in the memory module 122. For example, the storage status of the valid data in the memory module 122 can reflect the distribution status of the valid data in one or more physical units in the memory module 122. The memory control circuit 23 can evaluate the performance of the data consolidation operation according to the storage status of the valid data in the memory module 122.

[0078] In one embodiment, the memory control circuit 23 can use a value (also referred to as a second performance evaluation value) to represent the performance of the data consolidation operation. For example, the second performance evaluation value can be positively correlated to the performance of the data consolidation operation. That is, the larger the second performance evaluation value, the higher the performance of the data consolidation operation. In one embodiment, the second performance evaluation value can be positively correlated to the value of N.

[0079] In one embodiment, the memory control circuit 23 can obtain the second performance evaluation value according to the following algorithms (1.1) and (1.2).

[0080] R1 = (V1 - (V x f%)) / V (1.1)

[0081] R2 = R1 / UT (1.2)

[0082] In algorithms (1.1) and (1.2), the parameter V1 represents the total number of used physical units in the memory module 122 (i.e., the physical units in the memory module 122 currently storing valid data), the parameter V represents the total number of all physical units in the memory module 122, the parameter f% represents the proportion of the valid data stored in one or more used physical units in the total data, the parameter UT represents a unit time, and the parameter R2 represents the second performance evaluation value.

[0083] In one embodiment, the memory control circuit 23 can determine the adjustment parameter value (e.g., the threshold value THR) according to the following algorithm (2.1).Figure 4 ΔP) in equation (2.1).

[0084] ΔP = M / R2 (2.1)

[0085] In the algorithm (2.1), the parameter M can be "1" or other values greater than zero. It should be noted that the algorithms (1.1), (1.2) and (2.1) can be adjusted according to practical needs, and the present application is not limited thereto.

[0086] In an embodiment, the memory control circuit 23 can adjust the parameter M in the algorithm (2.1) according to the monitored host write operation. In an embodiment, if the host write operation currently being executed is a host low-speed write (i.e. the data write performance of the host write operation is lower than a preset performance), the memory control circuit 23 can predict the time range in which the host write operation remains in the host low-speed write according to the monitored host write operation. For example, within the predicted time range, the host write operation can have a relatively high probability of remaining in the host low-speed write. The memory control circuit 23 can determine the parameter M in the algorithm (2.1) according to the predicted time range. For example, the parameter M can be positively correlated with the predicted time range in which the host write operation remains in the host low-speed write. That is, the greater the predicted time range in which the host write operation remains in the host low-speed write, the greater the parameter M can be. Alternatively, in an embodiment, the parameter M can represent or reflect the time during which the host write operation is expected to remain in the low-speed write.

[0087] In an embodiment, the memory control circuit 23 can predict the time range in which the host write operation remains in the host low-speed write by analyzing at least one of the type of data written by the host write operation, the size of data written by the host write operation, the total number of instructions indicating the host write operation, and the frequency of obtaining instructions indicating the host write operation as a characteristic parameter. For example, the memory control circuit 23 can input one or more of the above-mentioned characteristic parameters to an operation model or a lookup table, and obtain the time range or the parameter M according to the output of the operation model or the lookup table. The details of the relevant operations can be designed or adjusted according to practical needs, and the present application is not limited thereto.

[0088] It can be seen that, by the method proposed in the above embodiments, when the first performance evaluation value is larger, Δp is set smaller, and the idle physical units are quickly released through short-time target data consolidation processing, thereby achieving the effect of quickly improving the host performance. When the first performance evaluation value is smaller, Δp is set relatively larger, and when the host write operation is in the low-speed write, the idle physical units can be quickly released by starting the target data consolidation processing earlier, thereby ensuring as much as possible that enough idle physical units are released before the host switches back to the high-speed data write operation.

[0089] Figure 5is a graph showing host write performance in a case where data consolidation is not triggered in advance according to an embodiment of the present application. Please refer to Figure 5 , assuming that the horizontal axis is time and the vertical axis is data write performance of a host write operation (also referred to as host write performance). Assume that before time point T(0), the storage device 12 is in an idle state. Therefore, before time point T(0), the memory control circuit 23 can instruct the storage device 12 to perform background data consolidation.

[0090] Assume that after time point T(0), the storage device 12 starts to perform a host write operation. The curve 51 can reflect the change of host write performance at different time points. For example, assume that at time point T(l), the cache entity units in the memory module 122 are exhausted. Therefore, after time point T(l), the host write performance starts to decrease. At time point T(2), the total number of idle entity units in the memory module 122 is less than a threshold value (i.e., a threshold value for triggering target data consolidation). Therefore, after time point T(2), the memory control circuit 23 triggers target data consolidation to release idle entity units belonging to the cache entity units. Moreover, assume that after time point T(3), the storage device 12 is in an idle state again. Note that in the embodiment of Figure 5 , between time point (1) (i.e., the time point when the cache entity units are exhausted) and T(2) (i.e., the time point when target data consolidation is triggered), the host write performance decreases significantly. Until target data consolidation is triggered, the host write performance tends to be stable.

[0091] Figure 6 is a graph showing host write performance in a case where data consolidation is triggered in advance according to an embodiment of the present application. Please refer to Figure 6 , the curve 61 can reflect the change of host write performance at different time points. Note that compared with the embodiment of Figure 5 , in the embodiment of Figure 6 , the threshold value for triggering target data consolidation is increased. For example, after time point T(l) (i.e., the time point when the cache entity units are exhausted), the threshold value for triggering target data consolidation can be increased according to the host write performance (and the execution performance of data consolidation operation). The related operation details have been described above and will not be repeated here.

[0092] After the threshold value is increased, at time point T(2)' (time point T(2)' is between time point T(l) and T(2)), target data consolidation is triggered in advance. After target data consolidation is triggered, during the execution of the host write operation after time point T(2)', data consolidation operation can be performed synchronously to gradually release idle entity units belonging to the cache entity units.

[0093] In particular, compared with the embodiment ofFigure 5 In an embodiment of the present application, the target data consolidation is triggered early. Thus, in an embodiment of the present application, the drop in host write performance after a time point T(l) (i.e. the time point at which the cache entity units are exhausted) is less than in a conventional storage device 12. Figure 6 In an embodiment of the present application, the target data consolidation is triggered early. Thus, in an embodiment of the present application, the drop in host write performance after a time point T(l) (i.e. the time point at which the cache entity units are exhausted) is less than in a conventional storage device 12. Figure 5 In an embodiment of the present application, the target data consolidation is triggered early. Thus, in an embodiment of the present application, the drop in host write performance after a time point T(l) (i.e. the time point at which the cache entity units are exhausted) is less than in a conventional storage device 12. Figure 7 In an embodiment of the present application, the target data consolidation is triggered early. Thus, in an embodiment of the present application, the drop in host write performance after a time point T(l) (i.e. the time point at which the cache entity units are exhausted) is less than in a conventional storage device 12. Thereby, the problem of a significant drop in performance of host write operations that is commonly encountered after a conventional storage device 12 has been in use for a period of time is ameliorated.

[0094] Figure 7 is a flowchart of a data consolidation method according to an embodiment of the present application. Please refer to Figure 7 The data consolidation method according to an embodiment of the present application comprises the following steps:

[0095] In step S701, a cache entity unit is configured in a memory module.

[0096] In step S702, a host write operation is performed to store data from a host system.

[0097] In step S703, it is determined whether the available capacity of the cache entity unit is less than a preset capacity. If the available capacity of the cache entity unit is not less than the preset capacity, step S702 is repeated.

[0098] If the available capacity of the cache entity unit is less than the preset capacity, in step S704, the data write performance of the host write operation is monitored.

[0099] In step S705, a threshold value is adjusted according to the data write performance, wherein the threshold value is used to represent a threshold condition for triggering target data consolidation.

[0100] In step S706, after the target data consolidation is triggered, a data consolidation operation is performed on the memory module synchronously during the host write operation. The data consolidation operation is used to move valid data in the memory module to release idle entity units.

[0101] In an embodiment, the step of adjusting the threshold value according to the data write performance comprises: determining whether the data write performance is lower than a preset performance; if the data write performance is lower than the preset performance, adjusting the threshold value from a first threshold value to a second threshold value, wherein the second threshold value is greater than the first threshold value; and if the data write performance is not lower than the preset performance, maintaining the threshold value at the first threshold value.

[0102] In one embodiment, the step of adjusting the threshold value from the first threshold value to the second threshold value comprises: evaluating an execution performance of the data coalescing operation; determining an adjustment parameter value according to the execution performance; and adjusting the threshold value from the first threshold value to the second threshold value according to the adjustment parameter value, wherein the adjustment parameter value is positively correlated to a difference between the first threshold value and the second threshold value.

[0103] In one embodiment, the step of evaluating the execution performance of the data coalescing operation comprises: evaluating the execution performance of the data coalescing operation according to a storage state of the valid data in the memory module.

[0104] In one embodiment, the step of monitoring the data write performance of the host write operation comprises: evaluating the data write performance of the host write operation according to a depth of an instruction queue, wherein the instruction queue is used to buffer at least one instruction from the host system.

[0105] In one embodiment, the data coalescing method further comprises: determining whether the total number of the idle physical units is less than the threshold value; and triggering the target data coalescing if the total number of the idle physical units is less than the threshold value.

[0106] However, Figure 7 The steps in the above embodiments have been described in detail, and thus will not be repeated here. It is worth noting that, Figure 7 The steps in the above embodiments can be implemented as a plurality of program codes or circuits, and the present application is not limited thereto. In addition, ​ The method in the above embodiments can be used in combination with the above exemplary embodiments, or can be used independently, and the present application is not limited thereto.

[0107] In summary, the data coalescing method and the storage device provided by the present application can adjust a threshold value for triggering a target data coalescing according to a data write performance of a host write operation when available capacity of cache physical units in a memory module is less than a preset capacity. Thus, the target data coalescing can be triggered early to release new idle physical units gradually without affecting the data write performance of the host write operation as much as possible, thereby improving the problem that the data write performance of the host write operation is greatly reduced after the storage device is used for a period of time and improving the operation stability of the storage device.

[0108] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some or all of the technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A data consolidation method, characterized in that: Used in a storage device, the storage device includes a memory module, and the data consolidation method includes: configuring a cache physical unit in the memory module; Performing host write operations to store data from the host system; Determining whether the available capacity of the cache physical unit is less than a preset capacity; If the available capacity is less than the preset capacity, monitoring the data writing efficiency of the host write operation; adjusting a threshold value according to the data writing performance, wherein the threshold value is used to represent a threshold condition for triggering target data consolidation; and If the target data consolidation is triggered, a data consolidation operation is synchronously performed on the memory module during the execution of the host write operation, wherein the data consolidation operation is used to move valid data in the memory module to release idle physical units.

2. The data consolidation method according to claim 1 , wherein the step of adjusting the threshold value according to the data writing performance comprises: Determining whether the data writing performance is lower than a preset performance; If the data writing performance is lower than the preset performance, adjusting the threshold from a first threshold to a second threshold, wherein the second threshold is greater than the first threshold; as well as If the data writing performance is not lower than the preset performance, the threshold is maintained at the first threshold.

3. The data consolidation method according to claim 2, wherein the step of adjusting the threshold from the first threshold to the second threshold comprises: evaluating the performance of the data consolidation operation; Determining adjustment parameter values ​​based on the execution performance; as well as The threshold value is adjusted from the first threshold value to the second threshold value according to the adjustment parameter value, wherein the adjustment parameter value is positively correlated with the difference between the first threshold value and the second threshold value.

4. The data consolidation method according to claim 3, wherein the step of evaluating the execution performance of the data consolidation operation comprises: The execution performance of the data merge operation is evaluated according to a storage status of the valid data in the memory module. 5 . The data consolidation method according to claim 3 , wherein the execution efficiency of the data consolidation operation is reflected in that N idle physical units are released per unit time during the execution of the data consolidation operation. 6 . The data consolidation method according to claim 3 , wherein the adjustment parameter value is negatively correlated with the execution performance of the data consolidation operation.

7. The data consolidation method according to claim 1 , wherein the step of monitoring the data writing efficiency of the host write operation comprises: The data write performance of the host write operation is evaluated according to the depth of a command queue, wherein the command queue is used to buffer at least one command from the host system.

8. The data consolidation method according to claim 1, further comprising: Determining whether the total number of the idle physical units is less than the critical value; as well as If the total number of the idle physical units is less than the threshold, the target data consolidation is triggered.

9. A storage device, characterized in that: include: A connection interface for connecting to a host system; Memory module; as well as a memory controller connected to the connection interface and the memory module, The memory controller is configured to: configuring a cache physical unit in the memory module; performing a host write operation to store data from the host system; Determining whether the available capacity of the cache physical unit is less than a preset capacity; If the available capacity is less than the preset capacity, monitoring the data writing efficiency of the host write operation; adjusting a critical value according to the data writing performance, wherein the critical value is used to represent a threshold condition for triggering target data consolidation; as well as If the target data consolidation is triggered, a data consolidation operation is synchronously performed on the memory module during the execution of the host write operation, wherein the data consolidation operation is used to move valid data in the memory module to release idle physical units.

10. The storage device according to claim 9, wherein the memory controller adjusts the threshold value according to the data writing performance comprises: Determining whether the data writing performance is lower than a preset performance; If the data writing performance is lower than the preset performance, adjusting the threshold from a first threshold to a second threshold, wherein the second threshold is greater than the first threshold; as well as If the data writing performance is not lower than the preset performance, the threshold is maintained at the first threshold.

11. The memory device according to claim 10 , wherein the memory controller adjusting the threshold from the first threshold to the second threshold comprises: evaluating the performance of the data consolidation operation; Determining adjustment parameter values ​​based on the execution performance; as well as The threshold value is adjusted from the first threshold value to the second threshold value according to the adjustment parameter value, wherein the adjustment parameter value is positively correlated with the difference between the first threshold value and the second threshold value.

12. The memory device according to claim 11, wherein the memory controller's operation of evaluating the execution performance of the data consolidation operation comprises: The execution performance of the data merge operation is evaluated according to a storage status of the valid data in the memory module. 13 . The storage device according to claim 11 , wherein the execution performance of the data consolidation operation is reflected in that N idle physical units are released per unit time during the execution of the data consolidation operation. 14 . The storage device of claim 11 , wherein the adjustment parameter value is negatively correlated with the execution performance of the data merge operation.

15. The storage device according to claim 9, wherein the memory controller monitors the data write efficiency of the host write operation, comprising: The data write performance of the host write operation is evaluated according to the depth of a command queue, wherein the command queue is used to buffer at least one command from the host system.

16. The storage device according to claim 9, wherein the memory controller is further configured to: Determining whether the total number of the idle physical units is less than the critical value; and If the total number of the idle physical units is less than the threshold, the target data consolidation is triggered.

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