Method for responding to DMA request, program product, storage medium, and electronic device

Abstract

The embodiment of the present application provides a method and program product, storage medium, and electronic device for responding to a DMA request, the method comprising: performing a first arbitration operation on a first request queue and a second request queue of a first data processing object to obtain a first target request queue; performing a second arbitration operation on the first target request queue and the second target request queue to obtain a third target request queue; sending the third target request queue to a target DMA controller to instruct the target DMA controller to respond to multiple DMA requests in the order of arrangement of the multiple DMA requests included in the third target request queue, the multiple DMA requests including all the DMA requests in the first target request queue and the second target request queue. Through the present application, the problem of being unable to respond to DMA requests in a timely manner in the related art can be solved, and the effect of responding to DMA requests in a timely and efficient manner can be achieved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computers, and more specifically, to a method for responding to a DMA request, a program product, a storage medium, and an electronic device. Background Art

[0002] The chip data transfer process usually requires the control and processing of the Central Processing Unit (CPU), which not only limits the data transfer rate, but also increases the CPU's running time and resource usage, resulting in CPU performance degradation, which in turn affects the performance of the entire system. Although direct memory access (DMA) type data transfer can directly access the memory without CPU participation, when multiple DMA initiators in the system initiate DMA requests at the same time, the relevant technology responds to these requests by using a fixed DMA channel priority, but there is a problem of being unable to respond to DMA requests in a timely manner. Summary of the invention

[0003] The embodiments of the present application provide a method and program product, a storage medium, and an electronic device for responding to a DMA request, so as to at least solve the problem in the related art that a DMA request cannot be responded to in a timely manner.

[0004] According to an embodiment of the present application, a method for responding to DMA requests is provided, which is applied to a DMA control device, wherein the DMA control device includes multiple DMA controllers, and the DMA control device is connected to a data processing device. The method includes: performing a first arbitration operation on a first request queue and a second request queue of a first data processing object to obtain a first target request queue, wherein the first request queue and the second request queue are both request queues created for the first data processing object, and the arrangement method of the first request queue is different from the arrangement method of the second request queue, and the first arbitration operation is used to sort the DMA requests in the first request queue and the DMA requests in the second request queue, and the first data processing object is any processing object among the multiple data processing objects included in the data processing device; performing a second arbitration operation on the first target request queue and the second target request queue The third target request queue is obtained by performing an arbitration operation on one or more third request queues of the second data processing object after performing the first arbitration operation, the second data processing object is any other processing object among the multiple data processing objects except the first data processing object, and the second arbitration operation is used to sort the DMA requests in the first target request queue and the DMA requests in the second target request queue; the third target request queue is sent to the target DMA controller to instruct the target DMA controller to respond to the multiple DMA requests according to the arrangement order of the multiple DMA requests included in the third target request queue, wherein the multiple DMA requests include all the DMA requests in the first target request queue and the second target request queue, and the target DMA controller is any DMA controller among the multiple DMA controllers.

[0005] In an exemplary embodiment, before a first arbitration operation is performed on a first request queue and a second request queue of a first data processing object to obtain a first target request queue, the method further includes: receiving a first DMA request sent by the first data processing object; caching the first DMA request in the first request queue or in a third request queue according to first request information included in the first DMA request, wherein the first request information includes identification information of the first data processing object, priority information of the first DMA request and target address information of the first DMA request, and the priority information of the DMA requests in the third request queue is different from that in the first request queue; performing a third arbitration operation on the DMA requests in the third request queue to cache the DMA requests in the third request queue in the second request queue, wherein the third arbitration operation is used to filter the DMA requests in the third request queue according to the target address information and the priority information.

[0006] In an exemplary embodiment, the first DMA request is cached in the first request queue or the third request queue according to the first request information included in the first DMA request, including: in a case where the priority information is queue-jumping information, the first DMA request is cached in the first request queue at a position corresponding to the queue-jumping position in the queue-jumping information according to the target address information, and the valid bit of the position corresponding to the queue-jumping position in the first request queue is set to valid; or, in a case where the priority information is a preset priority, the first DMA request is cached in the third request queue at a position corresponding to the preset priority according to the preset priority, and the valid bit of the position corresponding to the preset priority in the third request queue is set to valid.

[0007] In an exemplary embodiment, a third arbitration operation is performed on the DMA requests in the third request queue to cache the DMA requests in the third request queue in the second request queue, including: performing a screening operation on the DMA requests in the third request queue according to the target address information to obtain a plurality of second DMA requests, wherein the target address information of the plurality of second DMA requests are the same; in the case where the second request queue includes a DMA request having the same target address information as the second DMA request, the plurality of second DMA requests continue to be cached in the third request queue; in the case where there is no DMA request having the same target address information as the second DMA request in the second request queue, the DMA request with the highest priority among the plurality of second DMA requests is cached to a position in the second request queue corresponding to the target address information, and the valid bit of the position in the second request queue corresponding to the target address information is set to valid.

[0008] In an exemplary embodiment, a first arbitration operation is performed on a first request queue and a second request queue of a first data processing object to obtain a first target request queue, including: when the DMA requests in the first request queue and the DMA requests in the second request queue include a first target DMA request having the same target address information, and the position corresponding to the target address information in the first target request queue does not include a valid DMA request, the first target DMA request is cached to the position corresponding to the target address information in the first target request queue, and the valid bit of the position corresponding to the target address information in the first target request queue is set to valid; or, when the DMA requests in the first request queue and the DMA requests in the second request queue include a second target DMA request having the same target address information, and the position corresponding to the target address information in the first target request queue includes a valid DMA request, the second target DMA request continues to be cached in the first request queue and the second request queue, respectively.

[0009] In an exemplary embodiment, a first arbitration operation is performed on a first request queue and a second request queue of a first data processing object to obtain a first target request queue, including: when the DMA requests in the first request queue and the DMA requests in the second request queue do not include DMA requests with the same target address information, and the position corresponding to the target address information in the first target request queue does not include a valid DMA request, the DMA requests in the first request queue and the DMA requests in the second request queue are cached to the positions corresponding to the target address information in the first target request queue, respectively, and the valid bit of the position corresponding to the target address information in the first target request queue is set to valid; or, when the DMA requests in the first request queue and the DMA requests in the second request queue do not include DMA requests with the same target address information, and the position corresponding to the target address information in the first target request queue includes a valid DMA request, the DMA requests in the first request queue continue to be cached in the first request queue, and / or the DMA requests in the second request queue continue to be cached in the second request queue.

[0010] In an exemplary embodiment, a second arbitration operation is performed on the first target request queue and the second target request queue to obtain a third target request queue, including: performing a screening operation on the DMA requests in the first target request queue and the DMA requests in the second target request queue according to the target address information of the DMA request to obtain multiple third DMA requests, wherein the target address information corresponding to the third DMA requests are all the same; performing the second arbitration operation on the multiple third DMA requests according to the identification information of the data processing object and / or the priority information of the third DMA request, and caching the multiple third DMA requests after performing the second arbitration operation into the third target request queue.

[0011] In an exemplary embodiment, the second arbitration operation is performed on the plurality of third DMA requests according to the identification information and / or priority information of the data processing object, and the plurality of third DMA requests after the second arbitration operation is performed are cached in the third target request queue, including: when the plurality of priority information included in the plurality of third DMA requests are different, the plurality of third DMA requests are cached in the third target request queue according to the sorting method between the plurality of priority information; or, when the plurality of priority information included in the plurality of third DMA requests are the same, the plurality of third DMA requests are cached in the third target request queue according to the sorting method between the identification information of the data processing object.

[0012] In an exemplary embodiment, the third target request queue is sent to a target DMA controller to instruct the target DMA controller to respond to the multiple DMA requests in the order of arrangement of the multiple DMA requests included in the third target request queue, including: according to the target address information of the DMA request, sending the multiple DMA requests in the third target request queue to the target DMA controller according to the order of arrangement, wherein the identification information of the target DMA controller is in a one-to-one correspondence with the target address information; and controlling the target DMA controller to execute the multiple DMA requests in the order of sending.

[0013] In an exemplary embodiment, the DMA control device further includes a storage device, and the DMA control device is connected to the data processing device and the storage device. After sending the third target request queue to the target DMA controller to instruct the target DMA controller to respond to the multiple DMA requests in the order of arrangement of the multiple DMA requests included in the third target request queue, the method further includes: sending the execution status of the multiple DMA requests to the storage device; when the data processing device obtains the execution status of the DMA request from the storage device according to the polling method and / or interrupt feedback method of the register in the feedback queue, the feedback queue is used to obtain the execution status of the multiple DMA requests from the storage device, and the execution status of the multiple DMA requests is sent to the data processing device.

[0014] In an exemplary embodiment, the data processing device includes a plurality of data processing objects, and before performing a first arbitration operation on a first request queue and a second request queue of a first data processing object to obtain a first target request queue, the method further includes: configuring the number of request queues and target request queues according to the number of the data processing objects and the number of the DMA controllers, wherein the request queue includes the first request queue and the second request queue, and the target request queue includes the first target request queue and the second target request queue; configuring the cache space of the request queue and the target request queue according to the number of the DMA controllers; and setting the trigger conditions for the request queue and the target request queue to receive the DMA request, wherein the trigger conditions include the remaining cache space of the request queue and the target request queue, and the running status of the DMA controller.

[0015] According to one embodiment of the present application, there is provided a device for responding to DMA requests, which is applied to a DMA control device, wherein the DMA control device includes a plurality of DMA controllers, and the DMA control device is connected to a data processing device, and the device includes: a first execution module, which is used to perform a first arbitration operation on a first request queue and a second request queue of a first data processing object to obtain a first target request queue, wherein the first request queue and the second request queue are both request queues created for the first data processing object, and the arrangement of the first request queue is different from the arrangement of the second request queue, and the first arbitration operation is used to sort the DMA requests in the first request queue and the DMA requests in the second request queue, and the first data processing object is any one of the plurality of data processing objects included in the data processing device; and a second execution module, which is used to sort the first target request queue and the second target request queue. Execute a second arbitration operation to obtain a third target request queue, wherein the second target request queue is a queue after executing the first arbitration operation on one or more third request queues of the second data processing object, the second data processing object is any other processing object among the multiple data processing objects except the first data processing object, and the second arbitration operation is used to sort the DMA requests in the first target request queue and the DMA requests in the second target request queue; a first sending module is used to send the third target request queue to the target DMA controller to instruct the target DMA controller to respond to the multiple DMA requests in the order of arrangement of the multiple DMA requests included in the third target request queue, wherein the multiple DMA requests include all the DMA requests in the first target request queue and the second target request queue, and the target DMA controller is any DMA controller among the multiple DMA controllers.

[0016] In an exemplary embodiment, the device further includes: a first receiving module, configured to perform a first arbitration operation on a first request queue and a second request queue of a first data processing object, and receive a first DMA request sent by the first data processing object before obtaining the first target request queue; a first caching module, configured to cache the first DMA request in the first request queue or the third request queue according to the first request information included in the first DMA request, wherein the first request information includes identification information of the first data processing object, priority information of the first DMA request and target address information of the first DMA request, and the priority information of the DMA requests in the third request queue is different from that in the first request queue; a third execution module, configured to perform a third arbitration operation on the DMA requests in the third request queue, so as to cache the DMA requests in the third request queue in the second request queue, wherein the third arbitration operation is used to filter the DMA requests in the third request queue according to the target address information and the priority information.

[0017] In an exemplary embodiment, the first cache module includes: a first cache submodule, which is used to cache the first DMA request to a position in the first request queue corresponding to the queue interruption position in the queue interruption information according to the target address information when the priority information is queue interruption information, and set the valid bit of the position in the first request queue corresponding to the queue interruption position to valid; or, a second cache submodule, which is used to cache the first DMA request to a position in the third request queue corresponding to the preset priority according to the preset priority when the priority information is a preset priority, and set the valid bit of the position in the third request queue corresponding to the preset priority to valid.

[0018] In an exemplary embodiment, the third execution module includes: a first execution submodule, used to perform a screening operation on the DMA requests in the third request queue according to the target address information to obtain multiple second DMA requests, wherein the target address information of the multiple second DMA requests are the same; a third cache submodule, used to continue to cache the multiple second DMA requests in the third request queue when the second request queue includes a DMA request having the same target address information as the second DMA request; and a fourth cache submodule, used to cache the DMA request with the highest priority among the multiple second DMA requests to a position in the second request queue corresponding to the target address information when there is no DMA request having the same target address information as the second DMA request in the second request queue, and set the valid bit of the position in the second request queue corresponding to the target address information to valid.

[0019] In an exemplary embodiment, the first execution module comprises: a fifth cache submodule for caching the first target DMA request to the position corresponding to the target address information in the first target request queue, and setting the valid bit of the position corresponding to the target address information in the first target request queue to valid, when the DMA requests in the first request queue and the DMA requests in the second request queue include a first target DMA request with the same target address information, and the position corresponding to the target address information in the first target request queue does not include a valid DMA request; or, a sixth cache submodule for continuing to cache the second target DMA request in the first request queue and the second request queue, respectively, when the DMA requests in the first request queue and the DMA requests in the second request queue include a second target DMA request with the same target address information, and the position corresponding to the target address information in the first target request queue includes a valid DMA request.

[0020] In an exemplary embodiment, the first execution module comprises: a seventh cache submodule for caching the DMA requests in the first request queue and the DMA requests in the second request queue to the positions corresponding to the target address information in the first target request queue, respectively, and setting the valid bit of the position corresponding to the target address information in the first target request queue to valid, if the DMA requests in the first request queue and the DMA requests in the second request queue do not include DMA requests with the same target address information, and the position corresponding to the target address information in the first target request queue does not include a valid DMA request; or, an eighth cache submodule for continuing to cache the DMA requests in the first request queue in the first request queue, and / or continuing to cache the DMA requests in the second request queue in the second request queue, if the DMA requests in the first request queue and the DMA requests in the second request queue do not include DMA requests with the same target address information, and the position corresponding to the target address information in the first target request queue includes a valid DMA request.

[0021] In an exemplary embodiment, the second execution module includes: a first screening submodule, used to perform screening operations on the DMA requests in the first target request queue and the DMA requests in the second target request queue according to the target address information of the DMA request, so as to obtain multiple third DMA requests, wherein the target address information corresponding to the third DMA requests are all the same; a ninth cache submodule, used to perform the second arbitration operation on the multiple third DMA requests according to the identification information of the data processing object and / or the priority information of the third DMA request, and cache the multiple third DMA requests after the second arbitration operation is performed into the third target request queue.

[0022] In an exemplary embodiment, the ninth cache submodule comprises: a first cache unit for caching the plurality of third DMA requests into the third target request queue according to the sorting method between the plurality of priority information included in the plurality of third DMA requests when the plurality of priority information included in the plurality of third DMA requests are different; or, a second cache unit for caching the plurality of third DMA requests into the third target request queue according to the sorting method between the identification information of the data processing objects when the plurality of priority information included in the plurality of third DMA requests are the same.

[0023] In an exemplary embodiment, the above-mentioned first sending module includes: a first sending sub-module, used to send the multiple DMA requests in the above-mentioned third target request queue to the above-mentioned target DMA controller according to the above-mentioned arrangement order according to the target address information of the above-mentioned DMA request, wherein the identification information of the above-mentioned target DMA controller and the above-mentioned target address information are in a one-to-one correspondence; a second execution sub-module, used to control the above-mentioned target DMA controller to execute the multiple above-mentioned DMA requests in the sending order.

[0024] In an exemplary embodiment, the DMA control device further includes a storage device, the DMA control device is connected to the data processing device and the storage device, and the device further includes: a second sending module, used to send the third target request queue to the target DMA controller to instruct the target DMA controller to respond to the multiple DMA requests according to the arrangement order of the multiple DMA requests included in the third target request queue, and then send the execution status of the multiple DMA requests to the storage device; a first acquisition module, used to obtain the execution status of the multiple DMA requests from the storage device using the feedback queue when the data processing device obtains the execution status of the DMA requests from the storage device according to the polling method and / or interrupt feedback method of the register in the feedback queue, and send the execution status of the multiple DMA requests to the data processing device.

[0025] In an exemplary embodiment, the data processing device includes a plurality of data processing objects, and the apparatus further includes: a first configuration module, for performing a first arbitration operation on a first request queue and a second request queue of a first data processing object, and configuring the number of request queues and target request queues according to the number of the data processing objects and the number of the DMA controllers before obtaining the first target request queue, wherein the request queue includes the first request queue and the second request queue, and the target request queue includes the first target request queue and the second target request queue; a second configuration module, for configuring the cache space of the request queue and the target request queue according to the number of the DMA controllers; and setting the trigger conditions for the request queue and the target request queue to receive the DMA request, wherein the trigger conditions include the remaining cache space of the request queue and the target request queue, and the running status of the DMA controller.

[0026] According to another embodiment of the present application, a DMA control device is also provided, which is connected to a data processing device and a storage device, wherein the DMA control device is configured to execute the steps of any of the above method embodiments during operation.

[0027] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any one of the above method embodiments when running.

[0028] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0029] According to another embodiment of the present application, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0030] Through the present application, firstly, a first arbitration operation is performed on the first request queue and the second request queue of the first data processing object to obtain a first target request queue, and then a second arbitration operation is performed on the first target request queue of the first data processing object and the second target request queue of the second data processing object to obtain a third target request queue, and finally the third target request queue is sent to the target DMA controller to instruct the target DMA controller to respond to multiple DMA requests according to the arrangement order of the multiple DMA requests included in the third target request queue. Since the present application does not fix the priority of the DMA channel, but first performs a first arbitration operation on the DMA request of the same data processing object, and then performs a second arbitration operation on the DMA request between different data processing objects, the execution order of the DMA request can be quickly determined, and therefore, the problem of not being able to respond to DMA requests in a timely manner in the related art can be solved, and the effect of responding to DMA requests in a timely and efficient manner is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a hardware structure block diagram of a server device of a method for responding to a DMA request in an embodiment of the present application;

[0032] Figure 2 is a flow chart of a method for responding to a DMA request according to an embodiment of the present application;

[0033] Figure 3 is an architectural diagram of a method for responding to a DMA request according to an embodiment of the present application;

[0034] Figure 4 is a schematic diagram of performing a first arbitration operation according to an embodiment of the present application;

[0035] Figure 5 is a schematic diagram of performing a second arbitration operation according to an embodiment of the present application;

[0036] Figure 6 is a flow chart of a method for responding to a DMA request according to a specific embodiment of the present application;

[0037] Figure 7 It is a structural block diagram of a device for responding to a DMA request according to an embodiment of the present application. DETAILED DESCRIPTION

[0038] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0039] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0040] The method embodiments provided in the embodiments of the present application can be executed in a server device or a similar computing device. Taking running on a server device as an example, Figure 1 FIG. 1 is a hardware structure diagram of a server device of a method for responding to a DMA request in an embodiment of the present application. Figure 1 As shown, the server device may include one or more ( Figure 1 Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the above-mentioned server device may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above server device. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations shown.

[0041] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as a computer program corresponding to a method for responding to a DMA request in an embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to a server device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0042] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the server device. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0043] In this embodiment, a method for responding to a DMA request is provided, which is applied to a DMA control device. The DMA control device includes a plurality of DMA controllers. The DMA control device is connected to a data processing device. Figure 2 is a flow chart of a method for responding to a DMA request according to an embodiment of the present application. Figure 2 As shown, the process includes the following steps:

[0044] Step S202, performing a first arbitration operation on a first request queue and a second request queue of a first data processing object to obtain a first target request queue, wherein the first request queue and the second request queue are both request queues created for the first data processing object, and an arrangement method of the first request queue is different from an arrangement method of the second request queue, and the first arbitration operation is used to sort the DMA requests in the first request queue and the DMA requests in the second request queue, and the first data processing object is any one of a plurality of data processing objects included in the data processing device.

[0045] Optionally, the first data processing object is a data processing object that can issue a DMA request, including but not limited to a CPU, an Inter-Integrated Circuit (I2C) and a Universal Asynchronous Receiver / Transmitter (UART). Multiple data processing objects constitute a data processing device, and the data processing device is the initiator of the DMA request. Figure 3 As shown, it is an architectural diagram of a method for responding to a DMA request according to an embodiment of the present application. The data processing device sends a DMA request to a DMA control device, and the DMA control device responds to the DMA request and arbitrates the DMA request.

[0046] Optionally, the first arbitration operation is to arbitrate the DMA request initiated by the same data processing object, corresponding to Figure 3 Intra-group arbitration in .

[0047] Step S204, performing a second arbitration operation on the first target request queue and the second target request queue to obtain a third target request queue, wherein the second target request queue is a queue after performing the first arbitration operation on one or more third request queues of the second data processing object, the second data processing object is any other processing object among the multiple data processing objects except the first data processing object, and the second arbitration operation is used to sort the DMA requests in the first target request queue and the DMA requests in the second target request queue.

[0048] Optionally, the second arbitration operation is to arbitrate DMA requests initiated by different data processing objects, corresponding to Figure 3 Inter-group arbitration as shown in .

[0049] Step S206, sending the third target request queue to the target DMA controller to instruct the target DMA controller to respond to multiple DMA requests in the order of arrangement of the multiple DMA requests included in the third target request queue, wherein the multiple DMA requests include all DMA requests in the first target request queue and the second target request queue, and the target DMA controller is any DMA controller among the multiple DMA controllers.

[0050] Through the above steps, firstly, the first arbitration operation is performed on the first request queue and the second request queue of the first data processing object to obtain the first target request queue, and then the second arbitration operation is performed on the first target request queue of the first data processing object and the second target request queue of the second data processing object to obtain the third target request queue, and finally the third target request queue is sent to the target DMA controller to instruct the target DMA controller to respond to multiple DMA requests according to the arrangement order of the multiple DMA requests included in the third target request queue. Since the present application does not fix the priority of the DMA channel, but first performs the first arbitration operation on the DMA request of the same data processing object, and then performs the second arbitration operation on the DMA request between different data processing objects, the execution order of the DMA request can be quickly determined, therefore, the problem of not being able to respond to the DMA request in time in the related art can be solved, and the effect of responding to the DMA request in time and efficiently is achieved.

[0051] In an exemplary embodiment, before a first arbitration operation is performed on a first request queue and a second request queue of a first data processing object to obtain a first target request queue, the method further includes: receiving a first DMA request sent by the first data processing object; caching the first DMA request in the first request queue or in a third request queue according to first request information included in the first DMA request, wherein the first request information includes identification information of the first data processing object, priority information of the first DMA request and target address information of the first DMA request, and the priority information of the DMA requests in the third request queue is different from that in the first request queue; performing a third arbitration operation on the DMA requests in the third request queue to cache the DMA requests in the third request queue in the second request queue, wherein the third arbitration operation is used to filter the DMA requests in the third request queue according to the target address information and the priority information.

[0052] Optionally, the data processing device may include multiple data processing objects. For example, the four CPUs, three I2Cs and two UARTs included in the data processing device can all issue DMA requests. The identification information can be used to identify which data processing object specifically issues the DMA request. DMA requests issued by different data processing objects can be placed in different request queues. For example, DMA request 1 issued by CPU1 can be placed in request queue 1, and DMA request 2 issued by UART1 can be placed in request queue 3.

[0053] Optionally, priority information can be used to indicate the urgency of executing a DMA request. For example, the priority information of DMA request 1 is 0, the priority information of DMA request 2 is 1, and the priority information of DMA request 3 is f. Then the execution order of the above DMA requests is DMA request 3, DMA request 2, and DMA request 1.

[0054] Optionally, the DMA control device can manage multiple DMA controllers, each of which can respond to DMA requests. The target address information is used to specifically identify which DMA controller needs to execute the DMA request. For example, if the target address information of DMA request 1 is 0, then the DMA request is responded to by the DMA_0 controller.

[0055] Optionally, this embodiment is described by taking the first data processing object as a CPU as an example. Figure 4As shown, the DMA control device receives a first DMA request sent by the CPU, caches the first DMA request to the first request queue or the third request queue according to the priority information in the first request information of the first DMA request, and then performs a third arbitration operation on the DMA requests in the third request queue to cache the DMA requests in the third request queue to the second request queue.

[0056] This embodiment performs rapid screening and processing according to request information of DMA requests, and caches DMA requests in different request queues, thereby improving the efficiency of responding to DMA requests.

[0057] In an exemplary embodiment, the first DMA request is cached in the first request queue or the third request queue according to the first request information included in the first DMA request, including: in a case where the priority information is queue-jumping information, the first DMA request is cached in the first request queue at a position corresponding to the queue-jumping position in the queue-jumping information according to the target address information, and the valid bit of the position corresponding to the queue-jumping position in the first request queue is set to valid; or, in a case where the priority information is a preset priority, the first DMA request is cached in the third request queue at a position corresponding to the preset priority according to the preset priority, and the valid bit of the position corresponding to the preset priority in the third request queue is set to valid.

[0058] Alternatively, if Figure 4 As shown, if the priority information of the first DMA request is f, it means that the priority information is queue-jumping information, and the first DMA request is a queue-jumping request. It is necessary to cache the first DMA request in the first request queue according to the destination address information; if the priority information of the first DMA request is 0 / 1 / 2 / 3, it means that the priority information is the preset priority, and the first DMA request is a non-queue-jumping request. It is necessary to cache the first DMA request in the third request queue according to the preset priority. For example, assuming that the priority information of the first DMA request is f and the destination address information is 0, the first DMA request is placed at position 0 in the first request queue, and the effective position of the position is set to 1; assuming that the priority information of the first DMA request is 1, the first DMA request is placed at position 1 in the third request queue, and the effective position of the position is set to 1.

[0059] This embodiment caches DMA requests into different request queues based on the priority of DMA requests, thereby ensuring that high-priority DMA requests are given priority processing, so that key tasks can be completed in time, thereby avoiding the problem of system delays caused by the accumulation of low-priority tasks.

[0060] In an exemplary embodiment, a third arbitration operation is performed on the DMA requests in the third request queue to cache the DMA requests in the third request queue in the second request queue, including: performing a screening operation on the DMA requests in the third request queue according to the target address information to obtain a plurality of second DMA requests, wherein the target address information of the plurality of second DMA requests are the same; in the case where the second request queue includes a DMA request having the same target address information as the second DMA request, the plurality of second DMA requests continue to be cached in the third request queue; in the case where there is no DMA request having the same target address information as the second DMA request in the second request queue, the DMA request with the highest priority among the plurality of second DMA requests is cached to a position in the second request queue corresponding to the target address information, and the valid bit of the position in the second request queue corresponding to the target address information is set to valid.

[0061] Alternatively, if Figure 4 As shown, the DMA requests in the third request queue are sorted according to the priority information, and a third arbitration operation needs to be performed according to the target address information of the DMA request. For example, assume that the third request queue includes the following DMA requests: the priority information of DMA request 1-1 is 0, and the target address information is 0, the priority information of DMA request 1-2 is 1, and the target address information is 0, and the priority information of DMA request 1-3 is 1, and the target address information is 5 (the above three DMA requests are all issued by the same data processing object). First, filter out the DMA requests with the same target address information: DMA request 1-1, DMA request 1-2, and then check whether there is a valid DMA request at the position with the target address information of 0 in the second request queue. If not, cache the DMA request 1-2 with high priority information to the position 0, and set the valid bit of the position to 1. If it exists, continue to cache DMA request 1-1 and DMA request 1-2 in the third request queue.

[0062] Optionally, if the target address information of the DMA requests in the third request queue are all different, then directly check whether there is a valid DMA request at the position of the target address information in the second request queue. If not, cache the DMA request to that position in sequence and set the valid bit of that position to 1; if so, continue to cache the DMA request in the third request queue.

[0063] This embodiment writes DMA requests with different target address information into invalid positions in the second request queue based on the target address information of the DMA request, and caches DMA requests with the same target address information into invalid positions in the second request queue according to priority, thereby achieving the purpose of avoiding mutual blocking of DMA requests with different target address information.

[0064] In an exemplary embodiment, a first arbitration operation is performed on a first request queue and a second request queue of a first data processing object to obtain a first target request queue, including: when the DMA requests in the first request queue and the DMA requests in the second request queue include a first target DMA request having the same target address information, and the position corresponding to the target address information in the first target request queue does not include a valid DMA request, the first target DMA request is cached to the position corresponding to the target address information in the first target request queue, and the valid bit of the position corresponding to the target address information in the first target request queue is set to valid; or, when the DMA requests in the first request queue and the DMA requests in the second request queue include a second target DMA request having the same target address information, and the position corresponding to the target address information in the first target request queue includes a valid DMA request, the second target DMA request continues to be cached in the first request queue and the second request queue, respectively.

[0065] In an exemplary embodiment, a first arbitration operation is performed on a first request queue and a second request queue of a first data processing object to obtain a first target request queue, including: when the DMA requests in the first request queue and the DMA requests in the second request queue do not include DMA requests with the same target address information, and the position corresponding to the target address information in the first target request queue does not include a valid DMA request, the DMA requests in the first request queue and the DMA requests in the second request queue are cached to the positions corresponding to the target address information in the first target request queue, respectively, and the valid bit of the position corresponding to the target address information in the first target request queue is set to valid; or, when the DMA requests in the first request queue and the DMA requests in the second request queue do not include DMA requests with the same target address information, and the position corresponding to the target address information in the first target request queue includes a valid DMA request, the DMA requests in the first request queue continue to be cached in the first request queue, and / or the DMA requests in the second request queue continue to be cached in the second request queue.

[0066] Alternatively, if Figure 4As shown, it is assumed that the first request queue includes the following DMA requests: the priority information of DMA request 1-1 is f, and the target address information is 0, and the second request queue includes the following DMA requests: the priority information of DMA request 1-2 is 0, and the target address information is 0, the priority information of DMA request 1-3 is 1, and the target address information is 1, and the priority information of DMA request 1-4 is 1, and the target address information is 2 (the above four DMA requests are all issued by the same data processing object). First, filter out the DMA requests with the same target address information: DMA request 1-1 and DMA request 1-2, and then check whether there is a valid DMA request at the position with target address information 0 in the first target request queue. If not, cache the DMA request 1-1 with high priority information to position 0, and set the valid bit of the position to 1. If it exists, continue to cache DMA request 1-1 and DMA request 1-2 in the first request queue and the second request queue respectively. For DMA requests 1-3 and DMA requests 1-4 with different target address information, directly check whether there is a valid DMA request at the location of the target address information in the second request queue. If not, cache the DMA request to that location in sequence and set the valid bit of that location to 1. If so, continue to cache the DMA request in the second request queue.

[0067] This embodiment distributes requests sent to different DMA controllers and arbitrates the DMA request with the highest priority according to the priority during distribution, thereby achieving the purpose of ensuring that the DMA request with the highest priority is always responded to.

[0068] In an exemplary embodiment, a second arbitration operation is performed on the first target request queue and the second target request queue to obtain a third target request queue, including: performing a screening operation on the DMA requests in the first target request queue and the DMA requests in the second target request queue according to the target address information of the DMA request to obtain multiple third DMA requests, wherein the target address information corresponding to the third DMA requests are all the same; performing the second arbitration operation on the multiple third DMA requests according to the identification information of the data processing object and / or the priority information of the third DMA request, and caching the multiple third DMA requests after performing the second arbitration operation into the third target request queue.

[0069] In an exemplary embodiment, the second arbitration operation is performed on the plurality of third DMA requests according to the identification information and / or priority information of the data processing object, and the plurality of third DMA requests after the second arbitration operation is performed are cached in the third target request queue, including: when the plurality of priority information included in the plurality of third DMA requests are different, the plurality of third DMA requests are cached in the third target request queue according to the sorting method between the plurality of priority information; or, when the plurality of priority information included in the plurality of third DMA requests are the same, the plurality of third DMA requests are cached in the third target request queue according to the sorting method between the identification information of the data processing object.

[0070] Alternatively, if Figure 5 As shown, it is assumed that the first target request queue includes the following DMA requests: the priority information of DMA request 1-1 is f, the target address information is 0, and the identification information is 1; the priority information of DMA request 1-2 is 1, the target address information is 1, and the identification information is 1 (the above two DMA requests are both issued by the same data processing object), and the second target request queue includes the following DMA requests: the priority information of DMA request 2-1 is 0, the target address information is 0, and the identification information is 2; the priority information of DMA request 2-2 is 1, the target address information is 1, and the identification information is 2 (the above two DMA requests are both issued by the same data processing object). First, filter out DMA requests with the same target address information to obtain the third DMA request: DMA request 1-1, DMA request 2-1 (target address information is 0), DMA request 1-2, DMA request 2-2 (target address information is 1), then check the priority of DMA request 1-1 and DMA request 2-1, cache DMA request 1-1 and DMA request 2-1 in the order of priority information from high to low to the third target request queue; because DMA request 1-2 and DMA request 2-2 have the same priority, cache DMA request 1-2 and DMA request 2-2 in the order of identification information from low to high to the third target request queue, that is, the final DMA request order in the third target request queue is: DMA request 1-1, DMA request 2-1, DMA request 1-2, DMA request 2-2.

[0071] This embodiment implements the purpose of responding to DMA requests in a timely and efficient manner by performing the second arbitration operation on DMA requests between different data processing objects.

[0072] In an exemplary embodiment, the third target request queue is sent to a target DMA controller to instruct the target DMA controller to respond to the multiple DMA requests in the order of arrangement of the multiple DMA requests included in the third target request queue, including: according to the target address information of the DMA request, sending the multiple DMA requests in the third target request queue to the target DMA controller according to the order of arrangement, wherein the identification information of the target DMA controller is in a one-to-one correspondence with the target address information; and controlling the target DMA controller to execute the multiple DMA requests in the order of sending.

[0073] Optionally, assuming that the priority information of DMA request 1-1 is f, the target address information is 0, and the identification information is 1, the priority information of DMA request 1-2 is 1, the target address information is 1, and the identification information is 1 (both of the above two DMA requests are issued by the same data processing object), the priority information of DMA request 2-1 is 0, the target address information is 0, and the identification information is 2, and the priority information of DMA request 2-2 is 1, the target address information is 1, and the identification information is 2 (both of the above two DMA requests are issued by the same data processing object). Finally, the order of DMA requests in the third target request queue is: DMA request 1-1, DMA request 2-1, DMA request 1-2, DMA request 2-2, and according to the target address information of the DMA request, it is sent in sequence to: DMA_1 controller, DMA_0 controller, DMA_1 controller, DMA_0 controller. This embodiment achieves the purpose of ensuring that the current highest priority DMA request is always responded to by distributing the requests sent to different DMA controllers and arbitrating the DMA request with the highest priority according to the priority when distributing.

[0074] In an exemplary embodiment, the DMA control device further includes a storage device, and the DMA control device is connected to the data processing device and the storage device. After sending the third target request queue to the target DMA controller to instruct the target DMA controller to respond to the multiple DMA requests in the order of arrangement of the multiple DMA requests included in the third target request queue, the method further includes: sending the execution status of the multiple DMA requests to the storage device; when the data processing device obtains the execution status of the DMA request from the storage device according to the polling method and / or interrupt feedback method of the register in the feedback queue, the feedback queue is used to obtain the execution status of the multiple DMA requests from the storage device, and the execution status of the multiple DMA requests is sent to the data processing device.

[0075] Alternatively, if Figure 3As shown, the DMA control device also includes a storage device, the storage device obtains the execution status of DMA requests executed by DMA_1...DMA_N, and the data processing device obtains the DMA request execution status from the storage device based on the feedback queue. The feedback queue is usually composed of a number of registers and interrupts, which are used to feedback the execution status of the DMA request. The data processing device can select the polling method of the register or the interrupt feedback method according to the demand, and obtain the DMA request execution status through the feedback queue. This embodiment achieves the purpose of flexible feedback of the DMA request execution status by supporting interrupt triggering and polling methods.

[0076] In an exemplary embodiment, the data processing device includes a plurality of data processing objects, and before performing a first arbitration operation on a first request queue and a second request queue of a first data processing object to obtain a first target request queue, the method further includes: configuring the number of request queues and target request queues according to the number of the data processing objects and the number of the DMA controllers, wherein the request queue includes the first request queue and the second request queue, and the target request queue includes the first target request queue and the second target request queue; configuring the cache space of the request queue and the target request queue according to the number of the DMA controllers; and setting the trigger conditions for the request queue and the target request queue to receive the DMA request, wherein the trigger conditions include the remaining cache space of the request queue and the target request queue, and the running status of the DMA controller.

[0077] Optionally, before performing the arbitration operation, it is necessary to configure the number of request queues and target request queues and the cache space and bind the relationship between the data processing object and the request queue and the target request queue. Specifically, assuming that the data processing objects have 2 CPU1 and CPU2 and there are 4 DMA controllers, the number of request queues can be 2-4, and the number of target request queues can be 2-4. If the number of request queues and target request queues is 2, the binding relationship can be CPU1-request queue 1-target request queue 1, CPU2-request queue 2-target request queue 2. If the number of request queues and target request queues is 3, the binding relationship can be CPU1-request queue 1, 2-target request queue 1, 2, CPU2-request queue 3-target request queue 3.

[0078] Optionally, the number of arbitrators may be the same as the cache space of the request queue and the target queue, specifically the same as the number of the request queue and the target request queue.

[0079] The present application is described below in conjunction with specific embodiments: Figure 6 is a flow chart of a method for responding to a DMA request according to a specific embodiment of the present application, such as Figure 6 As shown, the specific steps include:

[0080] S602, initialize the number of request queues and target request queues and cache space according to the number of data processing objects and the number of DMA controllers: assuming that the data processing objects have 2 CPU1 and CPU2, and there are 4 DMA controllers, configure request queue 1, request queue 2, target request queue 1, target request queue 2, and the number of cache spaces is 2.

[0081] S604, bind the data processing object with the interface of the request queue and the target request queue: the binding relationship may be CPU1-request queue 1-target request queue 1, CPU2-request queue 2-target request queue 2.

[0082] S606, reset and cancel. After reset and cancel, the above configuration will take effect.

[0083] S608, setting the interrupt triggering conditions of the request queue and the target request queue. The configurable conditions include: the remaining buffer space threshold of the request queue and the target request queue, the DMA request execution status, etc., and enabling the interrupt switch.

[0084] S610, the data processing device reads the amount of remaining cache space in the request queue and the target request queue to determine whether a new request can be accepted: assuming that the amount of remaining cache space in the request queue and the target request queue is greater than 0, the new request can be accepted.

[0085] S612, setting the priority information of the direct memory access request, usually 0 / 1 / 2 / 3 / f, the larger the value, the higher the priority: the priority information of DMA request 1-1 is f, the target address information is 0, and the identification information is 1.

[0086] S614 , sending a direct memory access request: assuming that the priority information of the first DMA request 1 - 1 is f, the target address information is 0, and the identification information is 1.

[0087] S616, execute the first arbitration operation: the priority information of the first DMA request 1-1 is f, which is the queue-jumping information, and is cached to position 0 of the first request queue, and the valid bit of position 0 is set to 1; assuming that there is a DMA request 1-2 in the second request queue with a valid bit of 1, a target address information of 2, a priority information of 3, and an identification information of 1; since the target address information of DMA request 1-2 and the first DMA request 1-1 are different, there is no DMA request at positions 0 and 2 in the second request queue, so according to the target address information, DMA request 1-2 and the first DMA request 1-1 are cached to positions 0 and 2 in turn, and the valid bits of positions 0 and 2 are set to 1, to obtain the first target request queue.

[0088] S618, perform a second arbitration operation: Assume that the first target request queue includes the following DMA requests: the priority information of the first DMA request 1-1 is f, the target address information is 0, and the identification information is 1; the priority information of the DMA request 1-2 is 3, the target address information is 2, and the identification information is 1; the second target request queue includes the following DMA requests: the priority information of the DMA request 2-1 is f, the target address information is 0, and the identification information is 2. First, filter out the DMA requests with the same target address information to obtain the third DMA request: the first DMA request 1-1, the DMA request 2-1 (the target address information is 0), and then check the priorities of the DMA request 1-1 and the DMA request 2-1. Because the priorities of the DMA request 1-2 and the DMA request 2-2 are the same, the DMA request 1-2 and the DMA request 2-2 are cached in the third target request queue in the order of the identification information from low to high, that is, the final DMA request order in the third target request queue is: the first DMA request 1-1, the DMA request 2-1, and the DMA request 1-2.

[0089] S620, sending the arbitrated DMA request 1-1, DMA request 2-1, and DMA request 1-2 to the corresponding DMA controller to execute the DMA request and perform the next round of arbitration.

[0090] S622, the feedback queue is usually composed of several registers and interrupts, and is used to feedback the execution status of the DMA request. The data processing device can select the register polling method or the interrupt feedback method according to the demand, and obtain the DMA request execution status through the feedback queue.

[0091] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0092] In this embodiment, a device for responding to DMA requests is also provided, which is applied to a DMA control device, wherein the DMA control device includes multiple DMA controllers, and the DMA control device is connected to a data processing device. The device is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware for a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0093] Figure 7 is a structural block diagram of a device for responding to a DMA request according to an embodiment of the present application, such as Figure 7 As shown, the device comprises:

[0094] A first execution module 702 is used to perform a first arbitration operation on a first request queue and a second request queue of a first data processing object to obtain a first target request queue, wherein the first request queue and the second request queue are both request queues created for the first data processing object, and an arrangement method of the first request queue is different from an arrangement method of the second request queue, the first arbitration operation is used to sort the DMA requests in the first request queue and the DMA requests in the second request queue, and the first data processing object is any one of a plurality of data processing objects included in the data processing device;

[0095] A second execution module 704 is used to perform a second arbitration operation on the first target request queue and the second target request queue to obtain a third target request queue, wherein the second target request queue is a queue after the first arbitration operation is performed on one or more third request queues of a second data processing object, the second data processing object is any other processing object among the multiple data processing objects except the first data processing object, and the second arbitration operation is used to sort the DMA requests in the first target request queue and the DMA requests in the second target request queue;

[0096] The first sending module 706 is used to send the above-mentioned third target request queue to the target DMA controller to instruct the above-mentioned target DMA controller to respond to the multiple DMA requests according to the arrangement order of the multiple DMA requests included in the above-mentioned third target request queue, wherein the multiple DMA requests include all the DMA requests in the above-mentioned first target request queue and the above-mentioned second target request queue, and the above-mentioned target DMA controller is any DMA controller among the above-mentioned multiple DMA controllers.

[0097] In an exemplary embodiment, the device further includes: a first receiving module, configured to perform a first arbitration operation on a first request queue and a second request queue of a first data processing object, and receive a first DMA request sent by the first data processing object before obtaining the first target request queue; a first caching module, configured to cache the first DMA request in the first request queue or the third request queue according to the first request information included in the first DMA request, wherein the first request information includes identification information of the first data processing object, priority information of the first DMA request and target address information of the first DMA request, and the priority information of the DMA requests in the third request queue is different from that in the first request queue; a third execution module, configured to perform a third arbitration operation on the DMA requests in the third request queue, so as to cache the DMA requests in the third request queue in the second request queue, wherein the third arbitration operation is used to filter the DMA requests in the third request queue according to the target address information and the priority information.

[0098] In an exemplary embodiment, the first cache module includes: a first cache submodule, which is used to cache the first DMA request to a position in the first request queue corresponding to the queue interruption position in the queue interruption information according to the target address information when the priority information is queue interruption information, and set the valid bit of the position in the first request queue corresponding to the queue interruption position to valid; or, a second cache submodule, which is used to cache the first DMA request to a position in the third request queue corresponding to the preset priority according to the preset priority when the priority information is a preset priority, and set the valid bit of the position in the third request queue corresponding to the preset priority to valid.

[0099] In an exemplary embodiment, the third execution module includes: a first execution submodule, used to perform a screening operation on the DMA requests in the third request queue according to the target address information to obtain multiple second DMA requests, wherein the target address information of the multiple second DMA requests are the same; a third cache submodule, used to continue to cache the multiple second DMA requests in the third request queue when the second request queue includes a DMA request having the same target address information as the second DMA request; and a fourth cache submodule, used to cache the DMA request with the highest priority among the multiple second DMA requests to a position in the second request queue corresponding to the target address information when there is no DMA request having the same target address information as the second DMA request in the second request queue, and set the valid bit of the position in the second request queue corresponding to the target address information to valid.

[0100] In an exemplary embodiment, the first execution module comprises: a fifth cache submodule for caching the first target DMA request to the position corresponding to the target address information in the first target request queue, and setting the valid bit of the position corresponding to the target address information in the first target request queue to valid, when the DMA requests in the first request queue and the DMA requests in the second request queue include a first target DMA request with the same target address information, and the position corresponding to the target address information in the first target request queue does not include a valid DMA request; or, a sixth cache submodule for continuing to cache the second target DMA request in the first request queue and the second request queue, respectively, when the DMA requests in the first request queue and the DMA requests in the second request queue include a second target DMA request with the same target address information, and the position corresponding to the target address information in the first target request queue includes a valid DMA request.

[0101] In an exemplary embodiment, the first execution module comprises: a seventh cache submodule for caching the DMA requests in the first request queue and the DMA requests in the second request queue to the positions corresponding to the target address information in the first target request queue, respectively, and setting the valid bit of the position corresponding to the target address information in the first target request queue to valid, if the DMA requests in the first request queue and the DMA requests in the second request queue do not include DMA requests with the same target address information, and the position corresponding to the target address information in the first target request queue does not include a valid DMA request; or, an eighth cache submodule for continuing to cache the DMA requests in the first request queue in the first request queue, and / or continuing to cache the DMA requests in the second request queue in the second request queue, if the DMA requests in the first request queue and the DMA requests in the second request queue do not include DMA requests with the same target address information, and the position corresponding to the target address information in the first target request queue includes a valid DMA request.

[0102] In an exemplary embodiment, the second execution module includes: a first screening submodule, used to perform screening operations on the DMA requests in the first target request queue and the DMA requests in the second target request queue according to the target address information of the DMA request, so as to obtain multiple third DMA requests, wherein the target address information corresponding to the third DMA requests are all the same; a ninth cache submodule, used to perform the second arbitration operation on the multiple third DMA requests according to the identification information of the data processing object and / or the priority information of the third DMA request, and cache the multiple third DMA requests after the second arbitration operation is performed into the third target request queue.

[0103] In an exemplary embodiment, the ninth cache submodule comprises: a first cache unit for caching the plurality of third DMA requests into the third target request queue according to the sorting method between the plurality of priority information included in the plurality of third DMA requests when the plurality of priority information included in the plurality of third DMA requests are different; or, a second cache unit for caching the plurality of third DMA requests into the third target request queue according to the sorting method between the identification information of the data processing objects when the plurality of priority information included in the plurality of third DMA requests are the same.

[0104] In an exemplary embodiment, the above-mentioned first sending module includes: a first sending sub-module, used to send the multiple DMA requests in the above-mentioned third target request queue to the above-mentioned target DMA controller according to the above-mentioned arrangement order according to the target address information of the above-mentioned DMA request, wherein the identification information of the above-mentioned target DMA controller and the above-mentioned target address information are in a one-to-one correspondence; a second execution sub-module, used to control the above-mentioned target DMA controller to execute the multiple above-mentioned DMA requests in the sending order.

[0105] In an exemplary embodiment, the DMA control device further includes a storage device, the DMA control device is connected to the data processing device and the storage device, and the device further includes: a second sending module, used to send the third target request queue to the target DMA controller to instruct the target DMA controller to respond to the multiple DMA requests according to the arrangement order of the multiple DMA requests included in the third target request queue, and then send the execution status of the multiple DMA requests to the storage device; a first acquisition module, used to obtain the execution status of the multiple DMA requests from the storage device using the feedback queue when the data processing device obtains the execution status of the DMA requests from the storage device according to the polling method and / or interrupt feedback method of the register in the feedback queue, and send the execution status of the multiple DMA requests to the data processing device.

[0106] In an exemplary embodiment, the data processing device includes a plurality of data processing objects, and the apparatus further includes: a first configuration module, for performing a first arbitration operation on a first request queue and a second request queue of a first data processing object, and configuring the number of request queues and target request queues according to the number of the data processing objects and the number of the DMA controllers before obtaining the first target request queue, wherein the request queue includes the first request queue and the second request queue, and the target request queue includes the first target request queue and the second target request queue; a second configuration module, for configuring the cache space of the request queue and the target request queue according to the number of the DMA controllers; and setting the trigger conditions for the request queue and the target request queue to receive the DMA request, wherein the trigger conditions include the remaining cache space of the request queue and the target request queue, and the running status of the DMA controller.

[0107] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0108] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0109] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0110] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0111] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0112] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above method embodiments are implemented.

[0113] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0114] The embodiments of the present application also provide a computer program, which includes computer instructions stored in a computer-readable storage medium; a processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the steps of any one of the above method embodiments.

[0115] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0116] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0117] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for responding to a DMA request, characterized in that: Applied to a DMA control device, the DMA control device includes a plurality of DMA controllers, the DMA control device is connected to a data processing device, and the method includes: Performing a first arbitration operation on a first request queue and a second request queue of a first data processing object to obtain a first target request queue, wherein the first request queue and the second request queue are both request queues created for the first data processing object, and a sorting method of the first request queue is different from a sorting method of the second request queue, the first arbitration operation is used to sort DMA requests in the first request queue and DMA requests in the second request queue, and the first data processing object is any one of a plurality of data processing objects included in the data processing device; Performing a second arbitration operation on the first target request queue and the second target request queue to obtain a third target request queue, wherein the second target request queue is a queue after the first arbitration operation is performed on one or more request queues of a second data processing object, the second data processing object is any other processing object among the multiple data processing objects except the first data processing object, and the second arbitration operation is used to sort the DMA requests in the first target request queue and the DMA requests in the second target request queue; The third target request queue is sent to a target DMA controller to instruct the target DMA controller to respond to the multiple DMA requests in the order of arrangement of the multiple DMA requests included in the third target request queue, wherein the multiple DMA requests include all the DMA requests in the first target request queue and the second target request queue, and the target DMA controller is any DMA controller among the multiple DMA controllers.

2. The method according to claim 1, characterized in that Before performing a first arbitration operation on the first request queue and the second request queue of the first data processing object to obtain the first target request queue, the method further includes: receiving a first DMA request sent by the first data processing object; caching the first DMA request in the first request queue or the third request queue according to first request information included in the first DMA request, wherein the first request information includes identification information of the first data processing object, priority information of the first DMA request and target address information of the first DMA request, and the priority information of the DMA requests in the third request queue and the DMA requests in the first request queue are different; A third arbitration operation is performed on the DMA requests in the third request queue to cache the DMA requests in the third request queue into the second request queue, wherein the third arbitration operation is used to filter the DMA requests in the third request queue according to the target address information and the priority information.

3. The method according to claim 2, characterized in that Buffering the first DMA request in the first request queue or the third request queue according to the first request information included in the first DMA request includes: In the case where the priority information is queue interruption information, caching the first DMA request to a position in the first request queue corresponding to the queue interruption position in the queue interruption information according to the target address information, and setting a valid bit of a position in the first request queue corresponding to the queue interruption position to valid; or When the priority information is a preset priority, the first DMA request is cached to a position in the third request queue corresponding to the preset priority according to the preset priority, and the valid bit of the position in the third request queue corresponding to the preset priority is set to valid.

4. The method according to claim 2 or 3, characterized in that: Performing a third arbitration operation on the DMA requests in the third request queue to cache the DMA requests in the third request queue into the second request queue includes: According to the target address information, a screening operation is performed on the DMA requests in the third request queue to obtain a plurality of second DMA requests, wherein the target address information of the plurality of second DMA requests are all the same; When the second request queue includes a DMA request having the same target address information as the second DMA request, continue to cache a plurality of the second DMA requests in the third request queue; When there is no DMA request with the same target address information as the second DMA request in the second request queue, the DMA request with the highest priority among the multiple second DMA requests is cached to the position corresponding to the target address information in the second request queue, and the valid bit of the position corresponding to the target address information in the second request queue is set to valid.

5. The method according to claim 1, characterized in that Performing a first arbitration operation on a first request queue and a second request queue of a first data processing object to obtain a first target request queue includes: In a case where the DMA requests in the first request queue and the DMA requests in the second request queue include a first target DMA request having the same target address information, and a position corresponding to the target address information in the first target request queue does not include a valid DMA request, the first target DMA request is cached to a position corresponding to the target address information in the first target request queue, and a valid bit of the position corresponding to the target address information in the first target request queue is set to valid; or, When the DMA requests in the first request queue and the DMA requests in the second request queue include a second target DMA request with the same target address information, and the position corresponding to the target address information in the first target request queue includes a valid DMA request, the second target DMA request continues to be cached in the first request queue and the second request queue, respectively.

6. The method according to claim 1, characterized in that Performing a first arbitration operation on a first request queue and a second request queue of a first data processing object to obtain a first target request queue includes: In the case where the DMA requests in the first request queue and the DMA requests in the second request queue do not include DMA requests with the same target address information, and the position corresponding to the target address information in the first target request queue does not include a valid DMA request, the DMA requests in the first request queue and the DMA requests in the second request queue are cached to the positions corresponding to the target address information in the first target request queue, respectively, and the valid bit of the position corresponding to the target address information in the first target request queue is set to valid; or When the DMA requests in the first request queue and the DMA requests in the second request queue do not include DMA requests having the same target address information, and the position corresponding to the target address information in the first target request queue includes a valid DMA request, the DMA requests in the first request queue continue to be cached in the first request queue, and / or the DMA requests in the second request queue continue to be cached in the second request queue.

7. The method according to claim 1, characterized in that Performing a second arbitration operation on the first target request queue and the second target request queue to obtain a third target request queue includes: According to the target address information of the DMA request, a screening operation is performed on the DMA requests in the first target request queue and the DMA requests in the second target request queue to obtain a plurality of third DMA requests, wherein the target address information corresponding to the third DMA requests are all the same; According to the identification information of the data processing object and / or the priority information of the third DMA request, the second arbitration operation is performed on the multiple third DMA requests, and the multiple third DMA requests after the second arbitration operation are cached in the third target request queue.

8. The method according to claim 7, characterized in that The method further comprises: performing the second arbitration operation on the plurality of third DMA requests according to the identification information and / or priority information of the data processing object, and caching the plurality of third DMA requests after performing the second arbitration operation into the third target request queue, comprising: In the case where the plurality of priority information included in the plurality of third DMA requests are different, the plurality of third DMA requests are cached in the third target request queue according to the sorting manner between the plurality of priority information; or, In the case that the plurality of priority information included in the plurality of third DMA requests are all the same, the plurality of third DMA requests are cached in the third target request queue according to the ordering between the identification information of the data processing objects.

9. The method according to claim 1, characterized in that: Sending the third target request queue to a target DMA controller to instruct the target DMA controller to respond to the multiple DMA requests according to the arrangement order of the multiple DMA requests included in the third target request queue, comprising: According to the target address information of the DMA request, sending the multiple DMA requests in the third target request queue to the target DMA controller according to the arrangement order, wherein the identification information of the target DMA controller and the target address information are in a one-to-one correspondence; The target DMA controller is controlled to execute the plurality of DMA requests in a sending order.

10. The method according to claim 1 or 9, characterized in that: The DMA control device further includes a storage device, the DMA control device is connected to the data processing device and the storage device, and after sending the third target request queue to the target DMA controller to instruct the target DMA controller to respond to the plurality of DMA requests according to the arrangement order of the plurality of DMA requests included in the third target request queue, the method further includes: Sending the execution status of the plurality of DMA requests to the storage device; When the data processing device obtains the execution status of the DMA request from the storage device according to the polling method and / or interrupt feedback method of the register in the feedback queue, the feedback queue is used to obtain the execution status of multiple DMA requests from the storage device, and the execution status of multiple DMA requests is sent to the data processing device.

11. The method according to claim 1, characterized in that: The data processing device includes a plurality of data processing objects. Before performing a first arbitration operation on a first request queue and a second request queue of a first data processing object to obtain a first target request queue, the method further includes: According to the number of the data processing objects and the number of the DMA controllers, the number of request queues and the number of target request queues are configured, wherein the request queue includes the first request queue and the second request queue, and the target request queue includes the first target request queue and the second target request queue; According to the number of the DMA controllers, configuring the cache space of the request queue and the target request queue; A trigger condition for the request queue and the target request queue to receive the DMA request is set, wherein the trigger condition includes remaining cache space of the request queue and the target request queue, and an operating state of a DMA controller.

12. A DMA control device, characterized in that: The DMA control device includes a plurality of DMA controllers, the DMA control device is connected to a data processing device, and the DMA control device is used to implement the steps of the method described in any one of claims 1 to 11.

13. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method described in any one of claims 1 to 11 are implemented.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in any one of claims 1 to 11 when executed by a processor.

15. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the method described in any one of claims 1 to 11 are implemented.

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