Display system and method for time-division multiplexing of control signals

Abstract

The present application relates to a display system and method for time-sharing multiplexing of control signals. The display system includes: a main controller for generating a clock signal, storing initial data and generating marked pixel data; a pixel display chip, each of which is connected to the main controller and is used to generate a pixel drive signal based on the clock signal and the marked pixel data; a pixel unit, which is connected to the pixel display chip and is used to light up the pixel unit corresponding to the pixel drive signal based on the pixel drive signal. The present application can greatly reduce the number of pins used in the main controller by using the time-sharing multiplexing technology of pins between the main controller and the pixel display chip, so that one main controller can drive a larger number of pixel display chips, or a more economical main controller with fewer pins can be selected, thereby achieving the effect of driving each pixel unit to light up multiple times, for a long lighting time and at a high refresh rate at a lower economic cost.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display system and method for time-division multiplexing of control signals. Background Art

[0002] Large-screen display technology is becoming more and more widely used in modern applications, especially in large-scale indoor and outdoor advertising, exhibitions, sports events and other fields. Generally, a large-screen display is composed of multiple display modules spliced ​​together, which are installed on the steel structure through connectors to form the entire display system. Large-screen display technology also includes aspects such as drive communication, signal transmission, and display content management of display modules. Drive communication between display modules is the basis for the normal operation of the display system, ensuring the synchronization and unity between each module. At the same time, the stability and speed of signal transmission are also important factors to ensure the display effect, which needs to be achieved through appropriate signal transmission methods and technologies.

[0003] In the related art, the system controls the on and off state of each pixel row by row and column by column. After a quick scan, the state of all pixels will present a complete image.

[0004] However, in the above-mentioned related technologies, due to the lack of storage structure, each pixel can only be lit once in one frame time, which has the disadvantages of short time and low refresh rate. For large display screens with independent chip control for each pixel and built-in storage structure, each pixel is lit multiple times, the time is long, the refresh rate is high, and the display effect is better than that of traditional large display screens, but the number of pins of the main controller is very high, and there are disadvantages such as high requirements for the selection of the main controller and high economic cost of the entire system. Summary of the invention

[0005] Based on this, it is necessary to provide a method for solving the above technical problems by adding 1+2 j The design of the pins can greatly reduce the number of pins used in the main controller, so that one main controller can drive a larger number of pixel display chips, or a more economical main controller with a smaller number of pins can be selected, thereby achieving a display system, method, device, computer equipment, computer-readable storage medium and computer program product that uses time-sharing multiplexing of control signals to achieve the same large-screen display resolution and refresh rate, the same large-screen display clarity and color saturation effect at a lower economic cost.

[0006] In a first aspect, the present application provides a display system for time-division multiplexing of control signals, the display system comprising:

[0007] A main controller, used to generate a clock signal, store initial data and generate marked pixel data;

[0008] A pixel display chip, each of which is connected to the main controller and is used to generate a pixel driving signal based on the clock signal and the marked pixel data;

[0009] A pixel unit is connected to the pixel display chip and is used to light up the pixel unit corresponding to the pixel driving signal based on the pixel driving signal.

[0010] In one embodiment, the pixel display chip includes an input pin and an output pin, the main controller includes an output pin, the input pin of the pixel display chip includes a clock signal pin and a serial data pin, and the output pin of the main controller includes a clock signal pin and a serial data pin;

[0011] The clock signal pin of the pixel display chip is connected to the clock signal pin of the main controller;

[0012] The serial data pin of the pixel display chip is connected to the serial data pin of the main controller;

[0013] The output pin of the pixel display chip is connected to the pixel unit.

[0014] In one embodiment, a first pin quantity mapping relationship is set between the main controller and the pixel display chip, and the first pin quantity mapping relationship is:

[0015] In the case where the pixel display chip is provided with a*b pins, the main controller provides a+b pins, wherein a is the number of rows and b is the number of columns.

[0016] In one embodiment, the input pins of the pixel display chip further include a row chip select pin and a column chip select pin, the row chip select pin and the column chip select pin are both connected to the main controller, and a second pin quantity mapping relationship is further provided between the main controller and the pixel display chip, and the second pin quantity mapping relationship is:

[0017] In the case where each pixel display chip is added with a row chip selection pin, the main controller provides a / 2+b pins;

[0018] In the case where each pixel display chip is further provided with j column chip selection pins, the main controller provides (a / 2+b / 2 j ) pins.

[0019] In one embodiment, each row of the pixel display chip is provided with two data transmission modes, and the two data transmission modes are respectively:

[0020] When the row chip select pin is connected to the power supply, the pixel display chip samples data when the clock signal is at a rising edge; when the row chip select pin is grounded, the pixel display chip samples data when the clock signal is at a falling edge; or

[0021] When the row chip select pin is connected to the power supply, the pixel display chip samples data when the clock signal is at a falling edge; when the row chip select pin is grounded, the pixel display chip samples data when the clock signal is at a rising edge.

[0022] In one of the embodiments, when the row chip select pins of a row of the pixel display chips are connected to a power source, the row chip select pins of the pixel display chips of an adjacent row are grounded.

[0023] In one of the embodiments, when the column chip select pins of the pixel display chips in one column are connected to a power source, the column chip select pins of the pixel display chips in an adjacent column are grounded.

[0024] In one embodiment, the pixel display chip data has two data transmission schemes, and the two data transmission schemes are:

[0025] When the column chip select pin is connected to the power supply, the pixel units connected to the pixel display chips in the odd columns receive data; when the column chip select pin is grounded, the pixel units connected to the pixel display chips in the even columns receive data; or

[0026] When the column chip select pin is connected to the power supply, the pixel units connected to the pixel display chips in the even columns receive data; when the column chip select pin is grounded, the pixel units connected to the pixel display chips in the odd columns receive data.

[0027] In a second aspect, the present application provides a display method for time-division multiplexing of control signals, which is applicable to the display system for time-division multiplexing of control signals described in any of the above embodiments. The display method includes:

[0028] Generate a clock signal, store initial data and generate labeled pixel data;

[0029] generating a pixel driving signal based on the clock signal and the marked pixel data;

[0030] The pixel unit corresponding to the pixel driving signal is lit based on the pixel driving signal.

[0031] In one embodiment, the generating a pixel driving signal based on the clock signal and the marked pixel data comprises:

[0032] Determine a target row of pixel units based on the clock signal;

[0033] Determine a target column pixel unit based on the marked pixel data;

[0034] A pixel driving signal is generated based on the target row pixel unit and the target column pixel unit.

[0035] In a third aspect, the present application further provides a display device for time-division multiplexing of control signals, comprising:

[0036] A control module, used for generating a clock signal, storing initial data and generating marked pixel data;

[0037] A signal generating module, configured to generate a pixel driving signal based on the clock signal and the marked pixel data;

[0038] The display module is used to light up the pixel unit corresponding to the pixel driving signal based on the pixel driving signal.

[0039] In a fourth aspect, the present application further provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0040] Generate a clock signal, store initial data and generate labeled pixel data;

[0041] generating a pixel driving signal based on the clock signal and the marked pixel data;

[0042] The pixel unit corresponding to the pixel driving signal is lit based on the pixel driving signal.

[0043] In a fifth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the following steps are implemented:

[0044] Generate a clock signal, store initial data and generate labeled pixel data;

[0045] generating a pixel driving signal based on the clock signal and the marked pixel data;

[0046] The pixel unit corresponding to the pixel driving signal is lit based on the pixel driving signal.

[0047] In a sixth aspect, the present application further provides a computer program product, including a computer program, which implements the following steps when executed by a processor:

[0048] Generate a clock signal, store initial data and generate labeled pixel data;

[0049] generating a pixel driving signal based on the clock signal and the marked pixel data;

[0050] The pixel unit corresponding to the pixel driving signal is lit based on the pixel driving signal.

[0051] The above-mentioned display system, method, device, computer equipment, computer-readable storage medium and computer program product for time-sharing multiplexing of control signals connect a main controller to a pixel display chip, generate marked pixel data with a mark bit through the original data stored in the main controller, and then the pixel display chip determines the target row pixel unit based on the received clock signal and receives the marked pixel data, and then determines the target column pixel unit through the mark bit identification of the received marked pixel data, so that the target column pixel unit receives data in time-sharing, and the pixel display chip drives the target row pixel unit and the target column pixel unit according to the marked pixel data, thereby realizing that one main controller drives multiple pixel display chips, and realizes the effect of driving each pixel unit to light up multiple times, with a long lighting time and a high refresh rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0053] Figure 1 A structural block diagram of a display system for time-division multiplexing of control signals in one embodiment;

[0054] Figure 2 A connection diagram of a display system for time-division multiplexing of control signals in one embodiment;

[0055] Figure 3 A schematic diagram of a data structure of a display system for time-division multiplexing of control signals in one embodiment;

[0056] Figure 4 A schematic diagram of a data structure of a display system for time-division multiplexing of control signals in another embodiment;

[0057] Figure 5 A schematic diagram of a flow chart of a display method for time-division multiplexing of control signals in one embodiment;

[0058] Figure 6 A structural block diagram of a display device for time-division multiplexing of control signals in one embodiment;

[0059] Figure 7FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment.

[0060] Description of reference numerals:

[0061] data_clk: clock signal; coloum_data: serial data; col_data: serial data; Row_sel: row chip select; Coloum_sel: column chip select; VCC: power supply; GND: ground; R: drives red lamp beads; G: drives green lamp beads; B: drives blue lamp beads. DETAILED DESCRIPTION

[0062] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0063] In one embodiment, Figure 1 The above provides a display system for time-division multiplexing of control signals. The display system for time-division multiplexing of control signals includes a main controller 102, a pixel display chip 104 and a pixel unit 106, wherein the main controller 102 is connected to the pixel display chip 104, and the pixel display chip 104 is connected to the pixel unit 106. The main controller 102 stores original data and generates new data with a mark bit, i.e., marked pixel data, and generates a clock signal. The pixel display chip (i.e., a single pixel display chip) 104 receives the clock signal and receives the corresponding marked pixel data based on the clock signal, and then the pixel display chip 104 determines the pixel unit 106 to be driven according to the mark in the marked pixel data and generates the corresponding pixel drive signal. The pixel unit 106, i.e., a single pixel lamp bead, receives the pixel drive signal transmitted by the pixel display chip and lights up the corresponding single pixel lamp bead.

[0064] The main controller is connected to a plurality of pixel display chips arranged according to certain rules. The main controller can be an FPGA (Field Programmable Gate Array), an IC (integrated circuit) or other controllers. There is at least one main controller, and there are at least two pixel display chips, and the number of types is an even number. The light-emitting material of the pixel unit can be, but is not limited to, liquid crystal, LED (Light Emitting Diode), OLED (Organic Light Emitting Diode), micro LED (Micro LED) and Q-LED (Quantum Dot LED).

[0065] In the above-mentioned display system with time-sharing multiplexing of control signals, a main controller is connected to a pixel display chip, and marked pixel data with a mark bit is generated through the original data stored in the main controller. Then, the pixel display chip determines the target row pixel unit based on the received clock signal and receives the marked pixel data. Thereafter, the target column pixel unit is determined through the mark bit identification of the received marked pixel data, so that the target column pixel unit receives data in time-sharing. The pixel display chip drives the target row pixel unit and the target column pixel unit according to the marked pixel data, thereby realizing the effect of one main controller driving multiple pixel display chips, and driving each pixel unit to light up multiple times, with a long lighting time and a high refresh rate.

[0066] In an exemplary embodiment, Figure 2 As shown, a connection diagram of a display system for time-division multiplexing of control signals is provided. The pixel display chip in the display system for time-division multiplexing of control signals includes an input pin and an output pin. The input pin of the pixel display chip includes a clock signal pin (i.e., an input clock pin, such as data_clk in the figure) and a serial data pin (such as coloum_data in the figure). The main controller in the display system for time-division multiplexing of control signals includes an output pin. The output pin of the main controller includes a clock signal pin and a serial data pin.

[0067] The clock signal pin of the pixel display chip is connected to the clock signal pin of the main controller, the serial data pin of the pixel display chip is connected to the serial data pin of the main controller, and the output pin of the pixel display chip is connected to the pixel unit.

[0068] In an exemplary embodiment, a first pin quantity mapping relationship is set between the main controller and the pixel display chip. The first pin data mapping relationship is specifically:

[0069] A main controller is connected to a*b pixel display chips. When each pixel display chip only provides a clock signal pin and a serial data pin, the main controller provides a+b pins.

[0070] Among them, a is the number of rows and b is the number of columns.

[0071] In an exemplary embodiment, the input pins of the pixel display chip further include a row chip select pin and a column chip select pin, and both the row chip select pin and the column chip select pin can be connected to the main controller, and a second pin quantity mapping relationship is provided between the main controller and the pixel display chip. The second pin quantity mapping relationship is specifically:

[0072] In the case of adding a row chip select pin to each pixel display chip, the main controller provides a / 2+b pins;

[0073] When j column chip select pins are added to each pixel display chip, the main controller provides (a / 2+b / 2 j ) pins.

[0074] Among them, the row chip select is used to determine whether the pixel display chip receives the mark pixel data output by the main controller at the rising edge or the falling edge of the clock signal and determines whether the odd-numbered row pixel unit or the even-numbered row pixel unit in the display unit is lit, and the column chip select is used to determine whether the odd-numbered column pixel unit or the even-numbered column pixel unit in the display unit is lit. And j column chip select pins are time-division multiplexed to control 2 j is a column pixel unit of period.

[0075] Based on the above functions of row chip select and column chip select, pixel display chips can be divided into 4 basic types, specifically:

[0076] The rising edge of the clock signal receives odd-numbered row and odd-numbered column data;

[0077] The falling edge of the clock signal receives data in even rows and odd columns;

[0078] The rising edge of the clock signal receives odd-numbered row and even-numbered column data;

[0079] The falling edge of the clock signal receives even-row and even-column data.

[0080] In an exemplary embodiment, each row of pixel display chips is provided with two data transmission modes, and the two data transmission modes are specifically:

[0081] When the row chip select pin is connected to the power supply, the pixel display chip samples data when the clock signal is at the rising edge;

[0082] When the row chip select pin is grounded, the pixel display chip samples data when the clock signal is at the falling edge.

[0083] Or the two data transmission methods are:

[0084] When the row chip select pin is connected to the power supply, the pixel display chip samples data when the clock signal is at the falling edge;

[0085] When the row chip select pin is grounded, the pixel display chip samples data when the clock signal is at the rising edge.

[0086] And the pixel display chips in two adjacent rows use the same row selection clock signal, specifically:

[0087] When the rising edge of the clock signal is used for odd-numbered pixel display chips to receive data, the falling edge of the clock signal is used for even-numbered pixel display chips to receive data; at the same time, when the row chip select pin of a row of pixel display chips is connected to the power supply, the row chip select pin of the pixel display chip in the adjacent row is grounded. Figure 2 shown.

[0088] When the column chip select pin of a column of pixel display chips is connected to the power supply, the column chip select pin of the pixel display chips in the adjacent column is grounded. Figure 2 shown.

[0089] In an exemplary embodiment, continue to refer to Figure 2 , pixel display chip data has two data transmission schemes, the two data transmission schemes are:

[0090] In the first solution, when the column chip select pin is connected to the power supply, the pixel unit connected to the odd-numbered column pixel display chip receives data; when the column chip select pin is grounded, the pixel unit connected to the even-numbered column pixel display chip receives data;

[0091] In the second solution, when the column chip select pin is connected to the power supply, the pixel unit connected to the even-numbered column pixel display chip receives data; when the column chip select pin is grounded, the pixel unit connected to the odd-numbered column pixel display chip receives data.

[0092] In an exemplary embodiment, a display system with time-division multiplexing of control signals controls a large display screen with a grayscale depth of m+1 bits, and a pixel display chip of the display system is provided with a row chip select pin and a column chip select pin, such as Figure 3 As shown, a data structure diagram of a display system for time-division multiplexing of control signals is provided, showing the data structure of odd rows and odd columns and even rows and odd columns, and serial single bit (byte) transmission. Among them, serial single byte transmission can send the low bit first or the high bit first; Data_odd_odd flag indicates the mark bit of odd rows and odd columns, 1 indicates that the chip of odd rows and odd columns is enabled, receives data and lights up; Data_even_odd flag indicates the mark bit of even rows and odd columns, 1 indicates that the chip of even rows and odd columns is enabled, receives data and lights up.

[0093] Specifically, in the order of Data_odd_odd R_bit0 (0th bit of red data for pixels in odd rows and odd columns), Data_even_odd R_bit0 (0th bit of red data for pixels in even rows and odd columns), Data_odd_odd R_bit1 (1st bit of red data for pixels in odd rows and odd columns), Data_even_odd R_bit1 (1st bit of red data for pixels in even rows and odd columns), until Data_odd_odd R_bitm (mth bit of red data for pixels in odd rows and odd columns), Data_even_odd R_bitm (mth bit of red data for pixels in even rows and odd columns); then Data_odd_odd G_bit0 (0th bit of green data for pixels in odd rows and odd columns), Data_even_odd G_bit0 (0th bit of green data for pixels in even rows and odd columns), Data_odd_odd G_bit1 (1st bit of green data for pixels in odd rows and odd columns), Data_even_odd The order of Data_odd_odd G_bit1 (the 1st bit of green data for pixels in even rows and odd columns) is followed until Data_odd_odd G_bitm (the mth bit of green data for pixels in odd rows and odd columns) and Data_even_odd G_bitm (the mth bit of green data for pixels in even rows and odd columns); finally, the order of Data_odd_odd B_bit0 (the 0th bit of blue data for pixels in odd rows and odd columns) is followed, Data_even_odd B _bit0 (the 0th bit of blue data for pixels in even rows and odd columns) is followed, Data_odd_odd B _bit1 (the 1st bit of blue data for pixels in odd rows and odd columns) and Data_even_odd B _bit1 (the 1st bit of blue data for pixels in even rows and odd columns) is followed until Data_odd_odd B _bitm (the mth bit of blue data for pixels in odd rows and odd columns) and Data_even_odd B _bitm (the mth bit of blue data for pixels in even rows and odd columns).

[0094] According to the above sequence, data is sent in single bit mode, first sending each bit of red data, then each bit of green data, and finally each bit of blue data. Among them, the pixel data of odd rows and odd columns and even rows and odd columns are sent alternately in sequence, and the corresponding pixel units receive the sequence in turn and light up the pixel units.

[0095] In an exemplary embodiment, a display system with time-division multiplexing of control signals controls a large display screen with a grayscale depth of m+1 bits, and a pixel display chip of the display system is provided with a row chip select pin and a column chip select pin, such as Figure 4As shown, a data structure diagram of a display system with time-division multiplexing of control signals is provided, showing the data structure of odd rows and even columns and even rows and even columns, and serial single bit (byte) transmission; Data_odd_ even flag indicates the mark bit of odd rows and even columns, 0 indicates that the chip of odd rows and even columns is enabled, receives data and lights up; Data_even_ even flag indicates the mark bit of even rows and even columns, 0 indicates that the chip of even rows and even columns is enabled, receives data and lights up.

[0096] Specifically, in the order of Data_odd_ even R_bit0 (0th bit of red data for pixels in odd rows and even columns), Data_even_ even R_bit0 (0th bit of red data for pixels in even rows and even columns), Data_odd_ even R_bit1 (1st bit of red data for pixels in odd rows and even columns), Data_even_ even R_bit1 (1st bit of red data for pixels in even rows and even columns), until Data_odd_ even R_bitm (mth bit of red data for pixels in odd rows and even columns), Data_even_even R_bitm (mth bit of red data for pixels in even rows and even columns); then Data_odd_ even G_bit0 (0th bit of green data for pixels in odd rows and even columns), Data_even_ even G_bit0 (0th bit of green data for pixels in even rows and even columns), Data_odd_ even G_bit1 (1st bit of green data for pixels in odd rows and even columns), Data_even_ evenG_bit1 (the 1st bit of green data for even rows and even columns), until Data_odd_ even G_bitm (the mth bit of green data for pixels in odd rows and even columns), Data_even_ even G_bitm (the mth bit of green data for pixels in even rows and even columns); finally, the order of Data_odd_ even B_bit0 (the 0th bit of blue data for pixels in odd rows and even columns), Data_even_even B _bit0 (the 0th bit of blue data for pixels in even rows and even columns), Data_odd_ even B _bit1 (the 1st bit of blue data for pixels in odd rows and even columns), Data_even_ even B _bit1 (the 1st bit of blue data for pixels in even rows and even columns), until Data_odd_ even B _bitm (the mth bit of blue data for pixels in odd rows and even columns), Data_even_even B _bitm (the mth bit of blue data for pixels in even rows and even columns).

[0097] According to the above sequence, the data transmission order is described. The data is sent in a single bit manner, first sending each bit of the red data, then each bit of the green data, and finally each bit of the blue data. Among them, the pixel data of odd rows and even columns and even rows and even columns are sent alternately in sequence.

[0098] In an exemplary embodiment, taking 1920x1080, 8-bit grayscale depth, and a pixel display chip with a row chip select pin and a column chip select as an example, the data structure is as follows: Data_odd_odd flag represents the flag bit of odd rows and odd columns, 1 represents the chip enable of odd rows and odd columns, receives data and lights up, such as row 1, column 1, row 1, column 3…row 1, column 1919, row 3, column 1, row 3, column 3…row 1079, column 1919; Data_even_oddflag represents the flag bit of even rows and odd columns, 1 represents the chip enable of even rows and odd columns, receives data and lights up, such as row 2, column 1, row 2, column 3…row 2, column 1919, row 4, column 1, row 4, column 3…row 1080, column 1919; according to Data_odd_odd R_bit0, Data_even_odd R_bit0, Data_odd_odd R_bit1, Data_even_odd R_bit1... until Data_odd_odd R_bit7, Data_even_odd R_bit7, then Data_odd_odd G_bit0, Data_even_odd G_bit0, Data_odd_oddG_bit1, Data_even_odd G_bit1... until Data_odd_odd G_bit7, Data_even_odd G_bit7, finally Data_odd_odd B_bit0, Data_even_odd B _bit0, Data_odd_odd B _bit1, Data_even_odd B _bit1... until Data_odd_odd B _bit7, Data_even_odd B _bit7.

[0099] The data structure is as follows: Data_odd_ even flag indicates the flag bit of odd rows and even columns, 0 indicates that the chip of odd rows and even columns is enabled, receives data and lights up, such as row 1, column 2, row 1, column 4…row 1, column 1920, row 3, column 2, row 3, column 4…row 1079, column 1920; Data_even_ even flag indicates the flag bit of even rows and even columns, 0 indicates that the chip of even rows and even columns is enabled, receives data and lights up, such as row 2, column 2, row 4…row 2, column 1920, row 4, column 2, row 4, column 4…row 1080, column 1920; according to Data_odd_even R_bit0, Data_even_ even R_bit0, Data_odd_ even R_bit1, Data_even_ even R_bit1…until Data_odd_ even R_bit7, Data_even_ even R_bit7, then Data_odd_even G_bit0, Data_even_ even G_bit0, Data_odd_ even G_bit1, Data_even_ even G_bit1... until Data_odd_ even G_bit7, Data_even_ even G_bit7, and finally Data_odd_even B_bit0, Data_even_ even B _bit0, Data_odd_ even B _bit1, Data_even_ evenB _bit1...until Data_odd_ even B _bit7, Data_even_ even B _bit7.

[0100] The rising edge of the clock signal is used for data transmission in odd-numbered rows, such as row 1, row 3, row 5, ... row 1079; the falling edge of the clock signal is used for data transmission in even-numbered rows, such as row 2, row 4, row 6, ... row 1080.

[0101] After receiving this data structure, a corresponding driving signal is generated to light up the single-pixel lamp bead, completing the large-screen lighting display.

[0102] In an exemplary embodiment, Figure 5 As shown, a display method for time-division multiplexing of control signals is provided, and the method is applied to Figure 1 The display system for time-division multiplexing of control signals includes the following steps 502 to 506. Among them:

[0103] Step 502, generating a clock signal, storing initial data and generating marked pixel data.

[0104] The marked pixel data is new data with a marked bit.

[0105] Exemplarily, the main controller stores original data and generates new data with a mark bit. The main controller generates a clock signal and outputs the clock signal and the new data with the mark bit to the pixel display chip.

[0106] Step 504: Generate a pixel driving signal based on the clock signal and the marked pixel data.

[0107] Exemplarily, the pixel display chip receives data based on a mapping relationship that is preset as follows:

[0108] When the pixel display chip receives the rising edge of the clock signal, it is determined that the odd-numbered pixel units receive data; when the corresponding clock signal falls, it is determined that the even-numbered pixel units receive data. Or

[0109] When the pixel display chip receives the falling edge of the clock signal, it is determined that the odd-numbered pixel units receive data; when the corresponding clock signal rises, it is determined that the even-numbered pixel units receive data.

[0110] Based on any of the above preset mapping relationships, the pixel display chip receives data, and the pixel display chip identifies the mark bit in the mark pixel data to determine whether the odd column or the even column receives the corresponding data in time-sharing.

[0111] Step 506: Light up the pixel unit corresponding to the pixel driving signal based on the pixel driving signal.

[0112] Exemplarily, after identifying the mark bit, the pixel display chip generates a driving signal that can drive the target row and the target column based on the pixel unit of the determined target row and the pixel unit of the target column, and transmits the driving signal to the corresponding pixel unit, and the pixel unit receiving the data lights up.

[0113] In this embodiment, the main controller is connected to the pixel display chip, and marked pixel data with a mark bit is generated through the original data stored in the main controller. Then, the pixel display chip determines the target row pixel unit based on the received clock signal and receives the marked pixel data. Thereafter, the target column pixel unit is determined by identifying the mark bit of the received marked pixel data, so that the target column pixel unit receives data in a time-sharing manner. The pixel display chip drives the target row pixel unit and the target column pixel unit according to the marked pixel data, thereby realizing one main controller driving multiple pixel display chips, and realizing the effect of driving each pixel unit to light up multiple times, with a long lighting time and a high refresh rate.

[0114] In an exemplary embodiment, generating a pixel driving signal based on a clock signal and a marked pixel data includes:

[0115] A target row pixel unit is determined based on the clock signal; a target column pixel unit is determined based on the marked pixel data; and a pixel driving signal is generated based on the target row pixel unit and the target column pixel unit.

[0116] Exemplarily, the pixel display chip is preset to receive data for odd or even rows at the rising edge of the clock signal, and correspondingly, the even or odd rows are determined to receive data at the falling edge of the input clock; and the mark bit is preset to determine whether the odd or even columns receive data in time-sharing.

[0117] Through the pre-set data transmission rules, the pixel display chip receives the marked pixel data of the target row at the rising edge or falling edge of the clock signal. After receiving the marked pixel data of the target row, the pixel display chip identifies the mark bit in the marked pixel data of the target row, and then determines the target column. The pixel display chip determines the target pixel unit to be lit by determining the target column and target row, and then the pixel display chip generates a corresponding pixel drive signal and transmits the pixel drive signal to the target pixel unit.

[0118] In an exemplary embodiment, a display method for time-division multiplexing of a control signal is provided, wherein the method is applied to Figure 1 The display system for time-division multiplexing of control signals in the embodiment of the present invention comprises the following steps:

[0119] Generates clock signals, stores initial data, and generates marker pixel data.

[0120] A target row of pixel cells is determined based on the clock signal.

[0121] A target column pixel cell is determined based on the marker pixel data.

[0122] A pixel driving signal is generated based on the target row pixel unit and the target column pixel unit.

[0123] Based on the pixel driving signal, the pixel unit corresponding to the pixel driving signal is lit.

[0124] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0125] Based on the same inventive concept, the embodiment of the present application also provides a display device for time-division multiplexing of control signals for implementing the display method for time-division multiplexing of control signals involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations of the display device embodiment for time-division multiplexing of one or more control signals provided below can refer to the limitations of the display method for time-division multiplexing of control signals above, and will not be repeated here.

[0126] In an exemplary embodiment, Figure 6 As shown, a display device for time-division multiplexing of control signals is provided, comprising: a control module 602, a data processing module 604 and a driving module 606, wherein:

[0127] The control module 602 is used to generate a clock signal, store initial data and generate marked pixel data.

[0128] The data processing module 604 is used to generate a pixel driving signal based on the clock signal and the marked pixel data.

[0129] The driving module 606 is used to light up the pixel unit corresponding to the pixel driving signal based on the pixel driving signal.

[0130] In an exemplary embodiment, the data processing module 604 is further configured to determine a target row pixel unit based on a clock signal; determine a target column pixel unit based on the marked pixel data; and generate a pixel driving signal based on the target row pixel unit and the target column pixel unit.

[0131] Each module in the above-mentioned display device for time-division multiplexing of control signals can be implemented in whole or in part by software, hardware, or a combination thereof. Each of the above-mentioned modules can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each of the above modules.

[0132] In an exemplary embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as shown in FIG. Figure 7 As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. Among them, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store raw data and marked pixel data. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a display method of time-division multiplexing of control signals is implemented.

[0133] Those skilled in the art will understand that Figure 7 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0134] In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above-mentioned method embodiments when executing the computer program.

[0135] In an exemplary embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0136] In an exemplary embodiment, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps in the above method embodiments are implemented.

[0137] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0138] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0139] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0140] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A display system for time-division multiplexing of control signals, characterized in that: The display system comprises: A main controller, used to generate a clock signal, store initial data and generate marked pixel data; A pixel display chip, each of which is connected to the main controller and is used to generate a pixel driving signal based on the clock signal and the marked pixel data; the pixel display chip is provided with a*b chips, wherein a is the number of rows and b is the number of columns; the marked pixel data is new data with a mark bit, and the pixel display chip identifies the mark bit in the marked pixel data to determine whether the odd column or the even column receives the corresponding marked pixel data in a time-sharing manner; A pixel unit, the pixel unit being connected to the pixel display chip and configured to light up the pixel unit corresponding to the pixel driving signal based on the pixel driving signal; The pixel display chip includes an input pin and an output pin, the input pin of the pixel display chip includes a clock signal pin and a serial data pin, the input pin of the pixel display chip also includes a row chip select pin and a column chip select pin, the row chip select pin and the column chip select pin are both connected to the main controller, and a second pin quantity mapping relationship is also provided between the main controller and the pixel display chip, the second pin quantity mapping relationship is: when one row chip select pin is added to each pixel display chip, the main controller provides a / 2+b pins; when j column chip select pins are added to each pixel display chip, the main controller provides (a / 2+b / 2 j ) pins; When the row chip select pins of a row of pixel display chips are connected to a power source, the row chip select pins of an adjacent row of pixel display chips are grounded; When the column chip selection pins of the pixel display chips in one column are connected to a power source, the column chip selection pins of the pixel display chips in an adjacent column are grounded.

2. The display system for time-division multiplexing of control signals according to claim 1, characterized in that: The main controller comprises output pins, and the output pins of the main controller comprise a clock signal pin and a serial data pin; The clock signal pin of the pixel display chip is connected to the clock signal pin of the main controller; The serial data pin of the pixel display chip is connected to the serial data pin of the main controller; The output pin of the pixel display chip is connected to the pixel unit.

3. The display system for time-division multiplexing of control signals according to claim 1, characterized in that: Each row of pixel display chips is provided with two data transmission modes, and the two data transmission modes are respectively: When the row chip select pin is connected to the power supply, the pixel display chip samples data when the clock signal is at a rising edge; when the row chip select pin is grounded, the pixel display chip samples data when the clock signal is at a falling edge; or When the row chip select pin is connected to the power supply, the pixel display chip samples data when the clock signal is at a falling edge; when the row chip select pin is grounded, the pixel display chip samples data when the clock signal is at a rising edge.

4. The display system for time-division multiplexing of control signals according to claim 1, characterized in that: The pixel display chip data is provided with two data transmission schemes, and the two data transmission schemes are respectively: When the column chip select pin is connected to the power supply, the pixel units connected to the pixel display chips in the odd columns receive data; when the column chip select pin is grounded, the pixel units connected to the pixel display chips in the even columns receive data; or When the column chip select pin is connected to the power supply, the pixel units connected to the pixel display chips in the even columns receive data; when the column chip select pin is grounded, the pixel units connected to the pixel display chips in the odd columns receive data.

5. A display method for time-division multiplexing of control signals, applicable to the display system for time-division multiplexing of control signals as claimed in any one of claims 1 to 4, characterized in that: The display method comprises: Generate a clock signal, store initial data and generate labeled pixel data; generating a pixel driving signal based on the clock signal and the marked pixel data; The pixel unit corresponding to the pixel driving signal is lit based on the pixel driving signal.

6. The display method of time-division multiplexing of control signals according to claim 5, characterized in that: The generating a pixel driving signal based on the clock signal and the marked pixel data comprises: Determine a target row of pixel units based on the clock signal; Determine a target column pixel unit based on the marked pixel data; A pixel driving signal is generated based on the target row pixel unit and the target column pixel unit.

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