Drive Circuit, Display Panel and Electronic Device

Abstract

The present application provides a driving circuit, a display panel and an electronic device. The driving circuit includes m scanning driving units arranged in sequence and cascaded. In the i-th scanning cycle among the m consecutive scanning cycles included in a frame image display period, the i-th level of scanning driving unit is used to output a scanning signal and a compensation scanning signal. The scanning signal is a pulse signal with a duration of a first preset time, and the compensation scanning signal is a pulse signal with a duration of a second preset time. The scanning signal is used to load the pixel units at the first position during the data loading period in the i-th scanning cycle to control the pixel units to receive data signals for image display. The compensation scanning signal is used to be loaded to the pixel units during the compensation period in the i-th scanning cycle to perform data signal compensation on the pixel units. Wherein, the second preset time is greater than the first preset time, and the compensation period and the data loading period are consecutive in time sequence.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and in particular, to a driving circuit, a display panel, and an electronic device. Background Art

[0002] Display technology has always been one of the important research directions in electronic devices. For a display panel, since the circuit for driving pixel units is usually also disposed in the display area of the display panel, when the size of the display area is fixed, the more complex the driving circuit is, the fewer pixel units that can be added in the display area.

[0003] Currently, the number of electronic components in the circuit structure for driving pixel units is large, resulting in difficulties in achieving high efficiency of the driving signal output by the driving circuit and difficulties in achieving the effect of a narrow border when the size of the display panel is fixed. Summary of the Invention

[0004] Based on the foregoing technical problems, the present application provides a driving circuit with better efficiency and higher integration for outputting driving signals used when pixel units execute image display.

[0005] In a first aspect, the present application provides a driving circuit, including m scanning driving units arranged in sequence and cascaded. In the i-th scanning cycle among m consecutive scanning cycles included in a frame image display period, the i-th level scanning driving unit is configured to output a scanning signal and a compensation scanning signal. The scanning signal is a pulse signal with a duration of a first preset time, and the compensation scanning signal is a pulse signal with a duration of a second preset time. The scanning signal is used to load pixel units at a first position during a data loading period in the i-th scanning cycle to control the pixel units to receive data signals and execute image display. The compensation scanning signal is used to be loaded to the pixel units during a compensation period in the i-th scanning cycle to perform data signal compensation on the pixel units. Wherein, the second preset time is greater than the first preset time, the compensation period and the data loading period are consecutive in time, m is a positive integer greater than 1, and i is a positive integer greater than or equal to 1 and less than m.

[0006] In one embodiment, the scan driving unit includes an enable trigger terminal, a first clock signal input terminal, a second clock signal input terminal, a first signal output terminal, and a second signal output terminal. Among them, the enable trigger terminal is used to receive an enable trigger signal to enable the scan driving unit to work. The first clock signal input terminal and the second clock signal input terminal are used to receive two clock signals with a preset unit time interval. The scan driving unit outputs the scan signal from the first signal output terminal according to the clock signal of the first clock signal input terminal, and simultaneously outputs the compensation scan signal from the second signal output terminal, and stops the compensation scan signal according to the clock signal of the second clock signal input terminal. The clock signal is a periodic pulse signal with a pulse width of one unit time.

[0007] In one embodiment, the clock signals received by the first clock signal input terminal and the second clock signal input terminal are spaced b unit times apart, where the first preset duration corresponding to the scan signal is 1 unit time, and the second preset duration corresponding to the compensation scan signal is b unit times.

[0008] In one embodiment, the scan driving unit includes a first pull-up module, a first clock signal output module, and a first reset scan output module. The first pull-up module is connected to the enable trigger terminal, the high-voltage power supply terminal, and a first control node, and is used to pull up the voltage of the first control node to a high potential under the control of the enable trigger signal provided by the enable trigger terminal. The first clock signal output module is connected to the first control node, the first clock signal input terminal, and the first signal output terminal, and is used to output the clock signal as the scan signal when the voltage of the first control node is at a high potential, and at the same time maintain the voltage of the first control node at a high potential within the second preset duration. The first reset scan output module is connected to the first control node, the first clock signal input terminal, the high-voltage power supply terminal, and the second signal output terminal, and is used to output the power supply signal provided by the high-voltage power supply terminal as the compensation scan signal within the second preset duration under the control of the voltage of the first control node and the clock signal.

[0009] In one embodiment, the scan driving unit further includes a second pull-down module. The second pull-down module is connected to the first control node, the low-voltage power supply terminal, and a second control node, and is used to connect the low-voltage power supply terminal to the second control node when the voltage of the first control node is at a high potential to pull down the potential of the second control node to a low potential.

[0010] In one embodiment, the scan driving unit further includes a first pull-down module and a second pull-up module.

[0011] The second pull-up module is connected to the high-voltage power supply terminal and the second control node, and is configured to load the high-potential voltage provided by the high-voltage power supply terminal to the second control node to raise the potential of the second control node when the second control node is not loaded with a low potential; the first pull-down module is connected to the first control node, the second control node, and the second clock signal input terminal, and is configured to pull down the potential of the first control node under the control of the clock signal provided by the second clock signal input terminal or when the voltage of the second control node is high.

[0012] In one embodiment, the scan driving unit further includes a second clock signal output module and a second reset scan output module. The second clock signal output module is connected to the second control node, the low-voltage power supply terminal, and the first signal output terminal, and is configured to transmit a low-potential voltage to the first signal output terminal to stop outputting the scan signal when the voltage of the second control node is high. The second reset scan output module is connected to the second control node, the low-voltage power supply terminal, and the second signal output terminal, and is configured to transmit a low-potential voltage to the second signal output terminal to stop outputting the compensation scan signal when the voltage of the second control node is high.

[0013] In one embodiment, the scan driving unit further outputs a reset scan signal, and the scan signal output by the first signal output terminal also serves as the reset scan signal. The reset scan signal is configured to be loaded to the pixel unit at the second position during the reset period of the (i + b)-th scan cycle to control the pixel unit to receive the reset voltage to perform reset.

[0014] In one embodiment, within the display period of one frame of image, there are also f consecutive virtual scan cycles. The f consecutive virtual scan cycles are sequentially continuous in time with the first scan cycle. The scan driving circuit further includes f virtual scan driving units. The f virtual scan driving units are cascaded in sequence, and the f-th level virtual scan driving unit is connected to the first level scan driving unit, and the f-th level virtual scan driving unit outputs an enable trigger signal to trigger the first level scan driving unit to work. The first to f-th level virtual scan driving units are configured to sequentially output the reset scan signal and the compensation scan signal during the reset period and the compensation period of the first to f-th virtual scan cycles respectively.

[0015] In one embodiment, the driving circuit further includes m sequentially arranged light-emitting driving units. In the i-th scanning period, the i-th light-emitting driving unit is configured to output a light-emitting signal, and the light-emitting signal is provided to the pixel unit during the compensation period to cooperate with the compensation scanning signal to perform data signal compensation on the pixel unit. The light-emitting signal is further configured to control the pixel unit to emit light according to the data signal to display an image. Wherein, the light-emitting signal is a pulse signal lasting for the second preset duration, and the compensation period, the data loading period, and the light-emitting period are sequentially continuous in time.

[0016] In one embodiment, the light-emitting driving unit includes a light-emitting clock signal input terminal, a first light-emitting input terminal, a second light-emitting input terminal, a light-emitting output terminal, a first light-emitting pull-up module, and a first light-emitting signal output module. The light-emitting clock signal input terminal is configured to receive a light-emitting clock signal. The first light-emitting input terminal and the second light-emitting input terminal are connected to the first signal output terminals of two scanning driving units separated by a preset level to respectively receive two scanning signals. The first light-emitting pull-up module is connected to the light-emitting clock signal input terminal, the light-emitting high-voltage power supply terminal, and a first light-emitting control node, and is configured to load the high-potential voltage provided by the light-emitting high-voltage power supply terminal to the first light-emitting control node under the control of the light-emitting clock signal. The first light-emitting signal output module is connected to the first light-emitting control node, the light-emitting high-voltage power supply terminal, and the light-emitting output terminal, and is configured to output the high-potential voltage provided by the light-emitting high-voltage power supply terminal as a light-emitting signal from the light-emitting output terminal within the second preset duration under the control of the high-potential voltage of the first light-emitting control node.

[0017] In one embodiment, the light-emitting driving unit further includes a second light-emitting pull-down module. The second light-emitting pull-down module is connected to the first light-emitting control node, a second light-emitting control node, and the light-emitting low-voltage power supply terminal, and is configured to load the low-potential voltage provided by the light-emitting low-voltage power supply terminal to the second light-emitting control node when the first light-emitting control node is at a high-potential voltage.

[0018] In one embodiment, the light-emitting driving unit further includes a second light-emitting pull-up module and a second light-emitting signal output module. The second light-emitting pull-up module is connected to the first light-emitting input terminal, the second light-emitting input terminal, and the second light-emitting control node, and is configured to raise the voltage potential of the second light-emitting control node when the scan signal received at the first light-emitting input terminal or the second light-emitting input terminal. The second light-emitting signal output module is connected to the second light-emitting control node, the light-emitting low-voltage power supply terminal, the light-emitting clock signal input terminal, and the light-emitting output terminal, and the second light-emitting signal output module is configured to control the light-emitting output terminal to stop outputting the light-emitting signal when the voltage of the second light-emitting control node is at a high potential or when the light-emitting clock signal is received.

[0019] In one embodiment, the light-emitting driving unit further includes a first light-emitting pull-down module. The first light-emitting pull-down module is connected to the first light-emitting control node, the second light-emitting control node, and the light-emitting low-voltage power supply terminal, and is configured to load the low-potential voltage provided by the light-emitting low-voltage power supply terminal to the first light-emitting control node when the voltage of the second light-emitting control node is at a high potential, so as to control the first light-emitting signal output module to stop outputting the light-emitting signal.

[0020] In one embodiment, the light-emitting driving unit further includes a first light-emitting pull-down module. The first light-emitting pull-down module is connected to the light-emitting high-voltage power supply terminal, the first light-emitting control node, the second light-emitting control node, and the light-emitting low-voltage power supply terminal. When the voltage of the first light-emitting control node is at a high potential, the first light-emitting pull-down module is configured to disconnect the conductive path between the first light-emitting control node and the light-emitting low-voltage conductive terminal through the high-potential voltage provided by the light-emitting high-voltage power supply terminal; and when the voltage of the second light-emitting control node is at a high potential, the first light-emitting pull-down module is configured to load the low-potential voltage provided by the light-emitting low-voltage power supply terminal to the first light-emitting control node, so as to control the first light-emitting signal output module to stop outputting the light-emitting signal.

[0021] In a second aspect, a pixel unit applied to a display panel is provided, which includes at least one sub-pixel. The sub-pixel includes a control switch transistor, a driving switch transistor, a light-emitting element, a first energy storage element and a second energy storage element. The driving switch transistor is connected to the control switch transistor through a first node, and the driving switch transistor is also connected to a first power supply terminal through a second node and to the light-emitting element through a third node. The light-emitting element is connected between the third node and a second power supply terminal. The first energy storage element is connected between the first node and the third node. The second energy storage element is connected between the third node and the second power supply terminal. The control switch transistor is configured to receive a scan signal and a data signal during a data writing period of a frame image display period. The scan signal is used to control the control switch transistor to transmit the received data signal to the first energy storage element and the second energy storage element. The data signal is used to control the driving switch transistor to output a corresponding driving current to the light-emitting element in cooperation with a driving power supply provided by the first power supply terminal during a light-emitting period of the frame image display period, so as to drive the light-emitting element to emit light and display an image. The data writing period and the light-emitting period are sequentially continuous in time.

[0022] In one embodiment, the first energy storage element includes a first energy storage connection terminal and a second energy storage connection terminal. The first energy storage connection terminal is connected to the first node, and the second energy storage connection terminal is connected to the third node. The second energy storage element includes a third energy storage connection terminal and a fourth energy storage connection terminal. The third energy storage connection terminal is connected to the third node, and the fourth energy storage connection terminal is connected to the second power supply terminal.

[0023] In one embodiment, the pixel unit further includes a compensation switch transistor. The compensation switch transistor is connected between a compensation power supply terminal and the first node. The compensation switch transistor is configured to transmit a compensation signal to the first node when receiving a compensation scan signal during a compensation period of the frame image display period. Wherein, the compensation period and the data writing period are sequentially continuous in time.

[0024] In one embodiment, the pixel unit further includes a light-emitting switch transistor. The light-emitting switch transistor is connected between the second node and the first power supply terminal. The light-emitting switch is configured to transmit the driving power supply to the driving switch transistor when receiving a light-emitting signal during the light-emitting period.

[0025] In one embodiment, the pixel unit further includes a reset switch transistor. The reset switch transistor is connected to the second node. The light-emitting switch is configured to transmit a reset voltage to the second node when receiving a reset signal during a reset period of the frame image display period. The reset voltage is transmitted to the third node through the driving switch transistor to reset the light-emitting element. Wherein, the reset period and the compensation period are sequentially continuous in time.

[0026] In one embodiment, the pixel unit includes a plurality of sub-pixels, and the plurality of sub-pixels share the same light-emitting switching transistor; the plurality of sub-pixels respectively include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, wherein the red sub-pixel emits red light, the green sub-pixel emits green light, and the blue sub-pixel emits blue light.

[0027] In a third aspect, a display panel is provided, including m scan lines, n data lines, m light-emitting lines, m compensation scan lines, m compensation lines, m reset scan lines and m reset lines, a data driving circuit, a compensation circuit, a reset circuit, and the foregoing driving circuit, and the display panel further includes m×n pixel units, and each pixel unit is connected to one of the scan line, the data line, the light-emitting line, the compensation scan line, the compensation line, the reset scan line, and the reset line;

[0028] The m scan driving units included in the driving circuit are respectively connected to the m scan lines, the m compensation scan lines, and the m reset scan lines, and the m light-emitting driving units included in the driving circuit are respectively connected to the m scan lines;

[0029] The m light-emitting driving units included in the light-emitting driving circuit are connected to the pixel units through m light-emitting lines;

[0030] The compensation circuit is connected to the compensation line and outputs a compensation signal to the pixel unit when the pixel unit receives a compensation scan signal, so as to perform data signal compensation on the pixel unit;

[0031] The reset circuit is connected to the reset line and outputs a reset signal to the pixel unit when the pixel unit receives a reset scan signal to reset the pixel unit.

[0032] In one embodiment, the scan line and the data line are connected to the control switch transistor in the pixel unit. The scan line is used to output a scan signal to control the conduction of the control switch transistor. The data line outputs a data signal, which is transmitted to the first node through the control switch transistor. The light-emitting line is connected to the light-emitting switch transistor. The light-emitting switch transistor is used to output a light-emitting signal to control the conduction of the light-emitting switch transistor. When the control switch transistor is turned on, the driving power supply provided by the first power supply terminal is loaded to the second node. The compensation scan line and the compensation line are connected to the compensation switch transistor. The compensation scan line outputs a compensation scan signal to the compensation switch transistor. The compensation scan signal is used to control the conduction of the compensation switch transistor. The compensation line outputs the compensation signal, which is transmitted to the first node through the compensation switch transistor. The first node controls the conduction of the driving switch transistor and charges and compensates the third node through the second power supply terminal. The reset scan line and the reset line are connected to the reset switch transistor. The reset scan line is used to output a reset signal to control the conduction of the reset switch transistor. The reset line outputs a reset voltage to the second node. The reset voltage is transmitted to the third node through the driving switch transistor to reset the light-emitting element.

[0033] In a third aspect, an electronic device is provided. The electronic device includes a housing and the aforementioned display panel. The housing is used to carry the display panel.

[0034] Compared with the prior art, in the embodiments of the present application, the scan driving unit can output scan signals and compensation scan signals with different durations simultaneously. That is to say, in a single scan driving unit, it can output both scan signals and compensation scan signals, and can also ensure that the durations of the scan signals and the compensation scan signals are different, effectively simplifying the circuit structure of the scan driving unit, improving the signal output efficiency of the scan driving unit, and increasing the integration degree and design space of the scan driving circuit. Cooperating with the light-emitting driving unit further included in the driving circuit, it can also output corresponding light-emitting signals accordingly, thereby effectively improving the image display effect of the pixel unit and providing more space for the narrow border design of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0036] Figure 1 It is a schematic structural diagram of a display device provided by an embodiment of the present application;

[0037] Figure 2 is Figure 1 a schematic diagram of the functional modules of the display device shown;

[0038] Figure 3 is as Figure 2 a schematic diagram of the planar layout structure of the display panel shown;

[0039] Figure 4 is as Figure 3 a schematic diagram of the layout structure of any one pixel unit shown;

[0040] Figure 5 is as Figure 3 a schematic diagram of the specific circuit structure of any one sub-pixel shown;

[0041] Figure 6 is as Figure 5 a timing diagram of the operation of the pixel unit shown;

[0042] Figure 7 is as Figure 3 a connection diagram of the scan driving circuit and the light emitting driving circuit shown;

[0043] Figure 8 is as Figure 7 a schematic diagram of the circuit structure of any one scan driving unit shown;

[0044] Figure 9 is as Figure 8 a timing diagram of the operation of the scan driving unit shown;

[0045] Figure 10 is as Figure 6 a schematic diagram of the circuit structure of any one light emitting driving unit shown;

[0046] Figure 11 is as Figure 10 a timing diagram of the operation of the light emitting driving unit shown;

[0047] Figure 12 is as Figure 7 a schematic diagram of the circuit structure of the light emitting driving unit in a modified embodiment shown.

[0048] Explanation of the reference numerals in the drawings:

[0049] Display device - 100, display panel - 10, support frame - 30, first circuit board - 310, second circuit board - 320, power supply circuit 17, timing control circuit - 11, data driving circuit - 12, scan driving circuit - 13, light emitting driving circuit - 14, compensation circuit - 15, reset circuit - 16, power supply circuit - 17, display area - 10a, non - display area - 10b, scan clock signal - CK, light emitting clock signal - ECK, first direction - F1, second direction - F2, data lines - D1 to Dn, scan lines - G1 to Gm, compensation scan lines - Gc1 to Gcm, light emitting lines - E1 to Em, compensation lines - Dc1 to Dcm, reset scan lines - Rg1 to Rgm, reset lines - Rv1 to Rvm, data signal - Data, scan signal - Gs1 to Gsn, compensation scan signal - Gr1 to Grm, light emitting signal - Et1 to Etm, reset scan signal - Rsi, reset signal - INI, pixel unit - P, red sub - pixel - R, green sub - pixel - G, blue sub - pixel - B, control switch tube - M1, driving switch tube - M2, compensation switch tube - M3, light emitting element - L, first energy storage element - C1, second energy storage element - C2, first node - N1, second node - N2, third node - N3, first power supply terminal - VDD, second power supply terminal - VSS, reset period - H1, compensation period - H2, data loading period - H3, light emitting period - H4, GOA unit - 130, virtual GOA unit - 131, clock signals - CK1 to CK8, enable trigger terminal - En, first clock signal input terminal - CI1, second clock signal input terminal - CI2, first signal output terminal - SO1, second signal output terminal - SO2, first pull - up module - 31, first switch tube - T1, first control terminal - T10, first conductive terminal - T11, second conductive terminal - T12, first control node - PU, second control node - PU, third control node - PU, high - voltage power supply terminal - VGH, low - voltage power supply terminal - VGL, first pull - down module - 32, seventh switch tube - T7, seventh control terminal - T70, seventh pull - up conductive terminal - T71, seventh pull - down conductive terminal - T72, eighth switch tube - T8, eighth control terminal - T80, eighth pull - up conductive terminal - T81, eighth pull - down conductive terminal - T82, second pull - up module - 33, second switch tube - T2, second control terminal - T20, second pull - up conductive terminal - T21, second pull - down conductive terminal - T22, second pull - down module - 34, sixth switch tube - T6, sixth control terminal - T60, sixth pull - up conductive terminal - T61, sixth pull - down control terminal - T62, first clock signal output module - 35, third clock output switch tube - T3a, third clock output control terminal - T310, first clock output conductive terminal - T311, second clock output conductive terminal - T312, energy storage capacitor - Cc, second clock signal output module - 36, fourth clock output switch tube - T4aFourth clock output control terminal - T410, third clock output conductive terminal - T413, fourth clock output conductive terminal - T414, first reset scan output module - 37, third compensation scan output switching transistor - T3b, third compensation scan output control terminal - T320, first compensation scan output conductive terminal - T321, second compensation scan output conductive terminal - T322, fifth compensation scan output switching transistor - T5a, fifth compensation scan output control terminal - T510, fifth compensation scan output conductive terminal - T515, sixth compensation scan output conductive terminal - T516, second reset scan output module - 38, fourth compensation scan shutdown switching transistor - T4b, fourth compensation shutdown control terminal - T420, first compensation scan shutdown conductive terminal - T421, second compensation scan shutdown conductive terminal - T422, fifth compensation scan shutdown switching transistor - T5b, fifth compensation scan shutdown control terminal - T520, third compensation scan output conductive terminal - T523, fourth compensation scan shutdown conductive terminal - T524, light-emitting clock signal input terminal - EKI, first light-emitting input terminal - EI1, second light-emitting input terminal - EI2, light-emitting output terminal - EO, light-emitting high-voltage power supply terminal - EVGH, light-emitting low-voltage power supply terminal - EVGL, first light-emitting pull-up module - 41, first light-emitting switching transistor - ET1, first light-emitting control terminal - ET10, first light-emitting conductive terminal - ET11, second light-emitting conductive terminal - ET12, first light-emitting pull-down module - 42, seventh light-emitting switching transistor - ET7, seventh light-emitting control terminal - ET70, seventh light-emitting pull-up conductive terminal - ET71, seventh light-emitting pull-down conductive terminal - ET72, seventh upper-link light-emitting switching transistor - ET7a, seventh lower-link light-emitting switching transistor - ET7b, intermediate node - Nm, eighth light-emitting switching transistor - ET8, eighth light-emitting control terminal - ET80, eighth pull-up conductive terminal - ET81, eighth light-emitting pull-down conductive terminal - ET82, second light-emitting pull-up module - 43, second pull-up reset switching transistor - ET2a, second pull-up reset control terminal - ET210, first pull-up reset conductive terminal - ET211, second pull-up reset conductive terminal - ET212, second pull-up write switching transistor - ET2b, second pull-up write control terminal - ET220, first pull-up write conductive terminal - ET221, second pull-up write conductive terminal - ET222, second light-emitting pull-down module - 44, sixth light-emitting switching transistor - ET6, sixth light-emitting control terminal - ET60, sixth light-emitting pull-up conductive terminal - ET61, sixth light-emitting pull-down conductive terminal - ET62, first light-emitting signal output module - 45, third light-emitting clock output switching transistor - ET3, third light-emitting output control terminal - ET30, first light-emitting output conductive terminal - ET31, second light-emitting output conductive terminal - ET32, second light-emitting signal output module - 46, first light-emitting shutdown switching transistor - ET4, first light-emitting shutdown control terminal - ET40, first light-emitting shutdown conductive terminal - ET41, second light-emitting shutdown conductive terminal - ET42, second light-emitting shutdown switching transistor - ET5Second light-emitting turn-off control terminal - ET50, third light-emitting turn-off conductive terminal - ET53, fourth light-emitting turn-off conductive terminal - ET54. Detailed implementation manners

[0050] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0051] Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of a display device provided by an embodiment of the present application. The display device 100 includes a display panel 10 and a support frame 30, and the display panel 10 is fixed to the support frame 30. The support frame 30 provides a fixing and protecting function for the display panel 10. In other embodiments of the present application, the display device 100 may not need to be provided with the support frame 30, for example, it is a portable electronic device, such as a mobile phone, a tablet computer, etc.

[0052] Please refer to Figure 2 , Figure 2 is Figure 1 a schematic diagram of the functional modules of the display device 100 shown in the figure.

[0053] As Figure 2 shown, the display device 100 includes a display panel 10, a first circuit board 310, and a second circuit board 320. The first circuit board 310 is electrically connected to the display panel 10 and the second circuit board 320. The first circuit board 310 and the display panel 10 can be connected through a flexible conductive wire or a flexible conductive film, so that the first circuit board 310 can rotate or turn relative to the display panel 10 and be fixed on the display panel 10. Correspondingly, the first circuit board 310 and the second circuit board 320 are also connected through a flexible wire, so that the second circuit board 320 can first rotate with respect to the first circuit board 310 and be fixed on the display panel 10.

[0054] In this embodiment, the first circuit board 310 is a driving circuit board (X-board), and the second circuit board 320 is a control circuit board (C-board). Among them, the first circuit board 310 and the second circuit board 320 can be independently a driving circuit board (X-board) or a control circuit board (C-board), or can be obtained by integrating a driving circuit board (X-board) and a control circuit board (C-board).

[0055] The second circuit board 320 serves as a control circuit board (C-board) and mainly includes a power supply circuit 17 (PMIC), a timing control circuit 11, etc. The second circuit board 320 is mainly used to receive a display signal for image display provided externally and correspondingly output a data signal, a control signal, and a power signal. In this embodiment, the timing control circuit TCON is also connected to an image processing module (GPU), obtains image data for image display from the image processing module, and after performing encoding and decoding processing, transmits it to the pixel units in the display area of the display panel 10 to perform corresponding image display. It can be understood that the image processing module is arranged in a main device independent of the display device 100. For example, the image processing module is arranged in a host computer, or the image processing module can also be arranged in the display device 100 together.

[0056] The second circuit board 320 serves as a driving circuit board (X-board) and is mainly used to receive the data signal and the control signal provided by the first circuit board 310 and transmit them to a plurality of data driving chips (data driving circuits). In this embodiment, the first circuit board 310 includes a memory (not shown in the figure). The first circuit board 310 is connected to the display panel 10 through a chip on flex (COF). Data driving chips are arranged on the COF. Among them, the data driving chips are connected to the pixel units P ( Figure 3 ) through data lines ( Figure 3 ) to transmit the data signal to the pixel units P for image display.

[0057] Among them, a scanning driving circuit 13 is further arranged outside the display area 10a of the display panel 10. Among them, the scanning driving circuits 13 are respectively connected to the timing control circuit 11 through corresponding signal traces.

[0058] Among them, in the non-display area 10b outside the display area 10a of the display panel 10, a timing control circuit 11 ( Figure 3 ), a data driving circuit 12 ( Figure 3 ), a scanning driving circuit 13 ( Figure 3 ), a light emitting driving circuit 14 ( Figure 3 ) and other functional circuits are further arranged.

[0059] Refer to Figure 3 , Figure 3 which is Figure 2 a schematic diagram of the planar layout structure of the display panel shown.

[0060] Corresponding to the display area 10a of the display panel 10, it includes a plurality of pixel units P arranged in an m*n matrix, n data lines D1 to Dn extending along the second direction F2, m scan lines G1 to Gm extending along the first direction F1, m compensation scan lines Gc1 to Gcm, m light-emitting lines E1 to Em, m compensation lines Dc1 to Dcm, m reset scan lines Rg1 to Rgm, and m reset lines Rv1 to Rvm. m and n are natural numbers greater than 1. Among them, the first direction F1 and the second direction F2 are perpendicular to each other. The pixel unit P is located at the intersection of the scan lines G1 to Gm and the data lines D1 to Dn.

[0061] Corresponding to the non-display area 10b, corresponding functional circuits are provided. In this embodiment, the display panel 10 is provided with a scan driving circuit 13 in the non-display area. At the same time, in the first circuit board 310 and the second circuit board 320, a timing control circuit 11, a data driving circuit 12, a light-emitting driving circuit 14, a compensation circuit 15, a reset circuit 16, and a power supply circuit 17 are correspondingly provided.

[0062] Among them, the timing control circuit 11 receives an image signal representing image information from an external signal source, obtains a scan clock signal CK, a light-emitting clock signal ECK, a horizontal synchronization signal, and a vertical synchronization signal for synchronization, and outputs control signals for the scan driving circuit 13 and the data driving circuit 12 to control the scan signal and the data signal.

[0063] The data driving circuit 12 is used to receive the data signal from the timing control circuit 11, perform storage, amplification, and digital-to-analog conversion processing, and then output it to the pixel unit P in the display area 10a.

[0064] The scan driving circuit 13 is used to output corresponding scan signals to the pixel unit P in the display area 10a according to the clock signal CK, and at the same time, output corresponding compensation scan signals to the pixel unit P.

[0065] The light-emitting driving circuit 14 is used to output a corresponding light-emitting signal Et to the pixel unit P in the display area 10a according to the light-emitting clock signal ECK.

[0066] In this embodiment, the scan driving circuit 13 and the light-emitting driving circuit 14 can be synchronously formed in the same area of the display panel 10 through the same process, that is, the scan driving circuit 13 and the light-emitting driving circuit 14 are integrated in the same preset area to form a scan driving circuit (not labeled).

[0067] The compensation circuit 15 is used to provide corresponding compensation signals to the pixel unit P corresponding to the compensation scan signal.

[0068] The reset circuit 16 is used to provide a reset signal for all pixel units P during the blanking time between any two adjacent frames of image display times of the display panel 10, and eliminate the charges remaining in each pixel unit P during the previous frame image display period.

[0069] The power supply circuit 17 is used to provide driving power for the working circuits in the display panel 10. For example, the power supply circuit 17 provides the high potential voltage VGH and low potential voltage VGL for scanning for the scan driving circuit, provides the high potential voltage EVGH and low potential voltage EVGL for light emission for the light-emitting driving circuit 14, and provides the data power supply VDD for the data driving circuit 12, etc.

[0070] Specifically, n data lines D1 to Dn are connected to the data driving circuit 12 and are used to receive the data signal Data saved and transmitted in the form of gray scale values provided by the data driving circuit 12.

[0071] m scan lines G1 to Gn are connected to the scan driving circuit 13 and are used to receive the scan signals Gs1 to Gsn from the scan driving circuit 13. m compensation scan lines Gc1 to Gcm are connected to the scan driving circuit 13 and are used to receive the compensation scan signals Gr1 to Grm from the scan driving circuit 13. m light-emitting lines E1 to Em are connected to the light-emitting driving circuit 14 and are used to receive the light-emitting signals Et1 to Etm from the light-emitting driving circuit 14. m compensation lines Dc1 to Dcm are connected to the compensation circuit 15 and are used to receive the compensation signals from the compensation circuit 15. m reset scan lines Rg1 to Rgm are connected to the scan driving circuit 13 and are used to receive the reset scan signal Rs (Rs1 to Rsm) from the scan driving circuit 13. m reset lines Rv1 to Rvm are connected to the reset circuit 16 and are used to receive the reset signal INI from the reset circuit 16. Each frame image display period includes, in time sequence, a reset period H1, a compensation period H2, a data loading period H3, and a light-emitting period H4.

[0072] During the reset period H1, the scan driving circuit 13 outputs the reset scan signals Rs1 to Rsm through the reset scan lines Rg1 to Rgm and loads the reset signal INI into the pixel unit P, so as to reset each pixel unit P to eliminate the charges remaining during the previous frame image display period.

[0073] During the compensation period H2, the scan driving circuit 13 outputs the compensation scan signals Gr1 to Grm through the compensation scan lines Gc1 to Gcm, and the compensation circuit 15 outputs the compensation signals to the pixel unit P through the compensation lines Dc1 to Dcm, so as to compensate the data signals of the pixel unit P to eliminate the situation that the data signals cannot be uniformly and accurately displayed due to aging, different processes, or the working characteristics of each component in each pixel unit P.

[0074] During the data loading period H3, under the control of scan lines G1 to Gm, data voltages corresponding to the gray scale values in the data signals provided by data lines D1 to Dn are received within a predetermined time period.

[0075] During the light emitting period H4, the light emitting driving circuit 14 outputs light emitting signals Et1 to Etm to the pixel unit P through light emitting lines E1 to Em, thereby supplying a driving power supply to each pixel unit P. The driving power supply cooperates with the data signal to provide a corresponding driving current to the pixel unit, and accordingly drives the light emitting element to emit light of a corresponding brightness, so as to display an image by emitting light of a corresponding brightness according to the data signal.

[0076] Please refer to Figures 4 - 5 , Figure 4 as Figure 3 the layout structure schematic diagram of any one pixel unit P shown in Figure 5 as Figure 3 the specific circuit structure schematic diagram of any one sub-pixel shown in Figure 4 As shown in

[0077] As shown in Figure 5 the pixel unit P includes three sub-pixels, and the three sub-pixels can be a red sub-pixel R that emits red light, a green sub-pixel G that emits green light, and a blue sub-pixel B that emits blue light.

[0078] Among them, the driving switch transistor M2 is connected to the control switch transistor M1 through the first node N1, and the driving switch transistor M2 is also connected to the first power supply terminal VDD through the second node N2, and is connected to the light emitting element L through the third node N3. The light emitting element L is connected between the third node N3 and the second power supply terminal VSS. The first energy storage element C1 is connected between the first node N1 and the third node N3. The second energy storage element C2 is connected between the third node N3 and the second power supply VSS.

[0079] The control switch transistor M1 is used to receive a scan signal Gsi and a data signal Data during the data writing period of a frame image display period. The scan signal Gsi is used to control the control switch transistor M1 to transmit the received data signal Data to the first energy storage element C1 and the second energy storage element C2. The data signal Data is used to control the driving switch transistor M2 to output a corresponding driving current to the light emitting element L in cooperation with the driving power supply provided by the first power supply terminal VDD during the light emitting period of a frame image display period, so as to drive the light emitting element L to emit light to display an image.

[0080] The pixel unit P further includes a compensation switching transistor M3. The compensation switching transistor M3 is connected to the compensation scan line Gci and the compensation line Dci, and is also connected to the first node N1. The compensation switching transistor M3 is configured to transmit a compensation signal to the first node N1 when receiving a compensation scan signal Gri during a compensation period.

[0081] The pixel unit P further includes a light-emitting switching transistor M4. The light-emitting switching transistor M4 is connected to the second node N2 and the first power supply terminal VDD. The light-emitting switch M4 is configured to transmit a driving power supply to the driving switching transistor M2 when receiving a light-emitting signal Et during a light-emitting period.

[0082] The pixel unit P further includes a reset switching transistor M5. The reset switching transistor M5 is connected to the reset scan line Rgi, the reset line Rvi, and the second node N2. The light-emitting switch M5 is configured to receive a reset signal INI from the reset line Rvi under the control of a reset scan signal Rsi provided by the reset scan line Rgi during a reset period, and transmit a reset voltage to the second node N2. The reset voltage is transmitted to the third node N3 through the driving switching transistor M2 to reset the light-emitting element L.

[0083] In this embodiment, three sub-pixels in one pixel unit P share the same light-emitting switching transistor M4. At the same time, multiple pixel units P in the same row share the same reset switch M5.

[0084] In this embodiment, the light-emitting element L in the pixel unit P is an organic light-emitting diode (OLED).

[0085] In this embodiment, the control switching transistor M1, the driving switching transistor M2, the compensation switching transistor M3, the light-emitting switching transistor M4, and the reset switching transistor M5 are N-type thin film transistors. Of course, in other embodiments of the present application, the control switching transistor M1, the driving switching transistor M2, the compensation switching transistor M3, the light-emitting switching transistor M4, and the reset switching transistor M5 can also be P-type thin film transistors.

[0086] In this embodiment, the first energy storage element C1 and the second energy storage element C2 are energy storage capacitors.

[0087] More specifically, the gate of the control switching transistor M1 is connected to the scan line Gi as a control terminal to receive a scan signal Gsi. The control switching transistor M1 is turned on or off under the control of the scan signal Gsi. At the same time, the source and drain of the control switching transistor M1 are used as two conductive terminals to be respectively connected to the data line Dj and the first node N1. Thus, when the control switching transistor M1 is turned on, the data signal Data is transmitted to the first node N1 through the source and drain of the control switching transistor M1. In this embodiment, the source of the control switching transistor M1 is connected to the data line Dj, and the drain of the control switching transistor M1 is connected to the first node N1.

[0088] The gate of the driving switch transistor M2 is connected to the first node N1 as a control terminal to receive the data signal Data through the first node N1, and is turned on or off under the control of the voltage correspondingly loaded at the first node N1. At the same time, the source and drain of the driving switch transistor M2 are connected to the second node N2 and the third node N3 respectively as two conductive terminals. Among them, the second node N2 is connected to the first power supply terminal VDD through the light-emitting switch transistor M4. In this embodiment, the drain of the driving switch transistor M2 is connected to the second node N2, and the source of the driving switch transistor M2 is connected to the third node N3. When the driving switch transistor M2 is turned on, the driving power supply provided by the first power supply terminal VDD forms a driving current through the driving switch M2 under the voltage control of the first node and is transmitted to the light-emitting element L, thereby driving the light-emitting element L to emit corresponding light. Of course, in other embodiments, the source and drain of the driving switch transistor M2 can be interchanged, that is, the source of the driving switch transistor M2 is connected to the second node N2, and the drain of the driving switch transistor M2 is connected to the third node N3.

[0089] The gate of the compensation switch transistor M3 is connected to the compensation scan line Gci as a control terminal to receive the compensation scan signal Gri from the compensation scan line Gci, and the compensation switch transistor M3 is turned on or off under the control of the compensation scan signal Gri. At the same time, the source and drain of the compensation switch transistor M3 are connected to the compensation line Dci and the first node N1 respectively as conductive terminals. In this embodiment, the source of the compensation switch transistor M3 is connected to the compensation line Dci, and the drain of the compensation switch transistor M3 is connected to the first node N1. When the compensation switch transistor M3 is turned on, the compensation signal is transmitted to the first node N1 through the source and drain of the compensation switch transistor M3. Of course, in other embodiments, the source and drain of the compensation switch transistor M3 can be interchanged, that is, the drain of the compensation switch transistor M3 is connected to the compensation line Dci, and the source of the compensation switch transistor M3 is connected to the first node N1.

[0090] The gate of the reset switch transistor M5 is connected to the reset scan line Rgi as a control terminal and is turned on or off under the control of the reset scan signal Rsi provided by the reset scan line Rgi. At the same time, the source and drain of the reset switch transistor M5 are connected to the reset line Rvi and the second node N2 respectively as conductive terminals to transmit the reset voltage provided by the reset line Rvi to the second node N2 through the reset switch transistor M5 when the reset switch transistor M5 is turned on. In this embodiment, the source of the reset switch transistor M5 is connected to the reset line Rvi, and the drain of the reset switch transistor M5 is connected to the second node N2. Of course, in other embodiments, the source and drain of the reset switch transistor M5 can be interchanged, that is, the drain of the reset switch transistor M5 is connected to the reset line Rvi, and the source of the compensation switch transistor M3 is connected to the second node N2.

[0091] The gate of the light-emitting switch transistor M4 is connected to the light-emitting line Ei as a control terminal, and the light-emitting switch transistor M4 is turned on or off under the control of the light-emitting signal Esi provided by the light-emitting line Ei. At the same time, the source and drain of the light-emitting switch transistor M4 are connected to the first power supply terminal VDD and the second node N2 as conductive terminals respectively. When the light-emitting switch transistor M4 is turned on, the driving power supply provided by the first power supply terminal VDD is supplied to the second node N2 through the light-emitting switch transistor M4 and transmitted to the driving switch transistor M2 to provide a driving power supply for the driving switch transistor M2.

[0092] The first energy storage element C1 includes a first energy storage connection terminal C11 and a second energy storage connection terminal C12. The first energy storage connection terminal C11 is connected to the first node N1, and the second energy storage connection terminal C12 is connected to the third node N3. The second energy storage element C2 includes a third energy storage connection terminal C23 and a fourth energy storage connection terminal C24. The third energy storage connection terminal C23 is connected to the third node N3, and the fourth energy storage connection terminal C24 is connected to the second power supply terminal VSS. The first energy storage element C1 and the second energy storage element C2 cooperate to accurately maintain the voltage when a voltage is loaded at the first node N1 or the third node N3.

[0093] Please refer to Figure 6 , which is the working timing diagram of the pixel unit as shown in Figure 5 . Now, in combination with Figure 5 and Figure 6 , the working process of the pixel unit P will be specifically described.

[0094] It should be noted that for the display panel 10 as shown in Figures 2 - 3 , any frame image display period Frame includes f virtual scan cycles and m consecutive scan cycles. For example, the r-th frame image display period includes f virtual scan cycles and m scan cycles that are continuous in time. The f virtual scan cycles are used to pre-load some control signals to f rows of pixel units in sequence before the scan cycle, so as to perform reset and compensation before the formal loading of the scan signal. Or rather, the f virtual scan cycles are used to pre-load some control signals to the pixel units corresponding to the 1st to the f-th scan lines arranged in sequence before the scan cycle. In this embodiment, the f virtual scan cycles are respectively used to pre-load the reset scan signal and the compensation scan signal as control signals to f rows of pixel units. The m consecutive scan cycles respectively correspond to m scan lines G1 to Gm (m rows of pixel units P) in a one-to-one correspondence manner. In each scan cycle, the working process and timing phases of resetting, data compensation, data writing, and light emission can be performed for a row of pixel units connected to the same scan line. For example, in any one scan cycle, such as the i-th scan cycle, it includes a reset period H1, a compensation period H2, a data loading period H3, and a light emission period H4 that are adjacent in time. Among them, i is a positive integer greater than or equal to 1 and less than or equal to m.

[0095] During the reset period H1, the reset scan line Rgi outputs a reset scan signal Rsi. In this embodiment, the reset scan signal Rsi is a high-level pulse signal lasting for a first preset duration. In this embodiment, the first preset duration is one unit duration (1H). The reset switch transistor M5 is turned on under the control of the reset scan signal Rsi, and the reset signal INI provided by the reset line Rvi is transmitted to the second node N2 through the reset switch transistor M5. Since the first node N1 still maintains the voltage of the previous frame (the (n - 1)-th frame) due to the energy storage effect of the first energy storage element C1 and the second energy storage element C2, and since the voltage is higher than the reset voltage of the reset signal INI, the driving switch transistor M2 is turned on, and then the reset voltage is written into the third node N3, thereby resetting the third node N3, that is, resetting the light-emitting element L. Among them, the voltage of the third node N3 is the reset voltage Vint.

[0096] During the compensation period H2, the compensation scan line Gci outputs a compensation scan signal Gri. In this embodiment, the compensation scan signal Gri is also a high-level pulse signal lasting for a second preset duration. In this embodiment, the second preset duration is five unit durations 5H. The compensation switch transistor M3 is turned on under the control of the compensation scan signal Gri, and the compensation signal provided by the compensation line Dci is transmitted to the first node N1 through the compensation switch transistor M3. Among them, the first node N1 is loaded with the voltage of the written compensation signal, and the potential of the compensation signal can be the compensation voltage Vref. At the same time, the light-emitting switch transistor M4 receives the light-emitting signal Ei provided by the light-emitting driving circuit 14 from the light-emitting line Ei and is turned on under the control of the light-emitting signal Ei, so as to provide the driving voltage provided by the first power supply terminal VDD to the second node N2. In this embodiment, the light-emitting signal Esi is also a high-level pulse signal lasting for five unit durations (5H).

[0097] After the first node N1 is loaded with the compensation voltage Vref of the compensation signal, it controls the driving switch transistor M2 to be turned on, and the driving voltage of the second node N2 charges the third node N3 through the driving switch transistor M2. When the voltage of the third node N3 is charged to Vref - Vth, the driving switch transistor M2 is turned off. Among them, Vth is the threshold voltage of the driving switch transistor M2. Thus, during the compensation period H2, the voltage of the third node N3 is compensated and charged to Vref - Vth.

[0098] It can be understood that during the compensation period H2, the reset scan line Rgi stops outputting the reset scan signal Rsi.

[0099] During the data loading period H3, the scan line Gi outputs a scan signal Gsi, controlling the switching transistor M1 to conduct under the control of the scan signal Gsi. The data voltage of the data signal Data is loaded from the data line Dj to the first node N1 through the switching transistor M1. In this embodiment, the scan signal Gsi is a high-level pulse signal lasting for a first preset duration, and the first preset duration is one unit duration 1H. With the cooperation of the first energy storage element C1 and the second energy storage element C2, the voltage of the first node N1 is coupled to the third node N3, and the voltage of the third node N3 is coupled to: Vref - Vth + α(Vdata - Vref). Thus, the voltage VGS between the gate and the source of the driving switching transistor M2 is: (1 - α)(Vdata - Vref) + Vth, where α = C1 / (C1 + C2), Vdata is the voltage of the data signal Data, and C1 and C2 are the capacitance values of the first energy storage element C1 and the second energy storage element C2 as capacitors.

[0100] It can be understood that during the data loading period H3, the compensation scan line Gci stops outputting the compensation scan signal Gri, and at the same time, the light-emitting line Ei stops outputting the light-emitting signal.

[0101] During the light-emitting period H4, the light-emitting switching transistor M4 receives the light-emitting signal Ei provided by the light-emitting driving circuit 14 from the light-emitting line Ei again and conducts under the control of the light-emitting signal Ei, thereby providing the driving voltage provided by the first power supply terminal VDD to the second node N2. In this embodiment, the light-emitting signal Ei is a high-level pulse signal lasting for one unit duration (1H).

[0102] The driving switching transistor M2 conducts under the control of the voltage loaded on the first node N1. The driving power supply provides a corresponding driving current Ids through the driving switching transistor M2 in cooperation with the voltages of the first node N1 and the third node N3. The driving current Ids is transmitted to the light-emitting element L through the third node N3, thereby driving the light-emitting element L to emit light and correspondingly display the image of the data signal Data.

[0103] In this embodiment, both the compensation scan signal and the scan signal are output by the scan driving circuit 13, but their durations are not the same.

[0104] Please refer to Figure 7 , which is Figure 3 the connection schematic diagram of the scan driving circuit 13 and the light-emitting driving circuit 14 as shown. As Figure 7 shown, the scan driving circuit 13 includes a plurality of cascaded scan driving units (GOA units) 130, six virtual GOA units 131, eight clock signals CKq (q = 1, 2,..., 8), and a start signal STV. For the convenience of description, the scan driving units are represented by GOA units, and the virtual scan driving units are represented by virtual GOA units in the following text.

[0105] Among them, multiple cascaded GOA units 130 are connected to the scan lines one by one and output corresponding multiple scan drive signals. In this embodiment, when the number of corresponding scan lines m is 2160, the number of GOA units 130 is also 2160, and multiple scan signals can be expressed as Gs1~Gs2160. The scan signals G1~G2160 are used to drive the scan lines of the corresponding row pixel units in the display array substrate. In other embodiments of the present application, the number of scan lines can be set according to the actual resolution, but is not limited thereto.

[0106] In this embodiment, eight clock signals CKq (q=1, 2, ... 8) can be defined as clock signals CK1-CK8, and the eight clock signals CK1-CK8 are periodically output respectively, and the period of each clock signal is 8 unit time lengths 8H. The duration of an overall period of the overall output of the eight clock signals is also 8 unit time lengths 8H.

[0107] The clock signals CK1 to CK8 are arranged in sequence according to the output timing of the output, and each clock signal CK is a pulse signal that lasts for a unit time of 1H, and the interval between two adjacent clock signals is a unit time of 1H. For example, the interval between the clock signal CK1 and the clock signal CK2 is a unit time of 1H, the interval between the clock signal CK3 and the clock signal CK2 is a unit time of 1H, and so on, the interval between the clock signal CK8 and the clock signal CK7 is a unit time of 1H, or in other words, the time point of the output clock signal CK1 and the time point of the output clock signal CK2 are a unit time of 1H, the time point of the output clock signal CK3 and the time point of the output clock signal CK2 are a unit time of 1H, and so on, the time point of the output clock signal CK8 and the time point of the output clock signal CK7 are a unit time of 1H.

[0108] Each GOA unit 130 includes an enable trigger terminal En, a first clock signal input terminal CI1, a second clock signal input terminal CI2, a first signal output terminal SO1, and a second signal output terminal SO2. Among them, the enable trigger terminal En is used to receive an enable trigger signal STV, so that the GOA unit 130 starts working. It should be noted that for multiple cascaded GOA units 130, the first-stage GOA unit 130 receives the enable trigger signal STV provided by the timing control circuit 11, and the second-stage GOA unit 130 receives the scan signal Gsi output from the first signal output terminal SO1 from the first-stage GOA unit 130 as an enable trigger signal. The enable trigger signals received by the enable trigger terminals En of other cascaded GOA units 130 are similar, and this embodiment will not be repeated.

[0109] The first clock signal input terminal CI1 and the second clock signal input terminal CI2 are used to receive two clock signals with a preset unit time interval. The GOA unit 130 outputs signals from the first signal output terminal SO1 and the second signal output terminal SO2 according to the two clock signals. In this embodiment, the signals output from the first signal output terminal SO1 can be the scan signal Gs and the reset scan signal Rs, and the signals output from the second signal output terminal SO2 can be the compensation scan signal Gr. Specifically, the GOA unit 130 outputs the scan signal Gs from the first signal output terminal SO1 according to the clock signal CKe received by the first clock signal input terminal CI1, and outputs the compensation scan signal Gr from the second signal output terminal SO2, and stops outputting the compensation scan signal Gr from the second signal output terminal SO2 when the second clock signal input terminal CI2 receives the clock signal CKe + a.

[0110] In this embodiment, the clock signals received by the first clock signal input terminal CI1 and the second clock signal input terminal CI2 are separated by 5 unit time intervals, that is, a is 5 in this embodiment. If the first clock signal input terminal CI1 receives the clock signal CKe, then the second clock signal input terminal CI2 receives the clock signal CK(e + 5). For example, if the first clock signal input terminal CI1 receives the clock signal CK1, then the second clock signal input terminal CI2 receives the clock signal CK6; if the first clock signal input terminal CI1 receives the clock signal CK2, then the second clock signal input terminal CI2 receives the clock signal CK7, and so on; if the first clock signal input terminal CI1 receives the clock signal CK8, then the second clock signal input terminal CI2 receives the clock signal CK5.

[0111] The GOA unit 130 outputs the scan signal Gs from the first signal output terminal SO1 according to the clock signal CKa received by the first clock signal input terminal CI1. At the same time, the scan signal Gs also serves as the reset scan signal Rs of the GOA unit 130 that is m levels away from the current GOA unit 130. At the same time, the GOA unit 130 outputs the compensation scan signal Gr from the second signal output terminal SO2 according to the clock signal CKe received by the first clock signal input terminal CI1. The GOA unit 130 stops outputting the compensation scan signal Gr from the second signal output terminal SO2 after receiving the clock signal CKe + a from the second clock signal input terminal CI2. It can be understood that when the first clock signal input terminal CI1 does not receive the clock signal CKe, the GOA unit 130 stops outputting the scan signal Gs and the reset scan signal Rs from the first signal output terminal SO1.

[0112] In this embodiment, the GOA units 130 are cascaded in sequence. Specifically, for the cascaded GOA units 130, any one GOA unit 130 is cascaded with the GOA unit of 1 adjacent GOA unit. For example, the GOA unit 130 of the first stage is cascaded with the GOA unit 130 of the second stage, and the GOA unit 130 of the third stage is cascaded with the GOA unit 130 of the second stage.

[0113] The circuit structure and working mode of the virtual GOA unit 131 are the same as those of the GOA unit 130. Multiple virtual GOA units 131 are also cascaded with adjacent virtual GOA units 131 in sequence, and the last-stage virtual GOA unit 131 is cascaded with the GOA unit 130 of the first stage. In this embodiment, the number of virtual GOA units 131 corresponds to f virtual scan cycles, where f is 6.

[0114] The specific cascading method is as follows: The enable trigger terminal En of the virtual GOA unit 131 of the first stage receives the trigger signal STV output from the timing drive circuit. At the same time, the virtual GOA unit 131 of the first stage outputs a stage transmission signal to the virtual GOA unit 131 of the second stage, and so on. The last-stage virtual GOA unit 131 outputs a stage transmission signal to the enable trigger terminal En of the GOA unit 130 of the first stage, and the enable trigger terminal En of the GOA unit 130 of the second stage receives the stage transmission signal output by the GOA unit 130 of the first stage.

[0115] In this embodiment, the circuit structure and working principle of the virtual GOA unit 131 and the GOA unit 130 are the same. The only difference is that the second signal output terminal SO2 of the virtual GOA unit 131 is not directly connected to the scan line. The first signal output terminal SO1 outputs a reset scan signal Rs, and a compensation scan signal Gr is output from the second signal output terminal SO2. Considering the timing requirements, in this embodiment, six virtual GOA units 131 are used to output six groups of reset scan signals Rs and compensation scan signals Gr to the pixel units of the 1st to the 6th rows respectively, while the GOA units 130 of the (m - 6)th to the mth stages at the last position of the cascade do not need to output the corresponding reset scan signals Rs and compensation scan signals Gr to the pixel units of the (m - 6)th to the mth rows.

[0116] The corresponding relationship between the virtual GOA unit 131, the GOA unit 130, f virtual scan cycles, and m scan cycles is as follows: The f virtual scan cycles can be defined as the 1st to the fth virtual scan cycles in sequence, and the m scan cycles can be defined as the 1st to the mth scan cycles in sequence. And the fth virtual scan cycle is continuous with the 1st scan cycle in time. The virtual GOA unit 131 corresponds to f consecutive virtual scan cycles respectively, and the 1st to the fth stage virtual scan driving units are used to output the reset scan signal and the compensation scan signal respectively corresponding to the reset period and the compensation period in the 1st to the fth virtual scan cycles.

[0117] Correspondingly, the light-emitting driving circuit 14 includes a plurality of light-emitting driving units 140. For the convenience of description and understanding, the light-emitting driving unit 140 in this embodiment can be represented as an EOA unit 140. That is, the light-emitting driving circuit 14 includes a plurality of EOA units 140.

[0118] The EOA unit 140 includes a light-emitting clock signal input terminal EKI, a first light-emitting input terminal EI1, a second light-emitting input terminal EI2, and a light-emitting output terminal EO. Among them, the light-emitting clock signal input terminal EKI is used to receive the light-emitting clock signal EK. The first light-emitting input terminal EI1 and the second light-emitting input terminal EI2 are connected to the first signal output terminals SO1 of two GOA units 130 at a preset level interval to respectively receive two scanning signals Gs. The EOA unit 140 outputs a light-emitting signal from the light-emitting output terminal EO to the light-emitting line according to the two scanning signals Gs. In this embodiment, the two scanning signals Gs are spaced apart by b unit time lengths. It can be understood that b is the same as the number f of virtual GOA units 131. For example, b can be 6, that is, the two scanning signals Gs are spaced apart by 6 unit time lengths 6H. That is to say, the first light-emitting input terminal EI1 and the second light-emitting input terminal EI2 are respectively connected to the first signal output terminals SO1 of two GOA units 130 at an interval of six levels. For example, the first signal output terminals SO1 of the GOA unit 130 at the i-th level and the GOA unit 130 at the i-6-th level.

[0119] In this embodiment, for the EOA unit 140 at the i-th level, the first light-emitting input terminal EI1 is connected to the first signal output terminal SO1 of the GOA unit 130 at the i-6-th level, and the second light-emitting input terminal EI2 is connected to the first signal output terminal SO1 of the GOA unit 130 at the i-th level.

[0120] In this embodiment, in order to reduce the load of the light-emitting clock signal, two light-emitting clock signals EK are included, and two light-emitting clock signal lines are respectively connected to different EOA units 140. Among them, the two light-emitting clock signals EK are also pulse signals output periodically, and the pulse width of each pulse signal is 1 unit time length 8H. Among them, the light-emitting clock signal EK has a phase opposite to that of the clock signal CK, but the period, frequency, and duty cycle are the same.

[0121] More specifically, please refer to Figure 8 , which is Figure 7 a circuit structure schematic diagram of any one of the scanning driving units as shown. As Figure 8 shown, the GOA unit 130 includes a first pull-up module 31, a first pull-down module 32, a second pull-up module 33, a second pull-down module 34, a first clock signal output module 35, a second clock signal output module 36, a first reset scanning output module 37, and a second reset scanning output module 38.

[0122] The first pull-up module 31 is connected to the enable trigger terminal En, the high-voltage power supply terminal VGH, and the first control node PU, and is used to load the high-potential voltage provided by the high-voltage power supply terminal VGH to the first control node PU under the control of the enable trigger signal provided by the enable trigger terminal En, so as to control the voltage of the first control node PU to be at a high potential.

[0123] The second pull-down module 34 is connected to the first control node PU, the low-voltage power supply terminal VSS, and the second control node PD, and is used to connect the low-voltage power supply terminal VSS to the second control node PD when the voltage of the first control node PU is at a high potential, so as to pull down the potential of the second control node PD, that is, to make the potential of the second control node PD be at a low potential.

[0124] The first pull-down module 32 is connected to the first control node PU, the second control node PD, and the second clock signal input terminal CI2, and is used to pull down the potential of the first control node PU under the control of the clock signal CKe+a provided by the second clock signal input terminal CI2 or when the voltage of the second control node PD is at a high point, that is, to make the potential of the first control node PU be at a low potential.

[0125] The second pull-up module 33 is connected to the high-voltage power supply terminal VGH and the second control node PD, and is used to load the high-potential voltage provided by the high-voltage power supply terminal VGH to the second control node PD when the second control node PD is not loaded with a low potential, so as to raise the potential of the second control node PD.

[0126] The first clock signal output module 35 is connected to the first control node PU, the first clock signal input terminal CI1, and the first signal output terminal SO1, and is used to output the clock signal CKa as the scan signal Gs and the reset scan signal Rs when the voltage of the first control node PU is at a high potential, and at the same time maintain the voltage of the first control node PU at a high potential within a preset period.

[0127] The second clock signal output module 36 is connected to the second control node PD, the low-voltage power supply terminal VSS, and the first signal output terminal SO1, and is used to transmit a low-potential voltage to the first signal output terminal SO1 when the voltage of the second control node PD is at a high potential, so as to stop outputting the scan signal Gs and the reset scan signal Rs.

[0128] The first reset scan output module 37 is connected to the first control node PU, the first clock signal input terminal CI1, the high-voltage power supply terminal VGH, and the second signal output terminal SO2, and is used to output the voltage potential provided by the high-voltage power supply terminal VGH as the compensation scan signal Gr within a preset period under the control of the clock signal when the voltage of the first control node PU is at a high potential.

[0129] The second reset scan output module 38 is connected to the second control node PD, the low-voltage power supply terminal VSS, and the second signal output terminal SO2, and is configured to transmit a low-potential voltage to the second signal output terminal SO2 when the voltage of the second control node PD is at a high potential, thereby stopping the output of the compensation scan signal Gr.

[0130] More specifically, the first pull-up module 31 includes a first switching transistor T1. The first switching transistor T1 includes a first control terminal T10, a first conductive terminal T11, and a second conductive terminal T12. The first control terminal T10 is connected to the enable trigger terminal En, the first conductive terminal T11 is connected to the high-voltage power supply terminal VGH, and the second conductive terminal T12 is connected to the first control node PU. Wherein, the first switching transistor T1 is configured to conduct under the control of the enable trigger signal and load the high-potential voltage provided by the high-voltage power supply terminal VGH to the first control node PU. Correspondingly, the first switching transistor T1 is in a cut-off state when it does not receive the enable trigger signal, thereby stopping loading the high-potential voltage provided by the high-voltage power supply terminal VGH to the first control node PU.

[0131] In this embodiment, the first switching transistor T1 is an N-type thin-film transistor (TFT). Then the corresponding enable trigger signal is a high level, and its gate can be used as the first control terminal T10, or its gate is directly connected to the first control terminal T10; the drain of the first switching transistor T1 can be used as the second conductive terminal T12, or its drain is directly connected to the second conductive terminal T12; the source of the first switching transistor T1 can be used as the first conductive terminal T11, or its source is directly connected to the first conductive terminal T11. In other embodiments of the application, the first switching transistor T1 can also be a P-type thin-film transistor, and then the corresponding enable trigger signal is a low level.

[0132] The first pull-down module 32 includes a seventh switching transistor T7 and an eighth switching transistor T8.

[0133] The seventh switching transistor T7 includes a seventh control terminal T70, a seventh pull-up conductive terminal T71, and a seventh pull-down conductive terminal T72. Among them, the seventh control terminal T70 is connected to the second clock signal input terminal CI2, the seventh pull-up conductive terminal T71 is connected to the first control node PU, and the seventh pull-down conductive terminal T72 is connected to the low-voltage power supply terminal VSS. The seventh switching transistor T7 conducts under the control of the clock signal CKe+a received at the second clock signal input terminal CI2, thereby loading the low-potential voltage of the low-voltage power supply terminal VSS to the first control node PU. Correspondingly, the seventh switching transistor T7 is in a cut-off state when it does not receive the clock signal CKe+a, thereby stopping loading the low-potential voltage provided by the low-voltage power supply terminal VSS to the first control node PU.

[0134] In this embodiment, the seventh switching transistor T7 is an N-type thin film transistor (TFT). Then, the corresponding clock signal CKe+a is turned on when it is at a high level, and its gate can be used as the seventh control terminal T70, or rather, its gate is directly connected to the seventh control terminal T70. The drain of the seventh switching transistor T7 can be used as the seventh pull-up conduction terminal T71, or rather, its drain is directly connected to the seventh pull-up conduction terminal T71. The source of the seventh switching transistor T7 can be used as the seventh pull-down conduction terminal T72, or rather, its source is directly connected to the seventh pull-down conduction terminal T72. In other embodiments of the application, the seventh switching transistor T7 can also be a P-type thin film transistor, and then the corresponding clock signal CKa+b is turned on when it is at a low level.

[0135] The eighth switching transistor T8 includes an eighth control terminal T80, an eighth pull-up conduction terminal T81, and an eighth pull-down conduction terminal T82. Among them, the eighth control terminal T80 is connected to the second control node PD, the eighth pull-up conduction terminal T81 is connected to the first control node PU, and the eighth pull-down conduction terminal T82 is connected to the low-voltage power supply terminal VSS. The eighth switching transistor T8 is turned on under the control of the high voltage of the second control node PD, so as to load the low-potential voltage of the low-voltage power supply terminal VSS to the first control node PU. Correspondingly, when the second control node PD is at a low voltage, the eighth switching transistor T8 is in an off state, so as to stop loading the low-potential voltage provided by the low-voltage power supply terminal VSS to the first control node PU.

[0136] In this embodiment, the eighth switching transistor T8 is an N-type thin film transistor (TFT). Then, the corresponding second control node PD is turned on when it is at a high level, and its gate can be used as the eighth control terminal T80, or rather, its gate is directly connected to the eighth control terminal T80. The drain of the eighth switching transistor T8 can be used as the eighth pull-up conduction terminal T81, or rather, its drain is directly connected to the eighth pull-up conduction terminal T81. The source of the eighth switching transistor T8 can be used as the eighth pull-down conduction terminal T82, or rather, its source is directly connected to the eighth pull-down conduction terminal T82. In other embodiments of the application, the eighth switching transistor T8 can also be a P-type thin film transistor, and then the voltage of the corresponding second control node PD is turned on when it is at a low potential.

[0137] The second pull-up module 33 includes a second switching transistor T2. The second switching transistor T2 includes a second control terminal T20, a second pull-up conduction terminal T21, and a second pull-down conduction terminal T22. Among them, the second control terminal T20 and the second pull-up conduction terminal T21 are both connected to the high-voltage power supply terminal VGH. The second pull-down conduction terminal T22 is connected to the second control node PD. Since the second control terminal T20 and the second pull-up conduction terminal T21 are both connected to the high-voltage power supply terminal VGH, the second switching transistor T2 forms a diode connection, and the second switching transistor T2 can be directly turned on under the control of the high-voltage power supply terminal VGH, so that the high-potential voltage of the high-voltage power supply terminal VDD is applied to the second control node PU. It should be noted that when the second control node PD is not connected to the low potential by other switching transistors, the turned-on second switching transistor T2 will apply the high-potential voltage provided by the high-voltage power supply terminal VDD to the second control node PD. If the second control node PD has been connected to the low-voltage power supply terminal VSS or loaded with a low-potential voltage by other switching transistors, the second switching transistor T2 will not apply the high-potential voltage provided by the high-voltage power supply terminal VDD to the second control node PD.

[0138] In this embodiment, the second switching transistor T2 is an N-type thin-film transistor, and its gate can be used as the second control terminal T20, or its gate is directly connected to the second control terminal T20; the drain of the second switching transistor T2 can be used as the second pull-up conduction terminal T21, or its drain is directly connected to the second pull-up conduction terminal T21; the source of the second switching transistor T2 can be used as the second pull-down conduction terminal T22, or its source is directly connected to the second pull-down conduction terminal T22.

[0139] The second pull-down module 34 includes a sixth switching transistor T6. The sixth switching transistor T6 includes a sixth control terminal T60, a sixth pull-up conduction terminal T61, and a sixth pull-down conduction terminal T62. Among them, the sixth control terminal T60 is connected to the first control node PU, the sixth pull-up conduction terminal T61 is connected to the second control node PD, and the sixth pull-down conduction terminal T62 is connected to the low-voltage power supply terminal VSS. The sixth switching transistor T6 is turned on under the control of the high-potential voltage of the first control node PU, so as to provide the low-potential voltage provided by the low-voltage power supply terminal VSS to the second control node PD, that is, to control the voltage of the second control node PD to be low potential. Correspondingly, the sixth switching transistor T6 is in the cut-off state when the first control node PU is at a low voltage, so as to stop applying the low-potential voltage provided by the low-voltage power supply terminal VSS to the second control node PD.

[0140] In this embodiment, the sixth switching transistor T6 is an N-type thin-film transistor (TFT). Then, when the corresponding first control node PU is at a high level, it conducts. Its gate can serve as the sixth control terminal T60, or its gate is directly connected to the sixth control terminal T60. The drain of the sixth switching transistor T6 can serve as the sixth pull-up conductive terminal T61, or its drain is directly connected to the sixth pull-up conductive terminal T61. The source of the sixth switching transistor T6 can serve as the sixth pull-down conductive terminal T62, or its source is directly connected to the sixth pull-down conductive terminal T62. In other embodiments of the application, the sixth switching transistor T6 can also be a P-type thin-film transistor, and then it conducts when the voltage of the corresponding first control node PD is at a low level.

[0141] The first clock signal output module 35 includes a third clock output switching transistor T3a and a storage capacitor Cc. The third clock output switching transistor T3a includes a third clock output control terminal T310, a first clock output conductive terminal T311, and a second clock output conductive terminal T312. Among them, the third clock output control terminal T310 is connected to the first control node PU, the first clock output conductive terminal T311 is connected to the first clock signal input terminal CI1, the second clock output conductive terminal T312 is connected to the first signal output terminal SO1, and the storage capacitor Cc is connected between the first control node PU and the first signal output terminal SO1. The storage capacitor Cc is used to maintain the voltage of the first control node PU at a high level. The third clock output switching transistor T3a conducts under the control of the high-level voltage of the first control node PU, so as to output the clock signal CKa provided by the first clock signal input terminal CI1 as the scan signal Gs and the reset scan signal Rs from the first signal output terminal SO1. Correspondingly, it can be understood that when the third clock output switching transistor T3a conducts, if the first clock signal input terminal CI1 stops providing the clock signal CKa, the output of the scan signal Gs and the reset scan signal Rs from the first signal output terminal SO1 stops.

[0142] In this embodiment, the third clock output switching transistor T3a is an N-type thin-film transistor (TFT). Then, when the corresponding first control node PU is at a high level, it conducts. Its gate can serve as the third clock output control terminal T310, or its gate is directly connected to the third clock output control terminal T310. The source of the third clock output switching transistor T3a can serve as the first clock output conductive terminal T311, or its source is directly connected to the first clock output conductive terminal T311. The drain of the third clock output switching transistor T3a can serve as the second clock output conductive terminal T312, or its drain is directly connected to the second clock output conductive terminal T312. In other embodiments of the application, the third clock output switching transistor T3a can also be a P-type thin-film transistor, and then it conducts when the voltage of the corresponding first control node PD is at a low level.

[0143] The second clock signal output module 36 includes a fourth clock output switching transistor T4a. The fourth clock output switching transistor T4a includes a fourth clock output control terminal T410, a third clock output conduction terminal T413, and a fourth clock output conduction terminal T414. Among them, the fourth clock output control terminal T410 is connected to the second control node PD, the third clock output conduction terminal T413 is connected to the low-voltage power supply terminal VSS, and the fourth clock output conduction terminal T414 is connected to the first signal output terminal SO1. The fourth clock output switching transistor T4a is turned on under the control of the high-potential voltage of the second control node PD, so as to output the low-potential voltage provided by the low-voltage power supply section VSS from the first signal output terminal SO1, thereby ensuring that the first signal output terminal SO1 accurately stops outputting the scan signal Gs and the reset scan signal Rs. Correspondingly, when the second control node PD is at a low-potential voltage, the fourth clock output switching transistor T4a is cut off, so as to stop outputting the low-potential voltage provided by the low-voltage conduction terminal VSS from the first signal output terminal SO1.

[0144] In this embodiment, the fourth clock output switching transistor T4a is an N-type thin-film transistor, so it is turned on when the corresponding second control node PD is at a high level. Its gate can be used as the fourth clock output control terminal T410, or its gate is directly connected to the fourth clock output control terminal T410; the source of the fourth clock output switching transistor T4a can be used as the third clock output conduction terminal T413, or its source is directly connected to the third clock output conduction terminal T413; the drain of the fourth clock output switching transistor T4a can be used as the fourth clock output conduction terminal T414, or its drain is directly connected to the fourth clock output conduction terminal T414. In other embodiments of the application, the fourth clock output switching transistor T4a can also be a P-type thin-film transistor, so it is turned on when the voltage of the corresponding second control node PD is at a low level.

[0145] The first reset scan output module 37 includes a third compensation scan output switching transistor T3b, a fifth compensation scan output switching transistor T5a, and a compensation capacitor Cm.

[0146] Specifically, the fifth compensation scan output switching transistor T5a includes a fifth compensation scan output control terminal T510, a fifth compensation scan output conduction terminal T515, and a sixth compensation scan output conduction terminal T516. Among them, the fifth compensation scan output control terminal T510 is connected to the first clock signal input terminal CI1 through a compensation capacitor Cm, that is, the compensation capacitor Cm is connected between the first clock signal input terminal CI1 and the fifth compensation scan output control terminal T510 of the fifth compensation scan output switching transistor T5a. The fifth compensation scan output conduction terminal T515 is connected to the first control node PU, and the sixth compensation scan output conduction terminal T516 is connected to the third control node PUB. The fifth compensation scan output switching transistor T5a is turned on under the control of the clock signal CKa provided by the first clock signal input terminal CI1, so as to transmit and load the high-potential voltage of the first control node PU to the third control node PUB, so that the voltage of the third control node PUB also corresponds to a high potential. In this embodiment, the width-to-length ratio (W / L) of the conductive channel in the fifth compensation scan output switching transistor T5a is relatively large, that is, its parasitic capacitance is relatively large. After being turned on under the control of the clock signal CKa provided by the first clock signal input terminal CI1, it can maintain the on state within a preset period, so as to continuously control the high-potential voltage of the first control node PU to be transmitted and loaded to the third control node PUB within the preset period, so as to ensure that the voltage of the third control node PUB is at a high potential. In this embodiment, the duration of the preset period is 5 unit durations (5H). Of course, in other embodiments of the present application, the preset period can be adjusted according to actual needs.

[0147] The third compensation scan output switching transistor T3b includes a third compensation scan output control terminal T320, a first compensation scan output conduction terminal T321, and a second compensation scan output conduction terminal T322. Among them, the third compensation scan output control terminal T320 is connected to the third control node PUB, the first compensation scan output conduction terminal T321 is connected to the high-voltage power supply terminal VGH, and the second compensation scan output conduction terminal T322 is connected to the second signal output terminal SO2. The third compensation scan output switching transistor T3b is turned on under the control of the high-potential voltage provided by the third control node PUB, so as to transmit and load the high-potential voltage provided by the high-voltage power supply terminal VGH to the second signal output terminal SO2, so as to output it as a compensation scan signal Gr.

[0148] In this embodiment, the fifth compensation scan output switching transistor T5a and the third compensation scan output switching transistor T3b are also N-type thin film transistors. In the fifth compensation scan output switching transistor T5a, when the clock signal CKa provided by the corresponding first clock signal input terminal CI1 is at a high level, it is turned on, and its gate can be used as the fifth compensation scan output control terminal T510, or rather, its gate is directly connected to the fifth compensation scan output control terminal T510; the source of the fifth compensation scan output switching transistor T5a can be used as the fifth compensation scan output conducting terminal T515, or rather, its source is directly connected to the fifth compensation scan output conducting terminal T515; the drain of the fifth compensation scan output switching transistor T5a can be used as the sixth compensation scan output conducting terminal T516, or rather, its drain is directly connected to the sixth compensation scan output conducting terminal T516. In the third compensation scan output switching transistor T3b, when the voltage at the corresponding third control node PUB is at a high level, it is turned on, and its gate can be used as the third compensation scan output control terminal T320, or rather, its gate is directly connected to the third compensation scan output control terminal T320; the source of the third compensation scan output switching transistor T3b can be used as the first compensation scan output conducting terminal T321, or rather, its source is directly connected to the first compensation scan output conducting terminal T321; the drain of the third compensation scan output switching transistor T3b can be used as the second compensation scan output conducting terminal T322, or rather, its drain is directly connected to the second compensation scan output conducting terminal T322.

[0149] In other embodiments of the application, the fifth compensation scan output switching transistor T5a and the third compensation scan output switching transistor T3b can also be P-type thin film transistors, and then they are turned on when the clock signal CKa provided by the corresponding first clock signal input terminal CI1 and the voltage at the third control node PUB are at a low level.

[0150] The second reset scan output module 38 includes a fourth compensation scan turn-off switching transistor T4b and a fifth compensation scan turn-off switching transistor T5b.

[0151] The fourth compensation scan shutdown switch transistor T4b includes a fourth compensation shutdown control terminal T420, a first compensation scan shutdown conduction terminal T421, and a second compensation scan shutdown conduction terminal T422. Among them, the fourth compensation shutdown control terminal T420 is connected to the second control node PD, the first compensation scan shutdown conduction terminal T421 is connected to the low-voltage conduction terminal VSS, and the second compensation scan shutdown conduction terminal T422 is connected to the second signal output terminal SO2. The fourth compensation scan shutdown switch transistor T4b is turned on under the control of the high-potential voltage of the second control node PD, so as to output the low-potential voltage provided by the low-voltage conduction terminal VSS from the second signal output terminal SO2, thereby ensuring that the second signal output terminal SO2 accurately stops outputting the compensation scan signal Gs. Correspondingly, when the second control node PD is at a low-potential voltage, the fourth compensation scan shutdown switch transistor T4b is cut off, thereby stopping the output of the low-potential voltage provided by the low-voltage conduction terminal VSS from the second signal output terminal SO2.

[0152] In this embodiment, the fourth compensation scan shutdown switch transistor T4b is an N-type thin-film transistor (TFT). Then, when the corresponding second control node PD is at a high level, it is turned on. Its gate can be used as the fourth compensation shutdown control terminal T420, or its gate is directly connected to the fourth compensation shutdown control terminal T420; the source of the fourth compensation scan shutdown switch transistor T4b can be used as the first compensation scan shutdown conduction terminal T421, or its source is directly connected to the first compensation scan shutdown conduction terminal T421; the drain of the fourth compensation scan shutdown switch transistor T4b can be used as the second compensation scan shutdown conduction terminal T422, or its drain is directly connected to the second compensation scan shutdown conduction terminal T422. In other embodiments of the application, the fourth compensation scan shutdown switch transistor T4b can also be a P-type thin-film transistor, and then it is turned on when the voltage of the corresponding second control node PD is at a low level.

[0153] The fifth compensation scan shutdown switch transistor T5b includes a fifth compensation scan shutdown control terminal T520, a third compensation scan output conduction terminal T523, and a fourth compensation scan shutdown conduction terminal T524. Among them, the fifth compensation scan shutdown control terminal T520 is connected to the second control node PD, the third compensation scan output conduction terminal T523 is connected to the first control node PU, and the fourth compensation scan shutdown conduction terminal T524 is connected to the third control node PUB. The fifth compensation scan shutdown switch transistor T5b is turned on under the control of the high-potential voltage provided by the second control node PD, so as to transmit and load the low-potential voltage of the first control node PU to the third control node PUB, so that the voltage of the third control node PUB also corresponds to a low potential.

[0154] In this embodiment, the fifth compensation scan turn-off switch transistor T5b is an N-type thin-film transistor. The fifth compensation scan turn-off switch transistor T5b is turned on when the high-potential voltage provided by the second control node PD, and its gate can be used as the fifth compensation scan turn-off control terminal T520, or rather its gate is directly connected to the fifth compensation scan turn-off control terminal T520; the source of the fifth compensation scan turn-off switch transistor T5b can be used as the third compensation scan output conduction terminal T523, or rather its source is directly connected to the third compensation scan output conduction terminal T523; the drain of the fifth compensation scan turn-off switch transistor T5b can be used as the fourth compensation scan turn-off conduction terminal T524, or rather its drain is directly connected to the fourth compensation scan turn-off conduction terminal T524. In other embodiments of the application, the fifth compensation scan turn-off switch transistor T5b can also be a P-type thin-film transistor, and then it is turned on when the voltage of the corresponding second control node PD is at a low potential.

[0155] Please refer to Figure 9 , which is Figure 8 the working timing diagram of the scan driving unit shown. Among them, STV / Gs(i-1) is the waveform schematic diagram of the enable trigger signal provided by the enable signal terminal EN, CK(e) is the waveform schematic diagram of the clock signal CKe loaded by the first clock signal input terminal CI1, CK(e+a) is the waveform schematic diagram of the clock signal CKe+a loaded by the second clock signal input terminal CI2, PU is the voltage waveform schematic diagram of the first control node PU, PUB is the voltage waveform schematic diagram of the third control node PUB, PD is the voltage waveform schematic diagram of the second control node PD, Si is the waveform schematic diagram of the scan signal Gs and the reset scan signal Rs output by the first signal output terminal SO1, and R(n+m) is the waveform schematic diagram of the compensation scan signal Gri output by the second signal output terminal SO2.

[0156] Now in combination with Figures 8 - 9 , the working process of the GOA unit 130 will be specifically described.

[0157] During the enable trigger period EH, the enable trigger signal STV is output and loaded to the first control terminal T10 of the first switch transistor T1. The first switch transistor T1 is turned on under the control of the enable trigger signal, so as to load the high-potential voltage provided by the high-voltage power supply terminal VGH to the first control node PU, and pull up the voltage of the first control node PU to a high potential.

[0158] Since the voltage of the first control node PU is at a high potential, the corresponding control makes the sixth switching transistor T6 and the third clock output switching transistor T3a conduct. When the sixth switching transistor T6 conducts, the corresponding control makes the second control node PD at a low potential. When the third clock output switching transistor T3a conducts, the voltage of the first clock signal input terminal CI1 is output at the first signal output terminal SO1. It can be understood that at this time, the first clock signal input terminal CI1 does not receive the clock signal CKa, so the first signal output terminal SO1 does not output the clock signal CKa.

[0159] During the compensation period H2 and the data loading period H3, the first clock signal input terminal CI1 loads the clock signal CKa. Due to the storage effect of the energy storage capacitor Cc, the voltage of the first control node PU is further increased, so as to more accurately and stably control the third clock output switching transistor T3a to be in a conducting state. At this time, the clock signal CKa is output from the first signal output terminal SO1 through the third clock output switching transistor T3a to be used as the scanning signal Gsi of the current scanning line and the reset scanning signal Rsi of the GOA unit 130 with a preset level interval.

[0160] Meanwhile, the clock signal CKa is also transmitted from the first clock signal input terminal CI1 to the compensation capacitor Cm. The fifth compensation scanning output switching transistor T5a conducts under the control of the clock signal CKa provided by the first clock signal input terminal CI1 through the compensation capacitor Cm, so as to transmit and load the high-potential voltage of the first control node PU to the third control node PUB, making the voltage of the third control node PUB also corresponding to a high potential. Accordingly, the third compensation scanning output switching transistor T3b conducts under the control of the high-potential voltage provided by the third control node PUB, so as to transmit and load the high-potential voltage provided by the high-voltage power supply terminal VGH to the second signal output terminal SO2 to be output as the compensation scanning signal Gr.

[0161] After the clock signal CKa stops outputting after continuously outputting for a unit duration of 1H, although the third clock output switching transistor T3a is still in the on state, since the clock signal CKa stops outputting, the corresponding first signal output terminal SO1 stops outputting the scan signal Gs and the reset scan signal Rs. However, since the fifth compensation scan output switching transistor T5a can maintain the on state within a preset period after being turned on, the high-potential voltage transmission of the first control node PU is continuously controlled to be loaded to the third control node PUB within the preset period to ensure that the voltage of the third control node PUB is at a high potential. Then, the third compensation scan output switching transistor T3b can also be in the on state within the preset period, and can continuously transmit and load the high-potential voltage provided by the high-voltage power supply terminal VGH to the second signal output terminal SO2 within this preset period as the compensation scan signal Gr output, that is, continuously output the compensation scan signal Gr within the preset period. In this embodiment, the compensation scan signal Gr can be continuously output within a period of 5 unit durations of 5H.

[0162] After the compensation period H2, that is, after the preset period, the second clock signal input terminal CI2 receives the clock signal CKe+a, and the seventh switching transistor T7 and the eighth switching transistor T8 are turned on, so that the low-potential voltage of the low-voltage power supply terminal VSS is loaded to the first control node PU to pull down the voltage of the first control node PU to a low potential. Thus, the corresponding third clock output switching transistor T3a, fifth compensation scan output switching transistor T5a, and sixth switching transistor T6 are all turned off.

[0163] At the same time, the second switching transistor T2 is turned on under the control of the high-voltage power supply terminal VGH, so that the high-potential voltage of the high-voltage power supply terminal VDD is loaded to the second control node PD. The eighth switching transistor T8 is turned on under the control of the high-potential voltage of the second control node PD, so as to further pull down the voltage of the first control node PU to a low potential. Correspondingly, the fourth clock output switching transistor T4a, fourth compensation scan off-switching transistor T4b, and fifth compensation scan off-switching transistor T5b are all turned on, and the corresponding scan signal Gs, reset scan signal Rs, and compensation scan signal Gr output by the first signal output terminal SO1 and the second signal output terminal SO2 are accurately controlled to stop outputting.

[0164] In this embodiment, through the first clock signal output module 35, the second clock signal output module 36, the first reset scan output module 37, and the second reset scan output module 38 included in the GOA unit 130, it is possible to output scan signals Gs and compensation scan signals Gr with different durations. That is to say, in a single GOA unit 130, it is possible to output scan signals Gs and reset scan signals Rs, output compensation scan signals Gr, and ensure that the durations of the scan signals Gs and the compensation scan signals Gr are different, effectively simplifying the circuit structure of the GOA unit 130, improving the signal output efficiency of the GOA unit 130, and increasing the integration level and design space of the scan driving circuit 13.

[0165] Please refer to Figure 10 , which is a schematic circuit diagram of any one of the light-emitting driving units as shown in Figure 7 .

[0166] As shown in Figure 10 , the EOA unit 140 includes a first light-emitting pull-up module 41, a first light-emitting pull-down module 42, a second light-emitting pull-up module 43, a second light-emitting pull-down module 44, a first light-emitting signal output module 45, and a second light-emitting signal output module 46.

[0167] The first light-emitting pull-up module 41 is connected to the light-emitting clock signal input terminal EKI, the light-emitting high-voltage power supply terminal EVGH, and the first light-emitting control node EPU, and is used to load the high-potential voltage provided by the light-emitting high-voltage power supply terminal EVGH to the first light-emitting control node EPU under the control of the light-emitting clock signal EK, so as to control the voltage of the first light-emitting control node EPU to be at a high potential.

[0168] Specifically, the first light-emitting pull-up module 41 includes a first light-emitting switching transistor ET1. The first light-emitting switching transistor ET1 includes a first light-emitting control end ET10, a first light-emitting conduction end ET11, and a second light-emitting conduction end ET12. The first light-emitting control end ET10 is connected to the light-emitting clock signal input terminal EKI, the first light-emitting conduction end ET11 is connected to the light-emitting high-voltage power supply terminal EVGH, and the second light-emitting conduction end ET12 is connected to the first light-emitting control node EPU. Among them, the first light-emitting switching transistor ET1 is used to conduct under the control of the light-emitting clock signal EK and load the high-potential voltage provided by the light-emitting high-voltage power supply terminal EVGH to the first light-emitting control node EPU. Correspondingly, the first light-emitting switching transistor ET1 is in an off state when it does not receive the light-emitting clock signal EK, so as to stop loading the high-potential voltage provided by the light-emitting high-voltage power supply terminal EVGH to the first light-emitting control node EPU.

[0169] In this embodiment, the first light-emitting switching transistor ET1 is an N-type thin-film transistor. When the corresponding light-emitting clock signal EK is at a high level, it controls the conduction of the transistor. Its gate can be used as the first light-emitting control terminal ET10, or its gate is directly connected to the first light-emitting control terminal ET10. The drain of the first light-emitting switching transistor ET1 can be used as the second light-emitting conduction terminal ET12, or its drain is directly connected to the second light-emitting conduction terminal ET12. The source of the first light-emitting switching transistor ET1 can be used as the first light-emitting conduction terminal ET11, or its source is directly connected to the first light-emitting conduction terminal ET11. In other embodiments of the application, the first light-emitting switching transistor ET1 can also be a P-type thin-film transistor. When the corresponding light-emitting clock signal EK is at a high level, it controls the conduction of the transistor.

[0170] The first light-emitting pull-down module 42 is connected to the first light-emitting control node EPU, the second light-emitting control node EPD, and the light-emitting low-voltage power supply terminal EVSS. When the voltage of the second light-emitting control node EPD is at a high potential, it loads the low-potential voltage provided by the light-emitting low-voltage power supply terminal EVSS to the first light-emitting control node EPU, that is, pulls down the potential of the first light-emitting control node EPU.

[0171] Among them, the first light-emitting pull-down module 42 includes a seventh light-emitting switching transistor ET7. The seventh light-emitting switching transistor ET7 includes a seventh light-emitting control terminal ET70, a seventh light-emitting pull-up conduction terminal ET71, and a seventh light-emitting pull-down conduction terminal ET72. Among them, the seventh light-emitting control terminal ET70 is connected to the second light-emitting control node EPD, the seventh light-emitting pull-up conduction terminal ET71 is connected to the first light-emitting control node EPU, and the seventh light-emitting pull-down conduction terminal ET72 is connected to the light-emitting low-voltage power supply terminal EVSS. The seventh light-emitting switching transistor ET7 is turned on under the control of the high-potential voltage of the second light-emitting control node EPD, so as to load the low-potential voltage of the light-emitting low-voltage power supply terminal EVSS to the first light-emitting control node EPU. Correspondingly, when the voltage of the second light-emitting control node EPD is at a low potential, the seventh light-emitting switching transistor ET7 is in an off state, so as to stop loading the low-potential voltage provided by the light-emitting low-voltage power supply terminal EVSS to the first light-emitting control node EPU.

[0172] In this embodiment, the seventh light-emitting switch transistor ET7 is an N-type thin-film transistor (TFT). Correspondingly, the clock signal CKe+a is turned on when it is at a high level. Its gate can serve as the seventh control terminal T70, or rather, its gate is directly connected to the seventh light-emitting control terminal ET70. The drain of the seventh light-emitting switch transistor ET7 can serve as the seventh light-emitting pull-up conduction terminal ET71, or rather, its drain is directly connected to the seventh light-emitting pull-up conduction terminal ET71. The source of the seventh light-emitting switch transistor ET7 can serve as the seventh light-emitting pull-down conduction terminal ET72, or rather, its source is directly connected to the seventh light-emitting pull-down conduction terminal ET72. In other embodiments of the application, the seventh light-emitting switch transistor ET7 can also be a P-type thin-film transistor.

[0173] The second light-emitting pull-up module 43 is connected to the first light-emitting input terminal EI1, the second light-emitting input terminal EI2, and the second light-emitting control node EPD, and is used to raise the voltage potential of the second light-emitting control node EPD when the scan signal received at the first light-emitting input terminal EI1 or the second light-emitting input terminal EI2 is high.

[0174] The second light-emitting pull-up module 43 includes a second pull-up reset switch transistor ET2a and a second pull-up write switch transistor ET2b. The second pull-up reset switch transistor ET2a includes a second pull-up reset control terminal ET210, a first pull-up reset conduction terminal ET211, and a second pull-up reset conduction terminal ET212. Among them, the second pull-up reset control terminal ET210 and the first pull-up reset conduction terminal ET211 are both connected to the first light-emitting input terminal EI1, and the second pull-up reset conduction terminal ET212 is connected to the second light-emitting control node EPD. The second pull-up reset switch transistor ET2a is turned on under the control of the high-potential voltage of the scan signal Gs provided by the first light-emitting input terminal EI1, so as to transmit and load the high potential of the scan signal Gs to the second light-emitting control node EPD.

[0175] Correspondingly, it can be understood that when the second pull-up reset switch transistor ET2a is turned on, if the first light-emitting input terminal EI1 stops providing the scan signal Gs, the loading of the high-potential voltage to the second light-emitting control node EPD stops. And it should be noted that when the second light-emitting control node EPD is not connected to a low potential by other switch transistors, the turned-on second pull-up reset switch transistor ET2a will load the high-potential voltage provided by the scan signal Gs to the second light-emitting control node EPD. If the second light-emitting control node EPD has been connected to the light-emitting low-voltage power supply terminal EVSS through other switch transistors, the second pull-up reset switch transistor ET2a will not load the high-potential voltage in the scan signal Gs to the second light-emitting control node EPD.

[0176] Similarly, the second pull-up write switch transistor ET2b includes a second pull-up write control terminal ET220, a first pull-up write conduction terminal ET221, and a second pull-up write conduction terminal ET222. Among them, the second pull-up write control terminal ET220 and the first pull-up write conduction terminal ET221 are both connected to the second light-emitting input terminal EI2, and the second pull-up write conduction terminal ET222 is connected to the second light-emitting control node EPD. The second pull-up write switch transistor T2b is turned on under the control of the high-potential voltage of the scan signal Gs provided by the second light-emitting input terminal EEI2, so as to transmit and load the high potential of the scan signal Gs to the second light-emitting control node EPD.

[0177] In this embodiment, the second pull-up reset switch transistor ET2a and the second pull-up write switch transistor ET2b are N-type thin-film transistors. Their gates can serve as or be directly connected to the second pull-up reset control terminal ET210 and the second pull-up write control terminal ET220, while the source and drain electrodes can serve as the corresponding conduction terminals or be directly connected to the corresponding conduction terminals. Of course, in other embodiments of the present application, the second pull-up reset switch transistor ET2a and the second pull-up write switch transistor ET2b can also be P-type thin-film transistors.

[0178] The second light-emitting pull-down module 44 is connected to the first light-emitting control node EPU, the second light-emitting control node EPU, and the light-emitting low-voltage power supply terminal EVSS. When the first light-emitting control node EPU is at a high-potential voltage, it is used to load the low-potential voltage provided by the light-emitting low-voltage power supply terminal EVSS to the second light-emitting control node EPD, that is, to pull down the potential of the second light-emitting control node EPD.

[0179] Specifically, the second light-emitting pull-down module 44 includes a sixth light-emitting switch transistor ET6. The sixth light-emitting switch transistor ET6 includes a sixth light-emitting control terminal ET60, a sixth light-emitting pull-up conduction terminal ET61, and a sixth light-emitting pull-down conduction terminal ET62. Among them, the sixth light-emitting control terminal ET60 is connected to the first light-emitting control node EPU, the sixth light-emitting pull-up conduction terminal ET61 is connected to the second light-emitting control node EPU, and the sixth light-emitting pull-down conduction terminal ET62 is connected to the light-emitting low-voltage power supply terminal EVSS. The sixth light-emitting switch transistor ET6 is turned on under the control of the high-potential voltage of the first light-emitting control node EPU, so as to provide the low-potential voltage provided by the light-emitting low-voltage power supply terminal EVSS to the second light-emitting control node EPD, that is, to control the voltage of the second light-emitting control node EPD to be at a low potential. Correspondingly, the sixth light-emitting switch transistor ET6 is in an off state when the first light-emitting control node EPU is at a low voltage, so as to stop loading the low-potential voltage provided by the light-emitting low-voltage power supply terminal EVSS to the second light-emitting control node EPD.

[0180] In this embodiment, the sixth light-emitting switch transistor ET6 is an N-type thin-film transistor (TFT). Then, when the corresponding first light-emitting control node EPU is at a high level, it conducts, and its gate can be used as the sixth light-emitting control terminal ET60, or rather, its gate is directly connected to the sixth light-emitting control terminal ET60. The drain of the sixth light-emitting switch transistor ET6 can be used as the sixth light-emitting pull-up conduction terminal ET61, or rather, its drain is directly connected to the sixth light-emitting pull-up conduction terminal ET61. The source of the sixth light-emitting switch transistor ET6 can be used as the sixth light-emitting pull-down conduction terminal ET62, or rather, its source is directly connected to the sixth light-emitting pull-down conduction terminal ET62. In other embodiments of the application, the sixth light-emitting switch transistor ET6 can also be a P-type thin-film transistor, and then it conducts when the voltage of the corresponding first light-emitting control node EPD is at a low potential.

[0181] The first light-emitting signal output module 45 is connected to the first light-emitting control node EPU, the light-emitting high-voltage power supply terminal EVGH, and the light-emitting output terminal EO, and is configured to output the high-potential voltage provided by the light-emitting high-voltage power supply terminal EVGH as a light-emitting signal from the light-emitting output terminal EO under the control of the high potential of the first light-emitting control node EPU within a second preset duration.

[0182] The first light-emitting signal output module 45 includes a third light-emitting output switch transistor ET3 and a light-emitting energy storage capacitor ECc. The third light-emitting clock output switch transistor ET3 includes a third light-emitting output control terminal ET30, a first light-emitting output conduction terminal ET31, and a second light-emitting output conduction terminal ET32. Among them, the third light-emitting output control terminal ET30 is connected to the first light-emitting control node EPU, the first light-emitting output conduction terminal ET31 is connected to the light-emitting high-voltage power supply terminal EVGH, and the second light-emitting output conduction terminal ET32 is connected to the light-emitting output terminal EO.

[0183] The light-emitting energy storage capacitor ECc is connected between the first light-emitting control node EPU and the light-emitting output terminal EO. The light-emitting energy storage capacitor ECc is used to maintain the voltage of the first light-emitting control node EPU at a high potential during a preset period. In this embodiment, the duration of the preset period is 5 unit durations (5H). Of course, in other embodiments of the present application, the preset period can be adjusted according to actual needs.

[0184] The third light-emitting output switch transistor ET3 conducts under the control of the high-potential voltage of the first light-emitting control node EPU, so as to output the high-potential voltage provided by the light-emitting high-voltage power supply terminal EVGH as a light-emitting signal Es from the light-emitting output terminal EO.

[0185] In this embodiment, the third light-emitting output switching transistor ET3 is an N-type thin-film transistor, whose gate can serve as the third light-emitting output control terminal ET30, or rather, its gate is directly connected to the third light-emitting output control terminal ET30; its source and drain can respectively serve as two conductive terminals. In other embodiments of the present application, the third light-emitting output switching transistor ET3 can also be a P-type thin-film transistor, and then it conducts when the voltage of the corresponding first light-emitting control node EPD is at a low potential.

[0186] The second light-emitting signal output module 46 is connected to the second light-emitting control node EPD, the light-emitting low-voltage power supply terminal EVSS, the light-emitting clock signal input terminal EKI, and the light-emitting output terminal EO. The second light-emitting signal output module 46 is configured to control the light-emitting output terminal EO to stop outputting the light-emitting signal when the voltage of the second light-emitting control node EPD is at a high potential or when it receives the light-emitting clock signal.

[0187] The second light-emitting signal output module 46 includes a first light-emitting turn-off switching transistor ET4 and a second light-emitting turn-off switching transistor ET5. The second light-emitting signal output module 46 is configured to be connected to the second light-emitting control node EPD, the second light-emitting input terminal EI2, and the light-emitting output terminal EO, and is configured to control the light-emitting output terminal EO to stop outputting the light-emitting signal Es when it receives the light-emitting clock signal EK or when the second light-emitting control node EPD is at an effective trigger potential.

[0188] The first light-emitting turn-off switching transistor ET4 includes a first light-emitting turn-off control terminal ET40, a first light-emitting turn-off conductive terminal ET41, and a second light-emitting turn-off conductive terminal ET42. Among them, the first light-emitting turn-off control terminal ET40 is connected to the second light-emitting control node EPD, the first light-emitting turn-off conductive terminal ET41 is connected to the light-emitting clock signal input terminal EKI, and the second light-emitting turn-off conductive terminal T42 is connected to the light-emitting output terminal EO. The first light-emitting turn-off switching transistor ET4 conducts under the control of the high-potential voltage of the second light-emitting control node EPD, so as to output the light-emitting clock signal provided by the light-emitting clock signal input terminal EKI from the output light-emitting output terminal EO, that is, to load the transmission of the light-emitting clock signal input terminal EKI to the output light-emitting output terminal EO. In this embodiment, when the second light-emitting control node EPD is at a high potential, the light-emitting clock signal input terminal EKI does not output the light-emitting clock signal EK, and at this time, the corresponding light-emitting output terminal EO stops outputting the light-emitting signal Es.

[0189] In this embodiment, the first light-emitting turn-off switch transistor ET4 is an N-type thin-film transistor, which conducts when the voltage at the second light-emitting control node EPD is at a high potential and cuts off when the voltage at the second light-emitting control node EPD is at a low potential. Its gate can serve as or be directly connected to the first light-emitting turn-off control terminal T40, and its source and drain electrodes serve as two conductive terminals respectively. In other embodiments of the application, the first light-emitting turn-off switch transistor ET4 can also be a P-type thin-film transistor, which can conduct when the voltage at the second light-emitting control node EPD is at a low potential and cut off when the voltage at the second light-emitting control node EPD is at a high potential.

[0190] The second light-emitting turn-off switch transistor ET5 includes a second light-emitting turn-off control terminal ET50, a third light-emitting turn-off conductive terminal ET53, and a fourth light-emitting turn-off conductive terminal ET54. Among them, the second light-emitting turn-off control terminal ET50 is connected to the light-emitting clock signal input terminal EKI, the third light-emitting turn-off conductive terminal T53 is connected to the light-emitting low-voltage power supply terminal EVSS, and the fourth light-emitting turn-off conductive terminal ET54 is connected to the second light-emitting control node EPD.

[0191] The second light-emitting turn-off switch transistor ET5 conducts under the control of the high-potential voltage of the light-emitting clock signal EK provided by the light-emitting clock signal input terminal EKI, thereby loading the low-potential voltage provided by the light-emitting low-voltage power supply terminal EVSS to the second light-emitting control node EPD, and further controlling the first light-emitting turn-off switch transistor ET4 to be in a cut-off state, further accurately preventing the light-emitting clock signal EK provided by the light-emitting clock signal input terminal EKI from being transmitted to the light-emitting output terminal EO through the first light-emitting turn-off switch transistor ET4.

[0192] In this embodiment, the second light-emitting turn-off switch transistor ET5 is an N-type thin-film transistor, whose gate can serve as or be directly connected to the second light-emitting turn-off control terminal T50, and its source and drain electrodes serve as two conductive terminals respectively. In other embodiments of the application, the second light-emitting turn-off switch transistor ET5 can also be a P-type thin-film transistor.

[0193] Please refer to Figure 11 which is the working timing diagram of the light-emitting driving unit as shown in Figure 10 . Among them, Gs(i-b) is the waveform schematic diagram of the scanning signal output by the first light-emitting input terminal EI1, Gsi is the waveform schematic diagram of the scanning signal output by the second light-emitting input terminal EI2, ECK is the waveform schematic diagram of the light-emitting clock signal, EPU is the voltage waveform schematic diagram of the first light-emitting control node EPU, EPD is the voltage waveform schematic diagram of the second light-emitting control node EPD, and Es is the waveform schematic diagram of the light-emitting signal Es output by the light-emitting output terminal EO.

[0194] Now in combination with Figures 10 - 11 , the working process of the EOA unit 140 will be specifically described.

[0195] During the reset period H1, the scan signal Gs provided by the first light-emitting input terminal EI1 controls the second pull-up reset switch transistor ET2a to conduct, and loads the high-potential voltage in the scan signal Gs to the second light-emitting control node EPD, thereby pulling up the voltage of the second light-emitting control node EPD to a high potential.

[0196] The high-potential voltage of the first light-emitting control node PU controls the seventh light-emitting transistor ET7 to be in a conducting state, and then loads the low-potential voltage provided by the light-emitting low-voltage conductive end EVSS to the first light-emitting control node EPU. At the same time, the high-potential voltage of the first light-emitting control node PU controls the first light-emitting turn-off switch transistor ET4 to conduct, thereby transmitting the low voltage of the light-emitting clock signal EK in the light-emitting clock signal input terminal EKI at this time to the light-emitting output terminal EO.

[0197] During the compensation scan period H2 and the light-emitting period H4, the light-emitting clock signal input terminal EKI controls the first light-emitting switch transistor ET1 to conduct, thereby loading the high-potential voltage in the light-emitting high-voltage power supply terminal EVGH to the first light-emitting control node EPU, thereby pulling up the voltage of the first light-emitting control node EPU to a high potential.

[0198] The high-potential voltage of the first light-emitting control node EPU controls the third light-emitting output switch transistor ET3 to conduct, thereby loading the high-potential voltage in the light-emitting high-voltage power supply terminal EVGH to the light-emitting output terminal EO as the light-emitting signal Es for output. Due to the storage effect of the light-emitting energy storage capacitor ECc, the voltage of the first light-emitting control node EPU is accurately and stably maintained at a high potential state, thereby controlling the third light-emitting output switch transistor ET3 to continuously conduct, and further maintaining the continuous output of the light-emitting signal Es within a preset period.

[0199] At the same time, the high-potential voltage of the first light-emitting control node EPU controls the sixth light-emitting switch transistor ET6 to conduct, so that the low-potential voltage provided by the light-emitting low-voltage power supply terminal EVSS is loaded to the second light-emitting control node EPD, that is, pulling down the potential of the second light-emitting control node EPD to ensure the accurate output of the light-emitting signal Es.

[0200] During the data loading period H3, the scan signal Gs provided by the second light-emitting input terminal EI2 controls the second pull-up write switch transistor ET2b to conduct, and loads the high-potential voltage in the scan signal Gs to the second light-emitting control node EPD, thereby pulling up the voltage of the second light-emitting control node EPD to a high potential.

[0201] Similarly, the high potential of the voltage of the first light-emitting control node PU controls the seventh light-emitting transistor ET7 to be in a conducting state, and then loads the low-potential voltage provided by the light-emitting low-voltage conductive terminal EVSS to the first light-emitting control node EPU, causing the third light-emitting output switching transistor ET3 to cut off, and the light-emitting output terminal EO stops outputting the high-potential voltage provided by the light-emitting high-voltage power supply terminal EVGH.

[0202] Meanwhile, the high potential of the voltage of the first light-emitting control node PU controls the first light-emitting turn-off switching transistor ET4 to conduct, thereby transmitting the low voltage of the light-emitting clock signal EK in the light-emitting clock signal input terminal EKI at this time to the light-emitting output terminal EO, accurately controlling the light-emitting signal Es to stop outputting.

[0203] Please refer to Figure 12 , which is a schematic circuit diagram of any one of the light-emitting driving units in a modified embodiment as shown in Figure 7 . Figure 12 The circuit structure, working principle, and working timing of the EOA unit 140 shown and the Figure 10 shown EOA unit are basically the same, and the only difference lies in the circuit structure of the first light-emitting pull-down module 42, while the first light-emitting pull-up module 41, the second light-emitting pull-up module 43, the second light-emitting pull-down module 44, the first light-emitting signal output module 45, and the second light-emitting signal output module 46 are all the same.

[0204] Among them, the first light-emitting pull-down module 42 is connected to the light-emitting high-voltage power supply terminal EVGH, the first light-emitting control node EPU, the second light-emitting control node EPD, and the light-emitting low-voltage power supply terminal EVSS. When the voltage of the second light-emitting control node EPD is at a high potential, it is used to load the low-potential voltage provided by the light-emitting low-voltage power supply terminal EVSS to the first light-emitting control node EPU, that is, to pull down the potential of the first light-emitting control node EPU; at the same time, when the first light-emitting control node EPU is at a high potential, it disconnects the conductive path between the first light-emitting control node EPU and the light-emitting low-voltage conductive terminal through the high-potential voltage provided by the light-emitting high-voltage power supply terminal EVGH, preventing the current leakage of the first light-emitting control node EPU and ensuring that the voltage of the first light-emitting control node EPU is accurately positioned at a high potential.

[0205] Specifically, the first light-emitting pull-down module 42 includes two serially connected seventh light-emitting switching transistors and an eighth switching transistor ET8. The two serially connected seventh light-emitting switching transistors can be defined as a seventh upper light-emitting switching transistor ET7a and a seventh lower light-emitting switching transistor ET7b that are serially connected through an intermediate node Nm. More specifically, one of the conductive terminals of the seventh upper light-emitting switching transistor ET7a is connected to the first light-emitting control node EPU, and one of the conductive terminals of the seventh lower light-emitting switching transistor ET7b is connected to the light-emitting low-voltage power supply terminal EVSS. The other two conductive terminals of both are connected to the intermediate node Nm. The control terminals of the seventh upper light-emitting switching transistor ET7a and the seventh lower light-emitting switching transistor ET7b are both connected to the second light-emitting control node EPD. The two serially connected seventh light-emitting switching transistors are used to conduct simultaneously when the voltage at the second light-emitting control node EPD is at a high potential, thereby quickly pulling down the potential of the first light-emitting control node EPU and quickly releasing the charge of the first light-emitting control node EPU. It can effectively improve the safety of the current when the first light-emitting control node EPU is released and prevent the switching transistor from being damaged by a tip or surge current.

[0206] It can be understood that the control terminals of the seventh upper light-emitting switching transistor ET7a and the seventh lower light-emitting switching transistor ET7b are the gates of the two switching transistors, and the conductive terminals are the source-drain electrodes of the two switching transistors. In this embodiment, both the seventh upper light-emitting switching transistor ET7a and the seventh lower light-emitting switching transistor ET7b are N-type thin-film transistors. Then, both conduct when the voltage at the second light-emitting control node EPD is at a high potential, that is, the high-potential voltage of the second light-emitting control node EPD serves as its conduction trigger voltage. In other embodiments of the application, the seventh upper light-emitting switching transistor ET7a and the seventh lower light-emitting switching transistor ET7b can also be P-type thin-film transistors. Then, correspondingly, both conduct when the voltage at the second light-emitting control node EPD is at a low potential, that is, the low-potential voltage of the second light-emitting control node EPD serves as its conduction trigger voltage.

[0207] The eighth switching transistor ET8 includes an eighth light-emitting control terminal ET80, an eighth pull-up conductive terminal ET81, and an eighth light-emitting pull-down conductive terminal ET82. Among them, the eighth light-emitting control terminal ET80 is connected to the first light-emitting control node EPD, the eighth pull-up conductive terminal ET81 is connected to the light-emitting high-voltage power supply terminal EVGH, and the eighth light-emitting pull-down conductive terminal ET82 is connected to the intermediate node Nm between the two serially connected seventh light-emitting switching transistors.

[0208] The eighth light-emitting switch transistor ET8 is turned on under the control of the high-potential voltage of the first light-emitting control node EPU, thereby loading the high-potential voltage of the high-voltage power supply terminal EVGH to the intermediate node Nm. Correspondingly, the eighth light-emitting switch transistor ET8 is in the cut-off state when the first light-emitting control node EPU is at a low voltage, thereby stopping loading the high-potential voltage of the high-voltage power supply terminal EVGH to the intermediate node Nm. The eighth light-emitting switch transistor ET8 is used to load the high-potential voltage of the high-voltage power supply terminal EVGH to the intermediate node Nm under the high-potential voltage of the first light-emitting control node EPU, thereby effectively preventing the first light-emitting control node EPU from forming a conductive path through the seventh upper-link light-emitting switch transistor ET7a and the seventh lower-link light-emitting switch transistor ET7b, and discharging the current of the first light-emitting control node EPU. In other words, the eighth light-emitting switch transistor ET8 can effectively ensure that the potential of the first light-emitting control node EPU is accurately maintained at a high potential.

[0209] In this embodiment, the eighth light-emitting switch transistor ET8 is an N-type thin-film transistor, where its gate is the eighth light-emitting control terminal ET80, and the source and drain electrodes are respectively used as two conductive terminals. In other embodiments of the application, the eighth light-emitting switch transistor ET8 can also be a P-type thin-film transistor.

[0210] In the driving circuit composed of the scan driving circuit 13 and the light-emitting driving circuit 14 in the embodiment of the present application, a GOA unit 130 can simultaneously output multiple scan signals in the form of pulses with different durations, effectively improving the integration degree and output signal efficiency of the GOA unit 130. At the same time, in cooperation with the circuit structure of the EOA unit 140, corresponding light-emitting signals can also be output, thereby effectively improving the image display effect of the pixel unit, and at the same time providing more space for the narrow border design of the display panel 10.

[0211] In this article, specific examples are used to elaborate on the principle and implementation manner of the present application. The description of the above implementation manners is only used to help understand the core idea of the present application; at the same time, for those of ordinary skill in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A driving circuit includes m scanning driving units arranged in sequence and cascaded, characterized in that, In the i-th scanning period among the m consecutive scanning periods included in one frame image display period, the scanning driving unit of the i-th level is used to output a scanning signal and a compensation scanning signal. The scanning signal is a pulse signal with a first level and lasting for a first preset duration, and the compensation scanning signal is a pulse signal with the first level and lasting for a second preset duration. The scanning signal is used to be loaded to the pixel unit at the first position during the data loading period in the i-th scanning period to control the pixel unit to receive a data signal from the data line to perform image display. The compensation scanning signal is used to be loaded to the pixel unit during the compensation period in the i-th scanning period to control the pixel unit to receive a compensation signal from the compensation line to perform data signal compensation. Wherein, the second preset duration is greater than the first preset duration, the compensation period and the data loading period are consecutive in time and have no overlap. The m is a positive integer greater than 1, and i is a positive integer greater than or equal to 1 and less than m.

2. The drive circuit according to claim 1, wherein The scanning driving unit includes an enable trigger terminal, a first clock signal input terminal, a second clock signal input terminal, a first signal output terminal, and a second signal output terminal. Wherein, the enable trigger terminal is used to receive an enable trigger signal to enable and trigger the scanning driving unit to work. The first clock signal input terminal and the second clock signal input terminal are used to receive two clock signals with a preset unit duration interval. The scanning driving unit outputs the scanning signal from the first signal output terminal according to the clock signal of the first clock signal input terminal, and simultaneously outputs the compensation scanning signal from the second signal output terminal, and stops the compensation scanning signal according to the clock signal of the second clock signal input terminal. The clock signal is a periodic pulse signal with a pulse width of one unit duration.

3. The drive circuit according to claim 2, wherein, The clock signals received by the first clock signal input terminal and the second clock signal input terminal are spaced apart by a unit durations. Wherein, the first preset duration corresponding to the scanning signal is 1 unit duration, and the second preset duration corresponding to the compensation scanning signal is a unit durations. The a is a positive integer greater than 1.

4. The drive circuit according to claim 3, characterized in that, The scanning driving unit includes a first pull-up module, a first clock signal output module, and a first reset scanning output module, where: The first pull-up module is connected to the enable trigger terminal, the high-voltage power supply terminal, and the first control node, and is used to pull up and raise the voltage of the first control node to a high potential under the control of the enable trigger signal provided by the enable trigger terminal; The first clock signal output module is connected to the first control node, the first clock signal input terminal, and the first signal output terminal, and is used to output the clock signal as the scanning signal when the voltage of the first control node is at a high potential, and simultaneously maintain the voltage of the first control node at a high potential within the second preset duration; The first reset scan output module is connected to the first control node, the first clock signal input terminal, the high-voltage power supply terminal, and the second signal output terminal, and is configured to output the power supply signal provided by the high-voltage power supply terminal as the compensation scan signal within the second preset time duration under the control of the high potential of the voltage of the first control node and the clock signal.

5. The drive circuit according to claim 4, wherein The scan driving unit further includes a second pull-down module, which is connected to the first control node, the low-voltage power supply terminal, and the second control node, and is configured to connect the low-voltage power supply terminal to the second control node when the voltage of the first control node is at a high potential, so as to control the potential of the second control node to be at a low potential.

6. The drive circuit according to claim 5, wherein The scan driving unit further includes a first pull-down module and a second pull-up module. The second pull-up module is connected to the high-voltage power supply terminal and the second control node, and is configured to load the high-potential voltage provided by the high-voltage power supply terminal to the second control node to raise the potential of the second control node when the second control node is not loaded with a low potential. The first pull-down module is connected to the first control node, the second control node, and the second clock signal input terminal, and is configured to pull down the potential of the first control node under the control of the clock signal provided by the second clock signal input terminal or when the voltage of the second control node is at a high point.

7. The drive circuit according to claim 6, characterized in that, The scan driving unit further includes a second clock signal output module and a second reset scan output module, where: The second clock signal output module is connected to the second control node, the low-voltage power supply terminal, and the first signal output terminal, and is configured to transmit a low-potential voltage to the first signal output terminal to stop outputting the scan signal when the voltage of the second control node is at a high potential. The second reset scan output module is connected to the second control node, the low-voltage power supply terminal, and the second signal output terminal, and is configured to transmit a low-potential voltage to the second signal output terminal to stop outputting the compensation scan signal when the voltage of the second control node is at a high potential.

8. The drive circuit according to any one of claims 4 to 7, characterized in that, The scan driving unit further outputs a reset scan signal, and the scan signal output by the first signal output terminal also serves as the reset scan signal. The reset scan signal is configured to be loaded to the pixel unit at the second position during the reset period of the (i + b)-th scan cycle to control the pixel unit to receive a reset voltage to perform reset, where b is a positive integer greater than 1.

9. The drive circuit according to claim 8, wherein, During the display period of one frame of image, there are also f consecutive virtual scan cycles. The f consecutive virtual scan cycles are sequentially continuous in time with the first scan cycle. The scan driving circuit further includes f virtual scan driving units. The f virtual scan driving units are cascaded in sequence, and the f-th stage of the virtual scan driving unit is connected to the first stage of the scan driving unit, and the f-th stage of the virtual scan driving unit outputs an enable trigger signal to trigger the first stage of the scan driving unit to work. The 1st to fth virtual scan driving units are used to output the reset scan signal and the compensation scan signal correspondingly in the reset period and the compensation period of the 1st to fth virtual scan cycles respectively, where f is a positive integer greater than 1.

10. The drive circuit according to any one of claims 1-7, characterized in that, The driving circuit further includes m sequentially arranged light-emitting driving units. In the ith scan cycle, the ith light-emitting driving unit is used to output a light-emitting signal, which is used to be provided to the pixel unit in the compensation period to cooperate with the compensation scan signal to perform data signal compensation on the pixel unit. The light-emitting signal is also used to control the pixel unit to emit light according to the data signal to display an image. Wherein, the light-emitting signal is a pulse signal lasting for the second preset duration, and the compensation period, the data loading period and the light-emitting period are sequentially continuous in time.

11. The drive circuit according to claim 10, characterized in that, The light-emitting driving unit includes a light-emitting clock signal input terminal, a first light-emitting input terminal, a second light-emitting input terminal, a light-emitting output terminal, a first light-emitting pull-up module and a first light-emitting signal output module. Wherein, the light-emitting clock signal input terminal is used to receive a light-emitting clock signal, and the first light-emitting input terminal and the second light-emitting input terminal are connected to the first signal output terminals of two scan driving units with a preset level interval to respectively receive scan signals of two scan cycles with a preset scan cycle interval. The first light-emitting pull-up module is connected to the light-emitting clock signal input terminal, the light-emitting high-voltage power supply terminal and a first light-emitting control node, and is used to load the high-potential voltage provided by the light-emitting high-voltage power supply terminal to the first light-emitting control node under the control of the light-emitting clock signal. The first light-emitting signal output module is connected to the first light-emitting control node, the light-emitting high-voltage power supply terminal and the light-emitting output terminal, and is used to output the high-potential voltage provided by the light-emitting high-voltage power supply terminal as the light-emitting signal from the light-emitting output terminal within the second preset duration under the control of the high-potential voltage of the first light-emitting control node.

12. The drive circuit according to claim 11, wherein The light-emitting driving unit further includes a second light-emitting pull-down module, which is connected to the first light-emitting control node, a second light-emitting control node and a light-emitting low-voltage power supply terminal, and is used to load the low-potential voltage provided by the light-emitting low-voltage power supply terminal to the second light-emitting control node when the first light-emitting control node is at a high-potential voltage.

13. The drive circuit according to claim 11, wherein The light-emitting driving unit further includes a second light-emitting pull-up module and a second light-emitting signal output module. The second light-emitting pull-up module is connected to the first light-emitting input terminal, the second light-emitting input terminal and the second light-emitting control node, and is used to raise the voltage potential of the second light-emitting control node when the scan signal is received at the first light-emitting input terminal or the second light-emitting input terminal. The second light-emitting signal output module is connected to the second light-emitting control node, the light-emitting low-voltage power supply terminal, the light-emitting clock signal input terminal and the light-emitting output terminal. The second light-emitting signal output module is used to control the light-emitting output terminal to stop outputting the light-emitting signal when the voltage of the second light-emitting control node is at a high potential or the light-emitting clock signal is received.

14. The driving circuit according to claim 13, wherein the light-emitting driving unit further includes a first light-emitting pull-down module, the first light-emitting pull-down module is connected to the first light-emitting control node, the second light-emitting control node and the light-emitting low-voltage power supply terminal, and is used to load the low-potential voltage provided by the light-emitting low-voltage power supply terminal to the first light-emitting control node when the voltage of the second light-emitting control node is at a high potential, so as to control the first light-emitting signal output module to stop outputting the light-emitting signal; or the first light-emitting pull-down module is connected to the light-emitting high-voltage power supply terminal, the first light-emitting control node, the second light-emitting control node and the light-emitting low-voltage power supply terminal, and is used to disconnect the conduction path between the first light-emitting control node and the light-emitting low-voltage conduction terminal through the high-potential voltage provided by the light-emitting high-voltage power supply terminal when the voltage of the first light-emitting control node is at a high potential; and when the voltage of the second light-emitting control node is at a high potential, load the low-potential voltage provided by the light-emitting low-voltage power supply terminal to the first light-emitting control node, so as to control the first light-emitting signal output module to stop outputting the light-emitting signal.

15. A display panel, characterized in that, It includes m scanning lines, n data lines, m light-emitting lines, m compensation scanning lines, m compensation lines, m reset scanning lines and m reset lines, a data driving circuit, a compensation circuit, a reset circuit and the driving circuit according to any one of claims 1-14, and the display panel further includes a plurality of the pixel units, and each pixel unit is connected to one of the scanning line, the data line, the light-emitting line, the compensation scanning line, the compensation line, the reset scanning line and the reset line; the m scanning driving units included in the driving circuit are respectively connected to the m scanning lines, the m compensation scanning lines and the m reset scanning lines, and the m light-emitting driving units included in the driving circuit are respectively connected to the m scanning lines; the m light-emitting driving units included in the driving circuit are connected to the pixel units through the m light-emitting lines; the compensation circuit is connected to the compensation line and outputs a compensation signal to the pixel unit when the pixel unit receives a compensation scanning signal, so as to perform data signal compensation on the pixel unit; the reset circuit is connected to the reset line and outputs a reset signal to the pixel unit when the pixel unit receives a reset scanning signal to reset the pixel unit.

16. An electronic device, characterized in that, The electronic device includes a housing and the display panel according to claim 15, and the housing is used to carry the display panel.

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