Back-contact battery and its preparation method

Abstract

The present application discloses a back-contact battery and a preparation method thereof. The back-contact battery includes a silicon substrate, and a plurality of first regions and a plurality of second regions are alternately arranged in sequence on the back surface of the silicon substrate. A first semiconductor layer is provided in each first region, and a second semiconductor layer is provided in each second region. The second semiconductor layer extends from the second region to the first region and sequentially forms a climbing portion and a covering portion. The covering portion covers part of the first semiconductor layer, forming a bare first semiconductor region and a covered first semiconductor region. A first transparent electrode pattern is provided on the entire layer of the bare first semiconductor region and on part of the covering portion along the direction perpendicular to the extension from the first region to the second region. A second transparent electrode pattern is provided on the second region. There is always a first gap between the first transparent electrode pattern and the second transparent electrode pattern. The above solution can improve the conversion efficiency of the back-contact battery.

Description

Technical Field

[0001] The present invention generally relates to the field of photovoltaic technology, and in particular to a back-contact cell and a method for preparing the same. Background Art

[0002] Back-contact cell technology (Interdigitated Back Contact; IBC) moves the front electrode of the cell to the back, eliminating the grid lines on the front and eliminating the grid lines from blocking light. As a result, back-contact cells have a high conversion efficiency. Currently, the general photoelectric conversion efficiency can reach over 25%. However, in existing technologies, there is often a leakage current problem between the P and N regions of back-contact cells. To solve this leakage current problem, R&D technicians will add complex isolation structures, which will generate additional process steps and increase the manufacturing cost of the cell. Therefore, finding a back-contact cell that can reduce leakage current, improve the cell's photoelectric conversion efficiency, and simplify the cell manufacturing process has become a major problem that needs to be solved urgently in the photovoltaic industry. Summary of the Invention

[0003] The present application provides a back-contact battery, which improves the conversion efficiency of the back-contact battery by taking into account both structural optimization and reduction of leakage current.

[0004] In a first aspect, the present invention provides a back-contact battery, comprising a silicon substrate, the silicon substrate comprising a front surface and a back surface; a plurality of first regions and a plurality of second regions alternately disposed on the back surface of the silicon substrate, each first region being disposed with a first semiconductor layer, each second region being disposed with a second semiconductor layer, the second semiconductor layer extending from the second region toward the first region and sequentially comprising a climbing portion and a covering portion, the covering portion covering a portion of the first semiconductor layer to form an exposed first semiconductor region and a covered first semiconductor region;

[0005] A second transparent electrode pattern is provided on the second semiconductor layer above the orthographic projection of the second region;

[0006] A first transparent electrode pattern is provided on the entire exposed first semiconductor region and on a portion of the covering portion extending perpendicularly from the first region to the second region; or

[0007] A first transparent electrode pattern is provided on the exposed portion of the first semiconductor region and the portion of the covering portion; and

[0008] The first transparent electrode pattern and the second transparent electrode pattern are always separated by a first gap.

[0009] In the first aspect of the above solution, by setting the first gap, physical isolation of the transparent electrode patterns between the P and N regions of the back contact battery is ensured. In the second aspect, by setting electrode patterns on a partial surface of the covering portion, that is, only etching away the transparent electrode layer on a partial surface of the covering portion, the passivation range is maximally expanded from the passivation of the transparent electrode pattern layer, avoiding the recombination problem caused by poor lateral transport of the semiconductor layer in this part.

[0010] Optionally, a second transparent electrode pattern is provided on the entire second semiconductor layer above the orthographic projection of the second region.

[0011] Through the above solution, by providing a second transparent electrode pattern on the entire layer above the orthographic projection of the second region, the lateral extraction on the surface of the second region is maximally utilized, the transport path of holes or electrons in the semiconductor layer is reduced, and recombination is avoided.

[0012] Optionally, a second transparent electrode pattern is provided on a partial second semiconductor layer above the orthographic projection of the second region;

[0013] In the above solution, above the orthographic projection of the second region, or during the process of applying the etching paste on the covering portion, in order to facilitate the process and increase the process window of the etching paste, part of the etching paste is allowed to etch the transparent conductive layer above the orthographic projection of the second region, so that the formed second transparent electrode pattern is provided on a partial second semiconductor layer above the orthographic projection of the second region.

[0014] Optionally, a second transparent electrode pattern is provided on a partial second semiconductor layer above the orthographic projection of the second region and on a partial covering portion.

[0015] In the above solution, above the orthographic projection of the second region, or during the process of applying the etching paste on a partial covering portion, in order to facilitate the process and increase the process window of the etching paste, part of the etching paste is allowed to etch the transparent conductive layer above the orthographic projection of the second region, and part of the covering portion is not etched by the etching paste, so that the formed second transparent electrode pattern is provided on a partial second semiconductor layer and a partial covering portion above the orthographic projection of the second region.

[0016] Optionally, when a second transparent electrode pattern is provided on a partial second semiconductor layer above the orthographic projection of the second region, a second gap is formed between the edge of the second transparent electrode pattern and the climbing portion on the cross-section of the back contact battery; preferably, the width of the second gap is 10 to 80 microns, preferably 20 to 50 microns.

[0017] A second gap is formed between the edge of the second transparent electrode pattern and the climbing portion in the above solution. On the one hand, it can achieve better physical isolation and prevent the generation of leakage current. On the other hand, the gap between the second transparent electrode pattern and the climbing portion leaves the deformation position of the silicon substrate here, avoiding the peeling of the second transparent electrode pattern at the larger deformation position due to the large phase change here. In addition, according to the amount of deformation here, the width of the second gap here is appropriately controlled, and the effect is optimal within this range.

[0018] Optionally, a third gap is formed between the edge of the first transparent electrode pattern and the climbing portion. Preferably, the width of the third gap is 40 to 80 microns, preferably 40 to 60 microns.

[0019] A third gap is formed between the edge of the first transparent electrode pattern and the climbing portion in the above solution. On the one hand, it can achieve better physical isolation and prevent the generation of leakage current. On the other hand, the gap between the first transparent electrode pattern and the climbing portion leaves the deformation position of the silicon substrate here, avoiding the peeling of the first transparent electrode pattern at the larger deformation position due to the large phase change here. In addition, according to the amount of deformation here, the width of the third gap here is appropriately controlled, and the effect is optimal within this range.

[0020] Optionally, the ratio of the width of the third gap to the width of the second gap is between 1 and 3 times.

[0021] In the above solution, the width of the second gap plus the width of the third gap is the width of the first gap between the first transparent electrode pattern and the second transparent electrode pattern. Therefore, while ensuring the isolation effect and without further expanding the first gap, the third gap is in the overlapping region of the first semiconductor layer and the second semiconductor layer of the back-contact battery. This part of the overlapping region belongs to the dead zone of longitudinal transmission. Therefore, in this part, the width of the third gap can be increased, and the width of the second gap can be adjusted and reduced accordingly to control the total width of the first gap within a reasonable range. Further, when the ratio of the width of the third gap to the width of the second gap is between 1 and 3 times, within a certain range of the first gap, that is, when the first gap is in the range of 60 to 120 microns, the smallest third gap can maximize the current collection area while ensuring the isolation effect and the isolation opening process window, improve the fill factor of the battery, and thus improve the photoelectric conversion efficiency.

[0022] Optionally, the width of the covering portion is 60 to 200 microns, preferably 60 to 80 microns.

[0023] In a back-contact battery, the covering part is the overlapping area of the first semiconductor layer and the second semiconductor layer. This overlapping area belongs to the dead zone of longitudinal transmission. To achieve the maximum power generation efficiency, it is desirable to reduce the width of the dead zone. However, if the dead zone is completely eliminated, the first semiconductor layer will be formed separately at the junction of the climbing part and the covering part. Since the etching of the silicon substrate at the junction of the climbing part and the covering part is formed during the alkaline texturing process, in the direction perpendicular to the extension from the first region to the second region, the edge of the junction of the climbing part and the covering part is not a straight line. Due to different texturing rates, the climbing part generates a curved arc, and there will be exposed silicon substrate. To passivate the exposed silicon substrate here, the second semiconductor layer covers the exposed part of the first region, and the width of the covering part is set within the above range.

[0024] Optionally, the ratio of the width of the covering part to the width of the third gap is between 4:3 and 2.

[0025] When the ratio of the width of the above-mentioned covering part to the width of the third gap is 4:3, the maximum third gap is reached. At this time, using etching paste or laser etching, the transparent conductive layer on the remaining covering part belongs to the part that meets the process window requirements. This part is retained on the covering part, which can avoid damage to the transparent conductive layer on the effective power generation area of the exposed area of the first semiconductor, and at the same time, under a certain width of the covering part and the third gap, reducing the width of the covering part reduces the hole or electron transmission path of the first semiconductor layer under the covering part, reduces bulk recombination, and improves power generation efficiency.

[0026] Optionally, the vertical distance between the surface of the covering part facing away from the silicon substrate and a position on the silicon substrate is greater than the vertical distance between the surface of the second transparent electrode pattern facing away from the silicon substrate and a position on the silicon substrate.

[0027] Through the above setting, that is, taking the front surface of the silicon substrate as a reference, the surface of the covering part is set to be higher than the surface of the second transparent electrode pattern, thereby ensuring that there is a gap between the first transparent electrode pattern and the second transparent electrode pattern on the surface of the covering part, and further reducing the generation of leakage current.

[0028] Optionally, the first transparent electrode pattern includes a first central region and a first peripheral region surrounding the first central region, and the thickness of the first peripheral region is less than the average thickness of the first central region; and / or,

[0029] The second transparent electrode pattern includes a second central region and a second peripheral region surrounding the second central region, and the thickness of the second peripheral region is less than the average thickness of the second central region.

[0030] In the above solution, the thickness of the peripheral region of the transparent electrode pattern is less than that of the transparent electrode pattern in the central region, which can ensure the bonding force of the transparent electrode pattern in the central region of the transparent electrode. If there is a local tensile stress change in the peripheral region, due to the relatively thin peripheral region, the tensile stress change will not have a great impact on the central region. The lateral tensile stress generated in the peripheral region due to the tensile stress change can only automatically expand and contract within the peripheral region, or even if there is a hidden crack, it will only occur within the peripheral region and will not be transmitted to the central region, thus ensuring the lateral transmission performance of the battery.

[0031] Optionally, the first transparent electrode pattern includes a first central region and a first peripheral region surrounding the first central region. In the cross-section of the back-contact battery, the thickness of the first peripheral region gradually increases along the direction away from the edge of the first peripheral region; and / or,

[0032] The second transparent electrode pattern includes a second central region and a second peripheral region surrounding the second central region. In the cross-section of the back-contact battery, the thickness of the second peripheral region gradually increases along the direction away from the edge of the second peripheral region.

[0033] In the above solution, the thickness of the peripheral region gradually increases along the direction away from the edge of the peripheral region, which can linearly ensure the bonding force of the transparent electrode pattern in the central region of the transparent electrode. If there is a local tensile stress change in the peripheral region, due to the relatively thin peripheral region, the tensile stress change will not have a great impact on the central region. The lateral tensile stress generated in the peripheral region due to the tensile stress change can only automatically linearly expand and contract within the peripheral region, or even if there is a hidden crack, it will only linearly occur within the peripheral region and will not be directly transmitted to the central region, thus ensuring the lateral transmission performance of the battery.

[0034] Optionally, the first semiconductor layer includes a tunneling layer disposed on the silicon substrate, and an N-type doped polysilicon layer is disposed on the side of the tunneling layer facing away from the silicon substrate;

[0035] The second semiconductor layer includes an intrinsic amorphous silicon layer, and a P-type doped microcrystalline silicon layer is disposed on the side of the intrinsic amorphous silicon layer facing away from the silicon substrate.

[0036] By setting the above solutions, on the one hand, through the setting of the tunneling layer and the N-type polysilicon layer, the conductivity of the first semiconductor layer is improved, and the conductivity of polysilicon is stronger; on the other hand, by setting the intrinsic amorphous silicon layer and the doped microcrystalline silicon layer, a low-temperature process can be used to reduce the complexity of the process. At the same time, the low-temperature process will not affect the performance of the tunneling layer and the N-type polysilicon layer in the previous step, avoiding the influence of impurity diffusion of doping elements caused by secondary high temperature. Third, by extending the intrinsic amorphous silicon layer to form a covering part on the first semiconductor layer, the surface of the N-type polysilicon layer is further passivated, reducing recombination. At the same time, a doped P-type microcrystalline silicon layer is set on the intrinsic amorphous silicon layer. Due to the isolation and passivation effects of the intrinsic amorphous silicon layer and the conductivity of the low-temperature doped P-type microcrystalline silicon layer itself, current breakdown, short circuit, and leakage between the P and N-type semiconductor layers are avoided.

[0037] Optionally, the front surface of the silicon substrate is provided with a textured surface, and an intrinsic amorphous silicon layer is provided on the textured surface, or an aluminum oxide layer is provided on the textured surface.

[0038] Through the above setting solutions, the positive surface of the silicon substrate can be passivated to reduce recombination. On the other hand, the intrinsic amorphous silicon layer and the aluminum oxide layer on the front surface have stable properties, which can extend the life of the battery.

[0039] Optionally, an antireflection layer is provided on the surface of the intrinsic amorphous silicon facing away from the silicon substrate, or an antireflection layer is provided on the surface of the aluminum oxide layer facing away from the silicon substrate.

[0040] By setting the above solutions, the reflection of sunlight is reduced, the utilization rate of sunlight is improved, and the conversion efficiency of the back-contact battery can be improved.

[0041] Optionally, the climbing part is inclined with respect to the back surface of the silicon substrate. Preferably, the inclination angle of the climbing part with respect to the back surface of the silicon substrate is 5° to 80°, preferably 30° to 70°.

[0042] Through the above setting solutions, by inclining the back surface of the silicon substrate, the uniformity of the deposition of the intrinsic amorphous silicon here is improved, and the passivation effect on the semiconductor substrate is enhanced; at the same time, due to the better uniformity of the deposited intrinsic amorphous silicon layer and better surface topography retention, it is beneficial to the deposition and preparation of the doped amorphous silicon layer, forming a doped amorphous silicon layer with better electrical properties, thereby also enhancing the conversion efficiency of the battery.

[0043] Optionally, when a first transparent electrode pattern is provided on the entire exposed first semiconductor region layer and on the part of the covering portion extending in a direction perpendicular to the first region toward the second region; or,

[0044] When a first transparent electrode pattern is provided on a part of the exposed first semiconductor region and a part of the covering portion;

[0045] Along the direction perpendicular to the extension direction of the first region towards the second region, the edge of the first transparent electrode pattern is wavy.

[0046] Through the above setting scheme, by setting the edge of the transparent electrode pattern layer to be wavy, the edge stress of the transparent electrode pattern can be reduced, and the hidden crack of the transparent electrode pattern caused by the stress change of the silicon substrate at the edge can be avoided, which affects the lateral transmission performance.

[0047] Optionally, when a second transparent electrode pattern is provided on a part of the second semiconductor layer above the orthographic projection of the second region; and / or;

[0048] When a second transparent electrode pattern is provided on a part of the second semiconductor layer above the orthographic projection of the second region and on a part of the covering portion;

[0049] Along the direction perpendicular to the extension direction of the first region towards the second region, the edge of the second transparent electrode pattern is wavy.

[0050] Through the above setting scheme, by setting the edge of the transparent electrode pattern layer to be wavy, the edge stress of the transparent electrode pattern can be reduced, and the hidden crack of the transparent electrode pattern caused by the stress change of the silicon substrate at the edge can be avoided, which affects the lateral transmission performance.

[0051] In a second aspect, the present invention provides a method for manufacturing the above-mentioned back-contact battery, including the following steps:

[0052] Provide a battery precursor, the battery precursor includes a silicon substrate, the silicon substrate includes a front side and a back side; a plurality of first regions and a plurality of second regions are alternately arranged on the back side of the silicon substrate, a first semiconductor layer is provided in each first region, a second semiconductor layer is provided in each second region, the second semiconductor layer extends from the second region towards the first region, and sequentially includes a climbing portion and a covering portion, and the covering portion covers a part of the first semiconductor layer.

[0053] Form a transparent electrode thin film on the back side of the battery precursor;

[0054] On the transparent electrode thin film, etch at least corresponding to the climbing portion and the position of a part of the covering portion close to the climbing portion, so as to etch the transparent electrode thin film to form separated first and second transparent electrode patterns. Description of the Drawings

[0055] By reading the detailed description of the non-limiting embodiments with reference to the following drawings, other features, purposes and advantages of the present application will become more obvious:

[0056] Figure 1Rear view of the back-contact battery provided by the embodiment of the present invention;

[0057] Figure 2 is Figure 1 A-A cross-sectional view of;

[0058] Figure 3 is Figure 1 C-C cross-sectional view of;

[0059] Figure 4 Rear view of the back-contact battery provided by another embodiment of the present invention;

[0060] Figure 5 Rear view of the back-contact battery provided by another embodiment of the present invention;

[0061] Figure 6 Rear view of the back-contact battery provided by another embodiment of the present invention;

[0062] Figure 7 Rear view of the back-contact battery provided by another embodiment of the present invention;

[0063] Figure 8 is the cross-sectional view corresponding to the A-A position in Figure 1 of the back-contact battery provided by another embodiment of the present invention;

[0064] Figure 9 Rear view of the back-contact battery provided by another embodiment of the present invention;

[0065] Figures 10 - 18 is the structural schematic diagram of the preparation process corresponding to the E-E cross-sectional position in Figure 9 of the back-contact battery provided by the embodiment of the present invention.

[0066] Explanation of reference numerals:

[0067] N-type silicon substrate 1, first transparent electrode pattern 11, transparent conductive thin film 101, tunneling layer 2, second transparent electrode pattern 21, N-type polysilicon layer 3, intrinsic amorphous silicon layer 4, P-type microcrystalline silicon layer 5, antireflection layer 6, silicon nitride hydride layer 7, etching paste 8, first region Q1, second region Q2, electrode D, climbing portion P, covering portion G, first gap W1, second gap W2, first gap W3, partial positions J1, J2, J3, edges B1, B2. Detailed implementation manners

[0068] The present application will be further described in detail below with reference to the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the related invention, rather than limiting the invention. Additionally, it should be noted that for the convenience of description, only the parts related to the invention are shown in the drawings.

[0069] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments may be combined with each other. The following will describe the present application in detail with reference to the accompanying drawings and in combination with the embodiments.

[0070] In the embodiments of the present invention, the "lithography process" involved, if any, includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature preparation processes in the related art. The "lithography process" mentioned in this embodiment includes coating a film layer, mask exposure, and development, which are mature preparation processes in the related art. Deposition can use known processes such as sputtering, evaporation, and chemical vapor deposition, coating can use known coating processes, etching can use known methods, and epitaxial growth also uses known methods, and specific limitations are not made here.

[0071] In the description of this embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or growth processes. If the "thin film" does not require a lithography process or a lithography process during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" still requires a lithography process or a lithography process during the entire manufacturing process, it is called a "thin film" before the lithography process and a "layer" after the lithography process. The "layer" after the lithography process or the lithography process contains at least one "pattern". For example but not limited to, the thickness of the thin film referred to in this article can be below 100 μm.

[0072] In the related technology of solar cells, the selective passivation contact technology separates the metal from the semiconductor, avoiding the serious recombination caused by the direct contact between the metal and the semiconductor. At the same time, this selective passivation structure has obvious selectivity for the passage of specific carriers. One type of carrier can effectively pass through while having a shielding effect on the other type of carrier, avoiding the recombination of the two types of carriers in the electrode collection area, thereby effectively improving the photoelectric conversion efficiency of the solar cell device. The typical representatives of the application of this selective passivation contact structure in solar technology are the tunnel oxide passivated contact solar cell (TOPCon) and the hetero-junction with intrinsic thin-layer solar cell (HIT). Both of these cell structures are double-sided electrode structures, and the common efficiency bottleneck they face is the unavoidable light shielding caused by the front metal. For the TOPCon structure, the front is still the direct contact between the metal and the silicon substrate, and in addition to light shielding, the problem of serious metal recombination still exists; for the HIT structure, although the front metal recombination is effectively suppressed, the parasitic absorption of the incident light by the amorphous silicon / ITO layer causes a serious loss of the short-circuit current density.

[0073] To reduce the light-shielding effect of the front electrode, the Interdigitated Back Contact (IBC) cell technology emerged. IBC moves the front electrode of the cell to the back, thus avoiding the light-shielding and recombination of the front electrode, and effectively improving the conversion efficiency of the cell. The Tunnel oxide Back Contact (TBC) or Hetero-Junction Back Contact (HBC) technology, which combines the IBC technology with TOPCon or HJT technology, further reduces the recombination of the IBC back metal.

[0074] In the traditional HBC cell structure, the back n-region and p-region respectively adopt the stacked structure of intrinsic amorphous silicon and N-type doped amorphous silicon (abbreviated as i / n a-Si:H) and the stacked structure of intrinsic amorphous silicon and P-type doped amorphous silicon (abbreviated as i / p a-Si:H) to form an interdigitated pattern. During the manufacturing process, the damage of the laser to the n and p regions needs to be strictly controlled. Especially for the n-region, the process window of the laser is narrow, which increases the process difficulty. The HBC cell also has the following disadvantages in the manufacturing process: A large amount of masking and demasking techniques are used to form patterns, such as the lithography technique commonly used in the semiconductor field, with high production costs and great difficulty in process control; In terms of fixed equipment investment, the CVD equipment for depositing amorphous silicon thin films is costly and has low production capacity. These aspects restrict the efficiency improvement and cost reduction of HBC cells and limit their industrial application.

[0075] Since the TOPCon cell process has matured, the TBC cell, which absorbs the key technology process of the TOPCon cell, has become the most cost-effective IBC cell process route. SunPower and domestic enterprises attempting to mass-produce IBC cells have all transformed to this technology route. Based on the IBC cell structure, TBC replaces the phosphorus diffusion and boron diffusion doped matrix silicon in the back n-region and p-region structures of IBC with the SiOx / n+poly Si and SiOx / p+poly Si structures. This structure solves the serious metal recombination in the n and p regions. In addition, this tunneling oxide passivation contact structure also effectively suppresses the serious Auger recombination problem caused by the direct doping of impurities in the matrix in the traditional IBC structure. However, the TBC cell has the following disadvantages: The preparation process route is long. The two high-temperature preparations of p poly and n poly cause serious silicon wafer concentricity. Among them, the p poly passivation is at 10fa, and the n poly can reach 4fa; After the back interdigitated structure is completed, separate isolation of the P region and N region is required, and the preparation process is relatively complex.

[0076] Therefore, the technical solution of the present invention adopts a combined passivation technical route, that is, passivation is carried out using a tunneling layer in the N region and passivation is carried out using intrinsic silicon in the P region.

[0077] Specifically, the N region includes a tunneling layer and an N-type doped polysilicon layer which are stacked; the P region includes an intrinsic amorphous silicon layer and a P-type doped microcrystalline silicon layer which are stacked. Herein, the microcrystalline silicon referred to in this article may include nanocrystalline silicon.

[0078] In a first aspect, as Figures 1 - 3 shown, the present invention provides a back contact battery, including a silicon substrate, the silicon substrate including a front surface and a back surface. Herein, the front surface referred to in this article can be understood as the side facing the sun when the back contact battery is working, and the back surface is the side opposite to the front surface.

[0079] A plurality of first regions Q1 and a plurality of second regions Q2 are alternately arranged in sequence on the back surface of the silicon substrate. Each of the first regions Q1 is provided with a first semiconductor layer, and each of the second regions Q2 is provided with a second semiconductor layer. The second semiconductor layer extends from the second region Q2 to the first region Q1, and sequentially includes a climbing portion P and a covering portion G. The covering portion G covers part of the first semiconductor layer, forming an exposed first semiconductor region and a covered first semiconductor region; wherein, the exposed first semiconductor region refers to the part of the first semiconductor layer not covered by the covering portion G, and the covered first semiconductor region refers to the part of the first semiconductor layer covered by the covering portion G.

[0080] For example but not limited to, the silicon substrate adopts an N-type silicon substrate 1. The N-type silicon substrate 1 has a long minority carrier diffusion length, which can enable the photo-generated minority carriers not to be recombined before reaching the back junction region and to be separated by the back junction region electric field to form a current.

[0081] For example but not limited to, the first semiconductor layer material includes polysilicon, and the second semiconductor layer material includes microcrystalline silicon.

[0082] The polysilicon can be N-type doped to form an N-type doped layer; the microcrystalline silicon can be P-type doped to form a P-type doped layer.

[0083] In the above solution, the second semiconductor layer extends from the second region Q2 to the first region Q1 and sequentially includes a climbing portion P and a covering portion G. It can be understood that the second semiconductor layer located in the first region Q1, the climbing portion P and the covering portion G are an integral structure, and the three are prepared from the same material through the same process.

[0084] A second transparent electrode pattern 21 is provided on the second semiconductor layer above the positive projection of the second region Q2.

[0085] A first transparent electrode pattern 11 is provided on the entire layer of the exposed first semiconductor region and on part of the covering portion along the direction perpendicular to the extension from the first region Q1 to the second region Q2.

[0086] Among them, as Figure 1As shown, the direction in which the first region Q1 extends toward the second region Q2 is the X-axis direction, and the direction perpendicular to the extension of the first region Q1 toward the second region Q2 is the Y-axis direction. Then, in the Y-axis direction, a first transparent electrode pattern 11 is provided on some of the covering portions. That is to say, in the Y-axis direction, the first transparent electrode pattern 11 is provided on some parts of the covering portion (see also Figure 3 as shown), and the first transparent electrode pattern 11 is not provided on the remaining parts of the covering portion (see also Figure 2 as shown).

[0087] A first gap W1 is always provided between the first transparent electrode pattern 11 and the second transparent electrode pattern 21.

[0088] Optionally, the width of the first gap W1 (the dimension in the X-axis direction) is 60 to 120 micrometers, such as, but not limited to, 60 micrometers, 65 micrometers, 70 micrometers, 72 micrometers, 76 micrometers, 80 micrometers, 83 micrometers, 90 micrometers, 97 micrometers, 100 micrometers, 105 micrometers, 110 micrometers, 120 micrometers, etc.

[0089] The materials of the first transparent electrode pattern 11 and the second transparent electrode pattern 21 can be transparent conductive oxides (TCOs). TCOs include: indium tin oxide (ITO), zinc oxide (ZnO), cadmium tin oxide (CTO), aluminum zinc oxide (AZO), indium zinc oxide (IZO), titanium dioxide (TiO2), indium hydroxide doped (In(OH)3), indium tungsten oxide (IWO), etc. In this example, the materials of the first transparent electrode pattern 11 and the second transparent electrode pattern 21 are ITO.

[0090] Among them, the first transparent electrode pattern 11 is connected to the first semiconductor layer. For example, the first transparent electrode pattern 11 made of ITO material is directly disposed on the N-type doped layer of polysilicon material. According to specific circumstances, the contact area between the first transparent electrode pattern 11 and the N-type doped layer of polysilicon material can be increased as much as possible to expand the region for collecting current. In addition, since the polysilicon surface has many defects and is prone to surface recombination, by disposing the first transparent electrode pattern 11 on the surface of the N-type doped layer of polysilicon material, the first transparent electrode pattern 11 can block or reduce the recombination centers of the surface defects of the N-type doped layer of polysilicon material, reduce the recombination on the surface of the N-type doped layer of polysilicon material, and is beneficial to improving the conversion efficiency of the back contact battery.

[0091] In addition, as Figure 4 shown, the setting manner of the first transparent electrode pattern 11 can also be that the first transparent electrode pattern 11 is disposed on a part of the exposed first semiconductor region and a part of the covering portion G.

[0092] That is to say, the first transparent electrode pattern 11 is not disposed at a part position J1 of the exposed first semiconductor region, and this part position J1 exposes the first semiconductor layer. Along the X-axis direction and / or along the Y-axis direction of the covering portion G, the first transparent electrode pattern 11 is disposed in a partial region, and the remaining region is not provided with the first transparent electrode pattern 11.

[0093] In the first aspect of the above solution, by providing the first gap W1, it is ensured that the first transparent electrode pattern 11 and the second transparent electrode pattern 21 are always isolated, that is, the transparent electrode patterns between the P and N regions of the back contact battery are physically isolated. In the second aspect, by disposing the electrode pattern on a part of the surface of the covering portion G, that is, only etching away the transparent electrode layer on a part of the surface of the covering portion G, the passivation range is expanded as much as possible from the passivation of the transparent electrode pattern layer, and the recombination problem caused by the poor lateral transmission of the semiconductor layer in this part is avoided.

[0094] On the second semiconductor layer above the positive projection of the second region Q2, the second transparent electrode pattern 21 can be provided at least by the following solutions:

[0095] Optionally, as Figure 5 shown, the second transparent electrode pattern 21 is disposed on the entire second semiconductor layer above the positive projection of the second region Q2. That is, the region within the second region Q2 except for the climbing portion P is covered by the second transparent electrode pattern 21.

[0096] The above solution maximizes the use of the lateral conduction on the surface of the second region Q2 by disposing the second transparent electrode pattern 21 on the entire layer above the positive projection of the second region Q2, reduces the transmission path of holes or electrons in the semiconductor layer, and avoids recombination.

[0097] Optionally, at least as Figure 7 shown, a second transparent electrode pattern 21 is provided on a portion of the second semiconductor layer above the orthographic projection of the second region Q2. That is, a portion of the second semiconductor layer above the orthographic projection of the second region Q2 is exposed outside the second transparent electrode pattern 21. Figure 7 In [reference], no second transparent electrode pattern 21 is provided at a partial position J2 above the second semiconductor layer between the two climbing portions P within the second region Q2.

[0098] Wherein, Figures 1 - 4 、 Figure 6 and Figure 7 In any of the examples shown in [references], there is a second gap W2 between the boundary of the second transparent electrode pattern 21 and the boundary of the climbing portion P. When the boundary of the second transparent electrode pattern 21 is non-linear, the value of the second gap W2 is a variable value, and the second gap W2 can be equal or unequal depending on the position.

[0099] In the above solution, during the process of applying the etching paste above the orthographic projection of the second region Q2 or on the covering portion G, in order to facilitate the process and increase the process window of the etching paste, part of the etching paste is allowed to etch the transparent conductive layer above the orthographic projection of the second region Q2, so that the formed second transparent electrode pattern 21 is provided on a portion of the second semiconductor layer above the orthographic projection of the second region Q2.

[0100] Optionally, as Figure 7 shown, a second transparent electrode pattern 21 is provided on a portion of the second semiconductor layer above the orthographic projection of the second region Q2 and on a portion of the covering portion G. That is to say, a part of the second transparent electrode pattern 21 extends to a partial position J3 of the covering portion G, and no second transparent electrode pattern 21 is provided at a partial position J2 above the second semiconductor layer between the two climbing portions P within the second region Q2.

[0101] In the above solution, during the process of applying the etching paste above the orthographic projection of the second region Q2 or on a portion of the covering portion G, in order to facilitate the process and increase the process window of the etching paste, part of the etching paste is allowed to etch the transparent conductive layer above the orthographic projection of the second region Q2, and part of the covering portion G is not etched by the etching paste, so that the formed second transparent electrode pattern 21 is provided on a portion of the second semiconductor layer and a portion of the covering portion G above the orthographic projection of the second region Q2.

[0102] In the above solution, since the second semiconductor layer extends from the second region Q2 to the first region Q1 and sequentially includes a climbing portion P and a covering portion G, and the covering portion G covers a part of the first semiconductor layer, by providing the climbing portion at the junction of the first region Q1 and the second region Q2, the isolation distance between the first transparent electrode pattern and the second transparent electrode pattern can be extended, improving the isolation performance; a first gap W1 is provided between the first transparent electrode pattern 11 and the second transparent electrode pattern 21, so that the first transparent electrode pattern 11 and the second transparent electrode pattern 21 are disconnected, to improve the anti-leakage effect between the first region Q1 and the second region Q2. As the anti-leakage effect is improved, the conversion efficiency of the back contact battery is correspondingly improved.

[0103] Optionally, when a second transparent electrode pattern 21 is provided on a part of the second semiconductor layer above the orthographic projection of the second region Q2, in the cross-section of the back contact battery, for example Figure 1 on the A-A position cross-section as shown, a second gap W2 is formed between the edge of the second transparent electrode pattern 21 and the climbing portion P; preferably, the width of the second gap is 10 to 80 microns, such as but not limited to 10 microns, 15 microns, 20 microns, 22 microns, 26 microns, 30 microns, 33 microns, 40 microns, 47 microns, 50 microns, 55 microns, June 0 microns, 70 microns, 73 microns, 80 microns, etc.; preferably 20 to 50 microns.

[0104] Forming a second gap W2 between the edge of the second transparent electrode pattern and the climbing portion P, on the one hand, can achieve better physical isolation and prevent the generation of leakage current. On the other hand, the gap between the second transparent electrode pattern 21 and the climbing portion P leaves the deformation position of the silicon substrate here, avoiding the peeling of the second transparent electrode pattern 21 at a large deformation position due to a large phase change here. In addition, according to the amount of deformation here, the width of the second gap W2 here is appropriately controlled, and the effect is optimal within the above range.

[0105] As an implementable manner, a third gap is formed between the edge of the first transparent electrode pattern and the climbing portion. Preferably, the width of the third gap is 40 to 80 microns, such as but not limited to 40 microns, 45 microns, 50 microns, 52 microns, 56 microns, 60 microns, 63 microns, 70 microns, 80 microns, etc.; preferably 40 to 60 microns.

[0106] The region of the third gap W3 is within the range of the covering portion G. Since the region of the covering portion G is the overlapping region where the first semiconductor layer and the second semiconductor layer extend out of the second region Q2, this region belongs to the dead zone of the back contact battery and cannot export carriers from the surface of the second semiconductor layer. Therefore, when the total first gap W1 remains unchanged, the width of the second gap W2 can be increased as much as possible, and the width of the third gap W3 can be decreased.

[0107] A third gap W3 is formed between the edge of the first transparent electrode pattern 11 and the climbing portion P in the above solution. On the one hand, it can achieve better physical isolation and prevent the generation of leakage current. On the other hand, the gap between the first transparent electrode pattern 11 and the climbing portion P leaves the deformation position of the silicon substrate here, avoiding the peeling of the first transparent electrode pattern 11 at the position with a large phase change due to the large phase change here. In addition, according to the amount of deformation here, the width of the third gap W3 here is appropriately controlled, and the effect is optimal within this range.

[0108] Optionally, the ratio of the width of the third gap W3 to the width of the second gap W2 is between 1 and 3 times.

[0109] In the above solution, the sum of the width of the second gap W2 and the width of the third gap W3 is the width of the first gap W1 between the first transparent electrode pattern 11 and the second transparent electrode pattern 21. Therefore, while ensuring the isolation effect and without further expanding the first gap W1, the third gap W3 extends into the overlapping region of the second region Q2 in the first semiconductor layer and the second semiconductor layer of the back contact battery. This part of the overlapping region belongs to the dead zone of longitudinal transmission. Therefore, in this part, the width of the third gap W3 can be increased, and the width of the second gap W2 can be adjusted and reduced accordingly to control the total width of the first gap W1 within a reasonable range. Further, when the ratio of the width of the third gap W3 to the width of the second gap W2 is between 1 and 3 times, within a certain range of the first gap W1, that is, when the first gap is within the range of 60-120 microns, the smallest third gap W3 can maximize the current collection area on the premise of ensuring the isolation effect and the isolation opening process window, improve the fill factor of the battery, and thus improve the photoelectric conversion efficiency.

[0110] Optionally, the width of the covering portion P is between 60 and 200 microns, preferably between 60 and 80 microns, such as but not limited to 60 microns, 62 microns, 65 microns, 68 microns, 70 microns, 73 microns, 75 microns, 77 microns, 80 microns, 100 microns, 150 microns, 200 microns, etc.

[0111] In a back-contact battery, the covering part P is the overlapping area of the first semiconductor layer and the second semiconductor layer. This overlapping area belongs to the dead zone for longitudinal transmission. To achieve the maximum power generation efficiency, it is desired to reduce the width of the dead zone. However, if the dead zone is completely eliminated, the first semiconductor layer will be formed separately at the junction of the climbing part P and the covering part G. Since the etching of the silicon substrate at the junction of the climbing part P and the covering part G is formed during the alkaline texturing process, in the direction extending from the first region Q1 to the second region Q2 perpendicular to it, the edge of the junction of the climbing part P and the covering part G is not a straight line. Due to different texturing rates, the climbing part generates a curved arc, and an exposed silicon substrate will appear. To passivate the exposed silicon substrate here, the second semiconductor layer covers the exposed part of the first region Q1, and the width of the covering part G is set to be 60 - 80 microns.

[0112] Optionally, the ratio of the width of the covering part G to the width of the third gap W3 is between 4:3 and 2.

[0113] When the ratio of the width of the above-mentioned covering part G to the width of the third gap W3 is 4:3, the maximum third gap W3 is reached. At this time, using etching paste or laser etching, the transparent conductive layer on the remaining covering part G belongs to the part that meets the process window requirements. This part is retained on the covering part G, which can avoid damage to the transparent conductive layer on the effective power generation area of the exposed region of the first semiconductor, and at the same time, under certain widths of the covering part G and the third gap W3, reducing the width of the covering part G reduces the hole or electron transmission path of the first semiconductor layer under the covering part G, reduces bulk recombination, and improves the power generation efficiency.

[0114] Optionally, the vertical distance between the surface of the covering part G facing away from the silicon substrate and a position on the silicon substrate is greater than the vertical distance between the surface of the second transparent electrode pattern 21 facing away from the silicon substrate and a position on the silicon substrate.

[0115] Through the above setting, that is, taking the front surface of the silicon substrate as a reference, the surface of the covering part G is set to be higher than the surface of the second transparent electrode pattern 21, thereby ensuring that there is a gap between the first transparent electrode pattern 11 and the second transparent electrode pattern 21 on the surface of the covering part G, and further reducing the generation of leakage current.

[0116] As an implementable manner, the first transparent electrode pattern 11 includes a first middle region and a first peripheral region surrounding the first middle region, and the thickness of the first peripheral region is less than the average thickness of the first middle region.

[0117] The second transparent electrode pattern 21 includes a second middle region and a second peripheral region surrounding the second middle region, and the thickness of the second peripheral region is less than the average thickness of the second middle region.

[0118] The transparent electrode film can be etched by printing an etching paste 8 at the location of the climbing portion to form a first transparent electrode pattern 11 and a second transparent electrode pattern 21 that are disconnected from each other. Because the etching paste 8 has a certain degree of fluidity, an etched transition region is formed in the first peripheral region of the first transparent electrode pattern 11 and the second peripheral region of the second transparent electrode pattern 21. A portion of the transparent conductive oxide material in these regions is etched away, thereby forming a structure in which the thickness of the first peripheral region is less than the average thickness of the first central region, and the thickness of the second peripheral region is less than the average thickness of the second central region.

[0119] In the above scheme, the thickness of the peripheral area of each transparent electrode pattern is less than the thickness of the transparent electrode pattern in the central area, which can ensure that the bonding force of the transparent electrode pattern is in the central area of the transparent electrode. If a local tension change occurs in the peripheral area, due to the thinness of the peripheral area, the tension change will not have a significant impact on the central area. The lateral tension generated by the tension change in the peripheral area can only automatically expand and contract within the peripheral area, or even if a crack occurs, it will only occur in the peripheral area and will not be transmitted to the central area, thereby ensuring the lateral transmission performance of the battery.

[0120] Optionally, the first transparent electrode pattern 11 includes a first central region and a first peripheral region surrounding the first central region. In the cross section of the back contact battery, the thickness of the first peripheral region gradually increases along the edge direction away from the first peripheral region.

[0121] The second transparent electrode pattern 21 includes a second central region and a second peripheral region surrounding the second central region. In the cross section of the back contact battery, the thickness of the second peripheral region gradually increases away from the edge of the second peripheral region.

[0122] In the above scheme, the thickness of the peripheral area gradually increases in the direction away from the edge of the peripheral area, which can linearly ensure that the bonding force of the transparent electrode pattern is in the central area of the transparent electrode. If there is a local tension change in the peripheral area, since the peripheral area is thinner, the tension change will not have a significant impact on the central area. The lateral tension generated by the tension change in the peripheral area can only automatically expand and contract linearly within the peripheral area, or even if there is a crack, it will be linear in the peripheral area and will not be transmitted directly to the central area, thereby ensuring the lateral transmission performance of the battery.

[0123] Optionally, the first semiconductor layer includes a tunneling layer 2 disposed on the silicon substrate, and an N-type doped polysilicon layer is disposed on a side of the tunneling layer 2 facing away from the silicon substrate.

[0124] The material of the tunneling layer 2 is, for example but not limited to, silicon dioxide. That is, the tunneling layer 2 is a tunneling silicon dioxide layer, and its thickness can be 1 nm to 4 nm, preferably 1 nm to 1.8 nm.

[0125] Materials such as phosphorus, arsenic, antimony, selenium, tellurium, etc. can be doped in the polysilicon to form an N-type doped polysilicon layer. The thickness of the N-type doped polysilicon layer is 30 nm to 250 nm. In this example, phosphorus doping is used, and the phosphorus doping concentration in the N-type doped polysilicon layer is 8E19 to 5E20 cm -3 , preferably 3 to 9E20 cm -3 .

[0126] The tunneling layer 2 is disposed on the polished back surface of the silicon substrate, that is, the tunneling layer 2 is disposed on the polished surface, which is beneficial to improving the deposition uniformity of the tunneling layer 2. In addition, the thickness of the tunneling layer is relatively thin, generally 1 nm to 4 nm, preferably 1 nm to 1.8 nm. If the surface of the silicon substrate has a relatively high surface texture, it is not conducive to the deposition uniformity of the tunneling layer 2, and in the subsequent polycrystalline annealing process, the uneven surface further deteriorates the unevenness at high temperature, and will interact with the uneven surface texture. The exposed silicon substrate surface with cliffs at the tips of the texture pyramids affects the tunneling effect of the battery; while in this solution, the surface of the silicon substrate is polished to be more flat, improving the uniformity of the tunneling layer 2, thereby enhancing the tunneling passivation effect and reducing the recombination loss.

[0127] The second semiconductor layer includes an intrinsic amorphous silicon layer, and a P-type doped microcrystalline silicon layer is disposed on a side of the intrinsic amorphous silicon layer facing away from the silicon substrate.

[0128] Materials such as boron, aluminum, gallium, indium, beryllium, magnesium, etc. can be doped in the microcrystalline silicon to form a P-type doped microcrystalline silicon layer. In this example, boron doping is used, and the boron doping concentration in the P-type doped microcrystalline silicon layer is 10E20 cm -3 ~10E21 cm -3 .

[0129] The thickness of the intrinsic amorphous silicon layer is 10 nm to 20 nm, and the thickness of the P-type doped microcrystalline silicon layer is 5 nm to 45 nm, preferably 10 nm to 20 nm.

[0130] By setting the above solutions, on the one hand, through the setting of the tunneling layer 2 and the N-type polysilicon layer, the conductivity of the first semiconductor layer is improved, and the conductivity of polysilicon is stronger; on the other hand, by setting the intrinsic amorphous silicon layer and the doped microcrystalline silicon layer, a low-temperature process can be used to reduce the complexity of the process. At the same time, the low-temperature process will not affect the performance of the tunneling layer and the N-type polysilicon layer in the previous step, avoiding the influence of impurity diffusion of doping elements caused by secondary high temperature. Third, by extending the intrinsic amorphous silicon layer to form a covering part G on the first semiconductor layer, the surface of the N-type polysilicon layer is further passivated, reducing recombination. At the same time, a doped P-type microcrystalline silicon layer is set on the intrinsic amorphous silicon layer. Due to the isolation and passivation effects of the intrinsic amorphous silicon layer and the conductivity of the low-temperature doped P-type microcrystalline silicon layer itself, the current breakdown, short circuit and leakage between the P and N-type semiconductor layers are avoided.

[0131] The climbing part P covers the first semiconductor layer containing microcrystalline silicon. Therefore, the film formation quality of microcrystalline silicon deposition is worse at positions with weak lateral transmission and high and low climbing structures, further deteriorating the conductivity of the first semiconductor layer at the climbing structure, thereby further improving the anti-leakage effect between the first region and the second region. With the improvement of the anti-leakage effect, the conversion efficiency of the back contact battery is correspondingly improved.

[0132] In addition, by setting a second gap W2 between the second transparent electrode pattern 21 and the climbing part P; since the second semiconductor layer includes microcrystalline silicon, the position where the microcrystalline silicon is in direct contact with the second transparent electrode pattern 21 has good conductivity, while there is no electrical transmission of the transparent electrode pattern in the second gap W2. Because the lateral conductivity of microcrystalline silicon is poor, the leakage current between the first transparent electrode pattern 11 and the second transparent electrode pattern 21 is weakened.

[0133] Optionally, the front surface of the silicon substrate is provided with a textured surface, and the front surface of the silicon substrate is provided with a textured surface. An intrinsic amorphous silicon layer is provided on the textured surface, or an alumina layer is provided on the textured surface.

[0134] Through the above setting solutions, the front surface of the silicon substrate can be passivated to reduce recombination. On the other hand, the intrinsic amorphous silicon layer and the alumina layer on the front surface have stable properties and can extend the life of the battery.

[0135] Optionally, an antireflection layer is provided on the surface of the intrinsic amorphous silicon facing away from the silicon substrate, or an antireflection layer is provided on the surface of the alumina layer facing away from the silicon substrate.

[0136] By setting the above solutions, the reflection of sunlight is reduced, the utilization rate of sunlight is improved, and the conversion efficiency of the back contact battery can be improved.

[0137] Optionally, as Figure 8As shown, the climbing portion P is inclined with respect to the back surface of the silicon substrate. Preferably, the inclination angle α of the climbing portion P with respect to the back surface of the silicon substrate is 5° to 80°, such as but not limited to 5°, 9°, 11°, 15°, 20°, 30°, 40°, 45°, 50°, 53°, 58°, 65°, 70°, 80°, etc., and preferably 30° to 70°.

[0138] Through the above setting scheme, the climbing portion P is inclined on the back surface of the silicon substrate, improving the uniformity of the deposition of the intrinsic amorphous silicon here and enhancing the passivation effect on the semiconductor substrate. At the same time, due to the better uniformity of the deposited intrinsic amorphous silicon layer and better surface topography conformability, it is beneficial to the deposition and preparation of the doped amorphous silicon layer, forming a doped amorphous silicon layer with better electrical properties, thereby also improving the conversion efficiency of the battery.

[0139] Optionally, at least refer to Figure 7 As shown, when a first transparent electrode pattern 11 is provided on the entire exposed first semiconductor region layer and on a part of the covering portion G along the direction perpendicular to the first region Q1 extending towards the second region Q2; or, when a first transparent electrode pattern 11 is provided on a part of the exposed first semiconductor region and a part of the covering portion G;

[0140] Along the direction perpendicular to the first region Q1 extending towards the second region Q2, the edge B1 of the first transparent electrode pattern 11 is wavy. This wavy shape can be an irregular curve.

[0141] Through the above setting scheme, setting the edge of the transparent electrode pattern layer to be wavy can reduce the edge stress of the transparent electrode pattern, avoiding the hidden crack of the transparent electrode pattern caused by the stress change of the silicon substrate at the edge and affecting the lateral transmission performance.

[0142] Optionally, at least refer to Figure 7 As shown, when a second transparent electrode pattern 21 is provided on a part of the second semiconductor layer above the orthographic projection of the second region Q2; and / or; when a second transparent electrode pattern 21 is provided on a part of the second semiconductor layer above the orthographic projection of the second region Q2 and on a part of the covering portion G;

[0143] Along the direction perpendicular to the first region Q1 extending towards the second region Q2, the edge B2 of the second transparent electrode pattern 21 is wavy. This wavy shape can be an irregular curve.

[0144] Through the above setting scheme, setting the edge of the transparent electrode pattern layer to be wavy can reduce the edge stress of the transparent electrode pattern, avoiding the hidden crack of the transparent electrode pattern caused by the stress change of the silicon substrate at the edge and affecting the lateral transmission performance.

[0145] In a second aspect, the present invention provides a method for preparing any of the above back-contact batteries, comprising the following steps:

[0146] Provide a battery precursor, the battery precursor comprising a silicon substrate, the silicon substrate comprising a front side and a back side; a plurality of first regions and a plurality of second regions are alternately arranged in sequence on the back side of the silicon substrate, a first semiconductor layer is provided in each of the first regions, a second semiconductor layer is provided in each of the second regions, the second semiconductor layer extends from the second region towards the first region, and sequentially comprises a climbing portion and a covering portion, and the covering portion covers a part of the first semiconductor layer;

[0147] Form a transparent electrode film on the back side of the battery precursor;

[0148] On the transparent electrode film, etch at least corresponding to the climbing portion P and a part of the covering portion G close to the climbing portion P, so as to etch the transparent electrode film to form separated first transparent electrode patterns 11 and second transparent electrode patterns 21.

[0149] The embodiments of the present invention will be described in detail below. It should be noted that the embodiments described below are exemplary and are only used to explain the present invention, and should not be construed as a limitation to the present invention. Additionally, if not specified explicitly, all reagents used in the following embodiments are commercially available, or can be synthesized according to the methods described herein or known methods. For the reaction conditions not listed, they are also easily obtained by those skilled in the art.

[0150] Example 1

[0151] This example provides a back-contact battery, and its preparation method is as follows:

[0152] S1: As Figure 9 , Figure 10 shown, provide an N-type silicon substrate 1, and polish at least the front side and the back side of the N-type silicon substrate 1 by using a wet polishing process.

[0153] Among them, before polishing, the N-type silicon substrate 1 needs to be cleaned to remove surface impurities, particles and organic substances. Generally, multi-step cleaning can be performed using deionized water, an alkaline solution (such as sodium hydroxide NaOH) and an acidic solution (such as dilute nitric acid HNO3).

[0154] For example but not limited to, the N-type silicon substrate 1 is placed in a trough-type alkaline polishing machine for polishing and cleaning. The working volume of the cleaning machine trough is 360 L. First, the N-type silicon substrate 1 is pre-cleaned to remove organic and other contaminants generated during the cutting and transportation of the N-type silicon substrate 1. In this embodiment, the No. 1 solution of standard RCA cleaning (SC-1) is used for cleaning. The No. 1 solution is composed of NH4OH-H2O2-H2O, and the volume ratio of the three is 1:1:5. The temperature during cleaning is 65 °C. The main function of the SC-1 reagent cleaning is alkaline oxidation, removing particles on the silicon wafer, and oxidizing and removing a small amount of organic matter and metal atom contaminants such as Au, Ag, Cu, Ni, Cd, Zn, Ca, Cr on the surface. After water washing and removing the residual chemicals, alkaline polishing treatment is carried out. The alkaline polishing formula is 5.97% wt of KOH, the temperature is 80 °C, and the alkaline polishing treatment time is 300 s to remove damage and polish. Then, SC1 cleaning, ozone cleaning, and finally pickling and dehydration are carried out to complete the polishing and cleaning. After polishing, its polished surface has multiple tower bases with crystal cell residues, and the maximum distance between any two points of the tower bases is 4-6 μm. For example, the size of the remaining tower bases after polishing can be adjusted by controlling the concentration, temperature, and polishing time of the polishing liquid.

[0155] S2: In a Low Pressure Chemical Vapor Deposition (LPCVD) device, the N-type silicon substrate 1 is thermally oxidized to form a tunneling layer 2 made of silicon dioxide on the front and back surfaces of the N-type silicon substrate 1. The thickness of the tunneling layer 2 can be 1 nm - 5 nm, such as 1 nm, 1.5 nm, 1.8 nm, 2 nm, 2.3 nm, 2.6 nm, 3 nm, 3.5 nm, 4 nm, 4.7 nm, 5 nm, etc. Then, an intrinsic polysilicon layer is deposited on each tunneling layer 2 respectively. In addition to LPCVD, the deposition of the intrinsic polysilicon layer can also be achieved by Plasma Enhanced Chemical Vapor Deposition (PECVD), Physical Vapor Deposition (PVD), and Plasma Enhanced Atomic Layer Deposition (PEALD) for the preparation of the tunneling layer 2 and the intrinsic or in-situ doped poly Si. Preferably, LPCVD is used to deposit the back tunneling layer 2 and the polysilicon (poly) layer at a high temperature of 600 - 800 °C. In the existing HBC battery structure, the deposition of the intrinsic a-si:H + a-si:H(N) film layer mostly uses expensive CVD equipment, while this application uses a cheap LPCVD equipment to replace the expensive CVD equipment, effectively reducing the equipment investment cost.

[0156] During the formation of the tunneling layer 2 and the intrinsic polysilicon layer, a certain amount of silicon dioxide and intrinsic polysilicon wrap-around will be formed on the sides of the N-type silicon substrate 1.

[0157] It should be noted that in each of the attached drawings, various wrap-arounds are not shown.

[0158] S3: Perform phosphorus diffusion on the intrinsic amorphous silicon layers 4 on the front and back sides of the N-type silicon substrate 1 respectively to form N-type polysilicon layers 3. Among them, the phosphorus doping concentration is 8E19 - 5E20 cm -3 (For example, it can be 8E19 / 9E19 / 1E20 / 2E20 / 3E20 / 4E20 / 5E20 cm -3 ).

[0159] Phosphorus diffusion can be carried out in a tube furnace.

[0160] During the phosphorus diffusion process, a phosphosilicate glass layer (Phosphosilicate Glass; PSG) will be formed on the surface of the N-type polysilicon layer, and there will be PSG overplating on the sides.

[0161] S4: Remove the PSG on the front, back, and wrap-around.

[0162] For example but not limited to, in a wet cleaning equipment, the PSG can be removed by hydrofluoric acid.

[0163] S5: Deposit a hydrogenated silicon nitride layer 7 (SiNx:H) on the N-type polysilicon layer on the back.

[0164] For example, the hydrogenated silicon nitride layer 7 can be deposited in a tube PECVD equipment. The hydrogenated silicon nitride layer 7 can be used as a mask for subsequent processes. When performing laser opening of the film subsequently, the hydrogenated silicon nitride layer 7 serves as a laser energy absorption layer, which has the effect of reducing the influence of the laser film opening process on the passivation effect of the N region, and also has the effect of providing a hydrogen source to further passivate the polysilicon and the silicon substrate, improving the passivation effect, and protecting the N-type doped polysilicon layer 3 from being corroded by alkali in the texturing process. The thickness of the hydrogenated silicon nitride layer 7 can be 50 nm - 110 nm. The deposition temperature of the hydrogenated silicon nitride layer 7 can be 400 °C - 600 °C.

[0165] Among them, at least hydrogenated silicon nitride overplating will be formed on the N-type polysilicon layer 3 on the front.

[0166] S6: Open the film on the hydrogenated silicon nitride layer 7 within the second region Q2 to form a mask.

[0167] For example, the silicon nitride hydride layer 7 within the range of the second region Q2 can be removed by means of laser etching. In some examples, after the silicon nitride hydride layer 7 within the range of the second region Q2 is removed, etching continues downward to remove a part of the N-type polysilicon layer on the back surface. In other examples, after the silicon nitride hydride layer 7 within the range of the second region Q2 is removed, etching continues downward until the surface of the N-type silicon substrate 1 is etched, that is, the N-type polysilicon layer and the tunneling layer 2 within the range of the second region Q2 are both removed.

[0168] In this example, a part of the N-type polysilicon layer on the back surface is taken as an example for being etched and removed.

[0169] S7: As Figure 11 shown, texturing is performed on the front and back surfaces of the N-type silicon substrate 1 respectively.

[0170] Among them, the front surface of the N-type silicon substrate 1 is textured over the entire surface, and the back surface is textured only within the range of the second region Q2 to form a pyramid light-trapping structure, that is, the textured surface structure 12, at the corresponding position.

[0171] Before texturing, first, hydrofluoric acid is used for cleaning to remove the remaining silicon nitride hydride layer 7 after laser film opening, the tunneling layer 2 and the N-type polysilicon layer 3 within the second region, and the tunneling layer 2 and the N-type polysilicon layer 3 on the front surface of the N-type silicon substrate 1.

[0172] Among them, a potassium hydroxide solution with a concentration of 0.8% - 1.2% can be used for texturing. For example, a potassium hydroxide solution with a mass fraction of 0.8%, 0.9%, 0.95%, 1% or 1.2% etc. can be used as a texturing additive in a tank cleaning machine to texture the N-type silicon substrate 1, so as to form a textured surface on the front surface of the N-type silicon substrate 1 and the second region Q2 on the back surface of the N-type silicon substrate 1.

[0173] Among them, for the silicon nitride hydride overplating on the front surface of the N-type silicon substrate 1, it can be removed after texturing. Whether to retain the silicon nitride hydride overplating on the side can be determined according to the actual situation.

[0174] S8: As Figure 12 shown, an intrinsic amorphous silicon layer 4 is deposited on the front and back surfaces of the component formed after texturing respectively.

[0175] An intrinsic amorphous silicon layer 4 can be deposited on the front and back surfaces respectively by using a plate-type PECVD device. The intrinsic amorphous silicon layer 4 can be deposited on the front surface first and then on the back surface; it can also be that the intrinsic amorphous silicon layer 4 is deposited on the back surface first and then on the front surface. Among them, when depositing the intrinsic amorphous silicon layer 4, an intrinsic amorphous silicon layer 4 wrap-around will only be formed on some sides and will not wrap around to the opposite side of the current deposition surface.

[0176] S9: As shown in Figure 13 , a P-type microcrystalline silicon layer 5 is deposited on the front and back surfaces of the component formed in step S8, and a SiNx antireflection layer 6 is deposited on the P-type microcrystalline silicon layer 5 on the front surface.

[0177] Among them, there will be SiNx overplating on the back and side surfaces, and there will be P-type amorphous silicon overhang on the side surface.

[0178] S10: As shown in Figure 14 , the intrinsic amorphous silicon layer 4 and the P-type microcrystalline silicon layer 5 are opened in the first region Q1 until the N-type polysilicon layer 3 is exposed.

[0179] For example, the intrinsic amorphous silicon layer 4 and the P-type microcrystalline silicon layer 5 can be opened in the first region Q1 by means of laser etching. After opening the film, a second semiconductor layer is formed in the second region Q2, and extends from the second region to the first region Q1, and sequentially includes a climbing portion P and a covering portion G. The covering portion G covers a part of the first semiconductor layer, forming an exposed first semiconductor region and a covered first semiconductor region.

[0180] S11: After the film opening is completed, through a wet etching process, the SiNx overplating on the back surface and the residual oxides and residues in the film opening region are removed.

[0181] For example, a chain pickling machine can be used to etch the SiNx overplating on the back surface and the residual oxides and residues in the film opening region.

[0182] S12: As shown in Figure 15 , after the wet etching process, a transparent conductive thin film 101 is deposited on the back surface.

[0183] The material of the transparent conductive thin film 101 is, for example, ITO, etc. The thickness of the transparent conductive thin film 101 can be 10nm - 300nm; for example, 10nm, 20nm, 35nm, 40nm, 60nm, 85nm, 100nm, 110nm, 130nm, 150nm, 180nm, 210nm, 240nm, 270nm, 300nm, etc.

[0184] S13: As shown in Figure 16 , the transparent conductive thin film 101 is disconnected at the junction of the first region Q1 and the second region Q2 to form a first transparent electrode pattern 11 and a second transparent electrode pattern 21. The first transparent electrode pattern 11 and the second transparent electrode pattern 21 are each an integral body.

[0185] For example, by means of screen printing, a viscous etching paste 8 containing phosphoric acid is formed at the climbing part where the first region Q1 intersects with the second region Q2, and the etching paste 8 is cured to prevent excessive flow during the etching process, so that the etching paste 8 disconnects the transparent conductive film 101 to form a first transparent electrode pattern 11 and a second transparent electrode pattern 21. Among them, on the entire exposed first semiconductor region layer, and on a part of the covering part G along the direction perpendicular to the extension of the first region Q1 towards the second region, the first transparent electrode pattern 11 is provided, or on a part of the exposed first semiconductor region and a part of the covering part G, the first transparent electrode pattern 11 is provided. After the etching of the transparent conductive film 101 is completed, the above-mentioned second gap W2 and third gap W3 are formed. Among them, in a certain cross-section, for example but not limited to a plane parallel to the A-A cross-section, the second gap W2 is 20 μm and the third gap W3 is 50 μm. The sizes of the second gap W2 and the third gap W3 in the following different examples are at the same cross-section position as in this example.

[0186] The etching paste 8 is used to disconnect the transparent conductive film 101 to form a first transparent electrode pattern 11 and a second transparent electrode pattern 21. Compared with the method of disconnecting the transparent conductive film 101 by laser etching or photolithographic etching, this solution can effectively disconnect the transparent conductive film 101, reducing the problems of residual transparent conductive material and large leakage current caused by laser etching of the transparent conductive film 101, and also solving the problems that photolithographic etching requires several processes such as dry film lamination, exposure, development, etching, and dry film removal, resulting in a long production process for the battery, high difficulty in process control during production, and limitations in production capacity and cost, etc., and being unable to meet the requirements of large-scale production.

[0187] S14: As Figure 17 shown, the residue of the etching paste 8 is removed.

[0188] For example, by means of wet alkali etching, the residue of the etching paste 8 is removed; when using the method of wet alkali etching to remove the residue of the etching paste 8, it will not affect the first transparent electrode pattern 11 and the second transparent electrode pattern 21.

[0189] S15: As Figure 18 shown, an electrode D is formed on the first transparent electrode pattern 11 and the second transparent electrode pattern 21.

[0190] By means of screen printing, metal paste is printed on the first transparent electrode pattern 11 and the second transparent electrode pattern 21, and the metal paste is cured to form the corresponding electrode.

[0191] An electrode can also be formed by inkjet printing, laser transfer printing, electroless plating, electroplating or PVD method.

[0192] The tunneling layer 2 and the N-type polysilicon layer 3 are formed at a high temperature of 600 - 800 °C and are located on the polished surface of the N-type silicon substrate 1. Then, the contact interface between the electrode in the first region and the N-type polysilicon layer 3 is a smooth surface contact. Moreover, for the N-type polysilicon layer 3 formed in a high-temperature environment, its smooth surface structure can ensure the passivation effect of the tunneling layer 2. At the same time, due to the high-temperature process, the adhesion and compactness of the film layer are better, and the bonding force with the electrode is also stronger. In the second region, the intrinsic amorphous silicon layer 4 and the P-type microcrystalline silicon layer 5 do not undergo the high-temperature process of the tunneling layer 2 and the N-type polysilicon layer 3 in the first region. The electrode is connected to the P-type microcrystalline silicon layer 5, and the connection effect needs to be improved. The contact area of a simple smooth surface structure is small, which is not conducive to the bonding force of the electrode. Therefore, a matte surface structure is set in the second region, increasing the specific surface area of the contact surface and improving the bonding force between the electrode and the P-type microcrystalline silicon layer 5.

[0193] Example 2

[0194] This example provides a back-contact battery. The main difference between this example and Example 1 is as follows:

[0195] On the front surface of the N-type silicon substrate 1, between the intrinsic amorphous silicon layer 4 and the SiNx antireflection layer 6, the P-type microcrystalline silicon layer 5 is not provided.

[0196] Example 3

[0197] This example provides a back-contact battery. The main difference between this example and Example 1 is as follows:

[0198] S8: On the front surface of the N-type silicon substrate 1, the intrinsic amorphous silicon is replaced with alumina. The alumina deposition can be carried out by ALD deposition, and there will be alumina overplating on the side.

[0199] S9: Deposit the SiNx antireflection layer on the front surface of the component formed in step S8. Among them, there will be SiNx overplating on the back and side surfaces.

[0200] S10: Deposit the intrinsic amorphous silicon and doped P-type microcrystalline silicon on the back surface of the component after S9 is completed. Then, in the first region Q1, open the film of the intrinsic amorphous silicon layer 4 and the P-type microcrystalline silicon layer 5 until the N-type polysilicon layer 3 is exposed, and form the intrinsic amorphous silicon and P-type doped microcrystalline silicon covering the second region, as well as the part of the intrinsic amorphous silicon and P-type doped microcrystalline silicon extending to the first region, forming a climbing part and a covering part.

[0201] Example 4

[0202] This example provides a back-contact battery. The main difference between this example and Example 1 is as follows:

[0203] The second gap W2 is 10 μm, and the third gap W3 is 50 μm.

[0204] Example 5

[0205] This example provides a back-contact battery. The main difference between this example and Example 1 is as follows:

[0206] The second gap W2 is 20 μm, and the third gap W3 is 60 μm.

[0207] Example 6

[0208] This example provides a back-contact battery. The main difference between this example and Example 1 is as follows:

[0209] The second gap W2 is 20 μm, and the third gap W3 is 70 μm.

[0210] Example 7

[0211] This example provides a back-contact battery. The main difference between this example and Example 1 is as follows:

[0212] The second gap W2 is 30 μm, and the third gap W3 is 60 μm.

[0213] Example 8

[0214] This example provides a back-contact battery. The main difference between this example and Example 2 is as follows:

[0215] The second gap W2 is 30 μm, and the third gap W3 is 70 μm.

[0216] Example 9

[0217] This example provides a back-contact battery. The main difference between this example and Example 2 is as follows:

[0218] The second gap W2 is 30 μm, and the third gap W3 is 80 μm.

[0219] Example 10

[0220] This example provides a back-contact battery. The main difference between this example and Example 2 is as follows:

[0221] The second gap W2 is 40 μm, and the third gap W3 is 80 μm.

[0222] Comparative Example 1

[0223] This comparative example provides a back-contact battery, and its preparation method is as follows:

[0224] S1: Provide an N-type silicon substrate 1, and polish at least the front and back surfaces of the N-type silicon substrate 1 using a wet polishing process.

[0225] Among them, the N-type silicon substrate 1 needs to be cleaned before polishing to remove surface impurities, particles and organic substances. Generally, multi-step cleaning can be carried out using deionized water, alkaline solutions (such as sodium hydroxide NaOH) and acidic solutions (such as dilute nitric acid HNO3).

[0226] For example but not limited to, the N-type silicon substrate 1 is placed in a tank-type alkaline polishing machine for polishing and cleaning. The working volume of the cleaning machine tank is 360L. First, the N-type silicon substrate 1 is pre-cleaned to remove organic and other contaminants generated during the cutting and transportation of the N-type silicon substrate 1. In this embodiment, the No. 1 solution of standard RCA cleaning is used for cleaning. The No. 1 solution is composed of NH4OH-H2O2-H2O, and the volume ratio of the three is 1:1:5. The temperature during cleaning is 65°C. The main function of SC-1 reagent cleaning is alkaline oxidation, removing particles on the silicon wafer, and oxidizing and removing a small amount of organic substances and metal atom contaminants such as Au, Ag, Cu, Ni, Cd, Zn, Ca, Cr on the surface. After water washing and residual chemicals, alkaline polishing treatment is carried out. The alkaline polishing formula is 5.97%wt KOH, the temperature is 80°C, and the alkaline polishing treatment time is 300s to remove damage and polish. Then, SC1 cleaning, ozone cleaning, and finally pickling and dehydration are carried out to complete polishing and cleaning. After polishing, the polished surface has multiple tower bases with crystal cell residues, and the maximum distance between any two points of the tower bases is 4-6μm. For example, the size of the remaining tower bases after polishing can be controlled by controlling the concentration, temperature and polishing time of the polishing solution.

[0227] S2: In a Low Pressure Chemical Vapor Deposition (LPCVD) apparatus, a thermal oxidation treatment is performed on the N-type silicon substrate 1 to form a tunneling layer 2 made of silicon dioxide on the front and back surfaces of the N-type silicon substrate 1. The thickness of the tunneling layer 2 can be 1 nm - 5 nm, such as 1 nm, 1.5 nm, 1.8 nm, 2 nm, 2.3 nm, 2.6 nm, 3 nm, 3.5 nm, 4 nm, 4.7 nm, 5 nm, etc. Then, an intrinsic polysilicon layer is deposited on each of the tunneling layers 2. In addition to LPCVD, the intrinsic polysilicon layer can also be deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD), Physical Vapor Deposition (PVD), Plasma Enhanced Atomic Layer Deposition (PEALD), etc. Generally, it is preferably to use LPCVD to deposit the back tunneling layer 2 and the intrinsic polysilicon layer at a high temperature of 600 - 800 °C. Deposition using an LPCVD apparatus can reduce the equipment cost investment.

[0228] During the formation of the tunneling layer 2 and the intrinsic polysilicon layer, a certain amount of silicon dioxide and intrinsic polysilicon wrap-around will be formed on the side surfaces of the N-type silicon substrate 1.

[0229] It should be noted that in each of the drawings, various wrap-arounds are not shown.

[0230] S3: Phosphorus diffusion is respectively performed on the intrinsic amorphous silicon layers 4 on the front and back surfaces of the N-type silicon substrate 1 to form N-type polysilicon layers 3. Among them, the phosphorus doping concentration is 8E19 - 5E20 cm -3 (for example, it can be 8E19 / 9E19 / 1E20 / 2E20 / 3E20 / 4E20 / 5E20 cm -3 ).

[0231] Phosphorus diffusion can be carried out in a tube furnace.

[0232] During the phosphorus diffusion process, a phosphosilicate glass layer (PSG) will be formed on the surface of the N-type polysilicon layer, and PSG overplating will exist on the side surfaces.

[0233] S4: Remove the PSG on the front, back, and wrap-around.

[0234] For example but not limited to, in a tank cleaning apparatus, the PSG can be removed by hydrofluoric acid.

[0235] S5: Deposit a silicon nitride hydride layer 7 (SiNx:H) on the N-type polysilicon layer on the back side.

[0236] For example, the silicon nitride hydride layer 7 can be deposited in a tube-type PECVD device. The silicon nitride hydride layer 7 can serve as a mask for subsequent processes. During subsequent laser opening of the film, the silicon nitride hydride layer 7 acts as a laser energy absorption layer, which can reduce the impact of the laser film opening process on the passivation effect of the N region, and also has the function of providing a hydrogen source to further passivate the polysilicon and the silicon substrate, improving the passivation effect, and protecting the N-type doped crystalline silicon layer 3 from being corroded by alkali during the texturing process. The thickness of the silicon nitride hydride layer 7 can be 50 nm to 110 nm.

[0237] Among them, silicon nitride hydride overcoating is formed at least on the N-type polysilicon layer 3 on the front side.

[0238] S6: Open the silicon nitride hydride layer 7 within the second region Q2 to form a mask.

[0239] For example, the silicon nitride hydride layer 7 within the second region Q2 can be removed by laser etching. In some examples, after the silicon nitride hydride layer 7 within the second region Q2 is removed, etching continues downward to remove a part of the N-type polysilicon layer on the back side. In other examples, after the silicon nitride hydride layer 7 within the second region Q2 is removed, etching continues downward until the surface of the N-type silicon substrate 1 is reached, that is, the N-type polysilicon layer and the tunneling layer 2 within the second region Q2 are both removed.

[0240] In this example, take the case where a part of the N-type polysilicon layer on the back side is etched away.

[0241] S7: Perform texturing on the front and back sides of the N-type silicon substrate 1 respectively.

[0242] Among them, the front side of the N-type silicon substrate 1 is textured over the entire surface, and the back side is textured only within the second region Q2 to form a pyramid light-trapping structure, that is, the textured surface structure 12, at the corresponding position.

[0243] Before texturing, first clean with hydrofluoric acid to remove the remaining silicon nitride hydride layer 7 after laser film opening, the tunneling layer 2 and the N-type polysilicon layer 3 within the second region, and the tunneling layer 2 and the N-type polysilicon layer 3 on the front side of the N-type silicon substrate 1.

[0244] Among them, a potassium hydroxide solution with a concentration of 0.8% to 1.2% can be used for texturing. For example, a potassium hydroxide solution with a mass fraction of 0.8%, 0.9%, 0.95%, 1%, or 1.2% can be used as a texturing additive in a tank cleaning machine to texture the N-type silicon substrate 1, so as to form a textured surface on the front surface of the N-type silicon substrate 1 and the second region Q2 on the back surface of the N-type silicon substrate 1.

[0245] After texturing, cleaning can be carried out in the SC1 cleaning tank - CP circular chute - SC2 cleaning tank - pickling tank respectively; among them, the main function of the SC1 cleaning tank is to remove the contamination and chemical residues on the surface of the intermediate piece, the function of the CP circular chute is to smooth the pyramid tips and valleys to prevent the epitaxial growth of amorphous silicon deposition, the function of the SC2 cleaning tank is to remove the metal residues on the N-type silicon substrate 1, and the function of the pickling tank is to chemically passivate the intermediate piece and form a hydrophobic structure.

[0246] Among them, for the hydrogenated silicon nitride overcoating on the front surface of the N-type silicon substrate 1, it can be removed after texturing. Whether to retain the hydrogenated silicon nitride overcoating on the side can be determined according to the actual situation.

[0247] S8: Intrinsic amorphous silicon layers 4 are deposited on the front and back surfaces of the component formed after texturing respectively.

[0248] A plate-type PECVD device can be used to deposit the intrinsic amorphous silicon layer 4 on the front and back surfaces respectively. The intrinsic amorphous silicon layer 4 can be deposited on the front surface first, and then on the back surface; it can also be that the intrinsic amorphous silicon layer 4 is deposited on the back surface first, and then on the front surface. Among them, when depositing the intrinsic amorphous silicon layer 4, an intrinsic amorphous silicon layer 4 wrap-around will only be formed on some sides, and it will not overcoat to the opposite side of the current deposition surface.

[0249] S9: P-type microcrystalline silicon layers 5 are deposited on the front and back surfaces of the component formed in step S8 respectively, and a SiNx antireflection layer 6 is deposited on the P-type microcrystalline silicon layer 5 on the front surface.

[0250] Among them, there will be SiNx overcoating on the back and side surfaces, and there will be P-type amorphous silicon wrap-around on the side surfaces.

[0251] S10: The intrinsic amorphous silicon layer 4 and the P-type microcrystalline silicon layer 5 are opened in the first region Q1 until the N-type polysilicon layer 3 is exposed.

[0252] For example, the intrinsic amorphous silicon layer 4 and the P-type microcrystalline silicon layer 5 can be opened in the first region Q1 by laser etching.

[0253] After the opening is completed, through a wet etching process, the SiNx overcoating on the back and the remaining oxides and residues in the opening region are removed.

[0254] For example, a chain pickling machine can be used to etch the SiNx wrap-around plating on the back surface, as well as the remaining oxides and residues in the film opening area.

[0255] S12: After the wet etching process, a transparent conductive film 101 is deposited on the back surface.

[0256] The material of the transparent conductive film 101 is, for example, ITO, etc. The thickness of the transparent conductive film 101 can be 10 nm - 300 nm; for example, 10 nm, 20 nm, 35 nm, 40 nm, 60 nm, 85 nm, 100 nm, 110 nm, 130 nm, 150 nm, 180 nm, 210 nm, 240 nm, 270 nm, 300 nm, etc.

[0257] S13: At the junction of the first region Q1 and the second region Q2, the transparent conductive film 101 is disconnected to form a first transparent electrode pattern 11 and a second transparent electrode pattern 21.

[0258] For example, by means of laser film opening, at the climbing part where the first region Q1 and the second region Q2 meet, the transparent conductive film 101 is etched and disconnected to form a first transparent electrode pattern 11 and a second transparent electrode pattern 21, and having the above-mentioned second gap W2 and third gap W3. Among them, the second gap W2 is 20 μm, and the third gap W3 is 50 μm. The power of the laser is 28 W.

[0259] When using laser etching to disconnect the transparent conductive film 101, due to the large laser energy, the high temperature generated will affect the passivation of the back contact battery, thus affecting the electrical performance of the back contact battery.

[0260] Comparative Example 2

[0261] This comparative example provides a back contact battery, and its main difference from Comparative Example 1 is that: the power of the laser is 31 W.

[0262] Comparative Example 3

[0263] This comparative example provides a back contact battery, and its main difference from Comparative Example 1 is that: the power of the laser is 34 W.

[0264] Comparative Example 4

[0265] This comparative example provides a back contact battery, and its main difference from Comparative Example 1 is that: the power of the laser is 37 W.

[0266] Performance tests are carried out on the energy conversion efficiency Eta, parallel resistance Rsh, open circuit voltage Voc, fill factor FF, and leakage current I-RV of the back contact batteries prepared in Examples 1-9 and Comparative Examples 1-4, and the results are shown in the following table:

[0267]

[0268]

[0269] It can be easily seen from the above that the leakage currents of the examples of this solution are all much smaller than those of the comparative examples.

[0270] It should be understood that the orientation or positional relationship indicated by terms such as "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. in the above text is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it cannot be understood as a limitation to the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0271] The above description is only the preferred embodiment of this application and the explanation of the applied technical principles. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to the technical solution formed by the specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the technical solution formed by mutually replacing the above features with the (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A back-contact battery, characterized in that, It includes a silicon substrate, and the silicon substrate includes a front side and a back side; a plurality of first regions and a plurality of second regions are alternately arranged in sequence on the back side of the silicon substrate, and a first semiconductor layer is provided in each of the first regions. A second semiconductor layer is provided in each of the second regions. The second semiconductor layer extends from the second region to the first region and sequentially includes a climbing portion and a covering portion. The covering portion covers a part of the first semiconductor layer, forming an exposed first semiconductor region and a covered first semiconductor region. A second transparent electrode pattern is provided only on a part of the second semiconductor layer above the orthographic projection of the second region. There is no second transparent electrode pattern on a part of the second semiconductor layer above the orthographic projection of the second region, and a second transparent electrode pattern is provided only on a part of the covering portion. There is no second transparent electrode pattern on a part of the covering portion. The edge of the second transparent electrode pattern is wavy. A first transparent electrode pattern is provided on the entire layer of the exposed first semiconductor region and on a part of the covering portion along the direction perpendicular to the extension from the first region to the second region. Or, a part of the exposed first semiconductor region and a part of the covering portion are provided with a first transparent electrode pattern. Moreover, there is always a first gap between the first transparent electrode pattern and the second transparent electrode pattern.

2. The back-contact battery according to claim 1, characterized in that, When a second transparent electrode pattern is provided on a part of the second semiconductor layer above the orthographic projection of the second region, a second gap is formed between the edge of the second transparent electrode pattern and the climbing portion in the cross-section of the back-contact battery.

3. The back-contact battery according to claim 2, characterized in that, A third gap is formed between the edge of the first transparent electrode pattern and the climbing portion.

4. The back-contact battery according to claim 3, wherein The ratio of the width of the third gap to the width of the second gap is between 1 and 3 times.

5. The back contact battery according to claim 1, characterized in that, The width of the covering portion is 60 - 200 micrometers.

6. The back-contact battery according to claim 3, characterized in that, The ratio of the width of the covering portion to the width of the third gap is between 4:3 and 2.

7. The back contact battery according to claim 1, characterized in that, The vertical distance between the surface of the covering portion facing away from the silicon substrate and a position on the silicon substrate is greater than the vertical distance between the surface of the second transparent electrode pattern facing away from the silicon substrate and a position on the silicon substrate.

8. The back-contact battery according to claim 1, characterized in that, The first transparent electrode pattern includes a first central region and a first peripheral region surrounding the first central region. The thickness of the first peripheral region is less than the average thickness of the first central region; and / or, The second transparent electrode pattern includes a second central region and a second peripheral region surrounding the second central region. The thickness of the second peripheral region is less than the average thickness of the second central region.

9. The back-contact battery according to claim 1, wherein The first transparent electrode pattern includes a first central region and a first peripheral region surrounding the first central region. In the cross-section of the back-contact battery, the thickness of the first peripheral region gradually increases along the direction away from the edge of the first peripheral region; and / or, The second transparent electrode pattern includes a second central region and a second peripheral region surrounding the second central region. In the cross-section of the back-contact battery, the thickness of the second peripheral region gradually increases along the direction away from the edge of the second peripheral region.

10. The back-contact battery according to any one of claims 1 to 9, characterized in that, The first semiconductor layer includes a tunneling layer disposed on the silicon substrate, and an N-type doped polysilicon layer is disposed on a side of the tunneling layer facing away from the silicon substrate; The second semiconductor layer includes an intrinsic amorphous silicon layer, and a P-type doped microcrystalline silicon layer is disposed on a side of the intrinsic amorphous silicon layer facing away from the silicon substrate.

11. The back-contact battery according to claim 1, characterized in that, A matte surface is provided on a front surface of the silicon substrate, and an intrinsic amorphous silicon layer is provided on the matte surface, or an alumina layer is provided on the matte surface.

12. The back-contact battery according to claim 11, wherein, An antireflection layer is provided on a surface of the intrinsic amorphous silicon facing away from the silicon substrate, or an antireflection layer is provided on a surface of the alumina layer facing away from the silicon substrate.

13. The back-contact battery according to claim 1, characterized in that, The climbing portion is inclined with respect to a back surface of the silicon substrate.

14. The back contact battery according to claim 1, characterized in that, When a first transparent electrode pattern is provided on the entire exposed first semiconductor region layer and on a part of the covering portion along a direction perpendicular to the first region extending toward the second region; or, When a part of the exposed first semiconductor region and a part of the covering portion are provided with a first transparent electrode pattern; Along a direction perpendicular to the first region extending toward the second region, an edge of the first transparent electrode pattern on the covering portion is wavy.

15. The back contact battery according to claim 1, characterized in that, When a second transparent electrode pattern is provided on a part of the second semiconductor layer above a positive projection of the second region; and / or; When a second transparent electrode pattern is provided on a part of the second semiconductor layer above a positive projection of the second region and on a part of the covering portion; Along a direction perpendicular to the first region extending toward the second region.

16. A method for preparing a back-contact battery, characterized in that, Including the following steps: Providing a battery precursor, the battery precursor including a silicon substrate, the silicon substrate including a front surface and a back surface; a plurality of first regions and a plurality of second regions are alternately disposed on the back surface of the silicon substrate in sequence, a first semiconductor layer is provided in each of the first regions, a second semiconductor layer is provided in each of the second regions, the second semiconductor layer extends from the second region toward the first region and sequentially includes a climbing portion and a covering portion, and the covering portion covers a part of the first semiconductor layer, Forming a transparent electrode thin film on the back surface of the battery precursor; on the transparent electrode thin film, etching is performed at least corresponding to the climbing portion and a position of a part of the covering portion close to the climbing portion, so as to etch the transparent electrode thin film to form a separated first transparent electrode pattern and a second transparent electrode pattern, wherein, the second transparent electrode pattern is provided on a part of the second semiconductor layer above a positive projection of the second region, and the second transparent electrode pattern is provided on a part of the covering portion, and an edge of the second transparent electrode pattern is wavy.

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