A communication anti-interference method, device, medium and product

Abstract

The present invention discloses a communication anti-interference method, device, medium and product, and relates to the technical field of NPC-I three-level system. The method is applied to an NPC-I three-level system, and the method includes: after establishing communication with the NPC-I three-level system, a high-frequency clock continuously samples communication data, the sampled data enters a shift register, and the data signal waveform corresponding to the shift register sequence at different sampling times is determined; the initial frame header sampling time is determined according to a preset waveform template set and the data signal waveform corresponding to the shift register sequence at different sampling times, and the actual frame tail time corresponding to the initial frame header sampling time is determined according to a relaxation factor and the theoretical frame tail time corresponding to the initial frame header sampling time, and then an interference-free waveform signal is output. The present invention uses the actual frame tail time as the frame header sampling time of the next frame, and reduces the signal interference once each frame is extracted in the data frame extraction stage, thereby achieving signal accumulation anti-interference during long-term communication.

Description

Technical Field

[0001] The present invention relates to the technical field of NPC-I three-level systems, and in particular to a communication anti-interference method, device, medium and product. Background Art

[0002] The topology of the NPC-I three-level system is as follows: Figure 1 As shown, each phase includes 4 fully controlled devices (for example: IGBT) and two passive commutation clamping diodes. Each device only bears half the bus voltage and can be used in situations with higher voltage. Correspondingly, each phase drive bridge has a drive unit, and the entire system has three drive units. In this way, the controller only needs three communication signals to greatly reduce the size of the controller. In addition, the high-cost optical fiber direct drive signal driving method is abandoned, and the electrical signal communication transmission method is adopted. The controller sends the control signal to the drive unit. The drive unit has a dedicated signal logic processor to execute the IGBT control logic according to the received instructions. The drive unit also returns the current state to the control unit through communication, such as Figure 2 The NPC-I three-level system includes a control unit and a three-phase drive unit. The two communicate bidirectionally through electrical signals. The downlink communication link topology is shown in the figure below. Figure 3 , the processor on the control unit (which can be MCU, FPGA or CPLD) gives a low-voltage control signal, generally LVTTL or LVCMOS potential, generally 3.3V. Since the electrical signal transmission distance between the control unit and the drive unit is long (can reach more than 5 meters), in order to improve the anti-interference ability, the low-level signal is converted into a high-level signal (such as 15V or 24V) through a level conversion circuit. The signal is transmitted after impedance matching. After the drive unit receives the high-level signal, it passes through the high-level to low-level conversion circuit, and then passes through the Schmitt circuit to improve the anti-interference characteristics and drive the subsequent signal isolation circuit (which can be optical signal isolation or magnetic isolation. Here, if the system topology voltage level is higher, the corresponding signal isolation requirements must also be matched and improved). The isolated signal is at a non-safe ground potential and is transmitted to the processor of the drive unit (which can be MCU, FPGA or CPLD). The uplink communication link topology diagram is as follows Figure 4 , single-phase drive unit topology Figure 5, the processor on the drive unit (which can be MCU, FPGA or CPLD) drives the signal isolation circuit behind. Convert the signal from non-safe ground to safe ground potential. In order to improve the anti-interference ability, the low-level signal is converted into a high-level signal (such as 15V or 24V) through the level conversion circuit. The signal is transmitted after impedance matching. After the control unit receives the high-level signal, it passes through the high-level to low-level conversion circuit, and then passes through the Schmitt circuit to improve the anti-interference characteristics and transmit it to the processor of the control unit (which can be MCU, FPGA or CPLD). The control signal of the safe ground potential from the control unit sends the instruction to the driving logic control unit of the floating potential or the bus midpoint potential through the signal isolation circuit. The driving logic control unit controls the opening and closing of the four IGBTs on the phase bridge arm according to the received instructions, and receives the feedback signal from the drive circuit, which is encoded and returned to the control unit through the signal isolation circuit to complete the closed-loop control.

[0003] In terms of software, since the conventional direct drive method is not adopted, the control unit and the drive unit need to interact through communication. The communication volume between the two is not large, but the real-time requirement is high. Therefore, the communication frame rate needs to be increased as much as possible. Therefore, a fixed-cycle Bit pulse width encoding method is adopted. For example: if 5 control signals are to be transmitted, a fixed transmission cycle T = 6 times the bit rate can be set. Figure 6 As shown in the figure, 5 types of signals can be transmitted through 5 types of bit pulse widths. There is no need to set idle time, which saves communication transmission time and reduces communication delay. For the transmission of the above coded control signals, electrical signal transmission is used. In actual applications, there will be signal interference problems. Interference signals such as Figure 7 shown. Summary of the invention

[0004] The object of the present invention is to provide a communication anti-interference method, device, medium and product, which can reduce signal interference during communication of an NPC-I three-level system.

[0005] To achieve the above object, the present invention provides the following solutions:

[0006] A communication anti-interference method, the communication anti-interference method is applied to a communication anti-interference device; the anti-interference device is applied to an NPC-I three-level system, the communication anti-interference device comprises: a high-frequency sampling module, a shift register, a data frame parser and a frame header position discriminator, and a plurality of pulse width counting and analysis components;

[0007] The high-frequency sampling module is connected to the shift register; after the high-frequency sampling module establishes communication with the NPC-I three-level system, the high-frequency clock continuously samples the communication data and inputs the multiple sampling point data into the shift register;

[0008] The shift register is respectively connected to a plurality of pulse width counting and analysis components; the capacity of the shift register is N×Q; wherein N is the capacity of a pulse width counting and analysis component; and Q is the total number of pulse width counting and analysis components; when the high-frequency sampling module completes sampling at the t-th sampling time, the first element in the shift register sequence corresponding to the t-1-th sampling time is deleted, the element numbers of all elements in the shift register sequence except the first element are reduced by 1, and the sampling data at the t-th sampling time is used as the N×Q-th element to generate the shift register sequence corresponding to the t-th sampling time;

[0009] The plurality of pulse width counting and analysis components are all connected to the data frame parser; the qth pulse width counting and analysis component is used to obtain the qth bit data from the (q-1)×N+1th element to the q×Nth element in the shift register sequence corresponding to the tth sampling moment, and determine the calculation result of the qth bit data;

[0010] A pulse width counting and analysis component comprises a pulse width counter and a pulse width data analyzer connected in sequence; the pulse width counters in all pulse width counting and analysis components are connected to the shift register; the pulse width data analyzers in all pulse width counting and analysis components are connected to the data frame analyzer;

[0011] The data frame parser is connected to the frame header position discriminator; the data frame parser is used to generate a data signal waveform corresponding to the t-th sampling time according to the calculation results of Q bits of data;

[0012] The frame header position identifier is used to determine the initial frame header position according to the loose factor and the data signal waveform corresponding to different sampling moments;

[0013] The communication anti-interference method comprises:

[0014] When establishing communication with the NPC-I three-level system, let the sampling time sequence number t = 1;

[0015] Construct an empty set as the pending initial frame header sequence;

[0016] Determine whether the data signal waveform corresponding to the t-th sampling moment satisfies the pending initial frame header sequence condition, and obtain a first judgment result; the pending initial frame header sequence condition is that the data signal waveform corresponding to the t-th sampling moment is the same as any preset waveform template in the preset waveform template set, and the data signal waveform corresponding to the t-1-th sampling moment is the same as any preset waveform template in the preset waveform template set, and the preset waveform template corresponding to the t-th sampling moment is the same as the preset waveform template corresponding to the t-1-th sampling moment;

[0017] If the first judgment result is yes, then t+1-N×Q is added as the last element to the pending initial frame header sequence, the value of the sampling time sequence number t is increased by 1, and the step of "determining whether the data signal waveform corresponding to the t-th sampling time satisfies the pending initial frame header sequence condition to obtain the first judgment result" is returned;

[0018] If the first judgment result is no, then judging whether the number of elements in the pending initial frame header sequence is greater than a preset continuous value, and obtaining a second judgment result;

[0019] If the second judgment result is no, the value of the sampling time sequence number t is increased by 1, and the process returns to the step of "constructing an empty set as a pending initial frame header sequence";

[0020] If the second judgment result is yes, determining the first frame header sampling time according to the pending initial frame header sequence;

[0021] Let frame number i = 1;

[0022] When the sampling data at the i-th frame header sampling moment is in the first element in the shift register sequence, the corresponding shift register sequence is the i-th frame data;

[0023] Determine the sampling time corresponding to the N×Qth element of the i-th frame data as the theoretical frame end time of the i-th frame;

[0024] Determine a sequence formed by the easing factor sampling time before the theoretical frame end time of the i-th frame and the theoretical frame end time of the i-th frame, and the easing factor sampling time after the theoretical frame end time of the i-th frame, as the actual frame end sequence to be determined;

[0025] According to the pending actual frame end sequence, determine the actual frame end time of the i-th frame;

[0026] Determine that the data signal waveform corresponding to the interference-free time sequence of the i-th frame is the interference-free waveform signal of the i-th frame; the interference-free time sequence of the i-th frame includes the sampling time of the i-th frame head to the actual frame end time of the i-th frame; the interference-free waveform signal of the i-th frame is output by the data frame parser;

[0027] The actual end time of the i-th frame is used as the i+1-th frame header sampling time, the value of the frame number i is increased by 1, and the step of "obtaining the sampling data at the i-th frame header sampling time and the corresponding shift register sequence when the first element in the shift register sequence is the i-th frame data" is returned.

[0028] Optionally, determining the first frame header sampling time according to the pending initial frame header sequence includes:

[0029] Determine whether the number of elements of the pending initial frame header sequence is an odd number, and obtain a third determination result;

[0030] If the third judgment result is yes, then the (B+1) / 2th element in the pending initial frame header sequence is determined as the first frame header sampling time; B is the total number of elements in the pending initial frame header sequence;

[0031] If the third judgment result is no, then the B / 2th element in the pending initial frame header sequence is determined to be the first frame header sampling time.

[0032] Optionally, determining the actual frame end time of the i-th frame according to the to-be-determined actual frame end sequence includes:

[0033] Let the judgment number v = 1;

[0034] Construct the empty set as the decision sequence;

[0035] When the sampling data at the vth sampling time in the pending actual frame tail sequence is in the N×Qth element in the shift register sequence, the corresponding data signal waveform is the vth pending frame signal waveform;

[0036] Determine whether the vth pending frame signal waveform satisfies the determination sequence condition, and obtain a fourth determination result; the determination sequence condition is that the vth pending frame signal waveform is the same as any preset waveform template in the preset waveform template set, the v-1th pending frame signal waveform is the same as any preset waveform template in the preset waveform template set, and the preset waveform template corresponding to the vth pending frame signal waveform is the same as the preset waveform template corresponding to the v-1th pending frame signal waveform;

[0037] If the fourth judgment result is yes, the vth sampling moment in the pending actual frame end sequence is added as the last element to the determination sequence, the value of the determination sequence number v is increased by 1, and the step of "obtaining the sampling data at the vth sampling moment in the pending actual frame end sequence in the N×Qth element in the shift register sequence, and the corresponding data signal waveform is the vth pending frame signal waveform" is returned;

[0038] If the fourth judgment result is no, then judging whether the number of elements in the determination sequence is greater than a preset continuous value, and obtaining a fifth judgment result;

[0039] If the fifth judgment result is yes, determining the actual frame end time of the i-th frame according to the judgment sequence;

[0040] If the fifth judgment result is no, then judging whether the judgment sequence number v reaches the judgment sequence number threshold value is obtained to obtain a sixth judgment result; the judgment sequence number threshold value is equal to the difference between the total number of elements in the actual frame end sequence to be determined and the preset continuous value;

[0041] If the sixth judgment result is no, the value of the sampling time sequence number v is increased by 1, and the process returns to the step of "constructing an empty set as a judgment sequence";

[0042] If the sixth judgment result is yes, then the theoretical frame end time of the i-th frame is determined to be the actual frame end time of the i-th frame.

[0043] Optionally, determining the actual frame end time of the i-th frame according to the determination sequence includes:

[0044] Determine whether the number of elements of the determination sequence is an odd number, and obtain a seventh determination result;

[0045] If the seventh judgment result is yes, then the (A+1) / 2th element in the judgment sequence is determined to be the actual end time of the i-th frame; A is the total number of elements in the judgment sequence;

[0046] If the seventh judgment result is no, then the A / 2th element in the judgment sequence is determined to be the actual frame end time of the i-th frame.

[0047] Optionally, the calculation result of the qth bit data is the sum of the (q-1)×N+1th element to the q×Nth element in the shift register sequence corresponding to the tth sampling time.

[0048] Optionally, generating a data signal waveform corresponding to the t-th sampling time according to the calculation results of the Q bits of data includes:

[0049] Get the threshold factor;

[0050] Determine the first determination amount as half of the sum of the capacity N of the pulse width counting and analysis component and the threshold factor;

[0051] Determine half of the difference between the capacity N of the pulse width counting and analyzing component and the threshold factor as the second determination amount;

[0052] Set the pulse width counting and analysis component serial number q=1;

[0053] When the calculation result of the qth bit data is greater than the first determination value, determining that the qth analysis signal is a high level;

[0054] When the calculation result of the qth bit data is less than the second determination value, determining that the qth analysis signal is a low level;

[0055] Increase the value of the pulse width counting analysis component serial number q by 1, and return to the step "when the calculation result of the qth bit data is greater than the first judgment value, determine that the qth analysis signal is a high level" until the value of the pulse width counting analysis component serial number q reaches Q, arrange multiple analysis signals in ascending order according to the pulse width counting analysis component serial number q and connect them to generate a data signal waveform corresponding to the tth sampling moment.

[0056] Optionally, the method further includes:

[0057] When the communication is interrupted, return to the step "When establishing communication with the NPC-I three-level system, set the sampling time sequence number t=1".

[0058] A computer device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the communication anti-interference method described above.

[0059] A computer-readable storage medium stores a computer program, which implements the communication anti-interference method when executed by a processor.

[0060] A computer program product comprises a computer program, and when the computer program is executed by a processor, the communication anti-interference method is implemented.

[0061] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0062] The present invention provides a communication anti-interference method, device, medium and product. The method is applied to an NPC-I three-level system. After establishing communication with the NPC-I three-level system, a high-frequency clock continuously samples communication data, and the sampled data enters a shift register to determine the data signal waveform corresponding to the shift register sequence at different sampling times; the initial frame header sampling time is determined according to a preset waveform template set and the data signal waveform corresponding to the shift register sequence at different sampling times, and the actual frame end time corresponding to the initial frame header sampling time is determined according to a relaxation factor and a theoretical frame end time corresponding to the initial frame header sampling time, and an interference-free waveform signal is output according to the initial frame header sampling time and the actual frame end time, so as to complete the communication signal anti-interference during one iteration; the actual frame end time is used as the frame header sampling time of the next frame to complete the frame header correction, so as to realize signal accumulation anti-interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0064] Figure 1 It is a schematic diagram of the topological structure of the NPC-I three-level system in the prior art;

[0065] Figure 2 It is a communication schematic diagram of the NPC-I three-level system in the prior art;

[0066] Figure 3It is a downlink communication link topology diagram of the NPC-I three-level system in the prior art;

[0067] Figure 4 It is a topological diagram of the uplink communication link of the NPC-I three-level system in the prior art;

[0068] Figure 5 A topology diagram of a single-phase drive unit of an NPC-I three-level system in the prior art;

[0069] Figure 6 It is a schematic diagram of control signals before transmission of the NPC-I three-level system in the prior art;

[0070] Figure 7 A first schematic diagram of a control signal of an NPC-I three-level system in the prior art that is disturbed after transmission;

[0071] Figure 8 A schematic flow chart of a communication anti-interference method provided in Embodiment 1 of the present invention;

[0072] Fig. 9 FIG. 2 is a second schematic diagram of a control signal of an NPC-I three-level system in the prior art that is disturbed after transmission. DETAILED DESCRIPTION

[0073] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0074] The object of the present invention is to provide a communication anti-interference method, device, medium and product, which can reduce signal interference during communication of an NPC-I three-level system.

[0075] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0076] Example 1

[0077] like Figure 8 As shown, a communication anti-interference method in this embodiment is applied to a communication anti-interference device. The anti-interference device is applied to an NPC-I three-level system, and the communication anti-interference device includes: a high-frequency sampling module, a shift register, a data frame parser and a frame header position discriminator, and multiple pulse width counting and analysis components.

[0078] The high-frequency sampling module is connected to the shift register. After the high-frequency sampling module establishes communication with the NPC-I three-level system, the high-frequency clock continuously samples the communication data and inputs multiple sampling point data into the shift register.

[0079] The shift register is connected to a plurality of pulse width counting and analysis components respectively. The capacity of the shift register is N×Q. Where N is the capacity of a pulse width counting and analysis component. Q is the total number of pulse width counting and analysis components. When the high-frequency sampling module completes sampling at the t-th sampling time, the first element in the shift register sequence corresponding to the t-1-th sampling time is deleted, the element numbers of all elements in the shift register sequence except the first element are reduced by 1, and the sampling data at the t-th sampling time is used as the N×Q-th element to generate the shift register sequence corresponding to the t-th sampling time.

[0080] Multiple pulse width counting and analysis components are connected to the data frame parser. The qth pulse width counting and analysis component is used to obtain the qth bit data from the (q-1)×N+1th element to the q×Nth element in the shift register sequence corresponding to the tth sampling moment, and determine the calculation result of the qth bit data.

[0081] A pulse width counting and analysis component includes a pulse width counter and a pulse width data analyzer connected in sequence. The pulse width counters in all pulse width counting and analysis components are connected to the shift register. The pulse width data analyzers in all pulse width counting and analysis components are connected to the data frame analyzer.

[0082] The data frame parser is connected to the frame header position discriminator and is used to generate a data signal waveform corresponding to the t-th sampling time according to the calculation results of the Q-bit data.

[0083] The frame header position discriminator is used to determine the initial frame header position according to the relaxation factor and the data signal waveform corresponding to different sampling moments.

[0084] Communication anti-interference methods include:

[0085] Step 101: When establishing communication with the NPC-I three-level system, set the sampling time sequence number t=1.

[0086] Step 102: construct an empty set as a pending initial frame header sequence.

[0087] Step 103: Determine whether the data signal waveform corresponding to the t-th sampling moment satisfies the pending initial frame header sequence condition, and obtain a first determination result. The pending initial frame header sequence condition is that the data signal waveform corresponding to the t-th sampling moment is the same as any preset waveform template in the preset waveform template set, and the data signal waveform corresponding to the t-1-th sampling moment is the same as any preset waveform template in the preset waveform template set, and the preset waveform template corresponding to the t-th sampling moment is the same as the preset waveform template corresponding to the t-1-th sampling moment.

[0088] Step 104: If the first judgment result is yes, then t+1-N×Q is added as the last element to the pending initial frame header sequence, the value of the sampling time sequence number t is increased by 1, and the process returns to step 103.

[0089] Step 105: If the first judgment result is no, then determine whether the number of elements in the pending initial frame header sequence is greater than a preset continuous value to obtain a second judgment result.

[0090] Step 106: If the second judgment result is no, the value of the sampling time sequence number t is increased by 1, and the process returns to step 102.

[0091] Step 107: If the second judgment result is yes, determine the first frame header sampling time according to the pending initial frame header sequence.

[0092] Step 108: Set frame number i=1.

[0093] Step 109: When the sampling data at the i-th frame header sampling moment is in the first element in the shift register sequence, the corresponding shift register sequence is the i-th frame data.

[0094] Step 1010: Determine the sampling time corresponding to the N×Qth element of the i-th frame data as the theoretical frame end time of the i-th frame.

[0095] Step 1011: determine a sequence formed by the easing factor sampling time before the theoretical frame end time of the i-th frame, the theoretical frame end time of the i-th frame, and the easing factor sampling time after the theoretical frame end time of the i-th frame as the actual frame end sequence to be determined.

[0096] Step 1012: Determine the actual frame end time of the i-th frame according to the to-be-determined actual frame end sequence.

[0097] Step 1013: Determine that the data signal waveform corresponding to the interference-free time sequence of the i-th frame is the interference-free waveform signal of the i-th frame; the interference-free time sequence of the i-th frame includes the sampling time of the i-th frame head to the actual frame end time of the i-th frame; the interference-free waveform signal of the i-th frame is output by the data frame parser.

[0098] Step 1014: Use the actual end time of the i-th frame as the sampling time of the i+1-th frame head, increase the value of the frame number i by 1, and return to step 109.

[0099] Step 1015: When the communication is interrupted, return to step 101.

[0100] Step 107 includes:

[0101] Step 107 - 1 : Determine whether the number of elements of the to-be-determined initial frame header sequence is an odd number, and obtain a third determination result.

[0102] Step 107-2: If the third judgment result is yes, determine the (B+1) / 2th element in the pending initial frame header sequence as the first frame header sampling time. B is the total number of elements in the pending initial frame header sequence.

[0103] Step 107 - 3 : If the third judgment result is no, then determine that the B / 2th element in the pending initial frame header sequence is the first frame header sampling time.

[0104] Step 1012 includes:

[0105] Step 1012-1: Set the determination number v=1.

[0106] Step 1012-2: Construct an empty set as a decision sequence.

[0107] Step 1012-3: When the sampling data at the vth sampling time in the pending actual frame end sequence is in the N×Qth element in the shift register sequence, the corresponding data signal waveform is the vth pending frame signal waveform.

[0108] Step 1012-4: Determine whether the vth pending frame signal waveform satisfies the determination sequence condition, and obtain a fourth determination result. The determination sequence condition is that the vth pending frame signal waveform is the same as any preset waveform template in the preset waveform template set, the v-1th pending frame signal waveform is the same as any preset waveform template in the preset waveform template set, and the preset waveform template corresponding to the vth pending frame signal waveform is the same as the preset waveform template corresponding to the v-1th pending frame signal waveform.

[0109] Step 1012-5: If the fourth judgment result is yes, then add the vth sampling moment in the pending actual frame end sequence as the last element to the judgment sequence, increase the value of the judgment sequence number v by 1, and return to step 1012-3.

[0110] Step 1012-6: If the fourth judgment result is no, then determine whether the number of elements in the determination sequence is greater than a preset continuous value to obtain a fifth judgment result.

[0111] Step 1012-7: If the fifth judgment result is yes, determine the actual frame end time of the i-th frame according to the judgment sequence.

[0112] Step 1012-8: If the fifth judgment result is no, determine whether the judgment sequence number v reaches the judgment sequence number threshold to obtain a sixth judgment result. The judgment sequence number threshold is equal to the difference between the total number of elements in the actual frame end sequence to be determined and the preset continuous value.

[0113] Step 1012-9: If the sixth judgment result is no, increase the value of the sampling time sequence number v by 1, and return to step 1012-2.

[0114] Step 1012-10: If the sixth judgment result is yes, determine the theoretical frame end time of the i-th frame as the actual frame end time of the i-th frame.

[0115] Step 1012-7 includes:

[0116] Step 1012-7-1: Determine whether the number of elements in the determination sequence is an odd number, and obtain the seventh determination result.

[0117] Step 1012-7-2: If the seventh judgment result is yes, then determine that the (A+1) / 2th element in the judgment sequence is the actual end time of the i-th frame. A is the total number of elements in the judgment sequence.

[0118] Step 1012-7-3: If the seventh judgment result is no, determine that the A / 2th element in the judgment sequence is the actual end time of the i-th frame.

[0119] According to the calculation results of Q bits of data, the data signal waveform corresponding to the t-th sampling time is generated, including:

[0120] Step 1: Get the threshold factor.

[0121] Step 2: Determine half of the sum of the capacity N of the pulse width counting and analysis component and the threshold factor as the first determination amount.

[0122] Step 3: Determine half of the difference between the capacity N of the pulse width counting and analyzing component and the threshold factor as the second determination amount.

[0123] Step 4: Set the pulse width counting and analysis component serial number q=1.

[0124] Step 5: When the calculation result of the qth bit data is greater than the first determination value, determine that the qth analysis signal is a high level. The calculation result of the qth bit data is the sum of the (q-1)×N+1th element to the q×Nth element in the shift register sequence corresponding to the tth sampling time.

[0125] Step 6: When the calculation result of the qth bit data is less than the second determination value, determine that the qth analysis signal is a low level.

[0126] Step 7: Increase the value of the pulse width counting analysis component serial number q by 1, and return to step 5 until the value of the pulse width counting analysis component serial number q reaches Q, arrange multiple analysis signals in ascending order according to the pulse width counting analysis component serial number q and connect them to generate a data signal waveform corresponding to the tth sampling moment.

[0127] The present invention uses a programmable logic device (FPGA or CPLD), assuming an ideal condition:

[0128] The time of one bit is t, the communication cycle is T, then T = 6 times t. The sampling rate is increased inside the logic device. If one bit is sampled N times, using the shift register method, then the entire sampling sequence will be a binary number of 6×N bits.

[0129] For simplicity of description, N=10 (N>20 is the best for practical application). Then, ideally, the sampling result of a complete data frame with a 1-bit pulse width is:

[0130] 1111111111000000000000000000000000000000000000000000000000000000000000000000000000.

[0131] The data frame sampling result of 2-bit pulse width is:

[0132] 11111111111111111111000000000000000000000000000000000000000000000000000000.

[0133] And so on.

[0134] So Figure 7 The sampling results of the disturbed data frame may be:

[0135] 11111110000111111111000000000000000000000000000000000000000000000000000000.

[0136] The first two bit pulse widths are disturbed:

[0137] The first bit pulse width sampling result is: 1111111000.

[0138] The second bit pulse width sampling result is: 01111111111.

[0139] Then by calculating the number of 1s in each bit pulse width in the entire sampling sequence, the original data can be analyzed, as shown in the above sequence.

[0140] The first bit pulse width sampling result contains 7 1s.

[0141] The second bit pulse width sampling result contains 9 1s.

[0142] Set a threshold factor M.

[0143] If the sampling result > (N+M) / 2, this bit is high.

[0144] If the sampling result < (NM) / 2, this bit is low.

[0145] If the sampling result is between the two, it cannot be judged and the frame data is discarded.

[0146] However, the above methods cannot completely solve the problem. Fig. 9 In the waveform shown, the tail t0 time period of the last bit of the first communication cycle and the head t1 time period of the third bit of the second communication cycle are disturbed. Because the present invention adopts the sampling sequence of the shift register, the t0 time period and the t1 time period are both calculated when calculating the sampling result. The correct data should be:

[0147] 11111111111111111111000000000000000000000000000000000000000000000000000000.

[0148] But the result in the sampled data stream will appear:

[0149] 111111111111111111111111111100000000000000000000000000000000000000000000.

[0150] According to the method described in the previous paragraph, the third bit pulse width sampling result in the sequence contains 7 1s, and the sampling result of the third bit will be considered to be a high level, which is an error. Therefore, the present invention adds an error correction method. Because the communication cycle is fixed, after the previous data stream is completely received, the current communication cycle ends, and the redundant sampling data of t0 is discarded. The sampling result is refreshed from the beginning of the second cycle. By superimposing the above method, the data can be parsed.

[0151] In the case of continuous interference of the communication frame, the most accurate data frame can be found by the following method: set a data frame position factor X, and set the initial value to X = 6 × N; then ideally, a data frame will appear every X logic device sampling points, that is, a complete digital frame is currently parsed. For the logic sampling unit, another complete data frame will appear after X time points. Because the control unit and the drive unit use their own crystal oscillators, there will be errors. In addition, the waveform may be offset due to the influence of hardware and temperature during data transmission. Therefore, a time slack factor x is set, and the data in the time period of (Xx) to (X+x) will be parsed. Then, the 2x+1 data sets are analyzed, and the data that accounts for the majority of them is the most correct result. Assuming that there are Y consecutive correct data in the 2x+1 data, the middle position point of Y is the most accurate position to obtain the result, that is, the tail of the current data frame and the head of the next frame. Then, taking the middle point of Y as the reference, after the next frame of data is received, the data in the time period of (Xx) to (X+x) is parsed again using the above method, which can continuously play an anti-interference role.

[0152] like Figure 8 , the communication processing flow is as follows:

[0153] 1. The received communication signal is sampled at high frequency by the phase-locked loop high-frequency clock.

[0154] 2. The sampled data enters the shift register sequence.

[0155] 3. According to the agreed number of protocol data bits n, the sampled register sequence data is given to the corresponding Bit pulse width calculator.

[0156] 4. According to the agreed sampling coefficient N and threshold factor M, the corresponding analysis results are output through the data analyzer.

[0157] 4-1. If the result > (N+M) / 2, the bit is high.

[0158] 4-2. If the result < (NM) / 2, the bit is low.

[0159] 4-3. If none of the above is true, discard the current data.

[0160] 5. The analysis results enter the data frame parser, which has two parameters, the data frame position factor X and the looseness factor x.

[0161] 6. The data frame parser will continuously parse the data during the period from (Xx) to (X+x), where the majority of the data is the most correct result. The middle moment of the continuous correct result sequence can be considered as the end of the current data frame and the header of the next data frame. The header position identifier will parse out a new data frame position factor X to parse the next data frame, and the data frame parser will output the result.

[0162] The advantages of the above method are: after each clock cycle, the sampled data will be continuously stored and analyzed until the most correct result is given, and it has strong anti-interference performance. In addition, because the drive unit is close to the IGBT, there will be high voltage and high current interference during operation, especially the switching action of the IGBT is accompanied by a relatively large dv / dt, which will cause great interference to the communication. Therefore, on the basis of the above method, the following method is added: the drive unit logic controls the switching action of the IGBT, so the communication frame can be discarded during the switching action of the IGBT to improve the system reliability. In addition, the IGBT drive circuit has the following time parameters:

[0163] Tdon: opening delay time.

[0164] Tr: Rise time.

[0165] Tdoff: shutdown delay time.

[0166] Tf: Fall time.

[0167] The total delay for opening is Taon=Tdon+Tr.

[0168] The total shutdown delay Taoff=Tdoff+Tf.

[0169] Therefore, in this period of time after the driving signal changes, a communication frame discarding time can be set according to the total delay of opening or closing to improve reliability. Of course, in order to simplify the system, a fixed value Ta can be used, and Ta must be greater than Taon and Taoff.

[0170] Example 2

[0171] A computer device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement a communication anti-interference method in embodiment 1.

[0172] Example 3

[0173] A computer-readable storage medium stores a computer program, which implements a communication anti-interference method in embodiment 1 when executed by a processor.

[0174] Example 4

[0175] A computer program product includes a computer program, and when the computer program is executed by a processor, the communication anti-interference method in embodiment 1 is implemented.

[0176] Example 5

[0177] A computer device, which may be a database. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. The processor, the memory and the input / output interface are connected via a system bus, and the communication interface is connected to the system bus via the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store pending transactions. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, a communication anti-interference method in Example 1 is implemented.

[0178] It should be noted that the object information (including but not limited to object device information, object personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in the present invention are all information and data authorized by the object or fully authorized by all parties, and the collection, use and processing of relevant data need to comply with relevant laws, regulations and standards of relevant countries and regions.

[0179] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided by the present invention can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided by the present invention may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited thereto. The processor involved in each embodiment provided by the present invention may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited thereto.

[0180] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0181] The principles and implementation methods of the present invention are described herein using specific examples, and the description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those of ordinary skill in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A communication anti-interference method, characterized in that: The communication anti-interference method is applied to a communication anti-interference device; the anti-interference device is applied to an NPC-I three-level system, and the communication anti-interference device includes: a high-frequency sampling module, a shift register, a data frame parser and a frame header position discriminator, and a plurality of pulse width counting and analysis components; The high-frequency sampling module is connected to the shift register; after the high-frequency sampling module establishes communication with the NPC-I three-level system, the high-frequency clock continuously samples the communication data and inputs the multiple sampling point data into the shift register; The shift register is respectively connected to a plurality of pulse width counting and analysis components; the capacity of the shift register is N×Q; wherein N is the capacity of a pulse width counting and analysis component; and Q is the total number of pulse width counting and analysis components; when the high-frequency sampling module completes sampling at the t-th sampling time, the first element in the shift register sequence corresponding to the t-1-th sampling time is deleted, the element numbers of all elements in the shift register sequence except the first element are reduced by 1, and the sampling data at the t-th sampling time is used as the N×Q-th element to generate the shift register sequence corresponding to the t-th sampling time; The plurality of pulse width counting and analysis components are all connected to the data frame parser; the qth pulse width counting and analysis component is used to obtain the qth bit data from the (q-1)×N+1th element to the q×Nth element in the shift register sequence corresponding to the tth sampling moment, and determine the calculation result of the qth bit data; the calculation result of the qth bit data is the sum of the (q-1)×N+1th element to the q×Nth element in the shift register sequence corresponding to the tth sampling moment; A pulse width counting and analysis component comprises a pulse width counter and a pulse width data analyzer connected in sequence; the pulse width counters in all pulse width counting and analysis components are connected to the shift register; the pulse width data analyzers in all pulse width counting and analysis components are connected to the data frame analyzer; The data frame parser is connected to the frame header position discriminator; the data frame parser is used to generate a data signal waveform corresponding to the t-th sampling time according to the calculation results of Q bits of data; The frame header position identifier is used to determine the initial frame header position according to the data signal waveform corresponding to different sampling moments; The communication anti-interference method comprises: When establishing communication with the NPC-I three-level system, let the sampling time sequence number t = 1; Construct an empty set as the pending initial frame header sequence; Determine whether the data signal waveform corresponding to the t-th sampling moment satisfies the pending initial frame header sequence condition, and obtain a first judgment result; the pending initial frame header sequence condition is that the data signal waveform corresponding to the t-th sampling moment is the same as any preset waveform template in the preset waveform template set, and the data signal waveform corresponding to the t-1-th sampling moment is the same as any preset waveform template in the preset waveform template set, and the preset waveform template corresponding to the t-th sampling moment is the same as the preset waveform template corresponding to the t-1-th sampling moment; If the first judgment result is yes, then t+1-N×Q is added as the last element to the pending initial frame header sequence, the value of the sampling time sequence number t is increased by 1, and the step of "determining whether the data signal waveform corresponding to the t-th sampling time satisfies the pending initial frame header sequence condition to obtain the first judgment result" is returned; If the first judgment result is no, then judging whether the number of elements in the pending initial frame header sequence is greater than a preset continuous value, and obtaining a second judgment result; If the second judgment result is no, the value of the sampling time sequence number t is increased by 1, and the process returns to the step of "constructing an empty set as a pending initial frame header sequence"; If the second judgment result is yes, determining the first frame header sampling time according to the pending initial frame header sequence; Let frame number i = 1; When the sampling data at the i-th frame header sampling moment is in the first element in the shift register sequence, the corresponding shift register sequence is the i-th frame data; Determine the sampling time corresponding to the N×Qth element of the i-th frame data as the theoretical frame end time of the i-th frame; Determine a sequence formed by the easing factor sampling time before the theoretical frame end time of the i-th frame and the theoretical frame end time of the i-th frame, and the easing factor sampling time after the theoretical frame end time of the i-th frame, as the actual frame end sequence to be determined; According to the pending actual frame end sequence, determine the actual frame end time of the i-th frame; Determine that the data signal waveform corresponding to the interference-free time sequence of the i-th frame is the interference-free waveform signal of the i-th frame; the interference-free time sequence of the i-th frame includes the sampling time of the i-th frame head to the actual frame end time of the i-th frame; the interference-free waveform signal of the i-th frame is output by the data frame parser; The actual end time of the i-th frame is used as the i+1-th frame head sampling time, the value of the frame number i is increased by 1, and the step of "obtaining the sampling data at the i-th frame head sampling time and the corresponding shift register sequence when the first element in the shift register sequence is the i-th frame data" is returned.

2. A communication anti-interference method according to claim 1, characterized in that: Determining the first frame header sampling time according to the pending initial frame header sequence includes: Determine whether the number of elements of the pending initial frame header sequence is an odd number, and obtain a third determination result; If the third judgment result is yes, then the (B+1) / 2th element in the pending initial frame header sequence is determined as the first frame header sampling time; B is the total number of elements in the pending initial frame header sequence; If the third judgment result is no, then the B / 2th element in the pending initial frame header sequence is determined to be the first frame header sampling time.

3. A communication anti-interference method according to claim 1, characterized in that: According to the pending actual frame end sequence, determining the actual frame end time of the i-th frame includes: Let the judgment number v=1; Construct the empty set as the decision sequence; When the sampling data at the vth sampling time in the pending actual frame tail sequence is in the N×Qth element in the shift register sequence, the corresponding data signal waveform is the vth pending frame signal waveform; Determine whether the vth pending frame signal waveform satisfies the determination sequence condition, and obtain a fourth determination result; the determination sequence condition is that the vth pending frame signal waveform is the same as any preset waveform template in the preset waveform template set, the v-1th pending frame signal waveform is the same as any preset waveform template in the preset waveform template set, and the preset waveform template corresponding to the vth pending frame signal waveform is the same as the preset waveform template corresponding to the v-1th pending frame signal waveform; If the fourth judgment result is yes, the vth sampling moment in the pending actual frame end sequence is added as the last element to the determination sequence, the value of the determination sequence number v is increased by 1, and the step of "obtaining the sampling data at the vth sampling moment in the pending actual frame end sequence in the N×Qth element in the shift register sequence, and the corresponding data signal waveform is the vth pending frame signal waveform" is returned; If the fourth judgment result is no, then judging whether the number of elements in the determination sequence is greater than a preset continuous value, and obtaining a fifth judgment result; If the fifth judgment result is yes, determining the actual frame end time of the i-th frame according to the judgment sequence; If the fifth judgment result is no, then judging whether the judgment sequence number v reaches the judgment sequence number threshold value is obtained to obtain a sixth judgment result; the judgment sequence number threshold value is equal to the difference between the total number of elements in the actual frame end sequence to be determined and the preset continuous value; If the sixth judgment result is no, the value of the sampling time sequence number v is increased by 1, and the process returns to step "constructing an empty set as a judgment sequence"; If the sixth judgment result is yes, then the theoretical frame end time of the i-th frame is determined to be the actual frame end time of the i-th frame.

4. A communication anti-interference method according to claim 3, characterized in that: Determine the actual frame end time of the i-th frame according to the determination sequence, including: Determine whether the number of elements of the determination sequence is an odd number, and obtain a seventh determination result; If the seventh judgment result is yes, then the (A+1) / 2th element in the judgment sequence is determined to be the actual end time of the i-th frame; A is the total number of elements in the judgment sequence; If the seventh judgment result is no, then the A / 2th element in the judgment sequence is determined to be the actual frame end time of the i-th frame.

5. A communication anti-interference method according to claim 4, characterized in that: According to the calculation results of Q bits of data, the data signal waveform corresponding to the t-th sampling time is generated, including: Get the threshold factor; Determine the first determination amount as half of the sum of the capacity N of the pulse width counting and analysis component and the threshold factor; Determine half of the difference between the capacity N of the pulse width counting and analyzing component and the threshold factor as the second determination amount; Set the pulse width counting and analysis component serial number q=1; When the calculation result of the qth bit data is greater than the first determination value, determining that the qth analysis signal is a high level; When the calculation result of the qth bit data is less than the second determination value, determining that the qth analysis signal is a low level; Increase the value of the pulse width counting analysis component serial number q by 1, and return to the step "when the calculation result of the qth bit data is greater than the first judgment value, determine that the qth analysis signal is a high level" until the value of the pulse width counting analysis component serial number q reaches Q, arrange multiple analysis signals in ascending order according to the pulse width counting analysis component serial number q and connect them to generate a data signal waveform corresponding to the tth sampling moment.

6. A communication anti-interference method according to claim 1, characterized in that: The method further comprises: When the communication is interrupted, return to step "When establishing communication with the NPC-I three-level system, set the sampling time sequence number t=1".

7. A computer device comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement a communication anti-interference method as described in any one of claims 1 to 6.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, a communication anti-interference method according to any one of claims 1 to 6 is implemented.

9. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, a communication anti-interference method according to any one of claims 1 to 6 is implemented.

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