Memory management method and storage device

Abstract

The present invention provides a memory management method and a storage device. The method includes: configuring a first-type physical unit, a second-type physical unit, and a third-type physical unit in a memory module; monitoring a first usage state of the first-type physical unit; and executing a first data management strategy if the first usage state meets a first condition. The first data management strategy includes: storing first write data and second write data in the first physical unit, wherein the first write data belongs to the first type of data and the second write data belongs to the second type of data; triggering a first-stage data consolidation to identify first target data from a first source unit, and moving or copying the first target data to the first target unit, wherein the first target data belongs to the first type of data. This improves the operating efficiency of the storage device.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a memory management method and a storage device. Background Art

[0002] With the rapid development of storage technology, solid-state drives (SSDs) containing flash memory are becoming increasingly popular due to their excellent performance. These devices primarily use NAND flash as the storage medium and typically contain several flash particles (also known as memory cells). Common flash particle types include single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), and quad-level cell (QLC).

[0003] However, as the market evolves, many manufacturers are choosing to co-package triple-level cell (TLC) and quad-level cell (QLC) memory cells to reduce costs and increase capacity. Therefore, when a storage device incorporates both types of flash memory, designing a reasonable data management strategy to improve storage device performance is a pressing issue. Summary of the Invention

[0004] The present invention provides a memory management method and a storage device, which can effectively improve the technical problem of difficulty in properly operating and managing the storage device when there are at least two types of physical units in the storage device, and can effectively improve the working efficiency of the storage device when using at least two types of physical units.

[0005] An embodiment of the present invention provides a memory management method for a storage device. The storage device includes a memory module. The memory management method includes: configuring a first-type entity unit, a second-type entity unit, and a third-type entity unit in the memory module, wherein the first storage capacity of each first-type entity unit is less than the second storage capacity of each second-type entity unit, and the second storage capacity is less than the third storage capacity of each third-type entity unit; monitoring a first usage status of the first-type entity unit; and if the first usage status meets a first condition, executing a first data management strategy, wherein the first data management strategy includes: storing first write data and second write data in the first entity unit, wherein the first write data belongs to the first type of data, the second write data belongs to the second type of data, and the first entity unit belongs to the first type of entity unit; triggering a first-stage data consolidation; and in the first-stage data consolidation, identifying first target data from a first source unit and moving or copying the first target data to a first target unit, wherein the first source unit belongs to the first type of entity unit, the first target data belongs to the first type of data, and the first target unit belongs to the third type of entity unit.

[0006] An embodiment of the present invention further provides a storage device comprising a connection interface, a memory module, and a memory controller. The connection interface is configured to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory controller is configured to: configure first-type physical units, second-type physical units, and third-type physical units in the memory module, wherein the first storage capacity of each first-type physical unit is less than the second storage capacity of each second-type physical unit, and the second storage capacity is less than the third storage capacity of each third-type physical unit; monitor a first usage status of the first-type physical unit; and if the first usage status meets a first condition, execute a first data management policy, wherein the first data management policy comprises: storing first write data and second write data in the first physical unit, wherein the first write data belongs to the first type of data, the second write data belongs to the second type of data, and the first physical unit belongs to the first type of physical unit; triggering a first-stage data consolidation; and in the first-stage data consolidation, identifying first target data from a first source unit and moving or copying the first target data to a first target unit, wherein the first source unit belongs to the first type of physical unit, the first target data belongs to the first type of data, and the first target unit belongs to the third type of physical unit.

[0007] Based on the above, by configuring a memory module with multiple types of physical units and implementing an appropriate data management strategy, the technical issue of difficulty in properly operating and managing the storage device when at least two types of physical units are present in the storage device can be effectively addressed. Furthermore, the operating efficiency of the storage device using at least two types of physical units can be effectively improved and / or the service life of the memory module can be extended. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0009] Figure 2 is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0010] Figure 3 is a schematic diagram of a management memory module according to an embodiment of the present invention;

[0011] Figure 4 is a schematic diagram of managing a memory module based on a first data management policy according to an embodiment of the present invention;

[0012] Figure 5 is a schematic diagram of managing a memory module based on a second data management policy according to an embodiment of the present invention;

[0013] Figure 6 is a schematic diagram of managing a memory module based on a third data management strategy according to an embodiment of the present invention;

[0014] Figure 7 is a flowchart of a memory management method according to an embodiment of the present invention;

[0015] Figure 8 is a flowchart of a memory management method according to an embodiment of the present invention;

[0016] Figure 9 is a flowchart of a memory management method according to an embodiment of the present invention;

[0017] Figure 10 FIG. 4 is a flowchart of a memory management method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0018] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0019] Figure 1Schematic diagram of a data storage system according to an embodiment of the present invention. Figure 1 The data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, a tablet computer, a laptop computer, a desktop computer, an industrial computer, a game console, a server, or a computer system installed in a specific carrier (such as a vehicle, aircraft, or ship), and the type of host system 11 is not limited to this. In addition, the storage device 12 can include a solid-state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0020] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 may support an embedded Multi-Media Card (eMMC), Universal Flash Storage (UFS), Peripheral Component Interconnect Express (PCI Express), Non-Volatile Memory Express (NVM express), Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), or other types of connection interface standards. Therefore, the storage device 12 can communicate with the host system 11 (e.g., exchange signals, instructions, and / or data) via the connection interface 121.

[0021] The memory module 122 is used to store data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of a voltage (also known as a threshold voltage). For example, the memory module 122 may include a single-level cell (SLC) NAND flash memory module, a multi-level cell (MLC) NAND flash memory module, a triple-level cell (TLC) NAND flash memory module, a quad-level cell (QLC) NAND flash memory module, and / or other memory modules having the same or similar characteristics.

[0022] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be considered the control core of the memory device 12 and is used to control the memory device 12. For example, the memory controller 123 can be used to control or manage all or part of the operation of the memory device 12. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, a digital signal processor (DSP), a programmable controller, an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or other similar devices or a combination of these devices. In one embodiment, the memory controller 123 may include a flash memory controller.

[0023] The memory controller 123 can send a command sequence to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write command sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read command sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase command sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can send other types of command sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, and the present invention is not limited thereto. The memory module 122 can receive the command sequence from the memory controller 123 and access the memory cells within the memory module 122 according to the command sequence.

[0024] Figure 2 FIG is a schematic diagram of a memory controller according to an embodiment of the present invention. Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0025] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 can be used to control or manage all or part of the operation of the memory controller 123. For example, the memory control circuit 23 can communicate with the host system 11 via the host interface 21 and access the memory module 122 via the memory interface 22. For example, the memory control circuit 23 may include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is equivalent to the description of the memory controller 123.

[0026] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122. In one embodiment, the memory controller 123 may also include various other types of circuit modules (such as error detection circuits and power management circuits), which are not limited by the present invention.

[0027] Figure 3 FIG is a schematic diagram of a management memory module according to an embodiment of the present invention. Figures 1 to 3 The memory module 122 includes a plurality of physical units 301 ( 1 ) to 301 (F). Each physical unit includes a plurality of storage cells and is used for non-volatile data storage.

[0028] In one embodiment, a physical unit may include one or more physical erase units. A physical erase unit may include multiple physical programming units. A physical programming unit may include multiple physical sectors. For example, the data capacity of a physical sector may be 512 bytes (Bytes, B), and a physical programming unit may include 8 physical sectors. However, the data capacity of a physical sector and / or the total number of physical sectors included in a physical programming unit can be adjusted according to practical needs, and the present invention is not limited thereto. In one embodiment, a physical programming unit can be regarded as a physical page. For example, the storage capacity of a physical programming unit may be 4 kilobytes (4KB), and the present invention is not limited thereto.

[0029] In one embodiment, a physical programming unit is the smallest unit to which data is written synchronously in the memory module 122. For example, when a programming operation (also referred to as a write operation) is performed on a physical programming unit to write data to the physical programming unit, multiple memory cells in the physical programming unit may be programmed synchronously to store corresponding data. For example, when programming a physical programming unit, a write voltage may be applied to the physical programming unit to change the threshold voltage of at least some of the memory cells in the physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in the memory cell.

[0030] In one embodiment, multiple physical programming cells in a physical erase unit can be erased simultaneously. For example, when performing an erase operation on a physical erase unit, an erase voltage can be applied to multiple physical programming cells in the physical erase unit to change the threshold voltages of at least some of the memory cells in the physical programming cells. By performing an erase operation on a physical erase unit, data stored in the physical erase unit can be cleared.

[0031] In one embodiment, the memory control circuit 23 can logically associate the physical units 301(1) to 301(A), 301(A+1) to 301(B), and 301(B+1) to 301(C) with a data area (also referred to as a first type of data area or a cache area) 31, a data area (also referred to as a second type of data area) 32, and a data area (also referred to as a third type of data area) 33, respectively. The physical units 301(1) to 301(C) in the data areas 31, 32, and 33 all store data (also referred to as user data) from the host system 11. For example, any physical unit in the data areas 31, 32, and 33 can store valid data and / or invalid data.

[0032] In one embodiment, the memory control circuit 23 may logically associate the physical cells 301(C+1)-301(D), 301(D+1)-301(E), and 301(E+1)-301(F) with the spare area 34. For example, the physical cells 301(C+1)-301(D), 301(D+1)-301(E), and 301(E+1)-301(F) in the spare area 34 do not store data (e.g., valid data).

[0033] In one embodiment, if a physical unit does not store valid data, the physical unit may be associated with the idle area 34. Furthermore, the physical units in the idle area 34 may be erased to clear the data in the physical units. In one embodiment, the physical units in the idle area 34 are also referred to as idle physical units. In one embodiment, the idle area 34 is also referred to as a free pool.

[0034] In one embodiment, the memory control circuit 23 may configure the physical units 301(C+1)-301(D) as first-type physical units (also called cache physical units). That is, each of the physical units 301(C+1)-301(D) belongs to the first-type physical unit.

[0035] In one embodiment, the memory control circuit 23 may configure the physical units 301 (D+1) to 301 (E) as second-type physical units. That is, each of the physical units 301 (D+1) to 301 (E) belongs to the second-type physical unit.

[0036] In one embodiment, the memory control circuit 23 may configure the physical units 301(E+1)-301(F) as third-type physical units. That is, each of the physical units 301(E+1)-301(F) belongs to the third-type physical unit.

[0037] In one embodiment, the storage capacity of each first-type entity unit (also referred to as the first storage capacity) is smaller than the storage capacity of each second-type entity unit (also referred to as the second storage capacity). Furthermore, the storage capacity of each second-type entity unit (i.e., the second storage capacity) is smaller than the storage capacity of each third-type entity unit (also referred to as the third storage capacity).

[0038] In one embodiment, the access performance of each first-type physical unit may be higher than the access performance of each second-type physical unit, and the access performance of each second-type physical unit may be higher than the access performance of each third-type physical unit. For example, the speed at which the memory control circuit 23 accesses the first-type physical unit (e.g., the speed at which data is read from the first-type physical unit and / or the speed at which data is written to the first-type physical unit) may be higher than the speed at which the memory control circuit 23 accesses the second-type physical unit (e.g., the speed at which data is read from the second-type physical unit and / or the speed at which data is written to the second-type physical unit). Furthermore, the speed at which the memory control circuit 23 accesses the second-type physical unit (e.g., the speed at which data is read from the second-type physical unit and / or the speed at which data is written to the second-type physical unit) may be higher than the speed at which the memory control circuit 23 accesses the third-type physical unit (e.g., the speed at which data is read from the third-type physical unit and / or the speed at which data is written to the third-type physical unit).

[0039] In one embodiment, the memory control circuit 23 may program the first type of physical unit based on a certain programming mode (also referred to as a first programming mode) to store data in the first type of physical unit. In one embodiment, the memory control circuit 23 may program the second type of physical unit based on another programming mode (also referred to as a second programming mode) to store data in the second type of physical unit. In one embodiment, the memory control circuit 23 may program the third type of physical unit based on yet another programming mode (also referred to as a third programming mode) to store data in the third type of physical unit. The first programming mode, the second programming mode, and the third programming mode are different.

[0040] In one embodiment, the first programming mode may include an SLC mode or a pseudo SLC (pSLC) mode. In one embodiment, the second programming mode may include an MLC or TLC mode. In one embodiment, the third programming mode may include a QLC mode. It should be noted that the first, second, and third programming modes can be set or adjusted according to practical needs and are not limited by the present invention.

[0041] In one embodiment, a storage unit in the first type of physical unit can store k bits. In one embodiment, a storage unit in the second type of physical unit can store p bits. In one embodiment, a storage unit in the third type of physical unit can store r bits. k is less than p, and p is less than r. For example, assuming k is "1," p can be "2" or "3," and r can be "4." However, k, p, and r can be adjusted according to practical needs and are not limited by the present invention.

[0042] In one embodiment, when data is to be stored, the memory control circuit 23 may select one or more physical cells from the idle area 34 and instruct the memory module 122 to store the data in the selected physical cells. It should be noted that if the selected physical cell belongs to the first type of physical cell (e.g., one of the physical cells 301(C+1) to 301(D)), then after the data is stored in the physical cell, the physical cell may be associated with the data area 31 and become one of the physical cells 301(1) to 301(A). Alternatively, if the selected physical cell belongs to the second type of physical cell (e.g., one of the physical cells 301(D+1) to 301(E)), then after the data is stored in the physical cell, the physical cell may be associated with the data area 32 and become one of the physical cells 301(A+1) to 301(B). Alternatively, if the selected entity unit belongs to the third type of entity unit (for example, one of the entity units 301(E+1) to 301(F)), then after storing data in this entity unit, this entity unit can be associated with the data area 33 and become one of the entity units 301(B+1) to 301(C).

[0043] In other words, the first type of physical units (i.e., physical units 301(1) to 301(A) and 301(C+1) to 301(D)) can be used alternately between the data area 31 and the idle area 34. The second type of physical units (i.e., physical units 301(A+1) to 301(B) and 301(D+1) to 301(E)) can be used alternately between the data area 32 and the idle area 34. Furthermore, the third type of physical units (i.e., physical units 301(B+1) to 301(C) and 301(E+1) to 301(F)) can be used alternately between the data area 33 and the idle area 34.

[0044] In one embodiment, the memory control circuit 23 may configure a plurality of logical units 302(1)-302(G) to map the physical units in the data areas 31, 32, and 33 (i.e., physical units 301(1)-301(A), 301(A+1)-301(B), and 301(B+1)-301(C)). For example, a logical unit may correspond to a logical block address (LBA) or other logical management unit. A logical unit may be mapped to one or more physical units.

[0045] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 may determine that the data currently stored in the physical unit includes valid data. Conversely, if a physical unit is currently not mapped by any logical unit, the memory control circuit 23 may determine that the physical unit does not currently store any valid data.

[0046] In one embodiment, the memory control circuit 23 may record the mapping relationship between the logical units and the physical units in a logical-to-physical mapping table. In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data read, write, or erase based on the information in the logical-to-physical mapping table.

[0047] In one embodiment, the memory control circuit 23 may receive an instruction from the host system 11. For example, the instruction may include a write instruction. This write instruction may instruct the storage of specific data. In one embodiment, the memory control circuit 23 may perform a write operation (also referred to as a host write operation) based on this instruction to store the data from the host system 11. For example, in a host write operation, the memory control circuit 23 may send a write instruction sequence to the memory module 122 to instruct the memory module 122 to store the specific data in at least one physical unit of the memory module 122.

[0048] In one embodiment, during a host write operation, the memory control circuit 23 may preferentially instruct the memory module 122 to store data from the host system 11 in the first-type physical units. This improves the data writing efficiency of the host write operation. However, if the first-type physical units have been used up (for example, physical units 301(C+1)-301(D) are all associated with the data area 31) or are about to be used up, the memory control circuit 23 may instead store the data from the host system 11 in the second-type physical units or the third-type physical units. Although the data writing efficiency of the host write operation is reduced, the host write operation can still be performed normally.

[0049] In one embodiment, the memory control circuit 23 may monitor the usage status of the first-type physical units (also referred to as the first usage status). For example, the first usage status may reflect the total number of used first-type physical units and / or the total number of unused first-type physical units. In one embodiment, the memory control circuit 23 may determine whether the first usage status meets a specific condition (also referred to as the first condition).

[0050] In one embodiment, the first usage state meeting the first condition includes the remaining available number of the first-type physical units being no less than (e.g., greater than or equal to) a threshold value (also referred to as a first threshold value). For example, the remaining available number of the first-type physical units may reflect the total number of unused first-type physical units. In one embodiment, the memory control circuit 23 may determine the remaining available number of the first-type physical units based on the total number of physical units 301(C+1)-301(D) in the current idle area 34. For example, the remaining available number of the first-type physical units may be the same as or positively correlated with the total number of physical units 301(C+1)-301(D) in the current idle area 34.

[0051] In one embodiment, the memory control circuit 23 may compare the remaining available number of the first type of physical units with a first threshold. If the remaining available number of the first type of physical units is not less than (e.g., greater than or equal to) the first threshold, the memory control circuit 23 may determine that the first usage status meets the first condition (indicating that a considerable number of the first type of physical units remain unused). However, if the remaining available number of the first type of physical units is less than the first threshold, the memory control circuit 23 may determine that the first usage status does not meet the first condition (i.e., the first type of physical units have been used up or are about to be used up).

[0052] In one embodiment, if the first usage state meets the first condition, the memory control circuit 23 may execute a specific data management policy (also referred to as the first data management policy). That is, if the first usage state meets the first condition, the memory control circuit 23 may manage the memory module 122 based on the first data management policy.

[0053] In one embodiment, based on a first data management policy, the memory control circuit 23 may store multiple data (including first write data and second write data) in at least one physical unit (also referred to as a first physical unit) in the memory module 122. For example, both the first write data and the second write data are obtained from the host system 11, and the first physical unit belongs to a first type of physical unit. It should be noted that the data type of the first write data is different from the data type of the second write data. For example, the first write data belongs to the first type of data, while the second write data belongs to the second type of data.

[0054] In one embodiment, the memory control circuit 23 may determine the type of data based on the frequency with which the host system 11 or the memory control circuit 23 accesses the data. For example, if the host system 11 or the memory control circuit 23 accesses certain data (e.g., first write data) relatively infrequently, the memory control circuit 23 may classify the data as first-category data. Conversely, if the host system 11 or the memory control circuit 23 accesses certain data (e.g., second write data) relatively frequently, the memory control circuit 23 may classify the data as second-category data. That is, in one embodiment, the access frequency of the first-category data may be lower than the access frequency of the second-category data. Furthermore, accessing certain data may include reading the data and / or modifying the data.

[0055] In one embodiment, the memory control circuit 23 may determine whether the frequency of access to a particular piece of data by the host system 11 or the memory control circuit 23 exceeds a predetermined frequency. If the frequency of access to the data by the host system 11 or the memory control circuit 23 does not exceed the predetermined frequency, the memory control circuit 23 may classify the data as first-category data. However, if the frequency of access to the data by the host system 11 or the memory control circuit 23 exceeds the predetermined frequency, the memory control circuit 23 may classify the data as second-category data.

[0056] In one embodiment, the memory control circuit 23 may also determine the type of data based on other factors. For example, the memory control circuit 23 may determine whether data belongs to the first or second category based on the data size, importance, purpose, logical unit to which the data belongs, and / or physical unit used to store the data. The details of these operations may be determined based on practical needs and are not limited by the present invention.

[0057] In other words, when the first usage state meets the first condition, the memory control circuit 23 may preferentially use the first type of physical units to store data, and the type of data stored is not limited to the first type of data or the second type of data. Thus, when there are a relatively large number of available first type physical units, the host write efficiency can be effectively improved.

[0058] In one embodiment, based on the first data management policy, the memory control circuit 23 may trigger a data consolidation operation (also referred to as first-stage data consolidation). For example, the memory control circuit 23 may trigger the first-stage data consolidation based on a predetermined rule (e.g., whether the number of used first-type physical units has reached a quantity condition, etc.), although the present invention is not limited thereto. In one embodiment, the first-stage data consolidation includes a garbage collection (GC) operation performed based on the first data management policy.

[0059] In one embodiment, during the first stage of data consolidation, the memory control circuit 23 may identify specific data (also referred to as first target data) from at least one physical unit (also referred to as a first source unit). The first source unit belongs to a first type of physical unit. The first target data includes valid data stored in the first source unit, and the first target data belongs to a first type of data. The memory control circuit 23 may then move or copy the first target data to at least one physical unit (also referred to as a first target unit). The first target unit belongs to a third type of physical unit.

[0060] In one embodiment, if all valid data stored in the first source unit has been moved or copied to the first target unit, the memory control circuit 23 may associate the first source unit with the idle area 34. In one embodiment, the operation of associating the first source unit with the idle area 34 is equivalent to releasing the first source unit as a new idle physical unit.

[0061] In one embodiment, during the first phase of data consolidation, the data (i.e., first target data) copied or moved from the used first-type physical units (i.e., first source units) to the third-type physical units for centralized storage may be limited to first-type data (e.g., data with relatively low access frequency). Alternatively, in one embodiment, during the first phase of data consolidation, second-type data (e.g., data with relatively high access frequency) in the used first-type physical units will not (or may even be prohibited or excluded) be copied or moved to the third-type physical units as the first target data.

[0062] In one embodiment, by performing data consolidation (only) on the first-type data in the first-type physical units, when the first usage state meets the first condition (indicating that a considerable number of the first-type physical units remain unused), newly available first-type physical units can be released in a manner that minimizes the impact on the performance of host write operations, thereby maintaining smooth execution of host write operations and reducing unnecessary write amplification (WA). Furthermore, by storing (only) the first-type data (e.g., data with relatively low access frequency) in the third-type physical units, the subsequent operational performance of the memory module 112 can be optimized and / or the service life of the memory module 112 can be extended.

[0063] Figure 4 FIG is a schematic diagram of managing a memory module based on a first data management strategy according to an embodiment of the present invention. Figure 4 , assume that storage areas 41, 42, and 43 represent the usage status of first-category entity units, second-category entity units, and third-category entity units, respectively. For example, in storage area 41, the area marked with slashes is used to represent first-category entity units that have been used, while the blank area is used to represent first-category entity units that have not been used. Similarly, in storage area 42, the area marked with slashes is used to represent second-category entity units that have been used, while the blank area is used to represent second-category entity units that have not been used. In addition, in storage area 43, the area marked with slashes is used to represent third-category entity units that have been used, while the blank area is used to represent third-category entity units that have not been used.

[0064] In one embodiment, when the first usage state meets the first condition, the memory control circuit 23 may obtain data 401 (i.e., first write data) and 402 (i.e., second write data) from the host system 11. Data 401 belongs to the first category of data. Data 402 belongs to the second category of data. For example, data 401 may include data with a relatively low access frequency (also known as cold data), while data 402 may include data with a relatively high access frequency (also known as hot data). In the following embodiments, for ease of explanation, the first category of data may be labeled "C" in the figures, and the second category of data may be labeled "H" in the figures.

[0065] In one embodiment, based on the first data management policy, the memory control circuit 23 may store data 401 and 402 in the storage area 41. In one embodiment, based on the first data management policy, the memory control circuit 23 may restrict data 402 (i.e., the second type of data) from being stored in the storage area 42 (i.e., the second type of physical unit) and / or the storage area 43 (i.e., the third type of physical unit), thereby improving the performance of the storage device 12 and extending the service life of the memory module 112.

[0066] In one embodiment, based on the first data management policy, if the first-stage data consolidation is triggered, during the first-stage data consolidation, the memory control circuit 23 may identify data 411 (i.e., first target data) from the storage area 41. If the total amount of data 411 reaches a predetermined value, the memory control circuit 23 may copy or move the data 411 to the storage area 43. For example, the predetermined value may be equal to the storage capacity of a third-type physical unit. However, if the total amount of data 411 does not reach the predetermined value, the memory control circuit 23 may temporarily refrain from copying or moving the data 411 to the storage area 43.

[0067] In one embodiment, by performing the first phase of data consolidation, at least one first type physical unit in the storage area 41 may be gradually released. For example, the released first type physical unit may be associated with Figure 3 The idle area becomes one of the physical units 301(C+1)~301(D).

[0068] In one embodiment, the memory control circuit 23 may further monitor the usage status of the second-type physical units (also referred to as a second usage status). For example, the second usage status may reflect the total number of used second-type physical units and / or the total number of unused second-type physical units. In one embodiment, the memory control circuit 23 may determine whether the second usage status meets a specific condition (also referred to as a second condition).

[0069] In one embodiment, the second usage state meeting the second condition includes the remaining available number of the second type of physical units being no less than (e.g., greater than or equal to) a threshold value (also referred to as a second threshold value). For example, the remaining available number of the second type of physical units may reflect the total number of unused second type of physical units. For example, the memory control circuit 23 may determine the remaining available number of the second type of physical units based on the total number of physical units 301(D+1)-301(E) in the current idle area 34. For example, the remaining available number of the second type of physical units may be the same as or positively correlated with the total number of physical units 301(D+1)-301(E) in the current idle area 34.

[0070] In one embodiment, the memory control circuit 23 may compare the remaining available number of the second-type physical units with a second threshold. If the remaining available number of the second-type physical units is not less than (e.g., greater than or equal to) the second threshold, the memory control circuit 23 may determine that the second usage status meets the second condition (indicating that a considerable number of the second-type physical units remain unused). However, if the remaining available number of the second-type physical units is less than the second threshold, the memory control circuit 23 may determine that the second usage status does not meet the second condition (i.e., the second-type physical units have been exhausted or are about to be exhausted).

[0071] In one embodiment, if the first usage state does not meet the first condition and the second usage state meets the second condition, the memory control circuit 23 may implement a specific data management policy (also referred to as a second data management policy). That is, if the first usage state does not meet the first condition and the second usage state meets the second condition, the memory control circuit 23 may manage the memory module 122 based on the second data management policy.

[0072] In one embodiment, based on the second data management policy, the memory control circuit 23 may directly (i.e., without passing through the first-type physical unit) store data from the host system 11 into unused second-type physical units or third-type physical units. Alternatively, if there are newly released unused first-type physical units, the memory control circuit 23 may also store data from the host system 11 into the first-type physical units. The present invention is not limited to this.

[0073] In one embodiment, based on the second data management policy, the memory control circuit 23 may trigger a data consolidation operation (also referred to as second-stage data consolidation). For example, the memory control circuit 23 may trigger the second-stage data consolidation based on a predetermined rule (e.g., whether the number of used first-type physical units and / or the number of used second-type physical units has reached a quantity condition, etc.), although the present invention is not limited thereto. In one embodiment, the second-stage data consolidation includes a garbage collection (GC) operation performed based on the second data management policy.

[0074] In one embodiment, during the second stage of data consolidation, the memory control circuit 23 may identify specific data (also referred to as second target data) from at least one physical unit (also referred to as a second source unit) belonging to the first type of physical unit.

[0075] The second target data includes valid data stored in the second source unit, and the second target data belongs to the first type of data.

[0076] In one embodiment, the memory control circuit 23 may determine whether the total amount of the second target data reaches a predetermined value. For example, the predetermined value is equal to the storage capacity of a third-type physical unit. If the total amount of the second target data reaches the predetermined value, the memory control circuit 23 may move or copy the second target data to a specific physical unit (also referred to as a second target unit). The second target unit belongs to the third-type physical unit.

[0077] However, if the total amount of the second target data does not reach the predetermined value, the memory control circuit 23 may identify another data (also referred to as third target data) from the second source unit. The third target data includes valid data stored in the second source unit and belongs to the second type of data. The memory control circuit 23 may then move or copy the second target data together with the third target data to a specific physical unit (also referred to as the third target unit). Note that the third target unit belongs to the second type of physical unit.

[0078] In one embodiment, if all valid data stored in the second source unit has been moved or copied to the second target unit or the third target unit, the memory control circuit 23 may associate the second source unit with the idle area 34. In one embodiment, the operation of associating the second source unit with the idle area 34 is equivalent to releasing the second source unit as a new idle physical unit.

[0079] In one embodiment, during the second-stage data consolidation, the memory control circuit 23 may further identify specific data (also referred to as fourth target data) from at least one physical unit (also referred to as a third source unit). The third source unit belongs to the second type of physical unit. The fourth target data includes valid data stored in the third source unit, and the fourth target data belongs to the first type of data. If the total amount of the fourth target data reaches the predetermined value, the memory control circuit 23 may move or copy the fourth target data to the at least one physical unit (also referred to as the fourth target unit). However, if the total amount of the fourth target data does not reach the predetermined value, the memory control circuit 23 may not move or copy the fourth target data to the fourth target unit. The fourth target unit belongs to the third type of physical unit.

[0080] In one embodiment, if all valid data stored in the third source unit has been moved or copied to the fourth target unit, the memory control circuit 23 may associate the third source unit with the idle area 34. In one embodiment, the operation of associating the third source unit with the idle area 34 is equivalent to releasing the third source unit as a new idle physical unit.

[0081] In one embodiment, compared to the first-stage data consolidation, by opening up the second-type data in the first-type physical unit for data consolidation in the second-stage data consolidation, the release efficiency of the first-type physical unit can be improved when the first usage state does not meet the first condition (i.e., the first-type physical unit has been used up or is about to be used up), thereby improving the performance of the storage device 12.

[0082] Furthermore, by storing the first-type data along with the second-type data in the second-type physical units during the second-stage data consolidation, the first-type physical units can be released more quickly when the second usage state meets the second condition (indicating that a considerable number of the second-type physical units remain unused). This also helps optimize the subsequent operational performance of the memory module 112 and / or extend the service life of the memory module 112.

[0083] Figure 5 FIG is a schematic diagram of managing a memory module based on a second data management strategy according to an embodiment of the present invention. Figure 5 In one embodiment, when the first usage state does not meet the first condition and the second usage state meets the second condition, the memory control circuit 23 can obtain data 501 (i.e., the first write data) and 502 (i.e., the second write data) from the host system 11.

[0084] In one embodiment, based on the second data management policy, the memory control circuit 23 may store data 501 and 502 in the storage area 42. Alternatively, in one embodiment, based on the second data management policy, the memory control circuit 23 may store data 501 in the storage area 43 and data 502 in the storage area 42. In one embodiment, based on the second data management policy, the memory control circuit 23 may restrict data 502 (i.e., the second type of data) from being stored in the storage area 43 (i.e., the third type of physical unit), thereby improving the performance of the storage device 12 and extending the service life of the memory module 112.

[0085] In one embodiment, based on the second data management policy, if the second-stage data consolidation is triggered, during the second-stage data consolidation, the memory control circuit 23 may identify data 511 (i.e., second target data) from the storage area 41. If the total amount of data 511 reaches a predetermined value, the memory control circuit 23 may copy or move the data 511 to the storage area 43.

[0086] In one embodiment, during the second-stage data consolidation, the memory control circuit 23 may identify data 512 (i.e., second target data) from the memory area 41. If the total amount of data 512 does not reach a predetermined value, the memory control circuit 23 may further identify data 513 (i.e., third target data) from the memory area 41. The memory control circuit 23 may then copy or move the data 512 and the data 513 together to the memory area 43. For example, the data 512 and the data 513 may be stored in the same third-type physical unit in the memory area 43.

[0087] In one embodiment, during the second-stage data consolidation, the memory control circuit 23 may further identify data 514 (i.e., fourth target data) from the storage area 42. If the total amount of data 514 reaches a predetermined value, the memory control circuit 23 may copy or move the data 514 to the storage area 43. However, if the total amount of data 514 does not reach the predetermined value, the memory control circuit 23 may temporarily refrain from copying or moving the data 514 to the storage area 43.

[0088] In one embodiment, compared to the first-stage data consolidation, at least one first-type physical unit in the storage area 41 can be released more quickly by performing the second-stage data consolidation. Furthermore, at least one second-type physical unit in the storage area 42 can also be gradually released by performing the second-stage data consolidation.

[0089] In one embodiment, if the first usage state does not meet the first condition and the second usage state does not meet the second condition, the memory control circuit 23 may implement a specific data management policy (also referred to as a third data management policy). That is, if the first usage state does not meet the first condition and the second usage state does not meet the second condition, the memory control circuit 23 may manage the memory module 122 based on the third data management policy.

[0090] In one embodiment, based on the third data management policy, the memory control circuit 23 may directly (i.e., without passing through the first-type physical unit) store data from the host system 11 into unused second-type physical units or third-type physical units. Alternatively, if there are newly released unused first-type physical units, the memory control circuit 23 may also store data from the host system 11 into the first-type physical units. The present invention is not limited to this.

[0091] In one embodiment, based on the third data management policy, the memory control circuit 23 may trigger a data consolidation operation (also referred to as third-stage data consolidation). For example, the memory control circuit 23 may trigger the third-stage data consolidation based on a predetermined rule (e.g., whether the number of used first-type physical units and / or the number of used second-type physical units has reached a quantity condition, etc.), although the present invention is not limited thereto. In one embodiment, the third-stage data consolidation includes a garbage collection (GC) operation performed based on the third data management policy.

[0092] In one embodiment, compared to the second-stage data consolidation, in the third-stage data consolidation, the memory control circuit 23 may further evaluate the execution performance of the data consolidation operation performed (i.e., the third-stage data consolidation). The memory control circuit 23 may determine at least one physical unit (also referred to as a fourth source unit) based on the execution performance. For example, the memory control circuit 23 may determine whether the type of the fourth source unit is a first-type physical unit or a second-type physical unit based on the execution performance. The memory control circuit 23 may then move or copy specific data (also referred to as fifth target data) from the fourth source unit to the fifth target unit. For example, the fifth target data may include valid data stored in the fourth source unit, and the fifth target data may belong to the first-type data and / or the second-type data. In addition, the fifth target unit belongs to the third-type physical unit.

[0093] In one embodiment, the memory control circuit 23 may determine whether the performance of the third-stage data consolidation is higher than a predetermined performance. If the performance of the third-stage data consolidation is higher than the predetermined performance, the memory control circuit 23 may determine that the type of the fourth source unit is a first-type physical unit. In other words, if the performance of the third-stage data consolidation is higher than the predetermined performance, the memory control circuit 23 may select at least one first-type physical unit as the fourth source unit.

[0094] However, if the performance of the third-stage data consolidation is not higher than the predetermined performance, the memory control circuit 23 may determine that the type of the fourth source unit is a second-type physical unit. In other words, if the performance of the third-stage data consolidation is not higher than the predetermined performance, the memory control circuit 23 may select at least one second-type physical unit as the fourth source unit.

[0095] In one embodiment, the memory control circuit 23 may use an evaluation value (also referred to as a performance evaluation value) to represent the evaluated performance of the data consolidation operation. For example, this performance evaluation value may reflect or be positively correlated with the performance of the third-stage data consolidation. For example, this performance evaluation value may reflect the total number of idle physical units of one or more types released by the third-stage data consolidation within a unit of time (e.g., 30 seconds or another time range). In one embodiment, the memory control circuit 23 may obtain this performance evaluation value by monitoring the performance of the third-stage data consolidation.

[0096] In one embodiment, compared to the second-stage data consolidation, by opening up data consolidation for various types of data in the third-stage data consolidation, the release efficiency of the first-type physical units and / or the second-type physical units can be improved when the first usage state does not meet the first condition (i.e., the first-type physical units have been used up or are about to be used up) and the second usage state does not meet the second condition (i.e., the second-type physical units have been used up or are about to be used up), thereby improving the performance of the storage device 12.

[0097] In addition, by evaluating the performance of the evaluated data consolidation operation to determine the type of the fourth source unit, when the first and second types of physical units are almost exhausted, the physical units that best meet the current needs can be selected for recycling and release. For example, when the performance of the data consolidation operation is relatively high (for example, the performance of the third stage data consolidation is higher than the preset performance), the first type of physical units can be released first to meet the performance requirements of the host write operation. In addition, when the performance of the data consolidation operation is relatively low (for example, the performance of the third stage data consolidation is not higher than the preset performance), the second type of physical units can be released first to facilitate the acceleration of the data consolidation operation and maintain basic host write operations. This is also beneficial for optimizing the subsequent operational performance of the memory module 112 and / or extending the service life of the memory module 112.

[0098] Figure 6 FIG is a schematic diagram of managing a memory module based on a third data management strategy according to an embodiment of the present invention. Figure 6 In one embodiment, when the first usage state does not meet the first condition and the second usage state does not meet the second condition, the memory control circuit 23 can obtain data 601 (i.e., the first write data) and 602 (i.e., the second write data) from the host system 11.

[0099] In one embodiment, based on the third data management policy, the memory control circuit 23 may store data 601 in the storage area 43 and store data 602 in the storage area 42. In one embodiment, based on the third data management policy, the memory control circuit 23 may allow data 602 (i.e., the second type of data) to be stored in the storage area 43 (i.e., the third type of physical unit) to maintain basic host write operations.

[0100] In one embodiment, based on the third data management policy, if the third stage data consolidation is triggered, then in the third stage data consolidation, in addition to performing at least part of the operations of the first stage data consolidation and / or the second stage data consolidation described above, the memory control circuit 23 may also determine the type of source unit (i.e., the fourth source unit) based on the execution performance of the third stage data consolidation.

[0101] In one embodiment, if it is determined that the fourth source cell belongs to the first type of physical cell, the memory control circuit 23 may identify data 611 (i.e., fifth target data) from the memory area 41 and copy or move the data 611 to the memory area 42 or 43. Alternatively, in one embodiment, if it is determined that the fourth source cell belongs to the second type of physical cell, the memory control circuit 23 may identify data 612 (i.e., fifth target data) from the memory area 42 and copy or move the data 612 to the memory area 42 or 43.

[0102] It should be noted that in the aforementioned embodiment, the second-stage data consolidation can be forward-compatible with (i.e., support) at least some of the functionality of the first-stage data consolidation, depending on practical needs. Similarly, the third-stage data consolidation can be forward-compatible with (i.e., support) at least some of the functionality of the first-stage data consolidation and / or the second-stage data consolidation, depending on practical needs. Furthermore, the relevant operational details have been described above and will not be repeated here.

[0103] Figure 7 FIG is a flow chart of a memory management method according to an embodiment of the present invention. Figure 7 In step S701, a first-type entity unit, a second-type entity unit, and a third-type entity unit are configured in a memory module, wherein the first storage capacity of each first-type entity unit is less than the second storage capacity of each second-type entity unit, and the second storage capacity is less than the third storage capacity of each third-type entity unit. In step S702, a first usage status of the first-type entity unit is monitored. In step S703, it is determined whether the first usage status meets a first condition. If the first usage status meets the first condition, in step S704, a first data management policy is executed.

[0104] If the first usage state does not meet the first condition, in step S705, the second usage state of the second type of entity unit is monitored. In step S706, it is determined whether the second usage state meets the second condition. If the second usage state meets the second condition (and the first usage state does not meet the first condition), in step S707, the second data management policy is implemented. Additionally, if the second usage state does not meet the second condition (and the first usage state does not meet the first condition), in step S708, the third data management policy is implemented.

[0105] Figure 8 FIG is a flow chart of a memory management method according to an embodiment of the present invention. Figure 8 During execution of a first data management policy, in step S801, first write data and second write data are stored in a first physical unit, wherein the first write data belongs to a first type of data, the second write data belongs to a second type of data, and the first physical unit belongs to a first type of physical unit. In step S802, a first phase of data consolidation is triggered. In step S803, during the first phase of data consolidation, first target data is identified from a first source unit and moved or copied to a first target unit, wherein the first source unit belongs to a first type of physical unit, the first target data belongs to a first type of data, and the first target unit belongs to a third type of physical unit.

[0106] Figure 9 FIG is a flow chart of a memory management method according to an embodiment of the present invention. Figure 9 During the execution of the second data management strategy, in step S901, the second stage data consolidation is triggered. In step S902, in the second stage data consolidation, second target data is identified from the second source unit, wherein the second source unit belongs to the first type of entity unit, and the second target data belongs to the first type of data. In step S903, it is determined whether the total data volume of the second target data reaches a predetermined value. If the total data volume of the second target data reaches the predetermined value, in step S904, the second target data is moved or copied to the second target unit, wherein the second target unit belongs to the third type of entity unit. However, if the total data volume of the second target data does not reach the predetermined value, in step S905, third target data is identified from the second source unit, and the second target data together with the third target data are moved or copied to the third target unit, wherein the third target data belongs to the second type of data, and the third target unit belongs to the second type of entity unit.

[0107] Figure 10 FIG is a flow chart of a memory management method according to an embodiment of the present invention. Figure 10During execution of the third data management policy, in step S1001, a third-stage data consolidation is triggered. In step S1002, during the third-stage data consolidation, the execution performance of the third-stage data consolidation is evaluated. In step S1003, based on the execution performance, a fourth source unit is determined, wherein the fourth source unit belongs to at least one of the first-type entity unit and the second-type entity unit. In step S1004, fifth target data is moved or copied from the fourth source unit to a fifth target unit, wherein the fifth target data includes at least one of the first-type data and the second-type data, and the fifth target unit belongs to the third-type entity unit.

[0108] However, Figures 7 to 10 The steps have been described in detail above and will not be repeated here. Figures 7 to 10 Each step can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Figures 7 to 10 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0109] In summary, the memory management method and storage device provided by the present invention can monitor the usage of different types of physical units in a memory module and dynamically set a data management policy for managing the memory module. By dynamically setting an appropriate data management policy, data management operations currently performed on the memory module can achieve an optimal balance between maintaining the efficiency of host write operations, maintaining the efficiency of data consolidation operations, and extending the lifespan of the memory module.

[0110] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that: For use in a storage device, wherein the storage device includes a memory module, and the memory management method includes: Arrange a first type entity unit, a second type entity unit, and a third type entity unit in the memory module, wherein a first storage capacity of each first type entity unit is smaller than a second storage capacity of each second type entity unit, and the second storage capacity is smaller than a third storage capacity of each third type entity unit; monitoring a first usage state of the first type of entity units; and If the first usage status meets the first condition, executing the first data management policy, The first data management strategy includes: Storing first write data and second write data in a first entity unit, wherein the first write data belongs to a first type of data, the second write data belongs to a second type of data, and the first entity unit belongs to the first type of entity unit; Triggering the first phase of data consolidation; and In the first stage of data consolidation, first target data is identified from a first source unit and moved or copied to a first target unit, wherein the first source unit belongs to the first type of entity unit, the first target data belongs to the first type of data, and the first target unit belongs to the third type of entity unit. 2 . The memory management method according to claim 1 , wherein an access frequency of the first type of data is lower than an access frequency of the second type of data. 3 . The memory management method according to claim 1 , wherein the first usage status meets the first condition including that a remaining available number of the first type of physical units is not less than a first critical value.

4. The memory management method according to claim 1 , further comprising: monitoring a second usage state of the second-type entity unit; If the first usage state does not meet the first condition and the second type of entity unit meets the second condition, executing the second data management strategy, The second data management strategy includes: Trigger the second phase of data consolidation; In the second-stage data consolidation, second target data is identified from a second source unit, wherein the second source unit belongs to the first type of entity unit and the second target data belongs to the first type of data; If the total data volume of the second target data reaches a predetermined value, moving or copying the second target data to a second target unit, wherein the second target unit belongs to the third type of entity unit; and If the total data volume of the second target data does not reach the predetermined value, identify third target data from the second source unit, and move or copy the second target data together with the third target data to a third target unit, wherein the third target data belongs to the second category of data, and the third target unit belongs to the second category of physical units.

5. The memory management method according to claim 4, wherein the second data management strategy further comprises: In the second-stage data consolidation, fourth target data is identified from a third source unit, wherein the third source unit belongs to the second type of entity unit and the fourth target data belongs to the first type of data; and The fourth target data is moved or copied to a fourth target unit, wherein the fourth target unit belongs to the third type of physical unit. 6 . The memory management method according to claim 4 , wherein the second usage status meets the second condition comprising that the remaining available number of the second type of physical units is not less than a second critical value.

7. The memory management method according to claim 4, further comprising: If the first usage state does not meet the first condition and the second type of entity unit does not meet the second condition, executing the third data management strategy, The third data management strategy includes: Trigger the third phase of data consolidation; In the third stage data consolidation, evaluating the execution efficiency of the third stage data consolidation; determining a fourth source unit according to the execution performance, wherein the fourth source unit belongs to at least one of the first type of entity unit and the second type of entity unit; and The fifth target data is moved or copied from the fourth source unit to a fifth target unit, wherein the fifth target data includes at least one of the first type of data and the second type of data, and the fifth target unit belongs to the third type of physical unit.

8. The memory management method according to claim 7, wherein the step of determining the fourth source unit according to the execution performance comprises: If the execution performance is higher than a preset performance, determining that the type of the fourth source unit is the first type of physical unit; as well as If the execution performance is not higher than the preset performance, it is determined that the type of the fourth source unit is the second type of physical unit.

9. The memory management method according to claim 7, wherein the step of evaluating the execution performance of the third-stage data consolidation comprises: The execution performance is represented by a performance evaluation value, wherein the performance evaluation value reflects the total number of idle physical units released per unit time.

10. A storage device, characterized in that: include: A connection interface for connecting to a host system; Memory module; as well as a memory controller connected to the connection interface and the memory module, The memory controller is configured to: Arrange a first type entity unit, a second type entity unit, and a third type entity unit in the memory module, wherein a first storage capacity of each first type entity unit is smaller than a second storage capacity of each second type entity unit, and the second storage capacity is smaller than a third storage capacity of each third type entity unit; monitoring a first usage state of the first type of entity units; as well as If the first usage status meets the first condition, executing the first data management policy, The first data management strategy includes: Storing first write data and second write data in a first entity unit, wherein the first write data belongs to a first type of data, the second write data belongs to a second type of data, and the first entity unit belongs to the first type of entity unit; Trigger the first phase of data consolidation; as well as In the first stage of data consolidation, first target data is identified from a first source unit and moved or copied to a first target unit, wherein the first source unit belongs to the first type of entity unit, the first target data belongs to the first type of data, and the first target unit belongs to the third type of entity unit. The storage device according to claim 10 , wherein the access frequency of the first type of data is lower than the access frequency of the second type of data. 12 . The storage device according to claim 10 , wherein the first usage status meets the first condition comprising that a remaining available number of the first type of entity units is not less than a first critical value.

13. The storage device according to claim 10, further comprising: monitoring a second usage state of the second-type entity unit; If the first usage state does not meet the first condition and the second type of entity unit meets the second condition, executing the second data management strategy, The second data management strategy includes: Trigger the second phase of data consolidation; In the second-stage data consolidation, second target data is identified from a second source unit, wherein the second source unit belongs to the first type of entity unit and the second target data belongs to the first type of data; If the total data volume of the second target data reaches a predetermined value, moving or copying the second target data to a second target unit, wherein the second target unit belongs to the third type of entity unit; and If the total data volume of the second target data does not reach the predetermined value, identify third target data from the second source unit, and move or copy the second target data together with the third target data to a third target unit, wherein the third target data belongs to the second category of data, and the third target unit belongs to the second category of physical units.

14. The storage device according to claim 13, wherein the second data management policy further comprises: In the second-stage data consolidation, fourth target data is identified from a third source unit, wherein the third source unit belongs to the second type of entity unit and the fourth target data belongs to the first type of data; and The fourth target data is moved or copied to a fourth target unit, wherein the fourth target unit belongs to the third type of physical unit. 15 . The storage device according to claim 13 , wherein the second usage status meets the second condition comprising that a remaining available number of the second type of entity units is not less than a second critical value.

16. The storage device according to claim 13, further comprising: If the first usage state does not meet the first condition and the second type of entity unit does not meet the second condition, executing the third data management strategy, The third data management strategy includes: Trigger the third phase of data consolidation; In the third stage data consolidation, evaluating the execution efficiency of the third stage data consolidation; determining a fourth source unit according to the execution performance, wherein the fourth source unit belongs to at least one of the first type of entity unit and the second type of entity unit; and The fifth target data is moved or copied from the fourth source unit to a fifth target unit, wherein the fifth target data includes at least one of the first type of data and the second type of data, and the fifth target unit belongs to the third type of physical unit.

17. The storage device according to claim 16, wherein the step of determining the fourth source unit according to the execution performance comprises: If the execution performance is higher than a preset performance, determining that the type of the fourth source unit is the first type of physical unit; as well as If the execution performance is not higher than the preset performance, it is determined that the type of the fourth source unit is the second type of physical unit.

18. The storage device according to claim 16, wherein the step of evaluating the execution performance of the third stage data consolidation comprises: The execution performance is represented by a performance evaluation value, wherein the performance evaluation value reflects the total number of idle physical units released per unit time.

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