A boost backlight driving circuit and control method for realizing MPRT function

Abstract

The present invention discloses a boost-type backlight drive circuit and control method for realizing an MPRT function. An AC-DC converter converts commercial AC power into a first DC power, which is respectively connected to a power supply VDD pin of a backlight driver chip and an input end of a boost circuit. The boost circuit boosts the first DC power to obtain a second DC power required by an LED lamp tube. A control end of the boost circuit is electrically connected to a drive GATE pin of the backlight driver chip. A current detection end of the boost circuit is electrically connected to a current detection CS pin of a first transistor of the backlight driver chip. An output end of the LED lamp tube is electrically connected to a current sampling resistor Rfb and one end of a resistor Rdim1, the other end of the resistor Rfb is grounded, the other end of the resistor Rdim1 is electrically connected to an FB pin and one end of a resistor Rdim2, and the other end of the resistor Rdim2 is electrically connected to an LPWM output port of an image processor of a main substrate. The LPWM output port outputs a low level in a non-MPRT operating mode and outputs an LPWM signal synchronized with the field frequency of a liquid crystal display in the MPRT operating mode.

Description

Technical Field

[0001] The present invention relates to the field of liquid crystal display products, and in particular to a boost backlight driving circuit and a control method for realizing an MPRT function. Background Art

[0002] MPRT (Moving Picture Response time) refers to the time it takes for a monitor's pixels to switch from one state to another when displaying dynamic images. MPRT technology uses a method that continuously switches the backlight on and off at a frequency synchronized with the vertical frequency to insert a black screen between each frame (a black screen occurs when the backlight is off). This prevents the problem of image smearing caused by persistence of vision. The principle is that a black screen appears between adjacent frames. This allows the image to be "cleared" by the black screen after persistence of vision, resulting in smooth, continuous motion without image smearing. The MPRT signal that controls the backlight driver circuit must be synchronized with the monitor's vertical frequency.

[0003] Existing boost backlight drive circuits with MPRT function usually use accessories Figure 1 The conventional chip shown here features a backlight boost driver circuit with MPRT functionality. Existing dedicated backlight driver chips with MPRT functionality require a power supply VDD pin, a driver GATE pin, a current sensing CS pin, a lamp current input LED pin, a lamp current setting FB pin, a reference ground GND pin, a vertical frequency synchronization LPWM pin, and a PWM-to-DC dimming ADIM pin. Driver IC U1 must be packaged in an SOP-8 package and internally include a 2A / 60V DIM-MOS Q2. Summary of the Invention

[0004] The object of the present invention is to provide a boost backlight driving circuit and a control method for realizing the MPRT function.

[0005] The technical solution adopted in the present invention is:

[0006] A boost-type backlight driver circuit that implements MPRT function includes an AC-DC converter, a backlight driver chip, and a boost circuit. The backlight driver chip has a power supply VDD pin, a drive GATE pin, a first transistor current detection CS pin, a reference ground GND pin, an LED lamp current detection feedback FB pin, and a PWM to DC dimming ADIM pin.

[0007] The input end of the AC-DC converter is electrically connected to the mains AC power supply interface, and the output port of the AC-DC converter is respectively connected to the power supply VDD pin of the backlight driver chip and the input end of the boost circuit; the output end of the boost circuit is electrically connected to the input end of the LED lamp tube; the boost circuit has a control end and a current detection end, the control end of the boost circuit is electrically connected to the driving GATE pin of the backlight driver chip; the current detection end of the boost circuit is electrically connected to the current detection CS pin of the first transistor of the backlight driver chip; the AC-DC converter converts the mains AC power into a first DC power; the boost circuit boosts the first DC power to obtain the second DC power required by the LED lamp tube; the LED lamp tube output The ends are electrically connected to one end of the current sampling resistor Rfb and one end of the resistor Rdim1 respectively, the other end of the current sampling resistor Rfb is grounded, the other end of the resistor Rdim1 is electrically connected to the LED lamp current detection feedback pin FB of the backlight driver chip and one end of the resistor Rdim2 respectively, and the other end of the resistor Rdim2 is electrically connected to an LPWM output port of the main substrate image processor; the reference ground GND pin of the backlight driver chip is grounded; the PWM to DC dimming ADIM pin of the backlight driver chip is electrically connected to the HPWM port of the image processor of the main substrate and the anode of the diode D2 respectively, and the cathode of the diode D2 is electrically connected to the ENA enable pin output port of the image processor of the main substrate; the LPWM output port outputs an LPWM signal synchronized with the field frequency of the liquid crystal display in the MPRT working mode; the HPWM port of the image processor of the main substrate outputs an HPWM dimming signal, and the frequency of the HPWM dimming signal is greater than the frequency of the LPWM signal;

[0008] The backlight driver chip integrates a logic drive control circuit, a PWM to DC circuit and an error amplifier EA. The PWM to DC dimming ADIM pin is electrically connected to one port of the PWM to DC circuit, the other port of the PWM to DC circuit is electrically connected to the non-inverting input terminal of the error amplifier EA, and the inverting input terminal of the error amplifier EA is electrically connected to the LED lamp tube current detection feedback FB pin of the backlight driver chip; the power supply VDD pin, drive GATE pin, first transistor current detection CS pin and error amplifier EA output terminal of the backlight driver chip are electrically connected to the logic drive control circuit.

[0009] Furthermore, the output port of the AC-DC converter is electrically connected to a power supply VDD pin of the backlight driver chip via a resistor Rvdd.

[0010] Furthermore, the boost circuit includes a first transistor, a polar capacitor C1, a boost inductor L1, a boost diode D1, a capacitor C2 and a resistor Rcs; the output port of the AC-DC converter is electrically connected to the positive end of the polar capacitor C1 and one end of the boost inductor L1, respectively, and the negative end of the polar capacitor C1 is grounded; the other end of the boost inductor L1 is electrically connected to the input pin of the first transistor and the positive electrode of the boost diode D1, respectively; the negative electrode of the boost diode D1 is electrically connected to the positive electrode of the capacitor C2 and the input end of the LED lamp tube, respectively; the negative electrode of the capacitor C2 is grounded, the gate pin of the first transistor serves as the control end of the boost circuit and is electrically connected to the drive GATE pin of the backlight driver chip, the output pin of the first transistor is electrically connected to one end of the resistor Rcs and the current detection CS pin of the first transistor, respectively, and the other end of the resistor Rcs is grounded.

[0011] Furthermore, the commercial AC power is 220V / 50HZ AC power; the first DC power is, for example, 19V DC power; and the second DC power is, for example, 30~60V DC power.

[0012] Furthermore, the first transistor is an N-channel MOS transistor Q1 , the input pin of the first transistor is the drain of the N-channel MOS transistor Q1 , and the output pin of the first transistor is the source of the N-channel MOS transistor Q1 .

[0013] Furthermore, the LPWM output port of the main substrate image processor outputs an LPWM (low frequency) signal of 75HZ~520HZ.

[0014] Furthermore, the HPWM port of the image processor of the main substrate outputs an HPWM (high frequency) signal of 10KHZ or above.

[0015] Furthermore, the current output from the output end of the LED lamp tube is sampled by the sampling current sampling resistor Rfb, then divided by resistors Rdim1 and Rdim2, and provided to the FB pin of the backlight driver chip for current dimming control after being controlled by the LPWM signal; the HPWM port of the image processor on the main substrate outputs an HPWM signal to the ADIM pin of the backlight driver chip, and the voltage is converted through the PWM to DC circuit to generate a DC direct current dimming signal to be provided to the non-inverting input end of the error amplifier EA to control the LED lamp current.

[0016] Specifically, the backlight driver chip has a power supply VDD pin, a drive GATE pin, a MOS tube Q1 current detection CS pin, a reference ground GND pin, an LED lamp current detection feedback FB pin and a PWM to DC dimming ADIM pin;

[0017] A control method for a boost-type backlight drive circuit implementing an MPRT function is disclosed. The LPWM output port of an image processor on a main substrate outputs a low level in a non-MPRT operating mode. In the MPRT operating mode, the LPWM output port outputs an LPWM signal synchronized with the field frequency of a liquid crystal display. The HPWM port of the image processor on the main substrate outputs an HPWM dimming signal, wherein the frequency of the HPWM dimming signal is greater than the frequency of the LPWM signal. When the field frequency synchronization signal of the LPWM is at a logic low level, the display screen is bright, and when the field frequency synchronization signal of the LPWM is at a logic high level, the display screen is dark, which is referred to as LPWM inverse logic dimming. Specifically, the specific operating sequence is as follows:

[0018] t0 time: the display is in standby mode, the switch control signal output by the ENA enable port of the image processor on the main substrate inside the display is low, and the LED light does not work;

[0019] Time t1: The display enters the non-MPRT working mode. The ENA enable port of the main substrate's image processor outputs a continuous high-level signal. The ADIM pin of the backlight driver chip receives the HPWM dimming signal output by the HPWM port of the main substrate's image processor. The signal is converted into a DC dimming signal through the PWM-to-DC circuit inside the backlight driver chip. The LPWM port of the main substrate's image processor outputs a continuous low-level signal. At this time, the LED lamp current Iled=Vref*D1*(Rdim1+Rdim2) / Rdim2 / Rfb, where: Vref is a reference voltage inside the backlight driver chip, D1 is the duty cycle of the HPWM dimming signal, Rdim1 is the resistance of the Rdim1 resistor, Rdim2 is the resistance of the Rdim2 resistor, and Rfb is the resistance of the Rfb resistor.

[0020] t2 time: The display enters MPRT working mode. At this time, the ENA enable port of the image processor of the main substrate outputs a continuous high-level signal, and the ADIM pin of the backlight driver chip receives the HPWM dimming signal with a duty cycle greater than that in the non-MPRT working mode, ensuring that the LCD display still has a brighter display screen when entering the MPRT working mode; the LPWM signal output by the LPWM port of the image processor of the main substrate is the field frequency synchronization signal. When the field frequency synchronization signal of LPWM is a logic high level, the LED lamp has no output current and the screen is black; when the field frequency synchronization signal of LPWM is a logic low level, a peak current is output. The peak current of the LED lamp Iled (Peak) = Vref*D1*(Rdim1+Rdim2) / Rdim2 / Rfb, and the screen is bright. Set the circuit parameters so that VLPWM* Rdim1 / (Rdim1+Rdim2)>Vref, so that when the LPWM signal is at a logic high level, the LED lamp has no output current (a dark screen). VLPWM is the LPWM logic high voltage, Vref is a reference voltage inside the backlight driver chip, D1 is the duty cycle of the HPWM dimming signal, Rdim1 is the resistance of the Rdim1 resistor, Rdim2 is the resistance of the Rdim2 resistor, and Rfb is the resistance of the Rfb resistor.

[0021] Specifically, the dimming working principle in the non-MPRT working mode is: the LPWM port of the image processor of the main substrate maintains the output of a continuous low-level signal, and the HPWM port of the image processor of the main substrate outputs an HPWM dimming signal. The HPWM dimming signal is received by the ADIM pin of the backlight driver chip and converted into a voltage V(EA+)=Vref*D1 by the PWM to DC circuit inside the backlight driver chip, where Vref is a reference voltage inside the U2 backlight driver chip and D1 is the duty cycle Duty of the HPWM dimming. The LED lamp current Iled is calculated based on the virtual short circuit characteristic of the error amplifier EA input terminal. Furthermore, based on the virtual short circuit characteristic of the error amplifier EA input terminal, namely: V(EA+)= V(EA-)=Vref*D1, the LED lamp current Iled=Vref*D1*(Rdim1+Rdim2) / Rdim2 / Rfb, where: Vref is a reference voltage inside the backlight driver chip, D1 is the duty cycle of the HPWM dimming signal, Rdim1 is the resistance value of the Rdim1 resistor, Rdim2 is the resistance value of the Rdim2 resistor, and Rfb is the resistance value of the Rfb resistor.

[0022] The dimming principle when entering MPRT working mode is as follows: the vertical frequency synchronization signal output by the LPWM port of the image processor of the main substrate is mixed with the HPWM dimming signal output by the HPWM port of the image processor of the main substrate for dimming. When the vertical frequency synchronization signal of the LPWM is at a logic high level, the LED lamp has no output current and the screen is black. When the vertical frequency synchronization signal of the LPWM is at a logic low level, a peak current is output and the screen is bright. The calculated peak current of the LED lamp Iled (Peak) = Vref * D1 * (Rdim1 + Rdim2) / Rdim2 / Rfb. The circuit parameters are set so that VLPWM * Rdim1 / (Rdim1 + Rdim2) > Vref, so that when the LPWM signal is at a logic high level, the LED lamp has no output current (the screen is dark). Among them, when the LPWM signal is at a logic low level, the screen is bright, and when the LPWM signal is at a logic high level, the screen is black, which is called LPWM reverse logic dimming.

[0023] Furthermore, in the MPRT working mode, the calculation formula for the average current of the LED lamp is as follows:

[0024] Iled(av)=(1-D2)* Vref*D1*(Rdim1+Rdim2) / Rdim2 / Rfb

[0025] Wherein, D2 is the duty cycle Duty of the LPWM field frequency synchronization signal.

[0026] Specifically, when entering the MPRT working mode, the dimming working principle is: the LPWM port of the image processor of the main substrate outputs a field frequency signal with an operating frequency of about 75HZ~520HZ, and the HPWM port of the image processor of the main substrate outputs a HPWM dimming signal with a higher frequency of 10KHZ and above for mixed dimming. a. When LPWM is at a logic high level, a voltage Vref higher than the FB reference voltage is imposed on FB, causing the GATE pin of the backlight driver chip U2 to stop driving. The LED lamp has no output current and the screen is black. b. When LPWM is at a logic low level, a peak current is output, and the screen is bright. Iled (Peak) = Vref * D1 * (Rdim1 + Rdim2) / Rdim2 / Rfb. The circuit parameters are set so that VLPWM * Rdim1 / (Rdim1 + Rdim2) > Vref. This way, when the LPWM signal is at a logic high level, the LED lamp has no output current (the screen is dark). In MPRT working mode, the average current of the LED lamp is Iled (av) = (1-D2) * Vref * D1 * (Rdim1 + Rdim2) / Rdim2 / Rfb (where D2 is the duty cycle of the LPWM field frequency synchronization signal); when LPWM is at a logic low level, the display screen is bright, and when LPWM is at a logic high level, the display screen is black, which is called LPWM reverse logic dimming.

[0027] Furthermore, as another embodiment, it also includes a resistor Rdim3 and a second transistor, the other end of the resistor Rdim2 is electrically connected to one end of the resistor Rdim3 and the input pin of the second transistor respectively, the other end of the resistor Rdim3 receives a voltage source with a voltage of V1, the output pin of the second transistor is grounded, and the gate pin of the second transistor is electrically connected to an LPWM output port of the main substrate image processor; the LPWM output port outputs a high level in the non-MPRT working mode; the LPWM output port outputs an LPWM signal synchronized with the field frequency of the liquid crystal display in the MPRT working mode.

[0028] Furthermore, the second transistor is an N-channel MOS transistor Q2 , an input pin of the second transistor is a drain of the N-channel MOS transistor Q2 , and an output pin of the second transistor is a source of the N-channel MOS transistor Q2 .

[0029] Specifically, as another embodiment, based on Embodiment 1, further includes a resistor Rdim3 and an N-channel MOS transistor Q2. The output end of the LED lamp is electrically connected to one end of a current sampling resistor Rfb and one end of a resistor Rdim1. The other end of resistor Rfb is grounded. The other end of resistor Rdim1 is electrically connected to the FB pin of the backlight driver chip U2 and one end of resistor Rdim2. The other end of resistor Rdim2 is electrically connected to one end of resistor Rdim3 and the drain of the N-channel MOS transistor Q2. The other end of resistor Rdim3 receives a voltage source of voltage V1. The source of the N-channel MOS transistor Q2 is grounded. The gate of the N-channel MOS transistor Q2 is electrically connected to an LPWM output port of the main substrate image processor. The LPWM output port outputs a high level in non-MPRT operating mode. In MPRT operating mode, the LPWM output port outputs an LPWM signal synchronized with the LCD field frequency. This alternative solution is to set the MPRT dimming signal synchronized with the LPWM field frequency to normal logic control.

[0030] Another embodiment corresponds to a control method for a boost backlight drive circuit that implements an MPRT function, comprising: an LPWM output port outputting a high level in a non-MPRT operating mode; and an LPWM signal synchronized with the field frequency of a liquid crystal display in the MPRT operating mode; an HPWM port of an image processor on a main substrate outputting an HPWM dimming signal, wherein the frequency of the HPWM dimming signal is greater than the frequency of the LPWM signal; and when the field frequency synchronization signal of the LPWM is at a logic high level, the display screen is bright, and when the field frequency synchronization signal of the LPWM is at a logic low level, the display screen is black, which is referred to as LPWM positive logic dimming.

[0031] Specifically, when the LPWM signal is at a logic high level, the MOS tube Q2 is turned on, the LED tube peak current Iled (Peak) = Vref*D1*(Rdim1+Rdim2) / Rdim2 / Rfb, and the LCD screen is bright.

[0032] When the LPWM signal is at a logic low, MOS transistor Q2 is turned off. The inverting input terminal of the error amplifier EA inside the backlight driver chip, V(EA-) = V1*Rdim1 / (Rdim1+Rdim2+Rdim3) > Vref > V(EA+), and the error amplifier EA outputs a low level to the logic drive control circuit, causing the GATE pin to output a low signal. This means the boost circuit stops supplying power to the LED tube, resulting in no current flowing through the LED tube and a black screen. At this point, the average operating current of the LED tube, Iled(av), = Vref*D1*D2*(Rdim1+Rdim2) / Rdim2 / Rfb.

[0033] Specifically, the LPWM output port of the image processor of the main substrate outputs a high level in the non-MPRT working mode. In the MPRT working mode, the LPWM output port outputs an LPWM signal synchronized with the vertical frequency of the liquid crystal display. The HPWM port of the image processor of the main substrate outputs an HPWM dimming signal, and the frequency of the HPWM dimming signal is greater than the frequency of the LPWM signal. When the vertical frequency synchronization signal of the LPWM is at a logic high level, the display screen is bright, and when the vertical frequency synchronization signal of the LPWM is at a logic low level, the display screen is black. This is called LPWM positive logic dimming. That is, the specific working sequence is as follows:

[0034] t0 time: the display is in standby mode, the switch control signal output by the ENA enable port of the image processor on the main substrate inside the display is low, and the LED light does not work;

[0035] Time t1: The display enters the non-MPRT working mode. The ENA enable port of the image processor of the main substrate outputs a continuous high-level signal. The ADIM pin of the backlight driver chip receives the HPWM dimming signal output by the HPWM port of the image processor of the main substrate. The signal is converted into a DC dimming signal through the PWM-to-DC circuit inside the backlight driver chip. The LPWM port of the image processor of the main substrate outputs a continuous high-level signal, and the second transistor Q2 is turned on. At this time, the LED lamp current Iled=Vref*D1*(Rdim1+Rdim2) / Rdim2 / Rfb, where: Vref is a reference voltage inside the backlight driver chip, D1 is the duty cycle of the HPWM dimming signal, Rdim1 is the resistance of the Rdim1 resistor, Rdim2 is the resistance of the Rdim2 resistor, and Rfb is the resistance of the Rfb resistor.

[0036] t2 time: The display enters MPRT working mode. At this time, the ENA enable port of the image processor of the main substrate outputs a continuous high-level signal, and the ADIM pin of the backlight driver chip receives the HPWM dimming signal with a duty cycle greater than that in the non-MPRT working mode, ensuring that the LCD display still has a brighter display screen when entering the MPRT working mode; the LPWM signal output by the LPWM port of the image processor of the main substrate is the field frequency synchronization signal. When the field frequency synchronization signal of LPWM is a logic low level, the LED lamp has no output current and the screen is black; when the field frequency synchronization signal of LPWM is a logic high level, a peak current is output. The peak current of the LED lamp Iled (Peak) = Vref*D1*(Rdim1+Rdim2) / Rdim2 / Rfb, and the screen is bright. Set the circuit parameters so that V1*Rdim1 / (Rdim1+Rdim2+ Rdim3)>Vref, so that when the LPWM signal is at a logic low level, the second transistor Q2 is turned off, and the LED lamp has no output current (a dark screen), wherein V1 is a power supply voltage, Vref is a reference voltage inside the backlight driver chip, D1 is the duty cycle of the HPWM dimming signal, Rdim1 is the resistance value of the Rdim1 resistor, Rdim2 is the resistance value of the Rdim2 resistor, Rdim3 is the resistance value of the Rdim3 resistor, and Rfb is the resistance value of the Rfb resistor.

[0037] The present invention adopts the above technical solution and uses an existing low-cost SOT-26 packaged small 6-pin non-MPRT function IC to implement the MPRT function. Compared with the existing dedicated MPRT function using SOP-8 package and internal DIM-MOS, the IC cost is estimated to be reduced by about 25% to 30%. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments;

[0039] Figure 1 This is a schematic diagram of the structure of an existing boost backlight driving circuit with MPRT function;

[0040] Figure 2 This is a schematic structural diagram of a feasible embodiment of a boost backlight driving circuit for realizing the MPRT function of the present invention;

[0041] Figure 3 This is a reverse logic dimming timing diagram of a feasible embodiment of a boost backlight driving circuit for realizing the MPRT function of the present invention;

[0042] Figure 4 Schematic diagram of another feasible embodiment of a boost backlight driving circuit for realizing MPRT function according to the present invention;

[0043] Figure 5 This is a positive logic dimming timing diagram of another feasible embodiment of a boost backlight driving circuit for realizing the MPRT function of the present invention. Implementation Method

[0044] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0045] like Figures 1 to 5 As shown in FIG1 , the present invention discloses a boost-type backlight driving circuit for realizing MPRT function, which includes an AC-DC converter, a backlight driving chip, and a boost circuit. The backlight driving chip has a power supply VDD pin, a driving GATE pin, a first transistor current detection CS pin, a reference ground GND pin, an LED lamp current detection feedback FB pin, and a PWM to DC dimming ADIM pin.

[0046] The input end of the AC-DC converter is electrically connected to the mains AC power supply interface, and the output port of the AC-DC converter is respectively connected to the power supply VDD pin of the backlight driver chip and the input end of the boost circuit; the output end of the boost circuit is electrically connected to the input end of the LED lamp tube; the boost circuit has a control end and a current detection end, the control end of the boost circuit is electrically connected to the driving GATE pin of the backlight driver chip; the current detection end of the boost circuit is electrically connected to the current detection CS pin of the first transistor of the backlight driver chip; the AC-DC converter converts the mains AC power into a first DC power; the boost circuit boosts the first DC power to obtain the second DC power required by the LED lamp tube; the LED lamp tube output The ends are electrically connected to one end of the current sampling resistor Rfb and one end of the resistor Rdim1 respectively, the other end of the current sampling resistor Rfb is grounded, the other end of the resistor Rdim1 is electrically connected to the LED lamp current detection feedback pin FB of the backlight driver chip and one end of the resistor Rdim2 respectively, and the other end of the resistor Rdim2 is electrically connected to an LPWM output port of the main substrate image processor; the reference ground GND pin of the backlight driver chip is grounded; the PWM to DC dimming ADIM pin of the backlight driver chip is electrically connected to the HPWM port of the image processor of the main substrate and the anode of the diode D2 respectively, and the cathode of the diode D2 is electrically connected to the ENA enable pin output port of the image processor of the main substrate; the LPWM output port outputs an LPWM signal synchronized with the field frequency of the liquid crystal display in the MPRT working mode; the HPWM port of the image processor of the main substrate outputs an HPWM dimming signal, and the frequency of the HPWM dimming signal is greater than the frequency of the LPWM signal;

[0047] The backlight driver chip integrates a logic drive control circuit, a PWM to DC circuit and an error amplifier EA. The PWM to DC dimming ADIM pin is electrically connected to one port of the PWM to DC circuit, the other port of the PWM to DC circuit is electrically connected to the non-inverting input terminal of the error amplifier EA, and the inverting input terminal of the error amplifier EA is electrically connected to the LED lamp tube current detection feedback FB pin of the backlight driver chip; the power supply VDD pin, drive GATE pin, first transistor current detection CS pin and error amplifier EA output terminal of the backlight driver chip are electrically connected to the logic drive control circuit.

[0048] Furthermore, the output port of the AC-DC converter is electrically connected to a power supply VDD pin of the backlight driver chip via a resistor Rvdd.

[0049] Furthermore, the boost circuit includes a first transistor, a polar capacitor C1, a boost inductor L1, a boost diode D1, a capacitor C2 and a resistor Rcs; the output port of the AC-DC converter is electrically connected to the positive end of the polar capacitor C1 and one end of the boost inductor L1, respectively, and the negative end of the polar capacitor C1 is grounded; the other end of the boost inductor L1 is electrically connected to the input pin of the first transistor and the positive electrode of the boost diode D1, respectively; the negative electrode of the boost diode D1 is electrically connected to the positive electrode of the capacitor C2 and the input end of the LED lamp tube, respectively; the negative electrode of the capacitor C2 is grounded, the gate pin of the first transistor serves as the control end of the boost circuit and is electrically connected to the drive GATE pin of the backlight driver chip, the output pin of the first transistor is electrically connected to one end of the resistor Rcs and the current detection CS pin of the first transistor, respectively, and the other end of the resistor Rcs is grounded.

[0050] Furthermore, the commercial AC power is 220V / 50HZ AC power; the first DC power is, for example, 19V DC power; and the second DC power is, for example, 30~60V DC power.

[0051] Furthermore, the first transistor is an N-channel MOS transistor Q1 , the input pin of the first transistor is the drain of the N-channel MOS transistor Q1 , and the output pin of the first transistor is the source of the N-channel MOS transistor Q1 .

[0052] Furthermore, the LPWM output port of the main substrate image processor outputs an LPWM (low frequency) signal of 75HZ~520HZ.

[0053] Furthermore, the HPWM port of the image processor of the main substrate outputs an HPWM (high frequency) signal of 10KHZ or above.

[0054] Furthermore, the current output from the output end of the LED lamp tube is sampled by the sampling current sampling resistor Rfb, then divided by resistors Rdim1 and Rdim2, and provided to the FB pin of the backlight driver chip for current dimming control after being controlled by the LPWM signal; the image processor of the main substrate outputs an HPWM signal to the ADIM pin of the backlight driver chip, and the voltage is converted through the PWM to DC circuit to generate a DC direct current dimming signal to be provided to the non-inverting input end of the error amplifier EA to control the LED lamp current.

[0055] Specifically, the backlight driver chip has a power supply VDD pin, a drive GATE pin, a MOS tube Q1 current detection CS pin, a reference ground GND pin, an LED lamp current detection feedback FB pin and a PWM to DC dimming ADIM pin;

[0056] A control method for a boost-type backlight drive circuit implementing an MPRT function is disclosed. The LPWM output port of an image processor on a main substrate outputs a low level in a non-MPRT operating mode. In the MPRT operating mode, the LPWM output port outputs an LPWM signal synchronized with the field frequency of a liquid crystal display. The HPWM port of the image processor on the main substrate outputs an HPWM dimming signal, wherein the frequency of the HPWM dimming signal is greater than the frequency of the LPWM signal. When the field frequency synchronization signal of the LPWM is at a logic low level, the display screen is bright, and when the field frequency synchronization signal of the LPWM is at a logic high level, the display screen is dark, which is referred to as LPWM inverse logic dimming. Specifically, the specific operating sequence is as follows:

[0057] t0 time: the display is in standby mode, the switch control signal output by the ENA enable port of the image processor on the main substrate inside the display is low, and the LED light does not work;

[0058] Time t1: The display enters the non-MPRT working mode. The ENA enable port of the main substrate's image processor outputs a continuous high-level signal. The ADIM pin of the backlight driver chip receives the HPWM dimming signal output by the HPWM port of the main substrate's image processor. The signal is converted into a DC dimming signal through the PWM-to-DC circuit inside the backlight driver chip. The LPWM port of the main substrate's image processor outputs a continuous low-level signal. At this time, the LED lamp current Iled=Vref*D1*(Rdim1+Rdim2) / Rdim2 / Rfb, where: Vref is a reference voltage inside the backlight driver chip, D1 is the duty cycle of the HPWM dimming signal, Rdim1 is the resistance of the Rdim1 resistor, Rdim2 is the resistance of the Rdim2 resistor, and Rfb is the resistance of the Rfb resistor.

[0059] t2 time: The display enters MPRT working mode. At this time, the ENA enable port of the image processor of the main substrate outputs a continuous high-level signal, and the ADIM pin of the backlight driver chip receives the HPWM dimming signal with a duty cycle greater than that in the non-MPRT working mode, ensuring that the LCD display still has a brighter display screen when entering the MPRT working mode; the LPWM signal output by the LPWM port of the image processor of the main substrate is the field frequency synchronization signal. When the field frequency synchronization signal of LPWM is a logic high level, the LED lamp has no output current and the screen is black; when the field frequency synchronization signal of LPWM is a logic low level, a peak current is output. The peak current of the LED lamp Iled (Peak) = Vref*D1*(Rdim1+Rdim2) / Rdim2 / Rfb, and the screen is bright. Set the circuit parameters so that VLPWM* Rdim1 / (Rdim1+Rdim2)>Vref, so that when the LPWM signal is at a logic high level, the LED lamp has no output current (a dark screen). VLPWM is the LPWM logic high voltage, Vref is a reference voltage inside the backlight driver chip, D1 is the duty cycle of the HPWM dimming signal, Rdim1 is the resistance of the Rdim1 resistor, Rdim2 is the resistance of the Rdim2 resistor, and Rfb is the resistance of the Rfb resistor.

[0060] Specifically, the dimming working principle in the non-MPRT working mode is: the LPWM port of the image processor of the main substrate maintains the output of a continuous low-level signal, and the HPWM port of the image processor of the main substrate outputs an HPWM dimming signal. The HPWM dimming signal is received by the ADIM pin of the backlight driver chip and converted into a voltage V(EA+)=Vref*D1 by the PWM to DC circuit inside the backlight driver chip, where Vref is a reference voltage inside the U2 backlight driver chip and D1 is the duty cycle Duty of the HPWM dimming. The LED lamp current Iled is calculated based on the virtual short circuit characteristic of the error amplifier EA input terminal. Furthermore, based on the virtual short circuit characteristic of the error amplifier EA input terminal, namely: V(EA+)= V(EA-)=Vref*D1, the LED lamp current Iled=Vref*D1*(Rdim1+Rdim2) / Rdim2 / Rfb, where: Vref is a reference voltage inside the backlight driver chip, D1 is the duty cycle of the HPWM dimming signal, Rdim1 is the resistance value of the Rdim1 resistor, Rdim2 is the resistance value of the Rdim2 resistor, and Rfb is the resistance value of the Rfb resistor.

[0061] The dimming principle when entering MPRT working mode is as follows: the vertical frequency synchronization signal output by the LPWM port of the image processor of the main substrate is mixed with the HPWM dimming signal output by the HPWM port of the image processor of the main substrate for dimming. When the vertical frequency synchronization signal of the LPWM is at a logic high level, the LED lamp has no output current and the screen is black. When the vertical frequency synchronization signal of the LPWM is at a logic low level, a peak current is output and the screen is bright. The calculated peak current of the LED lamp Iled (Peak) = Vref * D1 * (Rdim1 + Rdim2) / Rdim2 / Rfb. The circuit parameters are set so that VLPWM * Rdim1 / (Rdim1 + Rdim2) > Vref, so that when the LPWM signal is at a logic high level, the LED lamp has no output current (the screen is dark). Among them, when the LPWM signal is at a logic low level, the screen is bright, and when the LPWM signal is at a logic high level, the screen is black, which is called LPWM reverse logic dimming.

[0062] Furthermore, in the MPRT working mode, the calculation formula for the average current of the LED lamp is as follows:

[0063] Iled(av)=(1-D2)* Vref*D1*(Rdim1+Rdim2) / Rdim2 / Rfb

[0064] Wherein, D2 is the duty cycle Duty of the LPWM field frequency synchronization signal.

[0065] Specifically, when entering the MPRT working mode, the dimming working principle is: the LPWM port of the image processor of the main substrate outputs a field frequency signal with an operating frequency of about 75HZ~520HZ, and the HPWM port of the image processor of the main substrate outputs a HPWM dimming signal with a higher frequency of 10KHZ and above for mixed dimming. a. When LPWM is at a logic high level, a voltage Vref higher than the FB reference voltage is imposed on FB, causing the GATE pin of the backlight driver chip U2 to stop driving. The LED lamp has no output current and the screen is black. b. When LPWM is at a logic low level, a peak current is output, and the screen is bright. Iled (Peak) = Vref * D1 * (Rdim1 + Rdim2) / Rdim2 / Rfb. The circuit parameters are set so that VLPWM * Rdim1 / (Rdim1 + Rdim2) > Vref. This way, when the LPWM signal is at a logic high level, the LED lamp has no output current (the screen is dark). In MPRT working mode, the average current of the LED lamp is Iled (av) = (1-D2) * Vref * D1 * (Rdim1 + Rdim2) / Rdim2 / Rfb (where D2 is the duty cycle of the LPWM field frequency synchronization signal); when LPWM is at a logic low level, the display screen is bright, and when LPWM is at a logic high level, the display screen is black, which is called LPWM reverse logic dimming.

[0066] As another embodiment, it also includes a resistor Rdim3 and a second transistor, the other end of the resistor Rdim2 is electrically connected to one end of the resistor Rdim3 and the input pin of the second transistor respectively, the other end of the resistor Rdim3 receives a voltage source with a voltage of V1, the output pin of the second transistor is grounded, and the gate pin of the second transistor is electrically connected to an LPWM output port of the main substrate image processor; the LPWM output port outputs a high level in a non-MPRT working mode; the LPWM output port outputs an LPWM signal synchronized with the field frequency of the liquid crystal display in the MPRT working mode.

[0067] Furthermore, the second transistor is an N-channel MOS transistor Q2 , an input pin of the second transistor is a drain of the N-channel MOS transistor Q2 , and an output pin of the second transistor is a source of the N-channel MOS transistor Q2 .

[0068] Specifically, as another embodiment, based on Embodiment 1, further includes a resistor Rdim3 and an N-channel MOS transistor Q2. The output end of the LED lamp is electrically connected to one end of a current sampling resistor Rfb and one end of a resistor Rdim1. The other end of resistor Rfb is grounded. The other end of resistor Rdim1 is electrically connected to the FB pin of the backlight driver chip U2 and one end of resistor Rdim2. The other end of resistor Rdim2 is electrically connected to one end of resistor Rdim3 and the drain of the N-channel MOS transistor Q2. The other end of resistor Rdim3 receives a voltage source of voltage V1. The source of the N-channel MOS transistor Q2 is grounded. The gate of the N-channel MOS transistor Q2 is electrically connected to an LPWM output port of the main substrate image processor. The LPWM output port outputs a high level in non-MPRT operating mode. In MPRT operating mode, the LPWM output port outputs an LPWM signal synchronized with the LCD field frequency. This alternative solution is to set the MPRT dimming signal synchronized with the LPWM field frequency to normal logic control.

[0069] Another embodiment corresponds to a control method for a boost backlight drive circuit that implements an MPRT function, comprising: an LPWM output port outputting a high level in a non-MPRT operating mode; and an LPWM signal synchronized with the field frequency of a liquid crystal display in the MPRT operating mode; an HPWM port of an image processor on a main substrate outputting an HPWM dimming signal, wherein the frequency of the HPWM dimming signal is greater than the frequency of the LPWM signal; and when the field frequency synchronization signal of the LPWM is at a logic high level, the display screen is bright, and when the field frequency synchronization signal of the LPWM is at a logic low level, the display screen is black, which is referred to as LPWM positive logic dimming.

[0070] Specifically, when the LPWM signal is at a logic high level, the MOS tube Q2 is turned on, the LED tube peak current Iled (Peak) = Vref*D1*(Rdim1+Rdim2) / Rdim2 / Rfb, and the LCD screen is bright.

[0071] When the LPWM signal is at a logic low, MOS transistor Q2 is turned off. The inverting input terminal of the error amplifier EA inside the backlight driver chip, V(EA-) = V1*Rdim1 / (Rdim1+Rdim2+Rdim3) > Vref > V(EA+), and the error amplifier EA outputs a low level to the logic drive control circuit, causing the GATE pin to output a low signal. This means the boost circuit stops supplying power to the LED tube, resulting in no current flowing through the LED tube and a black screen. At this point, the average operating current of the LED tube, Iled(av), = Vref*D1*D2*(Rdim1+Rdim2) / Rdim2 / Rfb.

[0072] Specifically, the LPWM output port of the image processor of the main substrate outputs a high level in the non-MPRT working mode. In the MPRT working mode, the LPWM output port outputs an LPWM signal synchronized with the vertical frequency of the liquid crystal display. The HPWM port of the image processor of the main substrate outputs an HPWM dimming signal, and the frequency of the HPWM dimming signal is greater than the frequency of the LPWM signal. When the vertical frequency synchronization signal of the LPWM is at a logic high level, the display screen is bright, and when the vertical frequency synchronization signal of the LPWM is at a logic low level, the display screen is black. This is called LPWM positive logic dimming. That is, the specific working sequence is as follows:

[0073] t0 time: the display is in standby mode, the switch control signal output by the ENA enable port of the image processor on the main substrate inside the display is low, and the LED light does not work;

[0074] Time t1: The display enters the non-MPRT working mode. The ENA enable port of the image processor of the main substrate outputs a continuous high-level signal. The ADIM pin of the backlight driver chip receives the HPWM dimming signal output by the HPWM port of the image processor of the main substrate. The signal is converted into a DC dimming signal through the PWM-to-DC circuit inside the backlight driver chip. The LPWM port of the image processor of the main substrate outputs a continuous high-level signal, and the second transistor Q2 is turned on. At this time, the LED lamp current Iled=Vref*D1*(Rdim1+Rdim2) / Rdim2 / Rfb, where: Vref is a reference voltage inside the backlight driver chip, D1 is the duty cycle of the HPWM dimming signal, Rdim1 is the resistance of the Rdim1 resistor, Rdim2 is the resistance of the Rdim2 resistor, and Rfb is the resistance of the Rfb resistor.

[0075] t2 time: The display enters MPRT working mode. At this time, the ENA enable port of the image processor of the main substrate outputs a continuous high-level signal, and the ADIM pin of the backlight driver chip receives the HPWM dimming signal with a duty cycle greater than that in the non-MPRT working mode, ensuring that the LCD display still has a brighter display screen when entering the MPRT working mode; the LPWM signal output by the LPWM port of the image processor of the main substrate is the field frequency synchronization signal. When the field frequency synchronization signal of LPWM is a logic low level, the LED lamp has no output current and the screen is black; when the field frequency synchronization signal of LPWM is a logic high level, a peak current is output. The peak current of the LED lamp Iled (Peak) = Vref*D1*(Rdim1+Rdim2) / Rdim2 / Rfb, and the screen is bright. Set the circuit parameters so that V1*Rdim1 / (Rdim1+Rdim2+ Rdim3)>Vref, so that when the LPWM signal is at a logic low level, the second transistor Q2 is turned off, and the LED lamp has no output current (a dark screen), wherein V1 is a power supply voltage, Vref is a reference voltage inside the backlight driver chip, D1 is the duty cycle of the HPWM dimming signal, Rdim1 is the resistance value of the Rdim1 resistor, Rdim2 is the resistance value of the Rdim2 resistor, Rdim3 is the resistance value of the Rdim3 resistor, and Rfb is the resistance value of the Rfb resistor.

[0076] The specific principle of the present invention is described in detail below:

[0077] refer to Figure 2 The backlight driver chip U2 includes the following functional pins: power supply VDD pin, drive GATE pin, MOS tube Q1 current detection CS pin, reference ground GND pin, LED lamp current detection feedback FB pin and PWM to DC dimming ADIM pin.

[0078] The input end of the AC-DC converter is electrically connected to a mains AC power supply interface, the output port of the AC-DC converter is electrically connected to one end of a resistor Rvdd, the positive end of a polarized capacitor C1, and one end of a boost inductor L1, the other end of the resistor Rvdd is electrically connected to the power supply VDD pin of the backlight driver chip, and the negative end of the polarized capacitor C1 is grounded; the other end of the boost inductor L1 is electrically connected to the drain of the N-channel MOS transistor Q1 and the positive end of the boost diode D1, the negative end of the boost diode D1 is electrically connected to the positive end of the capacitor C2 and the input end of the LED lamp tube, the negative end of the capacitor C2 is grounded, the gate of the N-channel MOS transistor Q1 is electrically connected to the drive GATE pin of the backlight driver chip, the source of the N-channel MOS transistor Q1 is electrically connected to one end of the resistor Rcs and the current detection CS pin of the MOS transistor Q1, and the other end of the resistor Rcs is grounded; The output end of the LED lamp is electrically connected to one end of the current sampling resistor Rfb and one end of the resistor Rdim1, the other end of the current sampling resistor Rfb is grounded, the other end of the resistor Rdim1 is electrically connected to the FB pin of the backlight driver chip and one end of the resistor Rdim2, and the other end of the resistor Rdim2 is electrically connected to an LPWM output port of the main substrate image processor; the GND pin of the backlight driver chip is grounded; the PWM to DC dimming ADIM pin of the backlight driver chip is electrically connected to the HPWM port of the image processor of the main substrate and the positive electrode of the diode D2, and the negative electrode of the diode D2 is electrically connected to the ENA enable pin output port of the image processor of the main substrate; the ADIM pin of the backlight driver chip is electrically connected to one port of the PWM to DC circuit inside the backlight driver chip, the other port of the PWM to DC circuit is electrically connected to the non-inverting input end of the error amplifier EA inside the backlight driver chip, the inverting input end of the error amplifier EA is electrically connected to the FB pin of the backlight driver chip, the output end of the error amplifier EA, the VDD pin, the GATE pin, and the CS pin are electrically connected to the logic drive control circuit inside the backlight driver chip.

[0079] Mains AC power (e.g., 220V / 50Hz) is converted to DC power (e.g., 19V) via an AC-DC converter. This DC power is then boosted by a boost circuit consisting of inductor L1, MOS transistor Q1, diode D1, polarized capacitors C1 and C2, and a backlight driver chip to generate the 30V-60V DC power required for LED lamps. The current at the LED lamp's output is sampled by current sampling resistor Rfb, divided by resistors Rdim1 and Rdim2, and controlled by an LPWM signal before being supplied to the FB pin of the backlight driver chip for current dimming control. The main board's image processor outputs an HPWM signal to the ADIM pin of the backlight driver chip. The chip's internal PWM-to-DC circuit then performs voltage conversion to generate a DC dimming signal, which is supplied to the non-inverting input of the error amplifier EA within the backlight driver chip to control the LED lamp current.

[0080] When the LPWM output port is in non-MPRT working mode, the output is a low level; when the LPWM output port is in MPRT working mode, it outputs an LPWM signal synchronized with the LCD field frequency (also known as frame frequency or refresh frequency, generally around 75HZ~520HZ).

[0081] In non-MPRT working mode, the dimming working principle is: the LPWM port keeps outputting a low-level signal, and the HPWM port of the image processor of the main substrate outputs a HPWM dimming signal with a higher frequency of 10KHZ or above. The HPWM dimming signal is received by the ADIM pin of the backlight driver chip and converted into a voltage V(EA+)=Vref*D1 (where Vref is a reference voltage inside the U2 chip, and D1 is the duty cycle of the HPWM dimming) by the PWM to DC circuit inside the chip. According to the virtual short characteristic of the input terminal of the error amplifier EA,

[0082] That is: V(EA+)= V(EA-)=Vref*D1, LED lamp current Iled=Vref*D1*(Rdim1+Rdim2) / Rdim2 / Rfb.

[0083] When entering the MPRT working mode, the dimming working principle is: the LPWM port of the image processor of the main substrate outputs a field frequency signal with an operating frequency of about 75HZ~520HZ, and the HPWM port of the image processor of the main substrate outputs a HPWM dimming signal with a higher frequency of 10KHZ and above for mixed dimming. a. When LPWM is at a logic high level, a voltage Vref higher than the FB reference voltage is applied to FB, causing the backlight driver chip to not drive, the LED lamp to have no output current, and the display screen to be black. b. When LPWM is at a logic low level, a peak current is output, and the display screen is bright. Iled (Peak) = Vref * D1 * (Rdim1 + Rdim2) / Rdim2 / Rfb. Set the circuit parameters so that VLPWM * Rdim1 / (Rdim1 + Rdim2) > Vref, so that when the LPWM signal is at a logic high level, the LED lamp has no output current (the screen is dark). In MPRT working mode, the average current of the LED lamp is Iled (av) = (1-D2) * Vref*D1*(Rdim1+Rdim2) / Rdim2 / Rfb (where: D2 is the duty cycle of the LPWM field frequency synchronization signal, Vref is a reference voltage inside the backlight driver chip, D1 is the duty cycle of the HPWM dimming signal, Rdim1 is the resistance value of the Rdim1 resistor, Rdim2 is the resistance value of the Rdim2 resistor, and Rfb is the resistance value of the Rfb resistor; when LPWM is a logic low level, the display screen is bright, and when LPWM is a logic high level, the display screen is black, which is called LPWM reverse logic dimming.

[0084] The LPWM signal continuously turns the backlight on and off at a frequency synchronized with the vertical frequency, inserting a black screen between each frame (a black screen appears when the backlight is off), thereby eliminating the problem of ghosting caused by persistence of vision. The principle is that a black screen appears between adjacent frames. This way, after persistence of vision, the resulting image has been "cleared" by the black screen, allowing for smooth, continuous motion without ghosting.

[0085] The present invention can implement the MPRT function based on an existing, inexpensive, 6-pin, non-MPRT IC packaged in a SOT-26 package. Compared to existing dedicated MPRT ICs that use an SOP-8 package and incorporate a DIM-MOS transistor, the IC cost is estimated to be reduced by approximately 25% to 30%. The present invention can also incorporate the Q1 MOS transistor into the backlight driver chip. If a boost-type backlight driver chip with an integrated N-channel MOS transistor Q1 is used, the chip includes the following pin functions: a power supply VDD pin, an N-channel MOS transistor Q1 drain pin, a reference ground GND pin, an LED lamp current detection feedback FB pin, and a PWM-to-DC dimming ADIM pin.

[0086] like Figure 3 As shown, as a feasible implementation, if Rfb=0.47Ω, Rdim1=1KΩ, Rdim2=4.7KΩ, Vref inside U2=0.4V.

[0087] t0 time: The display is in standby mode, the switch control signal output by the image processor ENA enable port of the main substrate inside the display is low, and the LED light does not work.

[0088] t1 time: The display enters non-MPRT working mode. At this time, the EN enable port outputs a continuous high-level signal, ADIM receives a PWM dimming signal with a frequency greater than 10KHZ and above, and the backlight driver chip U2 starts to work normally. The PWM to DC circuit inside the backlight driver chip U2 converts it into a DC dimming signal. The LPWM port of the image processor on the main substrate outputs a continuous low-level signal. At this time, the current of the LED lamp tube Iled=Vref*D1*(Rdim1+Rdim2) / Rdim2 / Rfb, where: Vref is a reference voltage inside the backlight driver chip, D1 is the duty cycle of the HPWM dimming signal, Rdim1 is the resistance value of the Rdim1 resistor, Rdim2 is the resistance value of the Rdim2 resistor, and Rfb is the resistance value of the Rfb resistor.

[0089] If HPWM Duty D1=50%, the LED lamp operating current.

[0090] Iled=Vref*D1*(Rdim1+Rdim2) / Rdim2 / Rfb

[0091] =0.4V*50%*(1KΩ+4.7KΩ) / 4.7KΩ / 0.47Ω

[0092] =516mA.

[0093] t2 time: The display enters MPRT working mode. At this time, the ENA enable port of the image processor of the main substrate outputs a continuous high-level signal, and the ADIM pin of the backlight driver chip receives the HPWM dimming signal with a duty cycle greater than that in the non-MPRT working mode, ensuring that the LCD display still has a brighter display screen when entering the MPRT working mode; the LPWM signal output by the LPWM port of the image processor of the main substrate is the field frequency synchronization signal. When the field frequency synchronization signal of LPWM is a logic high level, the LED lamp has no output current and the screen is black; when the field frequency synchronization signal of LPWM is a logic low level, a peak current is output. The peak current of the LED lamp Iled (Peak) = Vref*D1*(Rdim1+Rdim2) / Rdim2 / Rfb, and the screen is bright. Set the circuit parameters so that VLPWM* Rdim1 / (Rdim1+Rdim2)>Vref, so that when the LPWM signal is at a logic high level, the LED lamp has no output current (a dark screen). VLPWM is the LPWM logic high voltage, Vref is a reference voltage inside the backlight driver chip, D1 is the duty cycle of the HPWM dimming signal, Rdim1 is the resistance of the Rdim1 resistor, Rdim2 is the resistance of the Rdim2 resistor, and Rfb is the resistance of the Rfb resistor.

[0094] If HPWM Duty D1 = 90%, LPWM Duty D2 = 45%, then the peak current of the LED tube is:

[0095] Iled(Peak)=Vref*D1*(Rdim1+Rdim2) / Rdim2 / Rfb

[0096] =0.4V*90%*(1KΩ+4.7KΩ) / 4.7KΩ / 0.47Ω

[0097] =929mA;

[0098] Then the average current of the LED lamp is:

[0099] Iled(av)=(1-D2)* Vref*D1*(Rdim1+Rdim2) / Rdim2 / Rfb

[0100] = (1-45%)*0.4V*90%*(1KΩ+4.7KΩ) / 4.7KΩ / 0.47Ω

[0101] =510mA

[0102] LPWM uses inverse logic dimming: the output end of the LED lamp is electrically connected to one end of the current sampling resistor Rfb and one end of the resistor Rdim1, the other end of the resistor Rfb is grounded, the other end of the resistor Rdim1 is electrically connected to the FB pin of the backlight driver chip U2 and one end of the resistor Rdim2, and the other end of the resistor Rdim2 is electrically connected to an LPWM output port of the main substrate image processor. When the LPWM output port is in non-MPRT working mode, the output is a low level; when in MPRT working mode, the LPWM output port outputs an LPWM signal synchronized with the field frequency of the liquid crystal display.

[0103] Furthermore, if Figure 4 or Figure 5 As shown, as another embodiment, based on Example 1, further includes a resistor Rdim3 and an N-channel MOS transistor Q2. The output end of the LED lamp is electrically connected to one end of the current sampling resistor Rfb and one end of the resistor Rdim1. The other end of the resistor Rfb is grounded. The other end of the resistor Rdim1 is electrically connected to the FB pin of the backlight driver chip U2 and one end of the resistor Rdim2. The other end of the resistor Rdim2 is electrically connected to one end of the resistor Rdim3 and the drain of the N-channel MOS transistor Q2. The other end of the resistor Rdim3 receives a voltage source of voltage V1. The source of the N-channel MOS transistor Q2 is grounded. The gate of the N-channel MOS transistor Q2 is electrically connected to an LPWM output port of the main substrate image processor. This LPWM output port outputs a high level in non-MPRT operating mode; in MPRT operating mode, this LPWM output port outputs an LPWM signal synchronized with the LCD field frequency. This alternative solution is to set the MPRT dimming signal synchronized with the LPWM field frequency to normal logic control. Furthermore, the second transistor is an N-channel MOS transistor Q2. The input pin of the second transistor is the drain of the N-channel MOS transistor Q2 , and the output pin of the second transistor is the source of the N-channel MOS transistor Q2 .

[0104] Q2 N-channel MOS can also be replaced by an NPN transistor, and the corresponding drain, source, and gate of the N-channel MOS are changed to the collector, emitter, and base of the NPN transistor.

[0105] Specifically, if LPWM uses normal logic dimming: the output end of the LED lamp tube is electrically connected to one end of the current sampling resistor Rfb and one end of the resistor Rdim1, the other end of the resistor Rfb is grounded, the other end of the resistor Rdim1 is electrically connected to the FB pin of the backlight driver chip U2 and one end of the resistor Rdim2, the other end of the resistor Rdim2 is electrically connected to one end of the resistor Rdim3 and the drain of the Q2 N-channel MOS, the other end of the resistor Rdim3 receives a voltage source with a voltage of V1, the source of the Q2 N-channel MOS is grounded, and the gate of the Q2 N-channel MOST tube is electrically connected to an LPWM output port of the main substrate image processor. When the LPWM output port is in non-MPRT working mode, the output is a high level; when the LPWM output port is in MPRT working mode, it outputs an LPWM signal synchronized with the field frequency of the liquid crystal display.

[0106] Another embodiment corresponds to a control method for a boost backlight drive circuit that implements an MPRT function, comprising: an LPWM output port outputting a high level in a non-MPRT operating mode; and an LPWM signal synchronized with the field frequency of a liquid crystal display in the MPRT operating mode; an HPWM port of an image processor on a main substrate outputting an HPWM dimming signal, wherein the frequency of the HPWM dimming signal is greater than the frequency of the LPWM signal; and when the field frequency synchronization signal of the LPWM is at a logic high level, the display screen is bright, and when the field frequency synchronization signal of the LPWM is at a logic low level, the display screen is black, which is referred to as LPWM positive logic dimming.

[0107] Specifically, when the LPWM signal is at a logic high level, the MOS tube Q2 is turned on, the LED tube peak current Iled (Peak) = Vref*D1*(Rdim1+Rdim2) / Rdim2 / Rfb, and the LCD screen is bright.

[0108] When the LPWM signal is at a logic low, MOS transistor Q2 is turned off. The inverting input terminal of the error amplifier EA inside the backlight driver chip, V(EA-) = V1*Rdim1 / (Rdim1+Rdim2+Rdim3) > Vref > V(EA+), and the error amplifier EA outputs a low level to the logic drive control circuit, causing the GATE pin to output a low signal. This means the boost circuit stops supplying power to the LED tube, resulting in no current flowing through the LED tube and a black screen. At this point, the average operating current of the LED tube, Iled(av), = Vref*D1*D2*(Rdim1+Rdim2) / Rdim2 / Rfb.

[0109] like Figure 5 As shown in FIG. 1 , as another feasible implementation, if Rfb=0.47Ω, Rdim1=1KΩ, Rdim2=4.7KΩ, Vref inside U2=0.4V.

[0110] t0 time: The display is in standby mode, the switch control signal output by the image processor ENA enable port of the main substrate inside the display is low, and the LED light does not work.

[0111] t1 time: The display enters non-MPRT working mode. At this time, the EN enable port outputs a continuous high-level signal, ADIM receives a PWM dimming signal with a frequency greater than 10KHZ and above, and the backlight driver chip U2 starts to work normally. The PWM to DC circuit inside the backlight driver chip U2 converts it into a DC dimming signal. The LPWM port of the image processor on the main substrate outputs a continuous high-level signal. At this time, the current of the LED lamp tube Iled=Vref*D1*(Rdim1+Rdim2) / Rdim2 / Rfb, where: Vref is a reference voltage inside the backlight driver chip, D1 is the duty cycle of the HPWM dimming signal, Rdim1 is the resistance value of the Rdim1 resistor, Rdim2 is the resistance value of the Rdim2 resistor, and Rfb is the resistance value of the Rfb resistor.

[0112] If HPWM Duty D1=50%, the LED lamp operating current.

[0113] Iled=Vref*D1*(Rdim1+Rdim2) / Rdim2 / Rfb

[0114] =0.4V*50%*(1KΩ+4.7KΩ) / 4.7KΩ / 0.47Ω

[0115] =516mA.

[0116] t2 time: The display enters MPRT working mode. At this time, the ENA enable port of the image processor of the main substrate outputs a continuous high-level signal, and the ADIM pin of the backlight driver chip receives the HPWM dimming signal with a duty cycle greater than that in the non-MPRT working mode, ensuring that the LCD display still has a brighter display screen when entering the MPRT working mode; the LPWM signal output by the LPWM port of the image processor of the main substrate is the field frequency synchronization signal. When the field frequency synchronization signal of LPWM is a logic low level, the LED lamp has no output current and the screen is black; when the field frequency synchronization signal of LPWM is a logic high level, a peak current is output. The peak current of the LED lamp Iled (Peak) = Vref*D1*(Rdim1+Rdim2) / Rdim2 / Rfb, and the screen is bright. Set the circuit parameters so that V1*Rdim1 / (Rdim1+Rdim2+ Rdim3)>Vref, so that when the LPWM signal is at a logic low level, the second transistor Q2 is turned off, and the LED lamp has no output current (a dark screen). V1 is a voltage source, Vref is a reference voltage inside the backlight driver chip, D1 is the duty cycle of the HPWM dimming signal, Rdim1 is the resistance of the Rdim1 resistor, Rdim2 is the resistance of the Rdim2 resistor, Rdim3 is the resistance of the Rdim3 resistor, and Rfb is the resistance of the Rfb resistor.

[0117] If HPWM Duty D1 = 90%, LPWM Duty D2 = 55%, then the peak current of the LED tube is:

[0118] Iled(Peak)=Vref*D1*(Rdim1+Rdim2) / Rdim2 / Rfb

[0119] =0.4V*90%*(1KΩ+4.7KΩ) / 4.7KΩ / 0.47Ω

[0120] =929mA;

[0121] Then the average current of the LED lamp is:

[0122] Iled(av)=Vref*D1*D2*(Rdim1+Rdim2) / Rdim2 / Rfb

[0123] =0.4V*90%*55%*(1KΩ+4.7KΩ) / 4.7KΩ / 0.47Ω

[0124] =510mA

[0125] The output end of the LED lamp tube is electrically connected to one end of the current sampling resistor Rfb and one end of the resistor Rdim1, the other end of the resistor Rfb is grounded, the other end of the resistor Rdim1 is electrically connected to the FB pin of the backlight driver chip U2 and one end of the resistor Rdim2, the other end of the resistor Rdim2 is electrically connected to one end of the resistor Rdim3 and the drain of the Q2 N-channel MOS, the other end of the resistor Rdim3 receives a voltage source with a voltage of V1, the source of the Q2 N-channel MOS is grounded, and the gate of the Q2 N-channel MOST tube is electrically connected to an LPWM output port of the main substrate image processor. When the LPWM output port is in non-MPRT working mode, the output is a high level; when the LPWM output port is in MPRT working mode, it outputs an LPWM signal synchronized with the field frequency of the liquid crystal display.

[0126] The present invention employs the above technical solution and has the following technical features: 1) It utilizes an existing non-MPRT boost-type backlight driver chip, such as a small 6-pin SOT-26 IC, which has a power supply VDD pin, a driver GATE pin, a CS pin for current detection of the MOS tube Q1, a reference ground GND pin, an FB pin for current detection and feedback of the LED lamp current, and an ADIM pin for PWM-to-DC dimming. 2) The LED lamp output is electrically connected to one end of a current sampling resistor Rfb and one end of a resistor Rdim1. The other end of resistor Rfb is grounded. The other end of resistor Rdim1 is electrically connected to the FB pin of the backlight driver chip U2 and one end of resistor Rdim2. The other end of resistor Rdim2 is electrically connected to an LPWM output port of the main substrate image processor. This LPWM output port outputs a low level in non-MPRT operating mode. In MPRT operating mode, this LPWM output port outputs an LPWM signal synchronized with the LCD field frequency (also known as the frame rate or refresh rate, generally between 75 Hz and 520 Hz). 3) Dimming working principle in non-MPRT working mode: the LPWM port keeps outputting a low-level signal, and the HPWM port of the image processor of the main substrate outputs an HPWM dimming signal with a higher frequency of 10KHZ or above. The HPWM dimming signal is received by the ADIM pin of the chip U2 and converted by the PWM to DC circuit inside the chip into a voltage V(EA+)=Vref*D1 (where Vref is a reference voltage inside the U2 chip, and D1 is the duty cycle Duty of the HPWM dimming). According to the virtual short characteristic of the input terminal of the error amplifier EA, that is: V(EA+)= V(EA-)=Vref*D1; the current of the LED lamp tube Iled=Vref*D1*(Rdim1+Rdim2) / Rdim2 / Rfb. 4) When entering MPRT working mode, the dimming working principle is as follows: the LPWM port of the image processor of the main substrate outputs a field frequency signal with an operating frequency of about 75HZ~520HZ, and the HPWM port of the image processor of the main substrate outputs a HPWM dimming signal with a higher frequency of 10KHZ and above for mixed dimming.a. When LPWM is at a logic high level, a voltage Vref higher than the FB reference voltage is imposed on FB, causing chip U2 to not be driven, the LED tube to have no output current, and the screen to be black. b. When LPWM is at a logic low level, a peak current is output, and the screen to be bright. Iled (Peak) = Vref * D1 * (Rdim1 + Rdim2) / Rdim2 / Rfb. The circuit parameters are set so that VLPWM * Rdim1 / (Rdim1 + Rdim2) > Vref. This way, when the LPWM signal is at a logic high level, the LED tube has no output current (the screen to be dark). In MPRT working mode, the average current of the LED tube is Iled (av) = (1-D2) * Vref * D1 * (Rdim1 + Rdim2) / Rdim2 / Rfb (where D2 is the duty cycle of the LPWM vertical frequency synchronization signal) is used. When LPWM is at a logic low level, the display is bright, and when LPWM is at a logic high level, the display is black. This is called LPWM inverse logic dimming. 5) The LPWM signal continuously turns the backlight on and off at a frequency synchronized with the vertical frequency, inserting a black screen between each frame (backlight off results in a black screen), thereby addressing the problem of image smear caused by persistence of vision. The principle is that a black screen appears between adjacent frames. This way, after persistence of vision, the resulting image has been "cleared" by the black screen, resulting in smooth, continuous motion without artifacts.

[0127] This invention can implement the MPRT function using existing, inexpensive, 6-pin, non-MPRT ICs in SOT-26 packages. Compared to existing dedicated MPRT ICs in SOP-8 packages with integrated DIM-MOS, the IC cost is estimated to be reduced by approximately 25% to 30%.

[0128] Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. In the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of the present application is not intended to limit the scope of the application for protection, but merely represents the selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

Claims

1. A boost backlight driving circuit for realizing MPRT function, characterized in that: It includes an AC-DC converter, a backlight driver chip, and a boost circuit. The backlight driver chip has a power supply VDD pin, a drive GATE pin, a first transistor current detection CS pin, a reference ground GND pin, an LED lamp current detection feedback FB pin, and a PWM to DC dimming ADIM pin. The input end of the AC-DC converter is electrically connected to the mains AC power supply interface, and the output port of the AC-DC converter is respectively connected to the power supply VDD pin of the backlight driver chip and the input end of the boost circuit; the output end of the boost circuit is electrically connected to the input end of the LED lamp tube; the boost circuit has a control end and a current detection end, the control end of the boost circuit is electrically connected to the driving GATE pin of the backlight driver chip; the current detection end of the boost circuit is electrically connected to the current detection CS pin of the first transistor of the backlight driver chip; the AC-DC converter converts the mains AC power into a first DC power; the boost circuit boosts the first DC power to obtain the second DC power required by the LED lamp tube; the LED lamp tube output The ends are electrically connected to one end of the current sampling resistor Rfb and one end of the resistor Rdim1, the other end of the current sampling resistor Rfb is grounded, the other end of the resistor Rdim1 is electrically connected to the LED lamp current detection feedback FB pin of the backlight driver chip and one end of the resistor Rdim2, and the other end of the resistor Rdim2 is electrically connected to an LPWM output port of the main substrate image processor; the reference ground GND pin of the backlight driver chip is grounded; the PWM to DC dimming ADIM pin of the backlight driver chip is electrically connected to the HPWM port of the image processor of the main substrate and the anode of the diode D2, and the cathode of the diode D2 is electrically connected to the ENA enable pin output port of the image processor of the main substrate; The backlight driver chip integrates a logic drive control circuit, a PWM to DC circuit, and an error amplifier EA. The PWM to DC dimming ADIM pin is electrically connected to one port of the PWM to DC circuit, the other port of the PWM to DC circuit is electrically connected to the non-inverting input of the error amplifier EA, and the inverting input of the error amplifier EA is electrically connected to the LED lamp current detection feedback FB pin of the backlight driver chip; the power supply VDD pin, the drive GATE pin, the first transistor current detection CS pin, and the output of the error amplifier EA of the backlight driver chip are electrically connected to the logic drive control circuit; Among them, the boost circuit includes a first transistor, a polar capacitor C1, a boost inductor L1, a boost diode D1, a capacitor C2 and a resistor Rcs; the output port of the AC-DC converter is electrically connected to the positive end of the polar capacitor C1 and one end of the boost inductor L1, respectively, and the negative end of the polar capacitor C1 is grounded; the other end of the boost inductor L1 is electrically connected to the input pin of the first transistor and the positive electrode of the boost diode D1, respectively; the negative electrode of the boost diode D1 is electrically connected to the positive electrode of the capacitor C2 and the input end of the LED lamp tube, respectively; the negative electrode of the capacitor C2 is grounded, the gate pin of the first transistor serves as the control end of the boost circuit and is electrically connected to the drive GATE pin of the backlight driver chip, the output pin of the first transistor is electrically connected to one end of the resistor Rcs and the first transistor current detection CS pin of the backlight driver chip, respectively, and the other end of the resistor Rcs is grounded.

2. The boost backlight driving circuit for realizing MPRT function according to claim 1, characterized in that: The output port of the AC-DC converter is electrically connected to the power supply VDD pin of the backlight driver chip through the resistor Rvdd.

3. The boost backlight driving circuit for realizing MPRT function according to claim 1, characterized in that: The first transistor is an N-channel MOS transistor Q1 , an input pin of the first transistor is a drain of the N-channel MOS transistor Q1 , and an output pin of the first transistor is a source of the N-channel MOS transistor Q1 .

4. The boost backlight driving circuit for realizing MPRT function according to claim 1, characterized in that: The LPWM output port of the main substrate image processor outputs an LPWM signal of 75HZ~520HZ; the HPWM port of the main substrate image processor outputs an HPWM signal of 10KHZ and above.

5. The boost backlight driving circuit for realizing MPRT function according to claim 1, characterized in that: The current output from the LED lamp output terminal is sampled by the sampling resistor Rfb, then divided by resistors Rdim1 and Rdim2, and provided to the FB pin of the backlight driver chip for current dimming control after being controlled by the LPWM signal. The image processor on the main substrate outputs an HPWM signal to the ADIM pin of the backlight driver chip. The PWM-to-DC circuit performs voltage conversion to generate a DC dimming signal, which is provided to the non-inverting input of the error amplifier EA to control the LED lamp current.

6. The boost backlight driving circuit for realizing MPRT function according to claim 1, characterized in that: It also includes a resistor Rdim3 and a second transistor, the other end of the resistor Rdim2 is electrically connected to one end of the resistor Rdim3 and the input pin of the second transistor respectively, the other end of the resistor Rdim3 receives a voltage source with a voltage of V1, the output pin of the second transistor is grounded, and the gate pin of the second transistor is electrically connected to an LPWM output port of the main substrate image processor; the LPWM output port outputs a high level in non-MPRT working mode; the LPWM output port outputs an LPWM signal synchronized with the field frequency of the liquid crystal display in MPRT working mode.

7. The boost backlight driving circuit for realizing MPRT function according to claim 6, characterized in that: The second transistor is an N-channel MOS transistor Q2; the input pin of the second transistor is the drain of the N-channel MOS transistor Q2, and the output pin of the second transistor is the source of the N-channel MOS transistor Q2.

8. A control method for a boost backlight driving circuit for realizing MPRT function, characterized in that: A boost-type backlight driving circuit for realizing an MPRT function according to any one of claims 1 to 5, wherein the method is as follows: an LPWM output port of an image processor of a main substrate outputs a low level in a non-MPRT operating mode, and an LPWM output port outputs an LPWM signal synchronized with the field frequency of a liquid crystal display in the MPRT operating mode; an HPWM port of the image processor of the main substrate outputs an HPWM dimming signal, wherein the frequency of the HPWM dimming signal is greater than the frequency of the LPWM signal; when the field frequency synchronization signal of the LPWM is at a logic low level, the display screen is bright, and when the field frequency synchronization signal of the LPWM is at a logic high level, the display screen is black, which is referred to as LPWM inverse logic dimming; that is, the specific operating sequence is as follows: t0 time: the display is in standby mode, the switch control signal output by the ENA enable port of the image processor on the main substrate inside the display is low, and the LED light does not work; Time t1: The display enters the non-MPRT working mode. The ENA enable port of the main substrate's image processor outputs a continuous high-level signal. The ADIM pin of the backlight driver chip receives the HPWM dimming signal output by the HPWM port of the main substrate's image processor, which is converted into a DC dimming signal through the PWM-to-DC circuit inside the backlight driver chip. The LPWM port of the main substrate's image processor outputs a continuous low-level signal. At this time, the LED lamp current Iled=Vref*D1*(Rdim1+Rdim2) / Rdim2 / Rfb, where: Vref is a reference voltage inside the backlight driver chip, D1 is the duty cycle of the HPWM dimming signal, Rdim1 is the resistance of the Rdim1 resistor, Rdim2 is the resistance of the Rdim2 resistor, and Rfb is the resistance of the Rfb resistor. t2 time: The display enters MPRT working mode. At this time, the ENA enable port of the image processor of the main substrate outputs a continuous high-level signal, and the ADIM pin of the backlight driver chip receives the HPWM dimming signal with a duty cycle greater than that in the non-MPRT working mode, ensuring that the LCD display still has a brighter display screen when entering the MPRT working mode; the LPWM signal output by the LPWM port of the image processor of the main substrate is the field frequency synchronization signal. When the field frequency synchronization signal of LPWM is a logic high level, the LED lamp has no output current and the screen is black; when the field frequency synchronization signal of LPWM is a logic low level, a peak current is output. The peak current of the LED lamp Iled (Peak) = Vref*D1*(Rdim1+Rdim2) / Rdim2 / Rfb, and the screen is bright. Set the circuit parameters so that VLPWM* Rdim1 / (Rdim1+Rdim2)>Vref, so that when the LPWM signal is at a logic high level, the LED lamp has no output current, resulting in a dark screen. VLPWM is the LPWM logic high voltage, Vref is a reference voltage inside the backlight driver chip, D1 is the duty cycle of the HPWM dimming signal, Rdim1 is the resistance of the Rdim1 resistor, Rdim2 is the resistance of the Rdim2 resistor, and Rfb is the resistance of the Rfb resistor.

9. A control method for a boost backlight driving circuit for realizing MPRT function, characterized in that: A boost-type backlight driving circuit for realizing the MPRT function according to claim 6 is applicable, wherein: the LPWM output port of the image processor of the main substrate outputs a high level in a non-MPRT operating mode, and the LPWM output port outputs an LPWM signal synchronized with the field frequency of the liquid crystal display in the MPRT operating mode; the HPWM port of the image processor of the main substrate outputs an HPWM dimming signal, the frequency of the HPWM dimming signal being greater than the frequency of the LPWM signal; when the field frequency synchronization signal of the LPWM is at a logic high level, the display screen is bright, and when the field frequency synchronization signal of the LPWM is at a logic low level, the display screen is black, which is referred to as LPWM positive logic dimming; that is, the specific operating sequence is: t0 time: the display is in standby mode, the switch control signal output by the ENA enable port of the image processor on the main substrate inside the display is low, and the LED light does not work; Time t1: The display enters the non-MPRT working mode. The ENA enable port of the image processor of the main substrate outputs a continuous high-level signal. The ADIM pin of the backlight driver chip receives the HPWM dimming signal output by the HPWM port of the image processor of the main substrate. The signal is converted into a DC dimming signal through the PWM-to-DC circuit inside the backlight driver chip. The LPWM port of the image processor of the main substrate outputs a continuous high-level signal. The second transistor Q2 is turned on. At this time, the current of the LED lamp tube Iled=Vref*D1*(Rdim1+Rdim2) / Rdim2 / Rfb, where: Vref is a reference voltage inside the backlight driver chip, D1 is the duty cycle of the HPWM dimming signal, Rdim1 is the resistance of the Rdim1 resistor, Rdim2 is the resistance of the Rdim2 resistor, and Rfb is the resistance of the Rfb resistor. t2 time: The display enters MPRT working mode. At this time, the ENA enable port of the image processor of the main substrate outputs a continuous high-level signal, and the ADIM pin of the backlight driver chip receives the HPWM dimming signal with a duty cycle greater than that in the non-MPRT working mode, ensuring that the LCD display still has a brighter display screen when entering the MPRT working mode; the LPWM signal output by the LPWM port of the image processor of the main substrate is the field frequency synchronization signal. When the field frequency synchronization signal of LPWM is a logic low level, the LED lamp has no output current and the screen is black; when the field frequency synchronization signal of LPWM is a logic high level, a peak current is output. The peak current of the LED lamp Iled (Peak) = Vref*D1*(Rdim1+Rdim2) / Rdim2 / Rfb, and the screen is bright. Set the circuit parameters so that V1*Rdim1 / (Rdim1+Rdim2+ Rdim3)>Vref, so that when the LPWM signal is at a logic low level, the second transistor Q2 is turned off, the LED lamp tube has no output current, and the screen is dark, wherein V1 is a power supply voltage, Vref is a reference voltage inside the backlight driver chip, D1 is the duty cycle of the HPWM dimming signal, Rdim1 is the resistance value of the Rdim1 resistor, Rdim2 is the resistance value of the Rdim2 resistor, Rdim3 is the resistance value of the Rdim3 resistor, and Rfb is the resistance value of the Rfb resistor.

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