Semi-superjunction silicon carbide MOS device and preparation method and chip thereof

Abstract

The present application belongs to the technical field of power devices, and provides a semi-superjunction silicon carbide MOS device and a preparation method and chip thereof. A P-type well region is arranged on the left side of an N-type drift layer, and a P-type heavily doped region is arranged on the right side of the N-type drift layer. An insulating dielectric column is formed in a groove of the N-type drift layer, and the insulating dielectric column is isolated from the N-type drift layer by a P-type shielding region. Without affecting the drain-source breakdown voltage of the device, the N-type drift layer can be allowed to have a higher doping concentration, so that the device can have a better specific on-resistance. At the same time, the P-type shielding region can clamp the saturation current, and improve the short-circuit resistance of the device without affecting the on-resistance.

Description

Technical Field

[0001] The present application belongs to the technical field of power devices, and in particular, relates to a semi-superjunction silicon carbide MOS device and a preparation method and chip thereof. Background Art

[0002] Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) has become a strong competitor to silicon insulated-gate bipolar transistor (IGBT) in high-power applications such as electric vehicles and photovoltaic inverters due to its faster switching speed, lower switching loss and higher operating temperature range. Compared with IGBT, SiC MOSFET has a smaller chip area and higher current density, but this makes the heat generated by SiC MOSFET more concentrated during operation, which poses a huge challenge to device reliability.

[0003] The heat generated by SiC MOSFET is mainly concentrated in the active area within the range of 1-3μm at the top of the chip. The smaller area makes its heat dissipation ability worse. At high temperatures, SiC MOSFET no longer has an advantage over IGBT switches, and its short-circuit characteristics (SCWT) are worse. Eventually, SiC MOSFET will fail due to the high temperature of the active area causing the bipolar junction transistor (BJT) to turn on or the top metal to melt. Therefore, existing SiC MOSFETs generally have the problem of poor short-circuit capability. Summary of the invention

[0004] The embodiments of the present application provide a semi-superjunction silicon carbide MOS device and a preparation method and chip thereof, aiming to solve the problems of poor short-circuit characteristics of SiC MOSFET and high heat generated during operation.

[0005] A first aspect of an embodiment of the present application provides a semi-superjunction silicon carbide MOS device, comprising:

[0006] N-type substrate;

[0007] An N-type drift layer is formed on the front surface of the N-type substrate; wherein the N-type drift layer is a concave structure, and the height of the left side of the concave structure is greater than the height of the right side of the concave structure;

[0008] A P-type shielding region formed on the inner wall of the groove of the N-type drift layer;

[0009] An insulating dielectric column is formed in the groove of the N-type drift layer, and the insulating dielectric column is isolated from the N-type drift layer by the P-type shielding region;

[0010] A gate dielectric layer, formed on the insulating dielectric column;

[0011] a gate polysilicon layer, wrapped by the gate dielectric layer;

[0012] A P-type well region formed on a left side portion of the N-type drift layer;

[0013] An N-type heavily doped region is formed on the P-type well region;

[0014] A P-type heavily doped region is formed on the right side of the N-type drift layer;

[0015] A source layer, formed on the N-type heavily doped region, the P-type heavily doped region and the gate dielectric layer;

[0016] The drain layer is formed on the back side of the N-type substrate.

[0017] In some embodiments, the semi-super junction silicon carbide MOS device further comprises:

[0018] The first P-type buried layer is formed at one end of the P-type shielding region and contacts one end of the P-type shielding region and a left side portion of the N-type drift layer.

[0019] In some embodiments, the first P-type buried layer is disposed at a junction region between the insulating dielectric column and the gate dielectric layer.

[0020] In some embodiments, the first P-type buried layer and the P-type well region are disposed horizontally, and a width of the first P-type buried layer is smaller than a width of the P-type well region.

[0021] In some embodiments, the semi-super junction silicon carbide MOS device further comprises:

[0022] The second P-type buried layer is formed at the other end of the P-type shielding region and contacts the other end of the P-type shielding region, the right side of the N-type drift layer and the P-type heavily doped region.

[0023] In some embodiments, the width of the gate dielectric layer is greater than the width of the insulating dielectric column.

[0024] In some embodiments, the width of the gate dielectric layer decreases gradually from the source layer to the drain layer.

[0025] In some embodiments, the insulating dielectric column is silicon oxide.

[0026] A second aspect of the embodiment of the present application further provides a method for preparing a semi-superjunction silicon carbide MOS device, the method comprising:

[0027] An N-type drift layer is epitaxially generated on the front side of the N-type substrate;

[0028] In the first preset region of the N-type drift layer, P-type doping ions and N-type doping ions are sequentially implanted to form a P-type well region and an N-type heavily doped region, and P-type doping ions are implanted to form a P-type heavily doped region in the second preset region;

[0029] A gate trench is formed between the N-type heavily doped region and the P-type heavily doped region, between the P-type well region and the P-type heavily doped region, and between the N-type drift layer and the P-type heavily doped region by using a trench etching process; wherein the depth of the gate trench is less than the thickness of the P-type heavily doped region;

[0030] Continue etching in the gate trench to form a deep groove, so that the N-type drift layer has a concave structure, and form a P-type shielding region in the deep groove; wherein the P-type shielding region is formed on the inner wall of the groove of the N-type drift layer;

[0031] forming an insulating dielectric column in the deep trench, and isolating the insulating dielectric column from the N-type drift layer by the P-type shielding region;

[0032] forming a gate dielectric layer and a gate polysilicon layer in the gate trench; wherein the gate polysilicon layer is wrapped by the gate dielectric layer;

[0033] A source layer is formed on the N-type heavily doped region, the P-type heavily doped region, and the gate dielectric layer, and a drain layer is formed on the back side of the N-type substrate.

[0034] A third aspect of the embodiments of the present application further provides a chip, comprising a semi-super junction silicon carbide MOS device as described in any of the above embodiments.

[0035] The beneficial effects of the embodiments of the present application are as follows: by setting a P-type well region on the left side of the N-type drift layer, setting a P-type heavily doped region on the right side of the N-type drift layer, an insulating dielectric column is formed in the groove of the N-type drift layer, and the insulating dielectric column is isolated from the N-type drift layer by the P-type shielding region, the N-type drift layer can be allowed to have a higher doping concentration without affecting the drain-source breakdown voltage of the device, so that the device can have a better specific on-resistance, and at the same time, the P-type shielding region can clamp the saturation current, thereby improving the short-circuit resistance of the device without affecting the on-resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1a A structural schematic diagram 1 of a semi-superjunction silicon carbide MOS device provided in an embodiment of the present application;

[0037] Figure 1b A second structural diagram of a semi-superjunction silicon carbide MOS device provided in an embodiment of the present application;

[0038] Figure 1c A schematic diagram of the structure of a conventional silicon carbide MOS device provided in an embodiment of the present application;

[0039] Figure 1d Structural schematic diagram 3 of a semi-superjunction silicon carbide MOS device provided in an embodiment of the present application;

[0040] Figure 1e Schematic diagram of the structure of the semi-superjunction silicon carbide MOS device provided in the embodiment of the present application Figure 4 ;

[0041] Figure 1f Schematic diagram of the structure of the semi-superjunction silicon carbide MOS device provided in the embodiment of the present application Figure 5 ;

[0042] Figure 1g Schematic diagram of the structure of the semi-superjunction silicon carbide MOS device provided in the embodiment of the present application Figure 6 ;

[0043] Figure 2a Schematic diagram of simulation curves of drain-source avalanche voltage of a conventional planar super junction MOSFET and a semi-super junction silicon carbide MOS device in an embodiment of the present application;

[0044] Figure 2b It is a schematic diagram of a simulation curve of the threshold voltage of a conventional planar super junction MOSFET and a semi-super junction silicon carbide MOS device in an embodiment of the present application;

[0045] Figure 2c It is a schematic diagram of simulation curves of saturation current of a conventional planar super junction MOSFET and a semi-super junction silicon carbide MOS device in an embodiment of the present application;

[0046] Figure 2d Schematic diagram of simulation curves of gate charges of a conventional planar super junction MOSFET and a semi-super junction silicon carbide MOS device in an embodiment of the present application;

[0047] Figure 3a It is a schematic diagram of the simulation structure of the traditional planar super junction MOSFET;

[0048] Figure 3b Schematic diagram 1 of the simulation structure of the semi-superjunction silicon carbide MOS device in the embodiment of the present application;

[0049] Figure 3c FIG2 is a second schematic diagram of a simulation structure of a semi-superjunction silicon carbide MOS device in an embodiment of the present application;

[0050] Figure 4 It is a schematic flow chart of a method for preparing a semi-superjunction silicon carbide MOS device provided in an embodiment of the present application;

[0051] Figure 5 is a schematic diagram of forming an N-type drift layer 120 on an N-type substrate 110 provided in an embodiment of the present application;

[0052] Figure 6 It is a schematic diagram after forming a P-type well region 140, an N-type heavily doped region 150, and a P-type heavily doped region 160 according to an embodiment of the present application;

[0053] Figure 7a This is a schematic diagram 1 after forming the gate trench 101 according to an embodiment of the present application;

[0054] Figure 7b This is a second schematic diagram after the gate trench 101 is formed according to an embodiment of the present application;

[0055] Figure 8a This is a schematic diagram 1 after a deep groove is formed according to an embodiment of the present application;

[0056] Figure 8b This is a second schematic diagram after the deep groove is formed according to an embodiment of the present application;

[0057] Fig. 9 It is a schematic diagram after forming a gate dielectric layer 130 and a gate polysilicon layer 131 according to an embodiment of the present application. DETAILED DESCRIPTION

[0058] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0059] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0060] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0061] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means one or more, unless otherwise clearly and specifically defined.

[0062] SiC MOSFET has become a strong competitor to silicon insulated gate bipolar transistor (IGBT) in high-power applications such as electric vehicles and photovoltaic inverters due to its faster switching speed, lower switching loss and higher operating temperature range. Compared with IGBT, SiC MOSFET has a smaller chip area and higher current density. However, this makes the heat generated by SiC MOSFET more concentrated during operation, which poses a huge challenge to device reliability.

[0063] The heat generated by SiC MOSFET is mainly concentrated in the active area within 1-3μm at the top of the chip. The smaller area makes its heat dissipation ability worse. At high temperatures, SiC MOSFET no longer has an advantage over IGBT switches, and its short-circuit characteristics (SCWT) are worse. Eventually, SiC MOSFET will fail due to BJT conduction or melting of the top metal caused by the high temperature of the active area.

[0064] In order to solve the above technical problems, an embodiment of the present application provides a semi-superjunction silicon carbide MOS device, which can allow the N-type drift layer to have a higher doping concentration without affecting the drain-source breakdown voltage of the device, so that the device can have a better specific on-resistance. At the same time, the P-type shielding region can clamp the saturation current, thereby improving the short-circuit resistance of the device without affecting the on-resistance.

[0065] like Figure 1a As shown, in one embodiment provided in the present application, a semi-super junction silicon carbide MOS device includes: an N-type substrate 110, an N-type drift layer 120, a P-type shielding region 121, an insulating dielectric column 122, a gate dielectric layer 130, a gate polysilicon layer 131, a P-type well region 140, an N-type heavily doped region 150, a P-type heavily doped region 160, a source layer 170 and a drain layer 180.

[0066] like Figure 1aAs shown, the N-type drift layer 120 is formed on the front side of the N-type substrate 110, and the N-type drift layer 120 is a concave structure, and the height of the left side of the concave structure is greater than the height of the right side of the concave structure. The P-type shielding region 121 is formed on the inner wall of the groove of the N-type drift layer 120. The insulating dielectric column 122 is formed in the groove of the N-type drift layer 120, and the insulating dielectric column 122 is isolated from the N-type drift layer 120 by the P-type shielding region 121. The gate dielectric layer 130 is formed on the insulating dielectric column 122; the gate polysilicon layer 131 is wrapped by the gate dielectric layer 130. The P-type well region 140 is formed on the left side of the N-type drift layer 120; the N-type heavily doped region 150 is formed on the P-type well region 140; the P-type heavily doped region 160 is formed on the right side of the N-type drift layer 120; the source layer 170 is formed on the N-type heavily doped region 150, the P-type heavily doped region 160 and the gate dielectric layer 130; and the drain layer 180 is formed on the back side of the N-type substrate 110.

[0067] Since the short circuit capability (SCWT) of SiC MOSFET is strongly correlated with the saturation current, the bus voltage overshoot during short circuit will cause the current of MOSFET to quickly transition from the linear region to the saturation region. The larger the saturation current means the greater the heat generation power. High temperature will increase phonon scattering, the internal resistance of the device will increase, and the heat generation will increase, forming positive feedback, and finally leading to device failure. In this embodiment, by providing an N-type drift layer 120 with a concave structure, a P-type shielding region 121 is formed on the inner wall of the groove of the N-type drift layer 120, and an insulating dielectric column 122 is formed in the groove of the N-type drift layer 120, and the insulating dielectric column 122 is isolated from the N-type drift layer 120 by the P-type shielding region 121. With such a design, the device can allow the N-type drift layer 120 to have a higher doping concentration without affecting the drain-source breakdown voltage (BVDSS), so that the device can have a better specific on-resistance (Ronsp). At the same time, the P-type shielding region can clamp the saturation current, and improve the short circuit resistance of the device without affecting the on-resistance.

[0068] In some embodiments, the depth of the recess of the N-type drift layer 120 is at least two-thirds of the thickness of the N-type drift layer 120 .

[0069] In another embodiment provided in the present application, Figure 1b As shown, the semi-superjunction silicon carbide MOS device is further provided with a first P-type buried layer 123. The first P-type buried layer 123 is formed at one end of the P-type shielding region 121, and the first P-type buried layer 123 contacts one end of the P-type shielding region 121 and the left side of the N-type drift layer 120. Figure 1b As shown, the first P-type buried layer 123 is formed on one side of the contact surface between the insulating dielectric column 122 and the gate dielectric layer 130 .

[0070] In this embodiment, by providing the first P-type buried layer 123, and connecting the first P-type buried layer 123 to the P-type heavily doped region 160 through the P-type shielding region 121 surrounding the insulating dielectric column 122 to achieve grounding, the first P-type buried layer 123 has a better current clamping ability. Figure 1a Based on the structure, the saturation current of SiC MOSFET is further reduced without reducing the specific on-resistance (Ronsp) of the device, the trade-off relationship between on-resistance (Ron) and short-circuit capability is optimized, and the device reliability is improved.

[0071] Specifically, as shown in Table 1 below, Figure 1a , Figure 1b and Figure 1c The drain-source avalanche voltage (BVDSS), specific on-resistance (Ronsp), threshold voltage (VTH), gate charge (Qg) and saturation current (Idssat) of the three structures of SiC MOSFET are compared. It can be seen that the three devices can reach a breakdown voltage of about 2000V under the conditions shown in Table 1, wherein N-drift in Table 1 represents the doping concentration of the N-type drift layer, P-region represents the doping concentration of the P-type shielding region, GOX represents the thickness of the gate oxide, Pitch represents the cell size, Ron represents the on-resistance, Ronsp represents the specific on-resistance, BVDSS represents the drain-source avalanche voltage, VTH represents the threshold voltage, Qg represents the gate charge, and Idssat represents the saturation current. Due to the presence of the P-type shielding region 121 (P-region in Table 1) and the insulating dielectric column 122, Figure 1b The devices shown and Figure 1a The device shown in FIG. 1 allows a higher doping concentration in the N-type drift layer 120 without affecting the BVDSS, which reduces the Ronsp of the device. Figure 1a The device shown, Figure 1b The device shown has an additional first P-type buried layer 123, which increases the Ronsp of the device; Figure 1b The device shown has the lowest saturation current Idssat among the three devices (the clamping effect of the first P-type buried layer 123). Figure 1a The saturation current Idssat of the device shown is Figure 1b The saturation current Idssat of the devices shown is close, and both Idssat are much lower than Figure 1c The comparative device shown ( Figure 1c The device shown has an Idssat that is more than 50% lower).

[0072]

[0073] by Figure 1a , Figure 1b , Figure 1c The on-resistance Ron of the three structures is 40mohm for illustration, the cell size Pitch of the three structures is 3.2um, the thickness of the gate oxide GOX is 50nm, and the Figure 2a to Figure 2d As shown, the linear regions of drain current and drain voltage (IDS-VDS) of the three structures coincide. Figure 2a Curve 1 in the figure indicates Figure 1a The simulated curve of the drain-source avalanche voltage of the device shown in Figure 2a Curve 2 in the figure shows Figure 1b The simulated curve of the drain-source avalanche voltage of the device shown in Figure 2a Curve 3 in the figure shows Figure 1c Simulation curve of drain-source avalanche voltage of the device shown in .

[0074] Figure 2b Curve 1 in the figure shows Figure 1a The threshold voltage simulation curve of the device shown in Figure 2b Curve 2 in the figure shows Figure 1b The threshold voltage simulation curve of the device shown in Figure 2b Curve 3 in the figure shows Figure 1c Simulation curve of the threshold voltage of the device shown in .

[0075] Figure 2c Curve 1 in the figure indicates Figure 1a The simulation curve of the saturation current of the device shown in Figure 2c Curve 2 in the figure shows Figure 1b The simulation curve of the saturation current of the device shown in Figure 2c Curve 3 in the figure shows Figure 1c Simulation curve of the saturation current of the device shown in .

[0076] Figure 2d Curve 1 in the figure shows Figure 1a The gate charge simulation curve of the device shown in Figure 2d Curve 2 in the figure shows Figure 1b The gate charge simulation curve of the device shown in Figure 2d Curve 3 in the figure shows Figure 1c Simulation curve of gate charge of the device shown in .

[0077] When the drain-source voltage VDS=100V, Figure 1b The devices shown and Figure 1a The devices shown are all saturated, but Figure 1c The device shown still has no saturation trend; Figure 1a and Figure 1bThe device structure shown can effectively clamp the saturation current, thereby improving the short-circuit capability of the device without sacrificing the Ronsp of the device, optimizing the trade-off relationship between Ron and short-circuit capability, and improving device reliability.

[0078] In addition, since the deep trench of the present application widens the distance between the gate and the source (the grounded P-type shielding region 121), Qgs and Cgs are reduced, but there is no significant effect on the Miller platform Qgd and Cgd; as shown in FIG 2 Qg-Vgs, under the same Ron specification (40mohm), Figure 1b The devices shown and Figure 1a The total Qg of the devices shown are Figure 1c The device shown is about 23% and 32% lower. This part of the performance improvement is basically brought about by the reduction of Qgs, and Qgd has no obvious change. In contrast, the switching characteristics of the structure of the present application are significantly improved.

[0079] In addition, if Figure 3a As shown, Figure 3a for Figure 1a Schematic diagram of the simulation results of the electric field at the bottom of the gate trench of the device shown in FIG. Figure 3b Shown Figure 1b Schematic diagram of the simulation results of the electric field at the bottom of the gate trench of the device shown in FIG. Figure 3c Shown Figure 1c Schematic diagram of the simulation results of the electric field at the bottom of the gate trench of the device shown. Comparison of the electric field at the bottom of the gate trench of the three devices under the conditions shown (forward blocking), Figure 1b Due to the presence of the first P-type buried layer 123, the electric field Eox at the bottom of the gate trench of the device shown is significantly lower than Figure 1c The electric field at the bottom of the gate trench of the device shown is Figure 1a The electric field at the bottom of the gate trench of the device shown, Figure 1a The device shown has the highest electric field at the bottom of the gate trench, which challenges gate oxide reliability. Figure 1b The device shown is a structure with optimal electrical characteristics (eg, Ronsp-BVDSS relationship, switching characteristics) and reliability (eg, electric field at the bottom of the gate trench, short-circuit capability).

[0080] In one embodiment, Figure 1b As shown, the first P-type buried layer 123 is disposed at the interface between the insulating dielectric column 122 and the gate dielectric layer 130 . The first P-type buried layer 123 is located at one side of the contact surface between the gate dielectric layer 130 and the insulating dielectric column 122 .

[0081] In this embodiment, the insulating dielectric column 122 is located below the gate dielectric layer 130, and a first P-type buried layer 123 can be set in the area on one side of the contact surface between the gate dielectric layer 130 and the insulating dielectric column 122. The first P-type buried layer 123 is in contact with the gate dielectric layer 130 and the insulating dielectric column 122, respectively. A P-type heavily doped region 160 can be set in the area on the other side of the contact surface between the gate dielectric layer 130 and the insulating dielectric column 122, and the P-type heavily doped region 160 can be in contact with the gate dielectric layer 130 and the insulating dielectric column 122, respectively.

[0082] In some embodiments, the height of the insulating dielectric pillar 122 is greater than the height of the gate dielectric layer 130 .

[0083] In one embodiment, the thickness of the first P-type buried layer 123 is 0.2 μm-0.4 μm, and the peak concentration of the first P-type buried layer 123 is 1E19 cm -3 ,

[0084] In one embodiment, the width of the first P-type buried layer 123 is 0.2 μm-0.4 μm.

[0085] like Figure 1b As shown, in one embodiment, the width of the first P-type buried layer 123 may be the same as the thickness of the P-type shielding region 121 .

[0086] In one embodiment, the first P-type buried layer 123 and the P-type heavily doped region 160 have the same P-type ion doping concentration.

[0087] In another embodiment of the present application, Figure 1d As shown, the width of the first P-type buried layer 123 can be greater than the width of the P-type shielding region 121 . At this time, the first P-type buried layer 123 is horizontally arranged with the P-type well region 140 , and the width of the first P-type buried layer 123 is less than the width of the P-type well region 140 .

[0088] In another embodiment of the present application, Figure 1e As shown, the semi-superjunction silicon carbide MOS device provided in the embodiment of the present application may also be provided with a second P-type buried layer 124. The second P-type buried layer 124 is formed at the other end of the P-type shielding region 121 and contacts the other end of the P-type shielding region 121, the right side of the N-type drift layer 120 and the P-type heavily doped region 160. It should be noted that in the embodiment of the present application, Figure 1e In the structure shown, the first P-type buried layer 123 , the second P-type buried layer 124 and the P-type heavily doped region 160 have the same P-type ion doping concentration.

[0089] In some embodiments, in combination Figure 1bAs shown, the insulating dielectric column 122 is located below the gate dielectric layer 130, and a first P-type buried layer 123 can be set in the area on one side of the contact surface between the gate dielectric layer 130 and the insulating dielectric column 122, and the first P-type buried layer 123 is in contact with the gate dielectric layer 130 and the insulating dielectric column 122 respectively, and a P-type heavily doped region 160 can be set in the area on the other side of the contact surface between the gate dielectric layer 130 and the insulating dielectric column 122, and the P-type heavily doped region 160 can be in contact with the gate dielectric layer 130 and the insulating dielectric column 122 respectively, and the P-type heavily doped region 160 is connected to the P-type shielding region 121 via the second P-type buried layer 124.

[0090] In one embodiment, Figure 1e As shown, the first P-type buried layer 123 and the second P-type buried layer 124 are arranged opposite to each other, and the first P-type buried layer 123 and the second P-type buried layer 124 are respectively in contact with the two ends of the P-type shielding region 121, and are separated by the gate dielectric layer 130 and the insulating dielectric column 122. The first P-type buried layer 123 is located between the left side of the N-type drift layer 120 and one end of the P-type shielding region 121, and the second P-type buried layer 124 is located between the right side of the N-type drift layer 120 and the other end of the P-type shielding region 121, so that the width of the structure formed by the combination of the gate dielectric layer 130 and the insulating dielectric column 122 gradually decreases from the source layer 170 to the drain layer 180, presenting a stepped distribution.

[0091] In one embodiment, Figure 1f As shown, the P-type heavily doped region 160 includes a first P-type doped region 161 and a second P-type doped region 162. The first P-type doped region 161 is located below the second P-type doped region 162, and the width of the second P-type doped region 162 is smaller than that of the first P-type doped region 161. The doping concentration of the second P-type doped region 162 is greater than that of the first P-type doped region 161, and the second P-type doped region 162 does not contact the gate dielectric layer 130.

[0092] In some embodiments, in combination Figure 1f As shown, the second P-type doping region 162 is isolated from the gate dielectric layer 130 by the N-type source doping region 151, and the N-type source doping region 151 is in contact with the second P-type doping region 162 and the gate dielectric layer 130 respectively, and a PN junction is formed between the N-type source doping region 151 and the second P-type doping region 162. The normal opening of the channel on the right side of the gate can be maintained by the N-type source doping region 151. With such a design, both sides of the device can be opened. In order to balance the intervention of the N-type source doping region 151, the doping concentration of the first P-type doping region 161 needs to be set lower than the doping concentration of the second P-type doping region 162.

[0093] In some embodiments, in combination Figure 1fAs shown, a first current spreading layer 124 and a second current spreading layer 123 can be respectively provided at both ends of the P-type shielding region 121, and the first current spreading layer 124 is formed between one end of the P-type shielding region 121 and the P-type well region 140, and the first current spreading layer 124 is in contact with the P-type shielding region 121, the P-type well region 140 and the gate dielectric layer 130.

[0094] In some embodiments, in combination Figure 1f As shown, the second current spreading layer 123 may be disposed between the first P-type doping region 161 and the N-type drift layer 120 .

[0095] In some embodiments, in combination Figure 1g As shown, the semi-super junction silicon carbide MOS device in this embodiment includes multiple gate structures, wherein the multiple gate structures are alternately arranged according to deep trench structures and shallow trench structures. In this way, the device can have more channels to be turned on, thereby improving the current density of the device when it is turned on, and is also beneficial to reducing the specific on-resistance of the device.

[0096] In some embodiments, in combination Figure 1g As shown, the plurality of gate structures include a first gate structure and a second gate structure, wherein the first gate structure and Figure 1a , Figure 1b , Figure 1d , Figure 1e The gate structure of the device is the same as that of the second gate structure. Figure 1g In the embodiment, the insulating dielectric column 122 and the P-type shielding region 121 are not provided below the gate dielectric layer 230, and the first gate structure and the second gate structure are alternately provided.

[0097] In some embodiments, Figure 1g As shown, a first gate structure is arranged on one side of the P-type well region 140, and a second gate structure is arranged on the other side of the P-type well region 140, and the second gate structure includes a gate dielectric layer 230 and a gate polysilicon layer 231, and the gate polysilicon layer 231 is wrapped by the gate dielectric layer 230. On one side of the first gate structure, only the side of the first gate structure close to the P-type heavily doped region 160 can be turned on. On both sides of the second gate structure, the device conduction function can be realized, and the thick gate oxide will balance the electric field, so that the electric field lines are away from the bottom of the second gate structure, reducing the electric field strength at the bottom of the second gate structure.

[0098] In some embodiments, Figure 1a , Figure 1b , Figure 1d , Figure 1e In the device, the second current spreading layer 123 may be disposed between the P-type heavily doped region 160 and the N-type drift layer 120 .

[0099] In one embodiment, Figure 1a , Figure 1b , Figure 1d , Figure 1e As shown, the width of the gate dielectric layer 130 is greater than the width of the insulating dielectric column 122 .

[0100] In one embodiment, Figure 1a , Figure 1b , Figure 1d , Figure 1e As shown, the width of the gate dielectric layer 130 decreases gradually from the source layer 170 to the drain layer 180 .

[0101] In one embodiment, the insulating dielectric column 122 may be made of silicon oxide, and the gate dielectric layer 130 may also be made of silicon oxide. That is, the insulating dielectric column 122 and the gate dielectric layer 130 may be made of the same material.

[0102] In one embodiment, the P-type shielding region 121 is in a U-shaped structure, and an end of the U-shaped structure is flush with the right side of the N-type drift layer 120 .

[0103] In one embodiment, the insulating dielectric pillar 122 is located directly below the gate polysilicon layer 131 and has a depth of 6 μm-7 μm.

[0104] In one embodiment, the width of the insulating dielectric pillar 122 is smaller than the width of the gate dielectric layer 130 .

[0105] In one embodiment, the width of the insulating dielectric pillar 122 is 0.2 μm smaller than the width of the gate dielectric layer 130 .

[0106] In one embodiment, the material of the insulating dielectric pillar 122 is silicon oxide, silicon nitride or other insulating dielectrics.

[0107] In one embodiment, the thickness of the P-type shielding region 121 is 0.2 μm-0.4 μm, the width is 0.2 μm-0.4 μm, and the peak concentration is 2E17-4E17 cm -3 .

[0108] In the present application embodiment, the above Figure 1a The device structure shown is a semi-super junction silicon carbide MOS device that does not include the first P-type buried layer 123, that is, a structure in which the width of the first P-type buried layer 123 is 0, with better Ronsp and better short-circuit capability, but the electric field at the bottom of the gate trench is the highest and the gate oxide reliability is the worst.

[0109] Above Figure 1bThe device structure shown is a semi-superjunction silicon carbide MOS device including a first P-type buried layer 123, and the thickness of the first P-type buried layer 123 is 0.2 μm-0.4 μm, and the width is 0.2 μm-0.4 μm. Its various performances are well balanced; therefore, it is a structure with an appropriate width of the first P-type buried layer 123.

[0110] Above Figure 1d The device structure shown is a structure in which the width of the first P-type buried layer 123 is relatively wide, and the width of the first P-type buried layer 123 is greater than the width of the P-type shielding region 121. At this time, the first P-type buried layer 123 is horizontally arranged with the P-type well region 140, and the width of the first P-type buried layer 123 is less than the width of the P-type well region 140. It has stronger current clamping capability, lower saturation current, better short-circuit capability, and lower electric field (Eox) at the bottom of the gate trench, but Ronsp will become higher.

[0111] Based on the above Figure 1a , Figure 1b and Figure 1d Comparison of the three device structures shows that the width change of the first P-type buried layer 123 has a great influence on the device characteristics. Therefore, in practical applications, the width of the first P-type buried layer 123 can be determined according to the target saturation current value and the target gate trench bottom electric field.

[0112] The present application also provides a method for preparing a semi-superjunction silicon carbide MOS device, see Figure 4 As shown, the preparation method in this embodiment includes steps S100 to S700.

[0113] In step S100 , an N-type drift layer 120 is epitaxially grown on the front surface of an N-type substrate 110 .

[0114] Combination Figure 1a and Figure 5 As shown, an N-type drift layer 120 may be formed on the front surface of the N-type substrate 110 by an epitaxial growth process, and the thickness of the N-type drift layer 120 is greater than the thickness of the N-type substrate 110 .

[0115] In some embodiments, the thickness of the N-type substrate 110 may be 3-10 um.

[0116] In some embodiments, the doping concentration of N-type doping ions in the N-type substrate 110 may be 1e 20 cm -3 .

[0117] In some embodiments, the thickness of the N-type drift layer 120 epitaxially grown on the front side of the N-type substrate 110 in step S100 may be 20-60 um.

[0118] In some embodiments, in step S100, in the N-type drift layer 120 epitaxially grown on the front side of the N-type substrate 110, the doping concentration of the N-type doping ions may be 1e 15 ~1e 17 cm -3 .

[0119] In step S200 , P-type doping ions and N-type doping ions are sequentially implanted in a first preset region of the N-type drift layer 120 to form a P-type well region 140 and an N-type heavily doped region 150 , and P-type doping ions are implanted in a second preset region to form a P-type heavily doped region 160 .

[0120] Combination Figure 1a and Figure 6 As shown, in this embodiment, the thickness of the P-type heavily doped region 160 is greater than the sum of the thicknesses of the P-type well region 140 and the N-type heavily doped region 150 .

[0121] In step S300 , a trench etching process is used to form gate trenches 101 between the N-type heavily doped region 150 and the P-type heavily doped region 160 , between the P-type well region 140 and the P-type heavily doped region 160 , and between the N-type drift layer 120 and the P-type heavily doped region 160 .

[0122] In the present application embodiment, combined Figure 7a As shown, the depth of the gate trench 101 is less than the thickness of the P-type heavily doped region 160 . The existence of the gate trench 101 makes the widths of the N-type heavily doped region 150 and the P-type heavily doped region 160 smaller than the width of the P-type heavily doped region 160 .

[0123] In some embodiments, the thickness of the N-type heavily doped region 150 is equal to the thickness of the P-type heavily doped region 160 .

[0124] In step S400 , etching is continued in the gate trench 101 to form a deep trench 102 , so that the N-type drift layer has a concave structure, and a P-type shielding region 121 is formed in the deep trench 102 .

[0125] In the embodiment of the present application, the P-type shielding region 121 is formed on the inner wall of the groove of the N-type drift layer 120, and the P-type shielding region 121 is in a U-shaped structure. Both ends of the U-shaped structure of the P-type shielding region 121 are flush, and one end of the U-shaped structure of the P-type shielding region 121 is in contact with the lower surface of the P-type heavily doped region 160, that is, the P-type shielding region 121 is located below the P-type heavily doped region 160.

[0126] In step S500 , an insulating dielectric pillar 122 is formed in the deep trench 102 .

[0127] In this embodiment, combined with Figure 1aAs shown, after the insulating dielectric column 122 is formed in the deep trench 102 , the P-type shielding region 121 isolates the insulating dielectric column 122 from the N-type drift layer 120 .

[0128] In step S600 , a gate dielectric layer 130 and a gate polysilicon layer 131 are formed in the gate trench 101 .

[0129] In this embodiment, combined with Figure 1a As shown, the gate polysilicon layer 131 is wrapped by the gate dielectric layer 130 , the gate dielectric layer 130 is in contact with the insulating dielectric column 122 , and the material of the gate dielectric layer 130 can be the same as that of the insulating dielectric column 122 .

[0130] In step S700 , a source layer 170 is formed on the N-type heavily doped region 150 , the P-type heavily doped region 160 , and the gate dielectric layer 130 , and a drain layer 180 is formed on the back side of the N-type substrate 110 .

[0131] In this embodiment, combined with Figure 1a As shown, the source layer 170 is in contact with the N-type heavily doped region 150 , the P-type heavily doped region 160 , and the gate dielectric layer 130 . The N-type heavily doped region 150 and the P-type heavily doped region 160 are respectively located on both sides of the gate dielectric layer 130 .

[0132] In some embodiments, the source electrode layer 170 and the drain electrode layer 180 may be formed by a process of electrode metal material deposition.

[0133] In the embodiment of the present application, the above-mentioned step S100 to step S700 can be prepared Figure 1a The semi-superjunction silicon carbide MOS device shown in the figure can allow the N-type drift layer 120 to have a higher doping concentration without affecting the drain-source breakdown voltage (BVDSS), so that the device can have a better specific on-resistance (Ronsp). At the same time, the P-type shielding region can clamp the saturation current, thereby improving the short-circuit resistance of the device without affecting the on-resistance.

[0134] Above Figure 1b The semi-super junction silicon carbide MOS device shown can be implemented through the following steps S601 to S608 .

[0135] In step S601 , an N-type drift layer 120 is epitaxially grown on the front surface of an N-type substrate 110 .

[0136] like Figure 5 As shown, an N-type drift layer 120 may be formed on the front surface of the N-type substrate 110 by an epitaxial growth process, and the thickness of the N-type drift layer 120 is greater than the thickness of the N-type substrate 110 .

[0137] In the embodiment of the present application, the implementation method of the above-mentioned step S601 can refer to the description of the above-mentioned step S100, which will not be repeated here.

[0138] In step S602 , P-type doping ions are implanted into a portion of the N-type drift layer 120 to form a P-type buried region 1231 .

[0139] like Figure 5 As shown, by implanting P-type doping ions into a portion of the N-type drift layer 120 , a P-type buried region 1231 may be formed. The width of the P-type buried region 1231 is greater than half of the width of the N-type drift layer 120 .

[0140] In step S603, the N-type drift layer 120 is further epitaxially grown, and P-type doping ions and N-type doping ions are sequentially implanted in a first preset region of the N-type drift layer 120 to form a P-type well region 140 and an N-type heavily doped region 150, and P-type doping ions are implanted in a second preset region to form a P-type heavily doped region 160.

[0141] like Figure 6 As shown, the P-type heavily doped region 160 is located on the P-type buried region 1231 , and the P-type well region 140 is located between the N-type drift layer 120 and the N-type heavily doped region 150 , and is isolated from the P-type buried region 1231 by the N-type drift layer 120 .

[0142] In one embodiment of the present application, the P-type ion doping concentration of the P-type heavily doped region 160 may be the same as the P-type ion doping concentration of the P-type buried region 1231 .

[0143] In step S604, if Figure 7b As shown, a trench etching process is used to form a gate trench 101 that penetrates into a partial area of ​​the P-type buried region 1231 between the N-type heavily doped region 150 and the P-type heavily doped region 160, between the P-type well region 140 and the P-type heavily doped region 160, and between the N-type drift layer 120 and the P-type heavily doped region 160.

[0144] In step S605, Figure 8b As shown, etching is continued to form a deep trench in the gate trench 101, so that the N-type drift layer 120 has a concave structure and one end of the P-type buried region 1231 is separated from the other end; a P-type shielding region 121 is formed in the deep trench.

[0145] In the embodiment of the present application, the P-type shielding region 121 is formed on the inner wall of the groove of the N-type drift layer 120. Figure 8b As shown, the P-type buried region 1231 is separated into a first P-type buried layer 123 formed at one end of the P-type shielding region 121 and in contact with one end of the P-type shielding region 121 and the left side portion of the N-type drift layer 120, and a P-type buried region 1232 in contact with the P-type heavily doped region 160.

[0146] In step S606, if Fig. 9 As shown, an insulating dielectric column 122 is formed in the deep trench.

[0147] In this embodiment, combined with Fig. 9 As shown, after the insulating dielectric column 122 is formed in the deep trench, the P-type shielding region 121 isolates the insulating dielectric column 122 from the N-type drift layer 120 .

[0148] In step S607, Fig. 9 As shown, a gate dielectric layer 130 and a gate polysilicon layer 131 are formed in the gate trench 101 , wherein the gate polysilicon layer 131 is wrapped by the gate dielectric layer 130 .

[0149] In step S608, Figure 1b As shown, a source layer 170 is formed on the N-type heavily doped region 150 , the P-type heavily doped region 160 , and the gate dielectric layer 130 , and a drain layer 180 is formed on the back side of the N-type substrate 110 .

[0150] In this embodiment, by providing the first P-type buried layer 123, and connecting the first P-type buried layer 123 to the P-type heavily doped region 160 through the P-type shielding region 121 surrounding the insulating dielectric column 122 to achieve grounding, the first P-type buried layer 123 has a better current clamping ability. Figure 1a Based on the structure, the saturation current of SiC MOSFET is further reduced without reducing the specific on-resistance (Ronsp) of the device, the trade-off relationship between on-resistance (Ron) and short-circuit capability is optimized, and the device reliability is improved.

[0151] In one embodiment of the present application, in the process of implanting P-type doping ions into a partial region of the N-type drift layer 120 to form a P-type buried region in step S602, the width of the P-type buried region can be widened so that the width of the first P-type buried layer 123 is greater than the thickness of the P-type shielding region 121, that is, forming Figure 1d At this time, the first P-type buried layer 123 is arranged horizontally with the P-type well region 140 , and the width of the first P-type buried layer 123 is smaller than the width of the P-type well region 140 .

[0152] In one embodiment of the present application, in the process of implanting P-type doping ions into a partial region of the N-type drift layer 120 to form a P-type buried region in the above step S602, the thickness of the P-type buried region can be thickened, so that the semi-superjunction silicon carbide MOS device is provided with a second P-type buried layer 124. The second P-type buried layer 124 is formed at the other end of the P-type shielding region 121, and is in contact with the other end of the P-type shielding region 121, the right side of the N-type drift layer 120, and the P-type heavily doped region 160. That is, the formation is as follows Figure 1eThe structure shown.

[0153] exist Figure 1e In the structure shown, the first P-type buried layer 123 and the second P-type buried layer 124 are arranged opposite to each other and are separated by the gate dielectric layer 130 and the insulating dielectric column 122 .

[0154] In some embodiments, the first P-type buried layer 123 is located between the left side of the N-type drift layer 120 and one end of the P-type shielding region 121, and the second P-type buried layer 124 is located between the right side of the N-type drift layer 120 and the other end of the P-type shielding region 121, so that the width of the structure formed by the combination of the gate dielectric layer 130 and the insulating dielectric column 122 gradually decreases from the source layer 170 to the drain layer 180, presenting a stepped distribution.

[0155] An embodiment of the present application also provides a chip, comprising a semi-super junction silicon carbide MOS device as described in any of the above embodiments.

[0156] In this embodiment, the chip includes a chip substrate, on which one or more semi-super junction silicon carbide MOS devices are arranged. The semi-super junction silicon carbide MOS device can be prepared by the preparation method in any of the above embodiments, or the semi-super junction silicon carbide MOS device in any of the above embodiments can be arranged on the chip substrate.

[0157] In a specific application embodiment, other related semiconductor devices may be integrated on the chip substrate and form an integrated circuit with a semi-superjunction silicon carbide MOS device.

[0158] In a specific application embodiment, the chip may be a switch chip or a driver chip.

[0159] The beneficial effects of the embodiments of the present application are as follows: by setting a P-type well region on the left side of the N-type drift layer, setting a P-type heavily doped region on the right side of the N-type drift layer, an insulating dielectric column is formed in the groove of the N-type drift layer, and the insulating dielectric column is isolated from the N-type drift layer by the P-type shielding region, the N-type drift layer can be allowed to have a higher doping concentration without affecting the drain-source breakdown voltage of the device, so that the device can have a better specific on-resistance, and at the same time, the P-type shielding region can clamp the saturation current, thereby improving the short-circuit resistance of the device without affecting the on-resistance.

[0160] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned doping regions and devices is used as an example for illustration. In actual applications, the above-mentioned functions can be assigned to different doping regions and devices as needed, that is, the internal structure of the device is divided into different doping regions to complete all or part of the functions described above. The doping regions and devices in the embodiments can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0161] In addition, the specific names of the doping regions and devices are only for the convenience of distinguishing each other and are not used to limit the scope of protection of the present application.

[0162] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0163] In addition, each doping region in each embodiment of the present application may be integrated into one unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0164] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A semi-superjunction silicon carbide MOS device, characterized in that: include: N-type substrate; An N-type drift layer is formed on the front surface of the N-type substrate; wherein the N-type drift layer is a concave structure, and the height of the left side of the concave structure is greater than the height of the right side of the concave structure; A P-type shielding region formed on the inner wall of the groove of the N-type drift layer; An insulating dielectric column is formed in the groove of the N-type drift layer, and the insulating dielectric column is isolated from the N-type drift layer by the P-type shielding region; A gate dielectric layer, formed on the insulating dielectric column; a gate polysilicon layer, wrapped by the gate dielectric layer; A P-type well region formed on a left side portion of the N-type drift layer; An N-type heavily doped region is formed on the P-type well region; A P-type heavily doped region is formed on the right side of the N-type drift layer; A first P-type buried layer is formed at one end of the P-type shielding region and contacts one end of the P-type shielding region and a left side portion of the N-type drift layer; A source layer is formed on the N-type heavily doped region, the P-type heavily doped region and the gate dielectric layer; the first P-type buried layer is connected to the P-type heavily doped region through the P-type shielding region surrounding the insulating dielectric column to achieve grounding; The drain layer is formed on the back side of the N-type substrate.

2. The semi-superjunction silicon carbide MOS device according to claim 1, characterized in that: The first P-type buried layer is arranged at a junction area between the insulating dielectric column and the gate dielectric layer.

3. The semi-superjunction silicon carbide MOS device according to claim 1, characterized in that: The first P-type buried layer is arranged horizontally with the P-type well region, and a width of the first P-type buried layer is smaller than a width of the P-type well region.

4. The semi-superjunction silicon carbide MOS device according to claim 1, characterized in that: The semi-superjunction silicon carbide MOS device further comprises: The second P-type buried layer is formed at the other end of the P-type shielding region and contacts the other end of the P-type shielding region, the right side of the N-type drift layer and the P-type heavily doped region.

5. The semi-superjunction silicon carbide MOS device according to any one of claims 1 to 4, characterized in that: The width of the gate dielectric layer is greater than the width of the insulating dielectric column.

6. The semi-superjunction silicon carbide MOS device according to claim 5, characterized in that: The width of the gate dielectric layer decreases gradually from the source layer to the drain layer.

7. The semi-superjunction silicon carbide MOS device according to any one of claims 1 to 4, characterized in that: The insulating medium column is silicon oxide.

8. A method for preparing a semi-superjunction silicon carbide MOS device, characterized in that: The preparation method comprises: An N-type drift layer is epitaxially generated on the front side of the N-type substrate; In the first preset region of the N-type drift layer, P-type doping ions and N-type doping ions are sequentially implanted to form a P-type well region and an N-type heavily doped region, and P-type doping ions are implanted to form a P-type heavily doped region in the second preset region; A gate trench is formed between the N-type heavily doped region and the P-type heavily doped region, between the P-type well region and the P-type heavily doped region, and between the N-type drift layer and the P-type heavily doped region by using a trench etching process; wherein the depth of the gate trench is less than the thickness of the P-type heavily doped region; Continue etching in the gate trench to form a deep groove, so that the N-type drift layer has a concave structure, and form a P-type shielding region in the deep groove; wherein the P-type shielding region is formed on the inner wall of the groove of the N-type drift layer; forming an insulating dielectric column in the deep trench, and isolating the insulating dielectric column from the N-type drift layer by the P-type shielding region; forming a first P-type buried layer at one end of the P-type shielding region, wherein the first P-type buried layer contacts one end of the P-type shielding region and a left side portion of the N-type drift layer; forming a gate dielectric layer and a gate polysilicon layer in the gate trench; wherein the gate polysilicon layer is wrapped by the gate dielectric layer; A source layer is formed on the N-type heavily doped region, the P-type heavily doped region, and the gate dielectric layer, and a drain layer is formed on the back side of the N-type substrate; the first P-type buried layer is connected to the P-type heavily doped region through the P-type shielding region surrounding the insulating dielectric column to achieve grounding.

9. A chip, characterized in that: It comprises a semi-super junction silicon carbide MOS device as claimed in any one of claims 1 to 7.

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