Circuit and method for re-editing video timing

Abstract

The present invention discloses a circuit and method for re-editing video timing, including: obtaining original video timing and video pixel data and caching the video pixel data according to a first video timing, wherein the original video timing includes a first video clock signal Video CLK, a first field synchronization signal Vsync_IN, a first line synchronization signal Hsync_IN, and a first data valid enable signal DataEn_IN; analyzing the first data valid enable signal DataEn_IN, the first field synchronization signal Vsync_IN, and the first line synchronization signal Hsync_IN according to the first video clock signal Video CLK to obtain first video timing information Video Timing Info; and fine-tuning the timing of the first video timing information according to a preset configuration strategy to obtain second video timing information New Video Timing Info. The circuit and method for re-editing video timing of the present application realize stable output of video timing, improve the stability of video data output, and reduce the probability of jitter or black screen in video display.

Description

Technical Field

[0001] The present invention relates to the technical field of video transmission, and in particular to a circuit and method for re-editing video timing. Background Art

[0002] The channel clock (Lane CLK) and video clock (VideoCLK) commonly used in decoding at the receiving end of ordinary video transmission are directly passed through the differential clock Lane CLK P / N at the transmitting end and regenerated and recovered through the clock generation and frequency detector (Clock Generator) in the receiving end PHY. The receiving end video clock Video CLK and the receiving end channel clock Lane CLK are both homologous clocks derived from Lane CLK P / N, and there is a specific ratio relationship between them, usually 1:1 or 1:1.2, etc.

[0003] The timing of the video after decoding at the receiving end and the timing before encoding at the sending end are usually the same stable and continuous data. For example, in the HDMI 1.4 and HDMI 2.0 standards, the differential signal line transmits 3 channels of channel data Lane Serial P / N and one Lane CLK P / N. Figure 1 As shown, the schematic diagram only shows one lane data Lane Serial P / N. Lane data has two forms: high-speed single-bit analog serial differential data (Lane Serial P / N) and multi-bit parallel data (Lane Parallel Data) (hereinafter referred to as: high-speed serial data and parallel data, respectively). High-speed serial data Lane Serial P / N belongs to the high-speed clock Lane CLK P / N clock domain, and parallel data Lane Parallel Data belongs to the Lane CLK clock domain. The clock rate of Lane CLK P / N is several times that of Lane CLK.

[0004] Another commonly used decoding solution for video transmission receiver uses the channel clock Lane CLK, which is also directly passed through the differential clock Lane CLK P / N at the sending end and regenerated and restored through the Clock Generator in the receiving end PHY. However, the video clock Video CLK is jointly generated by the crystal clock Crystal CLK and the clock generation and frequency detector. It is not homologous to the channel clock Lane CLK, and there is no specific proportional relationship between the two. It only requires that the bandwidth of the video data Video Data is greater than the channel data Lane Data. Moreover, in order to ensure the stability of the video timing, the video cache at the receiving end needs to store at least one row of data, and use digital logic to ensure that the output video timing is stable and continuous. For example, in the MIPI standard, the differential signal line transmits 4 channels of channel data Lane Serial P / N and one channel clock Lane CLK P / N. For example Figure 2 As shown, the same schematic diagram only shows one channel of channel data Lane Serial P / N.

[0005] As video equipment has higher and higher requirements for video accuracy and speed, based on the traditional differential signal line, the channel originally used to transmit Lane CLK P / N (differential clock) signals is also changed to transmit channel data Lane Data. In this way, there is one more Data Lane, and the total data bandwidth is larger than before. The channel clock Lane CLK is generated by the crystal clock Crystal CLK and the clock generation and frequency detector, and the frequency of the channel clock Lane CLK is locked (Frequency Lock) by comparing the rising and falling edges of the channel data Lane Data. This high-speed video transmission without Lane CLK P / N (differential clock) signals is becoming more and more common. For example, in the HDMI 2.1 and DP standards, the differential signal lines transmit 4 channels of channel data Lane Serial P / N, but there is no channel clock Lane CLK P / N. For example Figure 3 As shown in the figure, the same diagram only shows one channel of Lane Serial P / N. Figure 3 As shown in the figure, the receiving end video clock Video CLK and the channel clock Lane CLK generated by the crystal clock Crystal CLK and the clock generation and frequency detector are not homologous, and the Lane CLK of the receiving end and the Lane CLK of the transmitting end are also asynchronous, which inevitably leads to slight errors. Moreover, the video buffer in the receiving end digital core logic designed by different manufacturers may not meet the capacity of one line of data, which leads to unstable timing of the decoded video.

[0006] Common unstable manifestations include: 1. The Htotal (total number of line clocks, which is the sum of Hsync Width, Hback Porch, Hactive and Hfront Porch) between two Hsync (line synchronization) signals is inconsistent between different lines, which is usually caused by the asynchrony between Lane CLK and video clock Video CLK at the transmitter and receiver; 2. DataEn (data valid enable signal) is discontinuous, which is usually caused by the video clock frequency of the receiver being greater than the video clock frequency of the transmitter. The above two unstable forms may even overlap.

[0007] The digital core logic of the receiver of some IP companies outputs discontinuous Dataen (data valid enable) in certain usage scenarios, such as Figure 4.c And it does not output Hsync (horizontal synchronization) in the Vblank (field blanking area, including Vsync Width, Vback Porch and Vfront Porch) interval, as shown in the lower half. Figure 4.c In some specific application scenarios, Figure 4.b The unequal Htotal (total number of row clocks) will also be added to Figure 4.c The signal shown. Unstable video timing (including Htotal inequality and Dataen discontinuity) or Hsync (horizontal synchronization) missing in Vblank (field blanking area) cannot be accepted by most of the IPs of the digital core logic of the transmitter. For example, HDMI and MIPI Transmit (transmitter) will result in limited functions when forwarding unstable videos. Moreover, the above abnormal timing cannot be displayed normally by most displays, and jitter or black screen display effects will appear. Summary of the invention

[0008] In order to solve the technical problems existing in the background technology, the present invention provides a circuit and method for re-editing video timing.

[0009] The present invention provides a method for re-editing video timing, comprising:

[0010] Step S1, obtaining original video timing and video pixel data and caching the video pixel data according to a first video timing, wherein the original video timing includes a first video clock signal Video CLK, a first field synchronization signal Vsync_IN, a first row synchronization signal Hsync_IN, and a first data valid enable signal DataEn_IN;

[0011] Step S2, analyzing the first data valid enable signal DataEn_IN, the first field synchronization signal Vsync_IN, and the first line synchronization signal Hsync_IN according to the first video clock signal Video CLK to obtain first video timing information Video Timing Info;

[0012] Step S3, fine-tuning the first video timing information according to a preset configuration strategy to obtain second video timing information New Video Timing Info;

[0013] Step S4, obtaining the second video clock signal Retiming Video CLK and generating a stable second data valid enable signal DataEn_OUT, a second field synchronization signal Vsync_OUT, and a second row synchronization signal Hsync_OUT corresponding to the second video timing information New Video TimingInfo according to the first field synchronization signal Vsync_IN, the second video clock signal Retiming Video CLK, and the second video timing information New Video TimingInfo;

[0014] Step S5: Read and output the video pixel data from the buffer according to the second data valid enable signal DataEn_OUT, the second field synchronization signal Vsync_OUT, and the second row synchronization signal Hsync_OUT.

[0015] Preferably, step S2 specifically includes:

[0016] Processing the first field synchronization signal Vsync_IN to extract a first type rising edge pos_vsync and a first type falling edge neg_vsync of the first field synchronization signal Vsync_IN;

[0017] Processing the first row synchronization signal Hsync_IN to extract a second type rising edge pos_hsync and a second type falling edge neg_hsync of the first row synchronization signal Hsync_IN;

[0018] Processing the first data valid enable signal DataEn_IN to extract a third type rising edge pos_de and a third type falling edge neg_de of the first data valid enable signal DataEn_IN;

[0019] According to the first video clock signal Video CLK, the first third type rising edge pos_de after each second type rising edge pos_hsync is used as the first rising edge pos_hde;

[0020] According to the first video clock signal Video CLK, the first third type rising edge pos_de after each first type rising edge pos_vsync is used as the second rising edge pos_vde;

[0021] The first video timing information is calculated and obtained according to the first type rising edge pos_vsync, the first type falling edge neg_vsync, the second type rising edge pos_hsync, the second type falling edge neg_hsync, the first rising edge pos_hde, the third type rising edge pos_de, the third type falling edge neg_de, and the second rising edge pos_vde. The first video timing information specifically includes: field timing parameters, row timing parameters, and clock parameters.

[0022] Preferably, the field timing parameters include: first field synchronization width vsync_width, first field back porch width vback_porch, first field effective data width vactive, first field front porch width vfront_porch, and total number of rows in the first field vtotal; the field timing parameter acquisition process is as follows:

[0023] Calculate all the clock cycle numbers between every two adjacent second type rising edges pos_hsync according to the second type rising edge pos_hsync, and use all the clock cycle numbers as the first cycle number hcnt;

[0024] Calculate the number of first row synchronization signals Hsync_IN between every two adjacent first type rising edges pos_vsync according to the second type rising edge pos_hsync, and record the number of first row synchronization signals Hsync_IN as a first count vcnt;

[0025] Calculate the number of first rising edges pos_hde between every two first-type rising edges pos_vsync according to the first rising edge pos_hde, and record the number of first rising edges pos_hde as a second count vde_cnt;

[0026] When the third type falling edge neg_de is at a high level, the first cycle number hcnt and the first count vcnt are latched one by one to obtain the one-to-one corresponding original row front porch width hfront_porch_begin and original field front porch width vfront_porch_begin;

[0027] When the first type falling edge neg_vsync is at a high level, the first count vcnt is latched to obtain the first field synchronization width vsync_width;

[0028] When the second rising edge pos_vde is at a high level, the value of the first field synchronization width vsync_width minus the first count vcnt is latched to obtain the first field back porch width vback_porch;

[0029] When the first type rising edge pos_vsync is at a high level, the second count vde_cnt is latched to obtain the first field valid data width vactive;

[0030] When the first type rising edge pos_vsync is at a high level, the value of the first count vcnt minus the original field front shoulder width vfront_porch_begin is latched to obtain the first field front shoulder width vfront_porch;

[0031] When the first type rising edge pos_vsync is at a high level, the first count vcnt is latched to obtain the total number of rows vtotal in the first field.

[0032] Preferably, the row timing parameters include a first row synchronization width hsync_width, a first row back porch width hback_porch, a first row effective data width hactive, and a first row front porch width hfront_porch; the row timing parameter acquisition process is as follows:

[0033] Calculate the number of clock cycles of the first data valid enable signal DataEn_IN at a high level between every two adjacent second type rising edges pos_hsync according to the first data valid enable signal DataEn_IN, and use the number of clock cycles as the third cycle number hde_cnt;

[0034] When the second type falling edge neg_hsync is at a high level, the first cycle number hcnt is latched to obtain the first row synchronization width hsync_width;

[0035] When the first rising edge pos_hde is at a high level, the value of the first cycle number hcnt minus the first row synchronization width hsync_width is latched to obtain the first row back porch width hback_porch;

[0036] When the second type rising edge pos_hsync is at a high level, the third cycle number hde_cnt is latched to obtain the first row valid data width hactive;

[0037] When the second type rising edge pos_hsync is at a high level, the value of the first cycle number hcnt minus the original row front shoulder width hfront_porch_begin is latched to obtain the first row front shoulder width hfront_porch.

[0038] Preferably, the clock parameters include the total number of first row clocks htotal and the total number of first frame clocks ftotal; the clock parameter acquisition process is as follows:

[0039] Calculate all the clock cycle numbers of every two adjacent first type rising edges pos_vsync according to the first type rising edge pos_vsync, and use all the clock cycle numbers as the second cycle number fcnt;

[0040] When the second type rising edge pos_hsync is at a high level, the first cycle number hcnt is latched to obtain the first row clock total htotal;

[0041] When the first type rising edge pos_vsync is at a high level, the second cycle number fcnt is latched to obtain the first frame clock total number ftotal.

[0042] Preferably, the preset configuration strategy specifically includes:

[0043] fifo depth = 4*hactive;

[0044] new_vsync_width+new_vback_porch=vsync_width+vback_porch+4;

[0045] Vsync_OUT+new_vback_porch+new_vactive+new_vfront_porch is equal to or slightly less than Vsync+vback_porch+vactive+vfront_porch;

[0046] new_vactive=vactive, new_hactive=hactive;

[0047]

[0048] Among them, fifo depth is the configuration cache depth; hactive is the first line valid data width; new_vsync_width is the second field synchronization width; new_vback_porch is the second field back porch width; vsync_width is the first field synchronization width; vback_porch is the first field back porch width; Vsync_OUT is the second field synchronization signal; new_vback_porch is the second field back porch width; new_vactive is the second field valid data width; new_vfront_porch is the second field front porch width; Vsync_IN is the first field synchronization signal; vback_porch is the first field back porch width; vfront_porch is the first field front porch width; Hsync_OUT is the second line synchronization signal; new_hback_porch is the second line back porch width; new_hactive is the second line valid data width; new_hfront_porch is the second line front porch width; Hsync_IN is the first line synchronization signal; hback_porch is the first line back porch width; hfront_porch is the first line front porch width; f1 is Video f2 is the frequency of New Video CLK; f3 is the frequency of New Video CLK;

[0049] The second video timing information includes the second field synchronization width new_vsync_width, the second field back porch width new_vback_porch, the second field valid data width new_vactive, the second field front porch width new_vfront_porch, the second line synchronization width new_hsync_width, the second line back porch width new_hback_porch, the second line valid data width new_hactive, the second line front porch width new_hfront_porch, the total number of lines in the second field new_vtotal, and the total number of clocks in the second line new_htotal.

[0050] Preferably, step S4 specifically includes:

[0051] Add the second field synchronization width new_vsync_width, the second field back porch width new_vback_porch, the second field effective data width new_vactive, and the second field front porch width new_vfront_porch to obtain the total number of rows in the second field new_vtotal;

[0052] The second field synchronization width new_vsync_width, the second line back porch width new_hback_porch, the second line effective data width new_hactive, and the second line front porch width new_hfront_porch are added together to obtain the second line clock total new_htotal;

[0053] After delaying the first field synchronization signal Vsync_IN by 2 clock cycles according to the second video clock signal Retiming Video CLK, an AND operation is performed with the first field synchronization signal Vsync_IN which is delayed by 3 clock cycles and inverted to obtain a fourth type rising edge pos_vsync;

[0054] The third count new_vcnt and the total number of rows in the second field new_vtotal are judged for numerical relationship, and a first comparison value vmax is output; when the third count new_vcnt and the total number of rows in the second field vtotal are equal, the first comparison value vmax is a high level;

[0055] The fourth count new_hcnt and the second row clock total new_htotal are numerically judged, and a second comparison value hmax is output; when the fourth count new_hcnt and the second row clock total new_htotal are equal, the second comparison value hmax is a high level;

[0056] Performing a first preset logic operation on the fourth type rising edge pos_vsync, the first comparison value vmax, and the second comparison value hmax to obtain a third count new_vcnt;

[0057] A second preset logic operation is performed on the fourth type rising edge pos_vsync, the first comparison value vmax, and the second comparison value hmax to obtain a fourth count new_hcnt.

[0058] Preferably, when the value of the third count new_vcnt is smaller than the second field synchronization width new_vsync_width, the output second field synchronization signal Vsync_OUT is at a high level;

[0059] When the value of hcnt is less than the second row synchronization width new_hsync_width, the output second row synchronization signal Hsync_OUT is high level;

[0060] Add the second field synchronization width new_vsync_width to the second field back porch width new_vback_porch, and then perform a numerical judgment with the third count new_vcnt, and when the third count new_vcnt is greater than or equal to the sum of the second field synchronization width new_vsync_width and the second field back porch width new_vback_porch, generate a first signal;

[0061] When the third count new_vcnt is less than the difference between the total number of rows in the second field new_vtotal and the second field front porch width new_vfront_porch, a second signal is generated;

[0062] Add the second row synchronization width new_hsync_width and the second row back porch width new_hback_porch, and then perform a numerical judgment with the fourth count new_hcnt, and when the fourth count new_hcnt is greater than or equal to the value of the sum of new_hsync_width and new_hback_porch, generate a third signal;

[0063] When the fourth count new_hcnt is less than the difference between the second row clock total htotal and the second row front porch width new_hfront_porch, a fourth signal is generated;

[0064] A third preset logic operation is performed on the first signal, the second signal, the third signal, and the fourth signal based on the second video clock signal Retiming Video CLK to obtain a second data valid enable signal DataEn_OUT.

[0065] Preferably, the first preset logical operation is specifically: performing a "not" operation on the first comparison quantity vmax and then performing an "and" operation with the second comparison quantity hmax to obtain a first intermediate quantity, performing an "or" operation on the first intermediate quantity and the fourth type of rising edge pos_vsync to obtain an enable signal EN of the first type D flip-flop; using the fourth type of rising edge pos_vsync as the enable signal of the first selector, the first input end of the first selector is a low level, the second input end is electrically connected to the output end of the first counter, the input end of the first counter is electrically connected to the output end of the first type D flip-flop, the output end of the first selector is electrically connected to the input end of the first type D flip-flop, and the fourth type of rising edge pos_vsync is used as the input of the first type D flip-flop to obtain a third count new_vcnt.

[0066] Preferably, the second preset logical operation is specifically:

[0067] The first comparison value vmax is subjected to a "not" operation and then to an "and" operation with the second comparison value hmax to obtain a first intermediate value, the first intermediate value and the fourth type rising edge pos_vsync are subjected to an "or" operation and used as an enable input of the second selector, the first input end of the second selector is a low level, the second input end is electrically connected to the output end of the second counter, the input end of the second counter is electrically connected to the output end of the second type D flip-flop, the output end of the second selector is electrically connected to the input end of the second type D flip-flop, and the fourth count new_hcnt is obtained after the second type D flip-flop counting operation.

[0068] Preferably, the third preset logical operation is specifically:

[0069] Performing an AND operation on the first signal and the second signal to obtain a fifth signal;

[0070] Performing an AND operation on the third signal and the fourth signal to obtain a sixth signal;

[0071] The sixth signal is ANDed with the fifth signal and then inputted into the D terminal of the fifth type D flip-flop, and the output of the fifth type D flip-flop is used as the second data valid enable signal DataEn_OUT.

[0072] The present invention provides a circuit for re-editing video timing, comprising:

[0073] A data acquisition module, used for acquiring original video timing and video pixel data and caching the video pixel data according to a first video timing, wherein the original video timing includes a first video clock signal Video CLK, a first field synchronization signal Vsync_IN, a first line synchronization signal Hsync_IN, and a first data valid enable signal DataEn_IN;

[0074] A video analysis module, configured to analyze a first data valid enable signal DataEn_IN, a first field synchronization signal Vsync_IN, and a first line synchronization signal Hsync_IN according to a first video clock signal Video CLK to obtain first video timing information;

[0075] A video timing fine-tuning module, used to perform timing fine-tuning on the first video timing information according to a preset configuration strategy to obtain second video timing information;

[0076] A video timing generation module, used for obtaining a second video clock signal Retiming Video CLK and generating a stable second data valid enable signal DataEn_OUT, a second field synchronization signal Vsync_OUT, and a second row synchronization signal Hsync_OUT corresponding to the second video timing information according to the first field synchronization signal Vsync_IN, the second video clock signal Retiming Video CLK, and the second video timing information;

[0077] The data output module is used to control the FIFO read control module to read and output the video pixel data from the cache according to the second data valid enable signal DataEn_OUT, the second field synchronization signal Vsync_OUT, and the second line synchronization signal Hsync_OUT.

[0078] In the present invention, the circuit and method for re-editing video timing are proposed. After the unstable video timing data is processed by video timing re-editing, the problem of inconsistency of the total number of clocks htotal of the first line is solved. After the video timing re-editing, the problem of discontinuity of the first data valid enable signal DataEn_IN is solved. After the unstable video timing data is processed by video timing re-editing, the row synchronization Hsync will be continuously and stably output. In the unstable video timing, the total clock error between frames and rows and rows is processed by synchronous or asynchronous clocks in the video timing re-editing, so that the stable output of the video timing is realized, the stability of the video data output is improved, and the probability of jitter or black screen in the video display is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0079] Figure 1 It is a schematic diagram of the channel clock and video clock of the existing video receiving end being controlled by the transmitting end;

[0080] Figure 2 It is a schematic diagram that only the channel clock of the existing video receiving end is controlled by the transmitting end;

[0081] Figure 3 A schematic diagram showing that the clocks of an existing video receiving end and a transmitting end are not of the same source;

[0082] Figure 4.a This is a schematic diagram of the stable timing of the video;

[0083] Figure 4.b This is a schematic diagram of the unequal total number of clocks between Hsync (horizontal synchronization);

[0084] Figure 4.c This is a discontinuous diagram of Dataen (data valid enable signal);

[0085] Figure 5A video timing re-editing function block diagram of a video timing re-editing method proposed by the present invention;

[0086] Figure 6 A schematic diagram of the structure of a video analysis process of a video timing re-editing method proposed by the present invention;

[0087] Figure 7 A schematic diagram of the structure of video timing generation of a circuit and method for re-editing video timing proposed by the present invention;

[0088] Figure 8 A schematic diagram of a new video timing NewVideo Timing of a circuit and method for re-editing video timing proposed by the present invention. DETAILED DESCRIPTION

[0089] Reference Figure 1-8 The present invention provides a method for re-editing video timing, comprising:

[0090] Step S1, obtaining original video timing and video pixel data and caching the video pixel data according to a first video timing, wherein the original video timing includes a first video clock signal Video CLK, a first field synchronization signal Vsync_IN, a first row synchronization signal Hsync_IN, and a first data valid enable signal DataEn_IN.

[0091] In this embodiment, the original video timing and video pixel data are unstable video input Video Input.

[0092] Step S2: Analyze the first data valid enable signal DataEn_IN, the first field synchronization signal Vsync_IN, and the first line synchronization signal Hsync_IN according to the first video clock signal Video CLK to obtain first video timing information Video Timing Info.

[0093] In this embodiment, step S2 specifically includes:

[0094] Processing the first field synchronization signal Vsync_IN to extract a first type rising edge pos_vsync and a first type falling edge neg_vsync of the first field synchronization signal Vsync_IN;

[0095] Processing the first row synchronization signal Hsync_IN to extract a second type rising edge pos_hsync and a second type falling edge neg_hsync of the first row synchronization signal Hsync_IN;

[0096] Processing the first data valid enable signal DataEn_IN to extract a third type rising edge pos_de and a third type falling edge neg_de of the first data valid enable signal DataEn_IN;

[0097] According to the first video clock signal Video CLK, the first third type rising edge pos_de after each second type rising edge pos_hsync is used as the first rising edge pos_hde;

[0098] According to the first video clock signal Video CLK, the first third type rising edge pos_de after each first type rising edge pos_vsync is used as the second rising edge pos_vde;

[0099] The first video timing information is calculated and obtained according to the first type rising edge pos_vsync, the first type falling edge neg_vsync, the second type rising edge pos_hsync, the second type falling edge neg_hsync, the first rising edge pos_hde, the third type rising edge pos_de, the third type falling edge neg_de, and the second rising edge pos_vde. The first video timing information specifically includes: field timing parameters, row timing parameters, and clock parameters.

[0100] In this embodiment, the field timing parameters include: the first field synchronization width vsync_width, the first field back porch width vback_porch, the first field effective data width vactive, the first field front porch width vfront_porch, and the total number of rows in the first field vtotal; the field timing parameter acquisition process is as follows:

[0101] Calculate all the clock cycle numbers between every two adjacent second type rising edges pos_hsync according to the second type rising edge pos_hsync, and use all the clock cycle numbers as the first cycle number hcnt;

[0102] Calculate the number of first row synchronization signals Hsync_IN between every two adjacent first type rising edges pos_vsync according to the second type rising edge pos_hsync, and record the number of first row synchronization signals Hsync_IN as a first count vcnt;

[0103] Calculate the number of first rising edges pos_hde between every two first-type rising edges pos_vsync according to the first rising edge pos_hde, and record the number of first rising edges pos_hde as a second count vde_cnt;

[0104] When the third type falling edge neg_de is at a high level, the first cycle number hcnt and the first count vcnt are latched one by one to obtain the one-to-one corresponding original row front porch width hfront_porch_begin and original field front porch width vfront_porch_begin;

[0105] When the first type falling edge neg_vsync is at a high level, the first count vcnt is latched to obtain the first field synchronization width vsync_width;

[0106] When the second rising edge pos_vde is at a high level, the value of the first field synchronization width vsync_width minus the first count vcnt is latched to obtain the first field back porch width vback_porch;

[0107] When the first type rising edge pos_vsync is at a high level, the second count vde_cnt is latched to obtain the first field valid data width vactive;

[0108] When the first type rising edge pos_vsync is at a high level, the value of the first count vcnt minus the original field front shoulder width vfront_porch_begin is latched to obtain the first field front shoulder width vfront_porch;

[0109] When the first type rising edge pos_vsync is at a high level, the first count vcnt is latched to obtain the total number of rows vtotal in the first field.

[0110] In this embodiment, the row timing parameters include the first row synchronization width hsync_width, the first row back porch width hback_porch, the first row effective data width hactive, and the first row front porch width hfront_porch; the row timing parameter acquisition process is as follows:

[0111] Calculate the number of clock cycles of the first data valid enable signal DataEn_IN at a high level between every two adjacent second type rising edges pos_hsync according to the first data valid enable signal DataEn_IN, and use the number of clock cycles as the third cycle number hde_cnt;

[0112] When the second type falling edge neg_hsync is at a high level, the first cycle number hcnt is latched to obtain the first row synchronization width hsync_width;

[0113] When the first rising edge pos_hde is at a high level, the value of the first cycle number hcnt minus the first row synchronization width hsync_width is latched to obtain the first row back porch width hback_porch;

[0114] When the second type rising edge pos_hsync is at a high level, the third cycle number hde_cnt is latched to obtain the first row valid data width hactive;

[0115] When the second type rising edge pos_hsync is at a high level, the value of the first cycle number hcnt minus the original row front shoulder width hfront_porch_begin is latched to obtain the first row front shoulder width hfront_porch.

[0116] In this embodiment, the clock parameters include the total number of first row clocks htotal and the total number of first frame clocks ftotal. The clock parameter acquisition process is as follows:

[0117] Calculate all the clock cycle numbers of every two adjacent first type rising edges pos_vsync according to the first type rising edge pos_vsync, and use all the clock cycle numbers as the second cycle number fcnt;

[0118] When the second type rising edge pos_hsync is at a high level, the first cycle number hcnt is latched to obtain the first row clock total htotal;

[0119] When the first type rising edge pos_vsync is at a high level, the second cycle number fcnt is latched to obtain the first frame clock total number ftotal.

[0120] Step S3: fine-tune the first video timing information according to a preset configuration strategy to obtain second video timing information New Video Timing Info.

[0121] In this embodiment, the preset configuration strategy specifically includes:

[0122] fifo depth = 4*hactive;

[0123] new_vsync_width+new_vback_porch=vsync_width+vback_porch+4;

[0124] Vsync_OUT+new_vback_porch+new_vactive+new_vfront_porch is equal to or slightly less than Vsync+vback_porch+vactive+vfront_porch;

[0125] new_vactive=vactive, new_hactive=hactive;

[0126]

[0127]

[0128] Among them, fifo depth is the configuration cache depth; hactive is the first line valid data width; new_vsync_width is the second field synchronization width; new_vback_porch is the second field back porch width; vsync_width is the first field synchronization width; vback_porch is the first field back porch width; Vsync_OUT is the second field synchronization signal; new_vback_porch is the second field back porch width; new_vactive is the second field valid data width; new_vfront_porch is the second field front porch width; Vsync_IN is the first field synchronization signal; vback_porch is the first field back porch width; vfront_porch is the first field front porch width; Hsync_OUT is the second line synchronization signal; new_hback_porch is the second line back porch width; new_hactive is the second line valid data width; new_hfront_porch is the second line front porch width; Hsync_IN is the first line synchronization signal; hback_porch is the first line back porch width; hfront_porch is the first line front porch width; f1 is Video f2 is the frequency of New Video CLK; f3 is the frequency of New Video CLK;

[0129] The second video timing information includes the second field synchronization width new_vsync_width, the second field back porch width new_vback_porch, the second field valid data width new_vactive, the second field front porch width new_vfront_porch, the second line synchronization width new_hsync_width, the second line back porch width new_hback_porch, the second line valid data width new_hactive, the second line front porch width new_hfront_porch, the total number of lines in the second field new_vtotal, and the total number of clocks in the second line new_htotal.

[0130] Step S4, obtaining the second video clock signal Retiming Video CLK and generating a stable second data valid enable signal DataEn_OUT, a second field synchronization signal Vsync_OUT, and a second row synchronization signal Hsync_OUT corresponding to the second video timing information New Video TimingInfo according to the first field synchronization signal Vsync_IN, the second video clock signal Retiming Video CLK, and the second video timing information New Video TimingInfo.

[0131] In this embodiment, step S4 specifically includes:

[0132] Add the second field synchronization width new_vsync_width, the second field back porch width new_vback_porch, the second field effective data width new_vactive, and the second field front porch width new_vfront_porch to obtain the total number of rows in the second field new_vtotal;

[0133] The second field synchronization width new_vsync_width, the second line back porch width new_hback_porch, the second line effective data width new_hactive, and the second line front porch width new_hfront_porch are added together to obtain the second line clock total new_htotal;

[0134] After delaying the first field synchronization signal Vsync_IN by 2 clock cycles according to the second video clock signal Retiming Video CLK, an AND operation is performed with the first field synchronization signal Vsync_IN which is delayed by 3 clock cycles and inverted to obtain a fourth type rising edge pos_vsync;

[0135] The third count new_vcnt and the total number of rows in the second field new_vtotal are judged for numerical relationship, and a first comparison value vmax is output; when the third count new_vcnt and the total number of rows in the second field vtotal are equal, the first comparison value vmax is a high level;

[0136] The fourth count new_hcnt and the second row clock total new_htotal are numerically judged, and a second comparison value hmax is output; when the fourth count new_hcnt and the second row clock total new_htotal are equal, the second comparison value hmax is a high level;

[0137] Performing a first preset logic operation on the fourth type rising edge pos_vsync, the first comparison value vmax, and the second comparison value hmax to obtain a third count new_vcnt;

[0138] A second preset logic operation is performed on the fourth type rising edge pos_vsync, the first comparison value vmax, and the second comparison value hmax to obtain a fourth count new_hcnt.

[0139] In this embodiment, when the value of the third count new_vcnt is less than the second field synchronization width new_vsync_width, the output second field synchronization signal Vsync_OUT is at a high level;

[0140] When the value of hcnt is less than the second row synchronization width new_hsync_width, the output second row synchronization signal Hsync_OUT is high level;

[0141] Add the second field synchronization width new_vsync_width to the second field back porch width new_vback_porch, and then perform a numerical judgment with the third count new_vcnt, and when the third count new_vcnt is greater than or equal to the sum of the second field synchronization width new_vsync_width and the second field back porch width new_vback_porch, generate a first signal;

[0142] When the third count new_vcnt is less than the difference between the total number of rows in the second field new_vtotal and the second field front porch width new_vfront_porch, a second signal is generated;

[0143] Add the second row synchronization width new_hsync_width and the second row back porch width new_hback_porch, and then perform a numerical judgment with the fourth count new_hcnt, and when the fourth count new_hcnt is greater than or equal to the value of the sum of new_hsync_width and new_hback_porch, generate a third signal;

[0144] When the fourth count new_hcnt is less than the difference between the second row clock total htotal and the second row front porch width new_hfront_porch, a fourth signal is generated;

[0145] A third preset logic operation is performed on the first signal, the second signal, the third signal, and the fourth signal based on the second video clock signal Retiming Video CLK to obtain a second data valid enable signal DataEn_OUT.

[0146] In this embodiment, for Figure 4.cIn the video timing where the horizontal synchronization signal Hsync is missing in the field blanking area, the first field synchronization width vsync width, the first field back porch width vback porch and the first field front porch width vfront porch analyzed by the video analysis module are all 0. However, in this case, the other calculated data are sufficient to analyze the unstable timing of the video.

[0147] After the video timing information Video Timing Info is output from the video analysis module, it enters the video timing fine-tuning module. The CPU reads the video timing information Video Timing Info from the module and generates new video timing information New Video Timing Info according to the preset fine-tuning algorithm to ensure that the new video timing New Video Timing Info generated by the video timing generation module is read. Figure 5 When FIFO is in the middle, avoid the situation that the FIFO is read empty due to too fast reading rate, or the FIFO is filled due to too slow reading rate. The new video timing information New Video Timing Info is calculated. The new video timing information includes the second field synchronization width new_vsync width, the second field back porch width new_vback porch, the second field effective data width new_vactive, the second field front porch width new_vfront porch, the second line synchronization width new_hsync width, the second line back porch width new_hback porch, the second line effective data width new_hactive, the second line front porch width new_hfront porch, and generates a new and stable new video timing New Video Timing. The new video timing includes the second data effective enable signal DataEn_OUT, the second field synchronization signal Vsync_OUT, and the second line synchronization signal Hsync_OUT.

[0148] The principle of the video timing generation module is as follows Figure 7 As shown, the module calculates the new video timing New Video Timing based on the new video timing information New VideoTiming Info combined with Retiming Video CLK. Retiming Video CLK (video clock for retiming) comes from the synchronous clock of the subsequent video processing circuit, and can be a synchronous clock or an asynchronous clock with the Video CLK in the Video Input.

[0149] The new video timing generated by the video timing generation module includes the second data valid enable signal DataEn_OUT, the second field synchronization signal Vsync_OUT, the second line synchronization signal Hsync_OUT and the Retiming Video CLK. The generated new video timing will input the unstable video timing and data into the Video Input, and the total clock error between frames and lines will be uniformly placed in the unstable buffer Unstable Cushion of the last line of the new timing, such as Figure 8 shown.

[0150] Therefore, the second field synchronization width new_vsync width, the second field back porch width new_vback porch, the second field effective data width new_vactive, the second field front porch width new_vfront porch, the second line synchronization width new_hsync width, the second line back porch width new_hback porch, the second line effective data width new_hactive, and the second line front porch width new_hfront porch of the new video timing are all stable. Moreover, the total number of lines in the second field new_vtotal including the blanking line is also stable, and the total number of clocks in the second line new_htotal has a buffer in the last line of the field blanking area.

[0151] from Figure 7 As can be seen in the figure, new_hcnt and new_vcnt are only followed by Vsync reset in the last line ( Figure 7 In the two D flip-flops that generate new_vcnt and new_hcnt, when the pos_vsync signal is 1, new_vcnt and new_hcnt will be set to 0), and the total number of second-row clocks new_htotal of the remaining rows is also stable. This situation can be regarded as outputting stable video timing.

[0152] Unstable video timing and data input Video Input writes all valid pixel data into the dual-port asynchronous FIFO module through the FIFO write control module. Figure 5As shown in , the write clock FIFO WCLK is equal to the Video CLK in the video timing and data input Video Input. In the actual circuit, it may be necessary to add a buffer or inverter in front of one of the signals to meet the timing requirements. The write enable FIFO WE is equal to the first data valid enable signal DataEn_IN in the video timing and data input Video Input. The write data FIFO WData is equal to the video timing and the Pixel data in the data input Video Input. The clear FIFO CLR is generated in the blanking area by the first field synchronization signal Vsync_IN and the first line synchronization signal Hsync_IN in the video timing and data input Video Input.

[0153] Stable video timing and data output Video Output, through the FIFO read control module, read the valid pixel data from the dual-port asynchronous FIFO module. Figure 5 As shown in , the read clock FIFO RCLK is equal to the Video CLK in the new video timing NewVideo Timing. In the actual circuit, it may be necessary to add a buffer or inverter before one of the signals to meet the timing requirements. The read enable FIFO RE is equal to the second data valid enable signal DataEn_OUT of the new video timing New Video Timing. The clear FIFO CLR is used for frame synchronization in the FIFO read control module.

[0154] The Video Clock in the video timing and data output Video Output is equal to the Video CLK in the new video timing New VideoTiming, and the Vsync (field synchronization signal) and Hsync (horizontal synchronization signal) in the video timing and data output Video Output are equal to the second field synchronization signal Vsync_OUT and the second horizontal synchronization signal Hsync_OUT in the new video timing New Video Timing delayed by one clock. Because the RData of FIFO is delayed by one clock relative to RE, the Pixel data in the video timing and data output Video Output is equal to the read data FIFO RData. At this time, the video timing and data output Video Output can be stably output to the subsequent circuit.

[0155] Step S5: Read and output the video pixel data from the buffer according to the second data valid enable signal DataEn_OUT, the second field synchronization signal Vsync_OUT, and the second row synchronization signal Hsync_OUT.

[0156] In this embodiment, the first preset logical operation is specifically: the first comparison value vmax is subjected to a "not" operation and then to an "and" operation with the second comparison value hmax to obtain a first intermediate value, the first intermediate value and the fourth type of rising edge pos_vsync are subjected to an "or" operation to obtain an enable signal EN of the first type D flip-flop; the fourth type of rising edge pos_vsync is used as the enable signal of the first selector, the first input end of the first selector is a low level, the second input end is electrically connected to the output end of the first counter, the input end of the first counter is electrically connected to the output end of the first type D flip-flop, the output end of the first selector is electrically connected to the input end of the first type D flip-flop, and the fourth type of rising edge pos_vsync is used as the input of the first type D flip-flop to obtain a third count new_vcnt.

[0157] In this embodiment, the second preset logic operation is specifically:

[0158] The first comparison value vmax is subjected to a "not" operation and then to an "and" operation with the second comparison value hmax to obtain a first intermediate value, the first intermediate value and the fourth type rising edge pos_vsync are subjected to an "or" operation and used as an enable input of the second selector, the first input end of the second selector is a low level, the second input end is electrically connected to the output end of the second counter, the input end of the second counter is electrically connected to the output end of the second type D flip-flop, the output end of the second selector is electrically connected to the input end of the second type D flip-flop, and the fourth count new_hcnt is obtained after the second type D flip-flop counting operation.

[0159] In this embodiment, the third preset logic operation is specifically:

[0160] Performing an AND operation on the first signal and the second signal to obtain a fifth signal;

[0161] Performing an AND operation on the third signal and the fourth signal to obtain a sixth signal;

[0162] The sixth signal is ANDed with the fifth signal and then inputted into the D terminal of the fifth type D flip-flop, and the output of the fifth type D flip-flop is used as the second data valid enable signal DataEn_OUT.

[0163] Reference Figure 1-8 The present invention provides a video timing re-editing circuit, comprising:

[0164] A data acquisition module, used for acquiring original video timing and video pixel data and caching the video pixel data according to a first video timing, wherein the original video timing includes a first video clock signal Video CLK, a first field synchronization signal Vsync_IN, a first line synchronization signal Hsync_IN, and a first data valid enable signal DataEn_IN;

[0165] A video analysis module, configured to analyze a first data valid enable signal DataEn_IN, a first field synchronization signal Vsync_IN, and a first line synchronization signal Hsync_IN according to a first video clock signal Video CLK to obtain first video timing information;

[0166] A video timing fine-tuning module, used to perform timing fine-tuning on the first video timing information according to a preset configuration strategy to obtain second video timing information;

[0167] A video timing generation module, used for obtaining a second video clock signal Retiming Video CLK and generating a stable second data valid enable signal DataEn_OUT, a second field synchronization signal Vsync_OUT, and a second row synchronization signal Hsync_OUT corresponding to the second video timing information according to the first field synchronization signal Vsync_IN, the second video clock signal Retiming Video CLK, and the second video timing information;

[0168] The data output module is used to control the FIFO read control module to read and output the video pixel data from the cache according to the second data valid enable signal DataEn_OUT, the second field synchronization signal Vsync_OUT, and the second line synchronization signal Hsync_OUT.

[0169] In the specific working process of the circuit and method for re-editing the video timing of this embodiment, the total number of first-line clocks htotal between the two first-line synchronization signals Hsync_IN in the unstable video timing is inconsistent between different lines, which is usually caused by the asynchronous Lane clock and video clock at the transmitting end and the receiving end. The unstable video timing data is processed by video timing re-editing to solve the problem of inconsistent total number of first-line clocks htotal. The first data valid enable signal DataEn_IN in the unstable video timing is discontinuous, which is usually caused by the video clock at the receiving end being greater than the video clock at the transmitting end. The unstable video timing data is processed by video timing re-editing to solve the problem of discontinuity of the first data valid enable signal DataEn_IN. The unstable video timing usually does not output the line synchronization Hsync in the field blanking interval. The unstable video timing data will continuously and stably output the line synchronization Hsync after the video timing re-editing. In the unstable video timing, the total clock error between frames and lines is uniformly placed in the unstable buffer of the last line of the new timing after the video timing re-editing is processed with a synchronous or asynchronous clock. The total number of clocks of the second line of output video timing and data output new_htotal is stable except for the last line in the field blanking area where there is a buffer. This situation can be regarded as outputting stable video timing.

[0170] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A method for re-editing video timing, characterized in that: include: Step S1, obtaining original video timing and video pixel data and caching the video pixel data according to a first video timing, wherein the original video timing includes a first video clock signal Video CLK, a first field synchronization signal Vsync_IN, a first row synchronization signal Hsync_IN, and a first data valid enable signal DataEn_IN; Step S2, analyzing the first data valid enable signal DataEn_IN, the first field synchronization signal Vsync_IN, and the first line synchronization signal Hsync_IN according to the first video clock signal Video CLK to obtain first video timing information VideoTiming Info; Step S3, fine-tuning the first video timing information according to a preset configuration strategy to obtain second video timing information New Video Timing Info; Step S4, obtaining the second video clock signal Retiming Video CLK and generating a stable second data valid enable signal DataEn_OUT, a second field synchronization signal Vsync_OUT, and a second row synchronization signal Hsync_OUT corresponding to the second video timing information New Video TimingInfo according to the first field synchronization signal Vsync_IN, the second video clock signal Retiming Video CLK, and the second video timing information New Video Timing Info; Step S5, reading and outputting the video pixel data from the cache according to the second data valid enable signal DataEn_OUT, the second field synchronization signal Vsync_OUT, and the second row synchronization signal Hsync_OUT; The preset configuration strategy specifically includes: fifo depth = 4*hactive; new_vsync_width+new_vback_porch=vsync_width+vback_porch+4; Vsync_OUT+new_vback_porch+new_vactive+new_vfront_porch is equal to or less than Vsync+vback_porch+vactive+vfront_porch; new_vactive=vactive, new_hactive=hactive; Among them, fifo depth is the configuration cache depth; hactive is the first line valid data width; new_vsync_width is the second field synchronization width; new_vback_porch is the second field back porch width; vsync_width is the first field synchronization width; vback_porch is the first field back porch width; Vsync_OUT is the second field synchronization signal; new_vback_porch is the second field back porch width; new_vactive is the second field valid data width; new_vfront_porch is the second field front porch width; Vsync_IN is the first field synchronization signal; vback_porch is the first field back porch width; vfront_porch is the first field front porch width; Hsync_OUT is the second line synchronization signal; new_hback_porch is the second line back porch width; new_hactive is the second line valid data width; new_hfront_porch is the second line front porch width; Hsync_IN is the first line synchronization signal; hback_porch is the first line back porch width; hfront_porch is the first line front porch width; f1 is Video f2 is the frequency of New Video CLK; f3 is the frequency of New Video CLK; The second video timing information includes the second field synchronization width new_vsync_width, the second field back porch width new_vback_porch, the second field valid data width new_vactive, the second field front porch width new_vfront_porch, the second line synchronization width new_hsync_width, the second line back porch width new_hback_porch, the second line valid data width new_hactive, the second line front porch width new_hfront_porch, the total number of lines in the second field new_vtotal, and the total number of clocks in the second line new_htotal.

2. The method for re-editing video timing according to claim 1, characterized in that: Step S2 specifically includes: Processing the first field synchronization signal Vsync_IN to extract a first type rising edge pos_vsync and a first type falling edge neg_vsync of the first field synchronization signal Vsync_IN; Processing the first row synchronization signal Hsync_IN to extract a second type rising edge pos_hsync and a second type falling edge neg_hsync of the first row synchronization signal Hsync_IN; Processing the first data valid enable signal DataEn_IN to extract a third type rising edge pos_de and a third type falling edge neg_de of the first data valid enable signal DataEn_IN; According to the first video clock signal Video CLK, the first third type rising edge pos_de after each second type rising edge pos_hsync is used as the first rising edge pos_hde; According to the first video clock signal Video CLK, the first third type rising edge pos_de after each first type rising edge pos_vsync is used as the second rising edge pos_vde; The first video timing information is calculated and obtained according to the first type rising edge pos_vsync, the first type falling edge neg_vsync, the second type rising edge pos_hsync, the second type falling edge neg_hsync, the first rising edge pos_hde, the third type rising edge pos_de, the third type falling edge neg_de, and the second rising edge pos_vde. The first video timing information specifically includes: field timing parameters, row timing parameters, and clock parameters.

3. The method for re-editing video timing according to claim 2, characterized in that: The field timing parameters include: first field synchronization width vsync_width, first field back porch width vback_porch, first field effective data width vactive, first field front porch width vfront_porch, and total number of rows in the first field vtotal; the field timing parameter acquisition process is as follows: Calculate all the clock cycle numbers between every two adjacent second type rising edges pos_hsync according to the second type rising edge pos_hsync, and use all the clock cycle numbers as the first cycle number hcnt; Calculate the number of first row synchronization signals Hsync_IN between every two adjacent first type rising edges pos_vsync according to the second type rising edge pos_hsync, and record the number of first row synchronization signals Hsync_IN as a first count vcnt; Calculate the number of first rising edges pos_hde between every two first-type rising edges pos_vsync according to the first rising edge pos_hde, and record the number of first rising edges pos_hde as a second count vde_cnt; When the third type falling edge neg_de is at a high level, the first cycle number hcnt and the first count vcnt are latched one by one to obtain the one-to-one corresponding original row front porch width hfront_porch_begin and original field front porch width vfront_porch_begin; When the first type falling edge neg_vsync is at a high level, the first count vcnt is latched to obtain the first field synchronization width vsync_width; When the second rising edge pos_vde is at a high level, the value of the first field synchronization width vsync_width minus the first count vcnt is latched to obtain the first field back porch width vback_porch; When the first type rising edge pos_vsync is at a high level, the second count vde_cnt is latched to obtain the first field valid data width vactive; When the first type rising edge pos_vsync is at a high level, the value of the first count vcnt minus the original field front shoulder width vfront_porch_begin is latched to obtain the first field front shoulder width vfront_porch; When the first type rising edge pos_vsync is at a high level, the first count vcnt is latched to obtain the total number of rows vtotal in the first field.

4. The method for re-editing video timing according to claim 3, characterized in that: The row timing parameters include the first row synchronization width hsync_width, the first row back porch width hback_porch, the first row effective data width hactive, and the first row front porch width hfront_porch; the row timing parameter acquisition process is as follows: Calculate the number of clock cycles of the first data valid enable signal DataEn_IN at a high level between every two adjacent second type rising edges pos_hsync according to the first data valid enable signal DataEn_IN, and use the number of clock cycles as the third cycle number hde_cnt; When the second type falling edge neg_hsync is at a high level, the first cycle number hcnt is latched to obtain the first row synchronization width hsync_width; When the first rising edge pos_hde is at a high level, the value of the first cycle number hcnt minus the first row synchronization width hsync_width is latched to obtain the first row back porch width hback_porch; When the second type rising edge pos_hsync is at a high level, the third cycle number hde_cnt is latched to obtain the first row valid data width hactive; When the second type rising edge pos_hsync is at a high level, the value of the first cycle number hcnt minus the original row front shoulder width hfront_porch_begin is latched to obtain the first row front shoulder width hfront_porch.

5. The method for re-editing video timing according to claim 4, characterized in that: The clock parameters include the total number of clocks in the first row htotal and the total number of clocks in the first frame ftotal. The clock parameter acquisition process is as follows: Calculate all the clock cycle numbers of every two adjacent first type rising edges pos_vsync according to the first type rising edge pos_vsync, and use all the clock cycle numbers as the second cycle number fcnt; When the second type rising edge pos_hsync is at a high level, the first cycle number hcnt is latched to obtain the first row clock total htotal; When the first type rising edge pos_vsync is at a high level, the second cycle number fcnt is latched to obtain the first frame clock total number ftotal.

6. The method for re-editing video timing according to claim 1, characterized in that: Step S4 specifically includes: Add the second field synchronization width new_vsync_width, the second field back porch width new_vback_porch, the second field effective data width new_vactive, and the second field front porch width new_vfront_porch to obtain the total number of rows in the second field new_vtotal; The second field synchronization width new_vsync_width, the second line back porch width new_hback_porch, the second line effective data width new_hactive, and the second line front porch width new_hfront_porch are added together to obtain the second line clock total new_htotal; After delaying the first field synchronization signal Vsync_IN by 2 clock cycles according to the second video clock signal Retiming Video CLK, an AND operation is performed with the first field synchronization signal Vsync_IN which is delayed by 3 clock cycles and inverted to obtain a fourth type rising edge pos_vsync; The third count new_vcnt and the total number of rows in the second field new_vtotal are judged for numerical relationship, and a first comparison value vmax is output; when the third count new_vcnt and the total number of rows in the second field vtotal are equal, the first comparison value vmax is a high level; The fourth count new_hcnt and the second row clock total new_htotal are numerically judged, and a second comparison value hmax is output; when the fourth count new_hcnt and the second row clock total new_htotal are equal, the second comparison value hmax is a high level; Performing a first preset logic operation on the fourth type rising edge pos_vsync, the first comparison value vmax, and the second comparison value hmax to obtain a third count new_vcnt; A second preset logic operation is performed on the fourth type rising edge pos_vsync, the first comparison value vmax, and the second comparison value hmax to obtain a fourth count new_hcnt.

7. The method for re-editing video timing according to claim 6, characterized in that: When the value of the third count new_vcnt is less than the second field synchronization width new_vsync_width, the output second field synchronization signal Vsync_OUT is at a high level; When the value of hcnt is less than the second row synchronization width new_hsync_width, the output second row synchronization signal Hsync_OUT is high level; Add the second field synchronization width new_vsync_width to the second field back porch width new_vback_porch, and then perform a numerical judgment with the third count new_vcnt, and when the third count new_vcnt is greater than or equal to the sum of the second field synchronization width new_vsync_width and the second field back porch width new_vback_porch, generate a first signal; When the third count new_vcnt is less than the difference between the total number of rows in the second field new_vtotal and the second field front porch width new_vfront_porch, a second signal is generated; Add the second row synchronization width new_hsync_width and the second row back porch width new_hback_porch, and then perform a numerical judgment with the fourth count new_hcnt, and when the fourth count new_hcnt is greater than or equal to the value of the sum of new_hsync_width and new_hback_porch, generate a third signal; When the fourth count new_hcnt is less than the difference between the second row clock total htotal and the second row front porch width new_hfront_porch, a fourth signal is generated; A third preset logic operation is performed on the first signal, the second signal, the third signal, and the fourth signal based on the second video clock signal Retiming Video CLK to obtain a second data valid enable signal DataEn_OUT.

8. The method for re-editing video timing according to claim 6, characterized in that: The first preset logical operation is specifically: performing a "not" operation on the first comparison value vmax and then performing an "and" operation with the second comparison value hmax to obtain a first intermediate value, performing an "or" operation on the first intermediate value and the fourth type of rising edge pos_vsync to obtain an enable signal EN of the first type D flip-flop; using the fourth type of rising edge pos_vsync as the enable signal of the first selector, the first input end of the first selector is a low level, the second input end is electrically connected to the output end of the first counter, the input end of the first counter is electrically connected to the output end of the first type D flip-flop, the output end of the first selector is electrically connected to the input end of the first type D flip-flop, and the fourth type of rising edge pos_vsync is used as the input of the first type D flip-flop to obtain a third count new_vcnt.

9. The method for re-editing video timing according to claim 6, characterized in that: The second preset logical operation is specifically: The first comparison value vmax is subjected to a "not" operation and then to an "and" operation with the second comparison value hmax to obtain a first intermediate value, the first intermediate value and the fourth type rising edge pos_vsync are subjected to an "or" operation and used as an enable input of the second selector, the first input end of the second selector is a low level, the second input end is electrically connected to the output end of the second counter, the input end of the second counter is electrically connected to the output end of the second type D flip-flop, the output end of the second selector is electrically connected to the input end of the second type D flip-flop, and the fourth count new_hcnt is obtained after the second type D flip-flop counting operation.

10. The method for re-editing video timing according to claim 7, characterized in that: The third preset logical operation is specifically: Performing an AND operation on the first signal and the second signal to obtain a fifth signal; Performing an AND operation on the third signal and the fourth signal to obtain a sixth signal; The sixth signal is ANDed with the fifth signal and then inputted into the D terminal of the fifth type D flip-flop, and the output of the fifth type D flip-flop is used as the second data valid enable signal DataEn_OUT.

11. A video timing re-editing circuit, characterized in that: include: A data acquisition module, used for acquiring original video timing and video pixel data and caching the video pixel data according to a first video timing, wherein the original video timing includes a first video clock signal Video CLK, a first field synchronization signal Vsync_IN, a first line synchronization signal Hsync_IN, and a first data valid enable signal DataEn_IN; A video analysis module, configured to analyze a first data valid enable signal DataEn_IN, a first field synchronization signal Vsync_IN, and a first line synchronization signal Hsync_IN according to a first video clock signal Video CLK to obtain first video timing information; A video timing fine-tuning module, used to perform timing fine-tuning on the first video timing information according to a preset configuration strategy to obtain second video timing information; A video timing generation module, used for obtaining a second video clock signal Retiming Video CLK and generating a stable second data valid enable signal DataEn_OUT, a second field synchronization signal Vsync_OUT, and a second row synchronization signal Hsync_OUT corresponding to the second video timing information according to the first field synchronization signal Vsync_IN, the second video clock signal Retiming Video CLK, and the second video timing information; A data output module, used for controlling the FIFO read control module to read and output video pixel data from the cache according to a second data valid enable signal DataEn_OUT, a second field synchronization signal Vsync_OUT, and a second line synchronization signal Hsync_OUT; In the video timing fine-tuning module, the preset configuration strategy specifically includes: fifo depth = 4*hactive; new_vsync_width+new_vback_porch=vsync_width+vback_porch+4; Vsync_OUT+new_vback_porch+new_vactive+new_vfront_porch is equal to or less than Vsync+vback_porch+vactive+vfront_porch; new_vactive=vactive, new_hactive=hactive; Among them, fifo depth is the configuration cache depth; hactive is the first line valid data width; new_vsync_width is the second field synchronization width; new_vback_porch is the second field back porch width; vsync_width is the first field synchronization width; vback_porch is the first field back porch width; Vsync_OUT is the second field synchronization signal; new_vback_porch is the second field back porch width; new_vactive is the second field valid data width; new_vfront_porch is the second field front porch width; Vsync_IN is the first field synchronization signal; vback_porch is the first field back porch width; vfront_porch is the first field front porch width; Hsync_OUT is the second line synchronization signal; new_hback_porch is the second line back porch width; new_hactive is the second line valid data width; new_hfront_porch is the second line front porch width; Hsync_IN is the first line synchronization signal; hback_porch is the first line back porch width; hfront_porch is the first line front porch width; f1 is Video f2 is the frequency of New Video CLK; f3 is the frequency of New Video CLK; The second video timing information includes the second field synchronization width new_vsync_width, the second field back porch width new_vback_porch, the second field valid data width new_vactive, the second field front porch width new_vfront_porch, the second line synchronization width new_hsync_width, the second line back porch width new_hback_porch, the second line valid data width new_hactive, the second line front porch width new_hfront_porch, the total number of lines in the second field new_vtotal, and the total number of clocks in the second line new_htotal.

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