A method and apparatus for constructing a quantum circuit

Abstract

The application discloses a method and device for constructing a quantum circuit. The method comprises the following steps: obtaining first information, second information and a group of quantum bits of a problem to be solved, wherein the number of quantum bits is determined according to the first information; then determining the number of quantum logic gates acting on the quantum bits, the action timing of the quantum logic gates and the regulation relationship between the quantum bits and the quantum logic gates according to the second information, and generating a quantum circuit to be constructed. The quantum circuit is constructed based on the problem to be solved, the search space is accurately limited in a reasonable dimension, the parameter quantity of the circuit is reduced, the dimension of the search space is exponentially reduced, and the convergence speed of the classical optimization is accelerated.

Description

Technical Field

[0001] This invention belongs to the field of quantum computing technology, specifically a method and apparatus for constructing quantum circuits. Background Technology

[0002] Currently, the NISQ computer has a high noise level, which prevents it from achieving the exponential speedup of fault-tolerant quantum algorithms compared to classical algorithms. However, the variable quantum algorithm offers a potential way to achieve speedup using the NISQ computer.

[0003] Variable quantum algorithms are a hybrid quantum-classical algorithm, mainly including variable quantum eigenvalue solvers (VQE) and quantum approximation optimization algorithms (QAOA). These algorithms can transform the cost function of the problem to be solved into a Hamiltonian and configure it with a Hilbert space of the target quantum state characterized by parameterized quantum circuits. Then, the parameters are updated by classical optimization methods such as gradient descent to find the minimum expected value (ground state energy) of the Hamiltonian in this space. The quantum state corresponding to this minimum value can be regarded as the solution to the problem to be solved.

[0004] Since the execution efficiency of the VQE algorithm heavily depends on the design of the proposed quantum circuit (ansatz), namely the parameterized quantum circuit used to search for the target quantum state, a pressing issue arises: how to construct a quantum circuit that more precisely restricts the search space to a reasonable dimension based on the problem to be solved, thereby reducing the number of parameters in the proposed quantum circuit, achieving an exponential reduction in the dimensionality of the search space, and accelerating the convergence speed of classical optimization. Summary of the Invention

[0005] The purpose of this invention is to provide a method and apparatus for constructing quantum circuits to overcome the shortcomings of the prior art. It constructs quantum circuits based on the problem to be solved, which precisely restricts the search space to a reasonable dimension, thereby reducing the number of parameters of the proposed circuit, exponentially reducing the dimension of the search space, and accelerating the convergence speed of classical optimization.

[0006] One embodiment of this application provides a method for constructing a quantum circuit, the method comprising:

[0007] Obtain first information, second information, and a set of qubits for the problem to be solved, wherein the number of qubits is determined based on the first information;

[0008] Based on the second information, the number of quantum logic gates acting on the qubit, the timing of the quantum logic gates, and the control relationship between the qubit and the quantum logic gates are determined, and a quantum circuit to be constructed is generated.

[0009] Optionally, the problem to be solved includes a quadratic unrestricted binary optimization problem of selecting k elements from n elements, where n is the first information and k is the second information.

[0010] Optionally, the numbering of the qubit i satisfies 0 ≤ i ≤ n-1. The step of determining the number of quantum logic gates acting on the qubit, the timing sequence of the quantum logic gates, and the control relationship between the qubit and the quantum logic gates based on the second information, and generating the quantum circuit to be constructed, includes:

[0011] Determine the parity of k;

[0012] When k is odd, the first sub-quantum circuit module is constructed sequentially in the first time sequence of the even-numbered qubits in the first k qubits using the first quantum logic gate combination.

[0013] Using the second quantum logic gate combination, starting from the qubit numbered i=2, a second sub-quantum circuit module is constructed within the second time sequence of the qubit;

[0014] Using the second combination of quantum logic gates, a third sub-quantum circuit module is constructed within a third time sequence of all the qubits;

[0015] The first sub-quantum circuit module, the second sub-quantum circuit module, and the third sub-quantum circuit module are combined sequentially to obtain the first target quantum circuit to be constructed.

[0016] Optionally, the first sub-quantum circuit module includes A first quantum logic gate combination;

[0017] The second sub-quantum circuit module includes A combination of second quantum logic gates;

[0018] The third sub-quantum circuit module includes (n-1) combinations of second quantum logic gates.

[0019] Optionally, the method further includes:

[0020] When k is even, the fourth sub-quantum circuit module is constructed sequentially in the first time sequence of the odd-numbered qubits in the first k qubits by using the first quantum logic gate combination.

[0021] Using the second combination of quantum logic gates, starting from the qubit numbered i=1, a fifth sub-quantum circuit module is constructed within the second time sequence of the qubit;

[0022] Using the second combination of quantum logic gates, a sixth sub-quantum circuit module is constructed within the third time sequence of all the qubits;

[0023] The fourth sub-quantum circuit module, the fifth sub-quantum circuit module, and the sixth sub-quantum circuit module are combined sequentially to obtain the second target quantum circuit to be constructed.

[0024] Optionally, the fourth sub-quantum circuit module includes (k / 2) combinations of first quantum logic gates;

[0025] The fifth sub-quantum circuit module includes A combination of second quantum logic gates;

[0026] The sixth sub-quantum circuit module includes (n-1) combinations of second quantum logic gates.

[0027] Optionally, the first quantum logic gate combination includes Pauli-X gates;

[0028] The second quantum logic gate combination includes controlled NOT gates and controlled rotation gates.

[0029] Another embodiment of this application provides a quantum circuit construction apparatus, the apparatus comprising:

[0030] The acquisition module is used to acquire first information, second information, and a set of qubits for the problem to be solved, wherein the number of qubits is determined according to the first information;

[0031] The determining module is used to determine, based on the second information, the number of quantum logic gates acting on the qubit, the timing of the quantum logic gates, and the control relationship between the qubit and the quantum logic gates, and to generate the quantum circuit to be constructed.

[0032] Optionally, the determining module includes:

[0033] A determining unit is used to determine the parity of k;

[0034] The first building unit is used to construct the first sub-quantum circuit module in the first time sequence of the even-numbered qubits in the first k qubits by using the first quantum logic gate combination when k is odd.

[0035] The second building unit is used to construct a second sub-quantum circuit module within the second time sequence of the qubit, starting from the qubit numbered i=2, using the second combination of quantum logic gates;

[0036] The third building unit is used to construct a third sub-quantum circuit module within a third time sequence of all the qubits by utilizing the second quantum logic gate combination;

[0037] The first combination unit is used to sequentially combine the first sub-quantum circuit module, the second sub-quantum circuit module, and the third sub-quantum circuit module to obtain the first target quantum circuit to be constructed.

[0038] Optionally, the determining module further includes:

[0039] The fourth building unit is used to construct the fourth sub-quantum circuit module in the first time sequence of the first k qubits, using the first quantum logic gate combination when k is even;

[0040] The fifth building unit is used to construct a fifth sub-quantum circuit module, starting from the qubit numbered i=1, within the second time sequence of the qubit using the second combination of quantum logic gates;

[0041] The sixth building unit is used to construct a sixth sub-quantum circuit module within a third time sequence of all the qubits using the second quantum logic gate combination;

[0042] The second combination unit is used to sequentially combine the fourth sub-quantum circuit module, the fifth sub-quantum circuit module, and the sixth sub-quantum circuit module to obtain the second target quantum circuit to be constructed.

[0043] Another embodiment of this application provides a quantum super cooperative operating system, which implements quantum circuit construction processing according to the method described in any of the preceding claims.

[0044] Another embodiment of this application provides a storage medium storing a computer program, wherein the computer program is configured to execute the method described in any of the preceding claims when running.

[0045] Another embodiment of this application provides an electronic device including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the method described in any of the preceding claims.

[0046] Compared with existing technologies, this invention first obtains first information and second information about the problem to be solved, as well as a set of qubits, wherein the number of qubits is determined according to the first information. Then, based on the second information, it determines the number of quantum logic gates acting on the qubits, the timing of the quantum logic gates, and the control relationship between the qubits and the quantum logic gates, and generates a quantum circuit to be constructed. By constructing a quantum circuit based on the problem to be solved, the search space is precisely restricted to a reasonable dimension, thereby reducing the number of parameters of the proposed circuit, achieving an exponential reduction in the dimension of the search space, and accelerating the convergence speed of classical optimization. Attached Figure Description

[0047] Figure 1 This is a system network block diagram of a quantum circuit construction method provided in an embodiment of the present invention;

[0048] Figure 2 This is a schematic flowchart of a method for constructing a quantum circuit according to an embodiment of the present invention;

[0049] Figure 3 This is a schematic diagram of the structure of the first sub-quantum circuit module provided in an embodiment of the present invention;

[0050] Figure 4 This is a schematic diagram of the structure of the combination of the first sub-quantum circuit module and the second sub-quantum circuit module provided in an embodiment of the present invention;

[0051] Figure 5 This is a schematic diagram of the structure of the combination of the first sub-quantum circuit module, the second sub-quantum circuit module and the third sub-quantum circuit module provided in the embodiment of the present invention;

[0052] Figure 6 This is a schematic diagram of the structure of the fourth sub-quantum circuit module provided in an embodiment of the present invention;

[0053] Figure 7 This is a schematic diagram of the structure of the combination of the fourth sub-quantum circuit module and the fifth sub-quantum circuit module provided in an embodiment of the present invention;

[0054] Figure 8 This is a schematic diagram of the structure of the combination of the fourth sub-quantum circuit module, the fifth sub-quantum circuit module and the sixth sub-quantum circuit module provided in the embodiment of the present invention;

[0055] Figure 9 This is a schematic diagram of a quantum circuit construction device provided in an embodiment of the present invention. Detailed Implementation

[0056] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0057] This invention first provides a method for constructing quantum circuits, which can be applied to electronic devices, such as computer terminals, specifically ordinary computers, quantum computers, etc.

[0058] The following detailed explanation uses a computer terminal as an example. Figure 1This is a system network block diagram of a quantum circuit construction method provided in an embodiment of the present invention. The system applied to the quantum circuit construction method may include a network 110, a server 120, a wireless device 130, a client 140, a storage unit 150, a classical processing system 160, a quantum processing system 170, and may also include additional memory, classical processor, quantum processor and other devices not shown.

[0059] Network 110 is a medium that provides communication links between various devices and computers connected together in a system network for the construction of quantum circuits, including but not limited to the Internet, corporate intranets, local area networks, mobile communication networks and combinations thereof, and the connection method can be wired, wireless communication links or fiber optic cables, etc.

[0060] Server 120 and client 140 are conventional data processing systems that may contain data and applications or software tools that perform conventional computational processes. Client 140 may be a personal computer or a network computer, so the data may also be provided by server 120. Wireless device 130 may be a smartphone, tablet, laptop, smart wearable device, etc. Storage unit 150 may include database 151, which can be configured to store data such as qubit parameters, quantum logic gate parameters, quantum circuits, and quantum programs.

[0061] The classical processing system 160 (quantum processing system 170) may include a classical processor 161 (quantum processor 171) for processing classical data (quantum data) and a memory 163 (memory 172) for storing classical data (quantum data). The classical data (quantum data) may be a boot file, an operating system image, and an application program 162 (application program 173). The application program 162 (application program 173) may be used to implement a quantum algorithm compiled by the quantum circuit construction method provided in the embodiments of the present invention.

[0062] Any data or information stored or generated in the classical processing system 160 (quantum processing system 170) can also be configured to be stored or generated in another classical (quantum) processing system in a similar manner, and any application executed therein can also be configured to be executed in another classical (quantum) processing system in a similar manner.

[0063] It should be noted that a true quantum computer has a hybrid structure, which includes at least... Figure 1 The system consists of two main parts: the classical processing system 160, which is responsible for performing classical calculations and control; and the quantum processing system 170, which is responsible for running quantum programs and thus realizing quantum computing.

[0064] The aforementioned classical processing system 160 and quantum processing system 170 can be integrated into a single device or distributed across two different devices. For example, the first device, including the classical processing system 160, runs a classical computer operating system that provides quantum application development tools and services, as well as the storage and network services required for quantum applications. Users develop quantum applications using the quantum application development tools and services on the second device and send the quantum program to the second device, including the quantum processing system 170, via the network services. The second device runs a quantum computer operating system, which parses the code of the quantum program and compiles it into instructions that can be recognized and executed by the quantum computer control system. The quantum processor 170 then implements the quantum algorithm corresponding to the quantum program based on these instructions.

[0065] In the classic silicon-based processing system 160, the units of the classic processor 161 are CMOS transistors. These computing units are not limited by time or coherence; that is, they are available at any time without time constraints. Furthermore, the number of these computing units in a silicon chip is sufficient; currently, a classic processor contains tens of thousands of computing units. The sufficient number of computing units and the fixed selectable computing logic of the CMOS transistors, such as AND logic, allow for computational efficiency through a combination of numerous CMOS transistors and limited logic functions.

[0066] Unlike the logic units in the classical processing system 160, the basic computational unit of the quantum processor 171 in the quantum processing system 170 is the qubit. The input of a qubit is limited by coherence and coherence time; that is, a qubit is limited by its available usage time and is not always readily available. Making full use of qubits within their available usage time is a key challenge in quantum computing. Furthermore, the number of qubits in a quantum computer is one of the representative indicators of its performance. Each qubit performs computational functions through on-demand configured logic functions. Given the limited number of qubits and the diverse logic functions available in quantum computing, such as Hadamard gates (H gates), Pauli-X gates (X gates), Pauli-Y gates (Y gates), Pauli-Z gates (Z gates), X gates, RY gates, RZ gates, CNOT gates, CR gates, iSWAP gates, Tofoli gates, etc., quantum computing requires combining a limited number of qubits with diverse combinations of logic functions to achieve computational effects.

[0067] Based on these differences, the design of logical functions applied to qubits (including the design of whether qubits are used and the design of the efficiency of each qubit) is crucial to improving the computational performance of quantum computers and requires special design. The aforementioned design of qubits is a technical problem that ordinary computing devices do not need to consider or address. In this application, given that the execution efficiency of some quantum algorithms (such as the VQE algorithm) heavily depends on the design of the proposed quantum circuit (ansatz), how to construct a quantum circuit that more precisely restricts the search space to a reasonable dimension based on the problem to be solved has become an urgent problem to be solved. This application provides a method and apparatus for constructing a quantum circuit to overcome the shortcomings of the prior art. It reduces the number of parameters in the proposed circuit by constructing a quantum circuit that precisely restricts the search space to a reasonable dimension based on the problem to be solved, thereby achieving an exponential reduction in the dimensionality of the search space and accelerating the convergence speed of classical optimization.

[0068] See Figure 2 , Figure 2 This is a flowchart illustrating a method for constructing a quantum circuit according to an embodiment of the present invention, which may include the following steps:

[0069] S201: Obtain first information, second information, and a set of qubits for the problem to be solved, wherein the number of qubits is determined according to the first information.

[0070] Specifically, the problem to be solved includes a quadratic unrestricted binary optimization problem of selecting k elements from n elements, where n is the first information and k is the second information.

[0071] For example, in the field of financial investment, choosing k assets from n alternative assets to invest in in order to maximize returns while keeping risks under control, the total number of possible choices is (e.g., ...). To simulate the optimal solution to this problem using quantum algorithms, a minimum of n qubits is required.

[0072] As those skilled in the art will understand, in classical computers, the basic unit of information is the bit, which has two states: 0 and 1. The most common physical implementation uses high and low voltage levels to represent these states. In quantum computing, the basic unit of information is the qubit, which also has two states: 0 and 1, denoted as |0> and |1>. However, it can exist in a superposition of these two states, which can be represented as... Here, a and b are complex numbers representing the amplitudes (probability amplitudes) of the |0> and |1> states, respectively, which is not present in classical bits. After measurement, the state of a qubit collapses to a definite state, where the probability of collapsing to |0> is |a|. 2 The probability of collapsing to |1> is |b|.2 , |a| 2 +|b| 2 =1, |> is the Dirac notation.

[0073] S202: Based on the second information, determine the number of quantum logic gates acting on the qubit, the timing of the quantum logic gates, and the control relationship between the qubit and the quantum logic gates, and generate the quantum circuit to be constructed.

[0074] Quantum circuits, also known as quantum logic circuits, are a manifestation of quantum programming and the most commonly used general-purpose quantum computing model. They represent circuits that operate on qubits under an abstract concept. A quantum circuit consists of qubits, circuits (timelines), and various quantum logic gates. The results are often retrieved through quantum measurement operations. Unlike traditional circuits that use metal wires to transmit voltage or current signals, in quantum circuits, the circuits can be viewed as being connected by time. That is, the state of a qubit evolves naturally over time, following the instructions of Hamiltonian operators until it encounters a logic gate and is manipulated.

[0075] Specifically, the numbering of the qubit i satisfies 0 ≤ i ≤ n-1. The step of determining the number of quantum logic gates acting on the qubit, the timing sequence of the quantum logic gates, and the control relationship between the qubit and the quantum logic gates based on the second information, and generating the quantum circuit to be constructed, may include:

[0076] 1. Determine the parity of k.

[0077] Specifically, for the quadratic unrestricted binary optimization problem to be solved, the state of a specific Hamming weight can be understood as the selection of k corresponding schemes from n elements, where k is the Hamming weight.

[0078] 2. When k is odd, the first sub-quantum circuit module is constructed sequentially in the first time sequence of the even-numbered qubits among the first k qubits using the first quantum logic gate combination.

[0079] For example, taking n=6 and k=3 as an example, the first quantum logic gate combination is used to construct the first sub-quantum circuit module in the first time sequence of the even-numbered qubits in the first 3 qubits, namely q[0] and q[2]. The first quantum logic gate combination includes Pauli-X gate or simply X gate.

[0080] It's important to note that qubits can be manipulated using quantum logic gates. Quantum logic gates enable the evolution of quantum states and are the foundation of quantum circuits. These gates include single-qubit gates such as Hadamard gates (H-gates), Pauli-X gates (X-gates), Pauli-Y gates (Y-gates), Pauli-Z gates (Z-gates), RX gates, RY gates, RZ gates, etc.; and multi-qubit gates such as CNOT gates, CR gates, iSWAP gates, Tofoli gates, etc. Quantum logic gates are generally represented using unitary matrices, which are not only matrix forms but also operations and transformations. The effect of a quantum logic gate on a quantum state is typically calculated by left-multiplying the unitary matrix by the matrix corresponding to the right vector of the quantum state.

[0081] See Figure 3 , Figure 3 This is a schematic diagram of the structure of the first sub-quantum circuit module provided in an embodiment of the present invention, as shown below. Figure 3 As shown, a set of qubits are q[0], q[1], q[2], q[3], q[4], and q[5], representing the 0th, 1st, 2nd, 3rd, 4th, and 5th qubits, and ordered from most to least significant qubit as q[5]q[4]q[3]q[2]q[1]q[0]. The first time sequence of qubits numbered q[0] and q[2] includes... Each of the first quantum logic gate combinations consists of a Pauli-X gate.

[0082] 3. Using the combination of second quantum logic gates, starting from the qubit numbered i=2, construct the second sub-quantum circuit module within the second time sequence of the qubit.

[0083] For example, see Figure 4 , Figure 4 This is a schematic diagram of the structure of the combination of the first sub-quantum circuit module and the second sub-quantum circuit module provided in an embodiment of the present invention, as shown below. Figure 4 As shown, the second sub-quantum circuit module occupies a position in the quantum circuit, which can be collectively referred to as the second time sequence. Within the second time sequence, the second sub-quantum circuit module includes... A second quantum logic gate combination, comprising controlled NOT gates and controlled rotation gates, specifically three combinations of controlled NOT gates (CNOT quantum logic gates) and controlled rotation gates (e.g., controlled RY quantum logic gates). The controlled bits of the controlled RY quantum logic gates and CNOT quantum logic gates are different, and the three combinations of controlled RY and CNOT quantum logic gates exhibit a regular, stepped arrangement in the quantum circuit.

[0084] 4. Using the second quantum logic gate combination, construct a third sub-quantum circuit module within the third time sequence of all the qubits.

[0085] For example, see Figure 5 , Figure 5 This is a schematic diagram of the structure of the combination of the first sub-quantum circuit module, the second sub-quantum circuit module and the third sub-quantum circuit module provided in the embodiment of the present invention, as shown below. Figure 5 As shown, the third sub-quantum circuit module occupies a position in the quantum circuit, which can be collectively referred to as the third time sequence. Within the third time sequence, the third sub-quantum circuit module includes (6-1) combinations of second quantum logic gates, and these combinations include controlled NOT gates and controlled rotation gates. For example, it could be a combination containing 5 sets of CNOT quantum logic gates and controlled RY quantum logic gates. The controlled bits of the controlled RY quantum logic gates and CNOT quantum logic gates are different, and the 5 sets of controlled RY quantum logic gates and CNOT quantum logic gates are arranged in a regular, stepped pattern within the quantum circuit.

[0086] 5. The first sub-quantum circuit module, the second sub-quantum circuit module, and the third sub-quantum circuit module are combined sequentially to obtain the first target quantum circuit to be constructed.

[0087] For example, the first target quantum circuit to be constructed is composed of, for instance, Figure 5 The diagram shows the generation of the first sub-quantum circuit module, the second sub-quantum circuit module, and the third sub-quantum circuit module.

[0088] In an alternative implementation, determining the parity of k may further include the following steps:

[0089] Step 1: When k is even, the fourth sub-quantum circuit module is constructed sequentially in the first time sequence of the odd-numbered qubits in the first k qubits using the first quantum logic gate combination.

[0090] For example, taking n=6 and k=2 as an example, the first quantum logic gate combination is used to construct the fourth sub-quantum circuit module in the first two quantum bits, the odd-numbered quantum bits, i.e., the numbered q[1] in the first time sequence. The first quantum logic gate combination includes Pauli-X gate.

[0091] See Figure 6 , Figure 6 This is a schematic diagram of the structure of the fourth sub-quantum circuit module provided in an embodiment of the present invention, as shown below. Figure 6 As shown, a set of qubits are q[0], q[1], q[2], q[3], q[4], and q[5]. Among them, the first time sequence of the qubit numbered q[1] includes 2 / 2) combinations of first quantum logic gates, that is, only one Pauli-X gate is set.

[0092] Step 2: Using the second quantum logic gate combination, starting from the qubit numbered i=1, construct the fifth sub-quantum circuit module within the second time sequence of the qubit.

[0093] For example, see Figure 7 , Figure 7 This is a schematic diagram of the structure of the combination of the fourth sub-quantum circuit module and the fifth sub-quantum circuit module provided in an embodiment of the present invention, as shown below. Figure 7 As shown, the fifth sub-quantum circuit module occupies a position in the quantum circuit, which can be collectively referred to as the second time sequence. Within the second time sequence, the second sub-quantum circuit module includes... A second quantum logic gate combination, comprising controlled NOT gates and controlled rotation gates, such as a combination of four CNOT quantum logic gates and controlled RY quantum logic gates. The controlled bits of the controlled RY quantum logic gates and CNOT quantum logic gates are different, and the four combinations of controlled RY and CNOT quantum logic gates exhibit a regular, stepped arrangement in the quantum circuit.

[0094] Step 3: Using the second quantum logic gate combination, construct the sixth sub-quantum circuit module within the third time sequence of all the qubits.

[0095] For example, see Figure 8 , Figure 8 This is a schematic diagram of the structure of the combination of the fourth sub-quantum circuit module, the fifth sub-quantum circuit module, and the sixth sub-quantum circuit module provided in an embodiment of the present invention, as shown below. Figure 8 As shown, the sixth sub-quantum circuit module occupies a position in the quantum circuit, which can be collectively referred to as the third time sequence. Within the third time sequence, the sixth sub-quantum circuit module includes (6-1) combinations of second quantum logic gates, which include controlled NOT gates and controlled rotation gates, for example, combinations of 5 sets of CNOT quantum logic gates and controlled RY quantum logic gates. The controlled bits of the controlled RY quantum logic gates and CNOT quantum logic gates are different, and the 5 sets of controlled RY quantum logic gates and CNOT quantum logic gates are arranged in a regular, stepped pattern within the quantum circuit.

[0096] Step 4: Combine the fourth sub-quantum circuit module, the fifth sub-quantum circuit module, and the sixth sub-quantum circuit module in sequence to obtain the second target quantum circuit to be constructed.

[0097] For example, the second target quantum circuit to be constructed is composed of, for instance, Figure 8 The diagram shows the generation of the fourth, fifth, and sixth sub-quantum circuit modules.

[0098] It should be noted that the structure formed by the combination of controlled RY quantum logic gates and CNOT quantum logic gates in each sub-quantum circuit module can be an operator U, for example... Figure 7 The quantum circuit shown has superposition states composed of basis vectors |010000>, |001000>, |000100>, |000010>, and |000001>, where the controlled RY quantum logic gate can contain the parameters of the circuit.

[0099] Induction reveals that for the first and second target quantum circuits mentioned above, when k is odd, the quantum logic gates executed in the first time sequence are XIXIX…; when k is even, the gates executed in the first time sequence are IXIXIX…, where I is the identity matrix; and the X gates in subsequent quantum circuits need to be followed by a combination of controlled RY quantum logic gates and CNOT quantum logic gates. The number of such structures can be determined by the distance between the bottom X gate and the bottom qubit.

[0100] This application constructs a target quantum circuit and statistically analyzes the output under different inputs, summarizing a ladder-type proposed quantum circuit that only contains nearest-neighbor interactions. It is a problem-friendly proposed quantum circuit that meets the current limitations of quantum hardware. Its output quantum state mainly contains the basis vector of the target Hamming weight, which greatly reduces the dimensionality of space and the number of parameters in the proposed circuit, effectively overcoming the problem of barren plateau.

[0101] As can be seen, the present invention first obtains first information and second information about the problem to be solved, as well as a set of qubits, wherein the number of qubits is determined according to the first information; then, based on the second information, it determines the number of quantum logic gates acting on the qubits, the timing of the quantum logic gates, and the control relationship between the qubits and the quantum logic gates, and generates a quantum circuit to be constructed. By constructing a quantum circuit based on the problem to be solved, the search space is precisely restricted to a reasonable dimension, thereby reducing the number of parameters of the proposed circuit, achieving an exponential reduction in the dimension of the search space, and accelerating the convergence speed of classical optimization.

[0102] See Figure 9 , Figure 9 This is a schematic diagram of a quantum circuit construction device provided in an embodiment of the present invention. Figure 2 The process shown can include:

[0103] The module 901 is used to obtain first information, second information, and a set of qubits for the problem to be solved, wherein the number of qubits is determined according to the first information;

[0104] The determining module 902 is used to determine, based on the second information, the number of quantum logic gates acting on the quantum bit, the timing of the quantum logic gates, and the control relationship between the quantum bit and the quantum logic gates, and to generate the quantum circuit to be constructed.

[0105] Specifically, the determining module includes:

[0106] A determining unit is used to determine the parity of k;

[0107] The first building unit is used to construct the first sub-quantum circuit module in the first time sequence of the even-numbered qubits in the first k qubits by using the first quantum logic gate combination when k is odd.

[0108] The second building unit is used to construct a second sub-quantum circuit module within the second time sequence of the qubit, starting from the qubit numbered i=2, using the second combination of quantum logic gates;

[0109] The third building unit is used to construct a third sub-quantum circuit module within a third time sequence of all the qubits by utilizing the second quantum logic gate combination;

[0110] The first combination unit is used to sequentially combine the first sub-quantum circuit module, the second sub-quantum circuit module, and the third sub-quantum circuit module to obtain the first target quantum circuit to be constructed.

[0111] Specifically, the determining module further includes:

[0112] The fourth building unit is used to construct the fourth sub-quantum circuit module in the first time sequence of the first k qubits, using the first quantum logic gate combination when k is even;

[0113] The fifth building unit is used to construct a fifth sub-quantum circuit module, starting from the qubit numbered i=1, within the second time sequence of the qubit using the second combination of quantum logic gates;

[0114] The sixth building unit is used to construct a sixth sub-quantum circuit module within a third time sequence of all the qubits using the second quantum logic gate combination;

[0115] The second combination unit is used to sequentially combine the fourth sub-quantum circuit module, the fifth sub-quantum circuit module, and the sixth sub-quantum circuit module to obtain the second target quantum circuit to be constructed.

[0116] Compared with existing technologies, this invention first obtains first information and second information about the problem to be solved, as well as a set of qubits, wherein the number of qubits is determined according to the first information. Then, based on the second information, it determines the number of quantum logic gates acting on the qubits, the timing of the quantum logic gates, and the control relationship between the qubits and the quantum logic gates, and generates a quantum circuit to be constructed. By constructing a quantum circuit based on the problem to be solved, the search space is precisely restricted to a reasonable dimension, thereby reducing the number of parameters of the proposed circuit, achieving an exponential reduction in the dimension of the search space, and accelerating the convergence speed of classical optimization.

[0117] This invention also provides a quantum-supercomputer cooperating operating system, which runs on a quantum computer including a quantum processor and / or a supercomputer including a classical processor, for implementing the quantum circuit construction process according to the method described in the method-side embodiment of this invention.

[0118] This invention also provides a storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the method embodiments described above when running.

[0119] Specifically, in this embodiment, the storage medium can be configured to store a computer program for performing the following steps:

[0120] S201: Obtain first information, second information, and a set of qubits for the problem to be solved, wherein the number of qubits is determined according to the first information;

[0121] S202: Based on the second information, determine the number of quantum logic gates acting on the qubit, the timing of the quantum logic gates, and the control relationship between the qubit and the quantum logic gates, and generate the quantum circuit to be constructed.

[0122] Specifically, in this embodiment, the storage medium may include, but is not limited to, USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks, and other media capable of storing computer programs.

[0123] This invention also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the method embodiments described above.

[0124] Specifically, the aforementioned electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the aforementioned processor, and the input / output device is connected to the aforementioned processor.

[0125] Specifically, in this embodiment, the processor can be configured to perform the following steps via a computer program:

[0126] S201: Obtain first information, second information, and a set of qubits for the problem to be solved, wherein the number of qubits is determined according to the first information;

[0127] S202: Based on the second information, determine the number of quantum logic gates acting on the qubit, the timing of the quantum logic gates, and the control relationship between the qubit and the quantum logic gates, and generate the quantum circuit to be constructed.

[0128] The above description, based on the embodiments shown in the figures, details the structure, features, and effects of the present invention. The above description is only a preferred embodiment of the present invention, but the present invention is not limited to the scope of implementation shown in the figures. Any changes made in accordance with the concept of the present invention, or equivalent embodiments modified to have equivalent changes, that do not exceed the spirit covered by the specification and figures, should be within the protection scope of the present invention.

Claims

1. A method for constructing a quantum circuit, characterized in that, The method includes: The process involves obtaining first information, second information, and a set of qubits for a problem to be solved, wherein the number of qubits is determined based on the first information; the problem to be solved includes information from... Select from elements A quadratic unrestricted binary optimization problem, wherein, For the first information, This is the second piece of information; The numbering of the qubits satisfy When the When the number is odd, the first quantum logic gates are combined sequentially in the order of... Of the qubits, the even-numbered qubits are used to construct the first sub-quantum circuit module within the first time sequence; using the second quantum logic gate combination, from the numbered... Starting with a qubit, a second sub-quantum circuit module is constructed within a second time sequence of the qubit; using the second quantum logic gate combination, a third sub-quantum circuit module is constructed within a third time sequence of all the qubits; the first sub-quantum circuit module, the second sub-quantum circuit module, and the third sub-quantum circuit module are combined sequentially to obtain the first target quantum circuit to be constructed; When the When the number is even, the first quantum logic gates are combined sequentially in the order of... Of the qubits, the fourth sub-quantum circuit module is constructed within the first time sequence of the odd-numbered qubits; using the second quantum logic gate combination, from the numbered... Starting with the qubit, a fifth sub-quantum circuit module is constructed within the second time sequence of the qubit; using the second quantum logic gate combination, a sixth sub-quantum circuit module is constructed within the third time sequence of all the qubits; the fourth sub-quantum circuit module, the fifth sub-quantum circuit module, and the sixth sub-quantum circuit module are combined sequentially to obtain the second target quantum circuit to be constructed; The first quantum logic gate combination includes a Pauli-X gate; the second quantum logic gate combination includes a CNOT gate and a controlled RY gate, wherein the controlled bits of the controlled RY gate and the CNOT gate are different, and the controlled RY gate and the CNOT gate combination exhibits a regular ladder-like arrangement in the quantum circuit.

2. The method according to claim 1, characterized in that, The first sub-quantum circuit module includes A first quantum logic gate combination; The second sub-quantum circuit module includes A combination of second quantum logic gates; The third sub-quantum circuit module includes A combination of second quantum logic gates.

3. The method according to claim 1, characterized in that, The fourth sub-quantum circuit module includes A first quantum logic gate combination; The fifth sub-quantum circuit module includes A combination of second quantum logic gates; The sixth sub-quantum circuit module includes A combination of second quantum logic gates.

4. A device for constructing quantum circuits, characterized in that, The device includes: The acquisition module is used to acquire first information, second information, and a set of qubits for the problem to be solved, wherein the number of qubits is determined according to the first information; the problem to be solved includes information from... Select from elements A quadratic unrestricted binary optimization problem, wherein, For the first information, This is the second piece of information; Determining module for numbering the qubits satisfy When the When the number is odd, the first quantum logic gates are combined sequentially in the order of... Of the qubits, the even-numbered qubits are used to construct the first sub-quantum circuit module within the first time sequence; using the second quantum logic gate combination, from the numbered... Starting with the first qubit, a second sub-quantum circuit module is constructed within the second time sequence of the qubit; using the second quantum logic gate combination, a third sub-quantum circuit module is constructed within the third time sequence of all the qubits; the first sub-quantum circuit module, the second sub-quantum circuit module, and the third sub-quantum circuit module are sequentially combined to obtain the first target quantum circuit to be constructed; when the When the number is even, the first quantum logic gates are combined sequentially in the order of... Of the qubits, the fourth sub-quantum circuit module is constructed within the first time sequence of the odd-numbered qubits; using the second quantum logic gate combination, from the numbered... Starting with the first qubit, a fifth sub-quantum circuit module is constructed within the second time sequence of the qubit; using the second quantum logic gate combination, a sixth sub-quantum circuit module is constructed within the third time sequence of all the qubits; the fourth, fifth, and sixth sub-quantum circuit modules are sequentially combined to obtain the second target quantum circuit to be constructed; wherein, the first quantum logic gate combination includes Pauli-X gates; the second quantum logic gate combination includes CNOT gates and controlled RY gates, the controlled bits of the controlled RY gates and CNOT gates are different, and the combination of controlled RY gates and CNOT gates presents a regular ladder-like arrangement in the quantum circuit.

5. A quantity-capable collaborative operating system, characterized in that, The quantum super cooperative operating system implements the quantum circuit construction process according to any one of claims 1 to 3.

6. A storage medium, characterized in that, The storage medium stores a computer program, wherein the computer program is configured to execute the method described in any one of claims 1 to 3 when it is run.

7. An electronic device comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to run the computer program to perform the method described in any one of claims 1 to 3.

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