A signal processing method, device and medium

Abstract

The application discloses a signal processing method and device and a medium, and relates to the technical field of computers. The method applied to a receiving end device comprises the following steps: receiving a first signal sent by a sending end device; the first signal comprises a preamble and data code, the preamble carries first indication information, and the first indication information is used for indicating a first target bit in the preamble; according to the first indication information, the value of the first target bit is obtained and stored as a target value; the value of the first target bit is determined by the sending end device according to the number of logical '1' and the number of logical '0' in a source signal corresponding to the first signal, and the source signal is a signal that has not been subjected to source encoding; in the case that data decoding is performed and an error code is detected, the decoding value of a code block in which the error code occurs is determined as the target value. The embodiment of the application can reduce the receiving error rate.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a signal processing method, device and medium. Background Technology

[0002] The 3rd Generation Partnership Project (3GPP) sets the expected communication distance for cellular passive IoT technology at 30-50m indoors and around 200m outdoors, which is at least three times higher than the communication distance of Radio Frequency Identification (RFID). Therefore, the methods for improving the communication distance of cellular passive IoT need to be optimized.

[0003] Existing RFID protocols typically use Pulse Interval Encoding (PIE) for decoding, which is prone to bit misinterpretation. In cellular passive IoT systems, as communication distance increases, the system signal-to-noise ratio decreases. Continuing to use PIE encoding will inevitably lead to a higher system error rate, affecting the accuracy of system data transmission. Summary of the Invention

[0004] This invention provides a signal processing method, device, and medium to address the problem of low bit error rate in cellular passive Internet of Things (IoT) systems.

[0005] To solve the above-mentioned technical problems, the present invention is implemented as follows:

[0006] In a first aspect, embodiments of the present invention provide a signal processing method applied to a receiving device, the method comprising:

[0007] The receiver receives a first signal sent by the transmitting device. The first signal includes a preamble and a data code. The preamble carries first indication information, which is used to indicate a first target bit in the preamble.

[0008] According to the first indication information, the value of the first target bit is obtained and stored as a target value. The value of the first target bit is determined by the transmitting device based on the number of logic "1"s and logic "0"s in the source signal corresponding to the first signal. The source signal is a signal that has not undergone source coding.

[0009] If a data decoding process is performed and a bit error is detected, the decoded value of the code block containing the bit error is determined as the target value.

[0010] Optionally, if the number of logic "1"s in the source signal is greater than the number of logic "0", the value of the first target bit is 1;

[0011] When the number of logic "1"s in the source signal is less than the number of logic "0", the value of the first target bit is 0.

[0012] Optionally, the method further includes:

[0013] If a data decoding is performed and a bit error is detected, a second indication information is sent to the transmitting device. The second indication information is used to instruct the transmitting device to perform an odd number of repetitions based on the source signal.

[0014] The receiver receives a second signal transmitted by the transmitting end. The second signal includes N subsequences, which are obtained by encoding the source signal, where N is an odd number.

[0015] Data decoding is performed on the N subsequences respectively, and if a bit error is detected, the decoding value of the code block with the bit error is determined as the target value, so as to obtain N first decoding sequences corresponding to the N subsequences respectively;

[0016] The N first decoding sequences are accumulated according to their corresponding bits to obtain the first joint decoding sequence;

[0017] The final decoding result is determined based on the first joint decoding sequence.

[0018] Optionally, after receiving the second signal sent by the transmitting end, the method further includes:

[0019] If the second signal consists of M subsequences and M is an even number, discard k subsequences from the M subsequences to obtain the N subsequences, where k is an odd number and N = Mk;

[0020] When the second signal consists of M subsequences and M is an odd number, the M subsequences are obtained, and N = M.

[0021] Optionally, the step of performing corresponding bit-by-bit accumulation on the N first decoding sequences to obtain the first joint decoding sequence includes any one of the following:

[0022] The values ​​of each bit in each of the N first decoding sequences are accumulated one by one to obtain the first joint decoding sequence;

[0023] The values ​​of the second target bits of each of the N first decoding sequences are accumulated one by one to obtain the first joint decoding sequence, where the second target bit is the bit corresponding to the code block that has an error.

[0024] Optionally, N is an odd number and N = 2^n - 1, where n is a positive integer. The step of determining the final decoding result based on the first joint decoding sequence includes:

[0025] In the first joint decoding sequence, if the value of the first bit is greater than or equal to 2^(n-1), the value of the first bit is determined to be 1;

[0026] In the first joint decoding sequence, if the value of the second bit is less than 2^(n-1), the value of the second bit is determined to be 0.

[0027] Optionally, before obtaining the value of the first target bit according to the first indication information and storing it as a target value, the method further includes:

[0028] Perform a Cyclic Redundancy Check (CRC) on the preamble;

[0029] The step of obtaining the value of the first target bit according to the first indication information and storing it as a target value includes:

[0030] If the preamble CRC check passes, the value of the first target bit is obtained according to the first indication information and stored as the target value.

[0031] Optionally, the method further includes:

[0032] If the CRC check of the preamble fails and the preamble can be identified, the value of the first target bit is obtained according to the first indication information, and the value of the first target bit is inverted and stored as the target value.

[0033] Optionally, performing a Cyclic Redundancy Check (CRC) on the preamble includes:

[0034] If a first CRC checksum exists between the preamble and the data code, the preamble is subjected to CRC checksum verification based on the first CRC checksum.

[0035] Optionally, the data code comprises L sub-blocks, and the method further includes:

[0036] If a second CRC checksum is detected after data decoding, the i-th sub-block is subjected to CRC checksum based on the second CRC checksum, where 1≤i≤L;

[0037] If at least one of the L sub-blocks passes the CRC check, the final decoding result is determined based on the decoding result of the at least one sub-block that passed the CRC check.

[0038] If the CRC check of the L sub-blocks fails, the L second decoding sequences corresponding to the L sub-blocks are accumulated bit by bit to obtain the second joint decoding sequence, and the final decoding result is determined based on the second joint decoding sequence.

[0039] Optionally, determining the final decoding result based on the second joint decoding sequence includes:

[0040] In the second joint decoding sequence, if the value of the third bit is greater than or equal to (X+1) / 2, the value of the third bit is determined to be 1;

[0041] In the second joint decoding sequence, if the value of the fourth bit is less than (X+1) / 2, the value of the fourth bit is determined to be 0;

[0042] Where X represents the number of repetitions.

[0043] Secondly, embodiments of the present invention also provide a signal processing method applied to a transmitting device, the method comprising:

[0044] Acquire the source signal to be sent;

[0045] Based on the number of logic "1"s and logic "0"s in the source signal, a first logic value is determined. The first logic value is used by the receiving device to determine the decoding result of the first code block with the bit error when performing data decoding and detecting a bit error.

[0046] The source signal is source encoded to generate a preamble and a data code, and the value of the first target bit in the preamble is set to the first logic value. The preamble carries first indication information, which is used to indicate the first target bit.

[0047] A first signal is sent to the receiving device, the first signal including the preamble and the data code.

[0048] Optionally, determining the first logic value based on the number of logic "1"s and logic "0"s in the source signal includes:

[0049] If the number of logic "1"s in the source signal is greater than the number of logic "0", the first logic value is determined to be 1; or if the number of logic "1"s in the source signal is less than the number of logic "0", the first logic value is determined to be 0.

[0050] Optionally, the method further includes:

[0051] Upon receiving the second indication information sent by the receiving device, a second signal is sent to the receiving device. The second signal includes N sub-sequences, which are obtained by encoding the source signal, where N is an odd number.

[0052] Optionally, before sending the first signal to the receiving device, the method further includes:

[0053] A first CRC checksum is inserted between the preamble and the data code, wherein the first signal includes the preamble, the first CRC checksum, and the data code.

[0054] Optionally, before sending the first signal to the receiving device, the method further includes:

[0055] The data code is divided into L sub-blocks;

[0056] A second CRC checksum is inserted between any two adjacent sub-blocks in the L sub-blocks. The first signal includes the preamble, the data code, and L-1 second CRC checksums.

[0057] Optionally, neither the preamble nor the data code contains a sequence of two or more consecutive "10"s.

[0058] Optionally, the step of performing source coding on the source signal to generate a preamble and a data code includes:

[0059] The source signal is precoded to obtain a precoded signal, wherein the encoding length obtained by precoding logic "1" is equal to the encoding length obtained by precoding logic "0".

[0060] The precoded signal is subjected to Pulse Width Encoding (PIE) to generate a preamble and a data code.

[0061] Thirdly, embodiments of the present invention also provide a receiving end device, the device comprising:

[0062] A first receiving module is configured to receive a first signal sent by a transmitting device; the first signal includes a preamble and a data code, the preamble carries first indication information, and the first indication information is used to indicate a first target bit in the preamble.

[0063] The first acquisition module is used to acquire the value of the first target bit according to the first indication information and store it as a target value; the value of the first target bit is determined by the transmitting device according to the number of logic "1"s and logic "0"s in the source signal corresponding to the first signal, wherein the source signal is a signal that has not undergone source coding;

[0064] The first determining module is used to determine the decoded value of the code block that has an error as the target value when data decoding is performed and an error is detected.

[0065] Optionally, if the number of logic "1"s in the source signal is greater than the number of logic "0", the value of the first target bit is 1;

[0066] When the number of logic "1"s in the source signal is less than the number of logic "0", the value of the first target bit is 0.

[0067] Optionally, the device further includes:

[0068] The second sending module is used to send a second indication information to the sending end device when data decoding is performed and a bit error is detected. The second indication information is used to instruct the sending end device to perform an odd number of repetitions based on the source signal.

[0069] The second receiving module is used to receive the second signal sent by the transmitting end. The second signal includes N sub-sequences, which are obtained by encoding the source signal, where N is an odd number.

[0070] The second decoding module is used to decode the data of the N sub-sequences respectively, and when an error is detected, the decoding value of the code block with the error is determined as the target value, so as to obtain the N first decoding sequences corresponding to the N sub-sequences respectively.

[0071] The first joint module is used to perform corresponding accumulation processing on the N first decoding sequences according to their bits to obtain the first joint decoding sequence;

[0072] The third decoding module is used to determine the final decoding result based on the first joint decoding sequence.

[0073] Optionally, the device further includes:

[0074] The first processing module is configured to, when the second signal consists of M subsequences and M is an even number, discard k subsequences from the M subsequences to obtain the N subsequences, where k is an odd number and N = Mk;

[0075] The second processing module is used to acquire the M subsequences, N=M, when the second signal consists of M subsequences and M is an odd number.

[0076] Optionally, the first joint module is used for any of the following:

[0077] The values ​​of each bit in each of the N first decoding sequences are accumulated one by one to obtain the first joint decoding sequence;

[0078] The values ​​of the second target bits of each of the N first decoding sequences are accumulated one by one to obtain the first joint decoding sequence, where the second target bit is the bit corresponding to the code block that has an error.

[0079] Optionally, N is an odd number and N = 2^n - 1, where n is a positive integer; the third decoding module is used for:

[0080] In the first joint decoding sequence, if the value of the first bit is greater than or equal to 2^(n-1), the value of the first bit is determined to be 1;

[0081] In the first joint decoding sequence, if the value of the second bit is less than 2^(n-1), the value of the second bit is determined to be 0.

[0082] Optionally, the device further includes:

[0083] The first verification module is used to perform cyclic redundancy check (CRC) on the preamble.

[0084] The first acquisition module is used for:

[0085] If the preamble CRC check passes, the value of the first target bit is obtained according to the first indication information and stored as the target value.

[0086] Optionally, the device further includes:

[0087] The third acquisition module is used to acquire the value of the first target bit according to the first indication information when the CRC check of the preamble fails and the preamble can be identified, and to invert the value of the first target bit and store it as the target value.

[0088] Optionally, the first verification module includes:

[0089] If a first CRC checksum exists between the preamble and the data code, the preamble is subjected to CRC checksum verification based on the first CRC checksum.

[0090] Optionally, the data code comprises L sub-blocks, and the device further comprises:

[0091] The second verification module is used to perform CRC verification on the i-th sub-block according to the second CRC check code when the data is decoded and the existence of the second CRC check code is detected after the i-th sub-block, where 1≤i≤L;

[0092] The fourth decoding module is used to determine the final decoding result based on the decoding result of the at least one sub-block that has passed the CRC check if at least one sub-block among the L sub-blocks has passed the CRC check.

[0093] The fifth decoding module is used to perform corresponding bit-by-bit accumulation processing on the L second decoding sequences corresponding to the L sub-blocks when the CRC checks of the L sub-blocks all fail, to obtain a second joint decoding sequence, and to determine the final decoding result based on the second joint decoding sequence.

[0094] Optionally, the fifth decoding module is used for:

[0095] In the second joint decoding sequence, if the value of the third bit is greater than or equal to (X+1) / 2, the value of the third bit is determined to be 1;

[0096] In the second joint decoding sequence, if the value of the fourth bit is less than (X+1) / 2, the value of the fourth bit is determined to be 0;

[0097] Where X represents the number of repetitions.

[0098] Fourthly, embodiments of the present invention also provide a transmitting end device, the device comprising:

[0099] The second acquisition module is used to acquire the source signal to be transmitted;

[0100] The second determining module is used to determine a first logic value based on the number of logic "1"s and logic "0"s in the source signal. The first logic value is used by the receiving device to determine the decoding result of the first code block with the bit error as the first logic value when performing data decoding and detecting a bit error.

[0101] The generation module is used to perform source encoding on the source signal to generate a preamble and a data code, and to set the value of the first target bit in the preamble to the first logical value. The preamble carries first indication information, which is used to indicate the first target bit.

[0102] The first transmitting module is used to transmit a first signal to the receiving device, the first signal including the preamble and the data code.

[0103] Optionally, the second determining module is used to:

[0104] If the number of logic "1"s in the source signal is greater than the number of logic "0", the first logic value is determined to be 1; or, if the number of logic "1"s in the source signal is less than the number of logic "0", the first logic value is determined to be 0.

[0105] Optionally, the device further includes:

[0106] The third transmitting module is used to transmit a second signal to the receiving device upon receiving the second indication information transmitted by the receiving device. The second signal includes N sub-sequences, which are obtained by encoding the source signal, where N is an odd number.

[0107] Optionally, the device further includes:

[0108] A first insertion module is configured to insert a first CRC checksum between the preamble and the data code, wherein the first signal includes the preamble, the first CRC checksum, and the data code.

[0109] Optionally, the device further includes:

[0110] The segmentation module is used to segment the data code into L sub-blocks;

[0111] The second insertion module is used to insert a second CRC check code between any two adjacent sub-blocks in the L sub-blocks, wherein the first signal includes the preamble, the data code, and L-1 second CRC check codes.

[0112] Optionally, neither the preamble nor the data code contains a sequence of two or more consecutive "10"s.

[0113] Optionally, the generation module is used for:

[0114] The source signal is precoded to obtain a precoded signal, wherein the encoding length obtained by precoding logic "1" is equal to the encoding length obtained by precoding logic "0".

[0115] The precoded signal is subjected to Pulse Width Encoding (PIE) to generate a preamble and a data code.

[0116] Fifthly, embodiments of the present invention provide a receiving device, including a transceiver and a processor.

[0117] The transceiver is used for:

[0118] The receiver receives a first signal sent by the transmitting device; the first signal includes a preamble and a data code, the preamble carries first indication information, and the first indication information is used to indicate a first target bit in the preamble.

[0119] The processor is used for:

[0120] According to the first indication information, the value of the first target bit is obtained and stored as a target value; the value of the first target bit is determined by the transmitting device based on the number of logic "1"s and logic "0"s in the source signal corresponding to the first signal, wherein the source signal is a signal that has not undergone source coding;

[0121] If a data decoding process is performed and a bit error is detected, the decoded value of the code block containing the bit error is determined as the target value.

[0122] Optionally, if the number of logic "1"s in the source signal is greater than the number of logic "0", the value of the first target bit is 1;

[0123] When the number of logic "1"s in the source signal is less than the number of logic "0", the value of the first target bit is 0.

[0124] Optionally, the transceiver is further used for:

[0125] If a data decoding is performed and a bit error is detected, a second indication information is sent to the transmitting device. The second indication information is used to instruct the transmitting device to perform an odd number of repetitions based on the source signal.

[0126] The receiver receives a second signal transmitted by the transmitting end. The second signal includes N subsequences, which are obtained by encoding the source signal, where N is an odd number.

[0127] The processor is also used for:

[0128] Data decoding is performed on the N subsequences respectively, and if a bit error is detected, the decoding value of the code block with the bit error is determined as the target value, so as to obtain N first decoding sequences corresponding to the N subsequences respectively;

[0129] The N first decoding sequences are accumulated according to their corresponding bits to obtain the first joint decoding sequence;

[0130] The final decoding result is determined based on the first joint decoding sequence.

[0131] Optionally, the processor is further configured to:

[0132] If the second signal consists of M subsequences and M is an even number, discard k subsequences from the M subsequences to obtain the N subsequences, where k is an odd number and N = Mk;

[0133] When the second signal consists of M subsequences and M is an odd number, the M subsequences are obtained, and N = M.

[0134] Optionally, the processor is used to:

[0135] The values ​​of each bit in each of the N first decoding sequences are accumulated one by one to obtain the first joint decoding sequence;

[0136] The values ​​of the second target bits of each of the N first decoding sequences are accumulated one by one to obtain the first joint decoding sequence, where the second target bit is the bit corresponding to the code block that has an error.

[0137] Optionally, N is an odd number and N = 2^n - 1, where n is a positive integer; the processor is used for:

[0138] In the first joint decoding sequence, if the value of the first bit is greater than or equal to 2^(n-1), the value of the first bit is determined to be 1;

[0139] In the first joint decoding sequence, if the value of the second bit is less than 2^(n-1), the value of the second bit is determined to be 0.

[0140] Optionally, the processor is further configured to:

[0141] Perform a Cyclic Redundancy Check (CRC) on the preamble;

[0142] If the preamble CRC check passes, the value of the first target bit is obtained according to the first indication information and stored as the target value.

[0143] Optionally, the processor is further configured to:

[0144] If the CRC check of the preamble fails and the preamble can be identified, the value of the first target bit is obtained according to the first indication information, and the value of the first target bit is inverted and stored as the target value.

[0145] Optionally, the processor is used to:

[0146] If a first CRC checksum exists between the preamble and the data code, the preamble is subjected to CRC checksum verification based on the first CRC checksum.

[0147] Optionally, the processor is further configured to:

[0148] If a second CRC checksum is detected after data decoding, the i-th sub-block is subjected to CRC checksum based on the second CRC checksum, where 1≤i≤L;

[0149] If at least one of the L sub-blocks passes the CRC check, the final decoding result is determined based on the decoding result of the at least one sub-block that passed the CRC check.

[0150] If the CRC check of the L sub-blocks fails, the L second decoding sequences corresponding to the L sub-blocks are accumulated bit by bit to obtain the second joint decoding sequence, and the final decoding result is determined based on the second joint decoding sequence.

[0151] Optionally, the processor is used to:

[0152] In the second joint decoding sequence, if the value of the third bit is greater than or equal to (X+1) / 2, the value of the third bit is determined to be 1;

[0153] In the second joint decoding sequence, if the value of the fourth bit is less than (X+1) / 2, the value of the fourth bit is determined to be 0;

[0154] Where X represents the number of repetitions.

[0155] Sixthly, embodiments of the present invention also provide a transmitting end device, including a transceiver and a processor.

[0156] The processor is used for:

[0157] Acquire the source signal to be sent;

[0158] Based on the number of logic "1"s and logic "0"s in the source signal, a first logic value is determined. The first logic value is used by the receiving device to determine the decoding result of the first code block with the bit error when performing data decoding and detecting a bit error.

[0159] The source signal is source encoded to generate a preamble and a data code, and the value of the first target bit in the preamble is set to the first logic value. The preamble carries first indication information, which is used to indicate the first target bit.

[0160] The transceiver is used for:

[0161] A first signal is sent to the receiving device, the first signal including the preamble and the data code.

[0162] Optionally, the processor is used to:

[0163] If the number of logic "1"s in the source signal is greater than the number of logic "0", the first logic value is determined to be 1; or, if the number of logic "1"s in the source signal is less than the number of logic "0", the first logic value is determined to be 0.

[0164] Optionally, the transceiver is further used for:

[0165] Upon receiving the second indication information sent by the receiving device, a second signal is sent to the receiving device. The second signal includes N sub-sequences, which are obtained by encoding the source signal, where N is an odd number.

[0166] Optionally, the processor is further configured to:

[0167] A first CRC checksum is inserted between the preamble and the data code, wherein the first signal includes the preamble, the first CRC checksum, and the data code.

[0168] Optionally, the processor is further configured to:

[0169] The data code is divided into L sub-blocks;

[0170] A second CRC checksum is inserted between any two adjacent sub-blocks in the L sub-blocks. The first signal includes the preamble, the data code, and L-1 second CRC checksums.

[0171] Optionally, neither the preamble nor the data code contains a sequence of two or more consecutive "10"s.

[0172] Optionally, the processor is used to:

[0173] The source signal is precoded to obtain a precoded signal, wherein the encoding length obtained by precoding logic "1" is equal to the encoding length obtained by precoding logic "0".

[0174] The precoded signal is subjected to Pulse Width Encoding (PIE) to generate a preamble and a data code.

[0175] In a seventh aspect, embodiments of the present invention also provide a receiving device, comprising: a processor, a memory, and a program stored in the memory and executable on the processor, wherein the program, when executed by the processor, implements the steps of the signal processing method as described in the first aspect.

[0176] Eighthly, embodiments of the present invention also provide a transmitting device, including: a processor, a memory, and a program stored in the memory and executable on the processor, wherein the program, when executed by the processor, implements the steps of the signal processing method as described in the second aspect.

[0177] In a ninth aspect, embodiments of the present invention also provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the signal processing method as described in the first aspect, or, when executed by a processor, implements the steps of the signal processing method as described in the second aspect.

[0178] In this embodiment of the invention, the transmitting device determines a first logic value based on the number of logic "0" and logic "1" in the source signal, and carries the first logic value in the first target bit in the preamble part when generating the preamble to provide prior information to the receiving device. If the receiving device encounters a bit error during data decoding, the bit error block can be decoded into the first logic value to compensate for the bit error and reduce the receiving bit error rate. Attached Figure Description

[0179] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0180] Figure 1 This is one of the flowcharts of a signal processing method provided in an embodiment of the present invention;

[0181] Figure 2 This is a schematic diagram of a balanced PIE encoding preamble format provided in an embodiment of the present invention;

[0182] Figure 3 This is a schematic diagram comparing the performance of a decoding algorithm before and after improvement, according to an embodiment of the present invention.

[0183] Figure 4 This is a schematic diagram illustrating a PIE decoding error situation provided in an embodiment of the present invention;

[0184] Figure 5This is a schematic diagram illustrating the principle of a balanced PIE coding scheme that uses Manchester code for precoding processing, as provided in an embodiment of the present invention.

[0185] Figure 6 This is a schematic diagram comparing the bit error rate before and after PIE equal-length precoding, provided by an embodiment of the present invention;

[0186] Figure 7 This is one of the schematic diagrams of a PIE equal-length precoding and decoding rule provided in an embodiment of the present invention;

[0187] Figure 8 This is the second schematic diagram of a PIE equal-length precoding and decoding rule provided in this embodiment of the invention;

[0188] Figure 9 This is a schematic diagram illustrating the principle of a transmitting device repeating original bits an odd number of times, according to an embodiment of the present invention.

[0189] Figure 10 This is a schematic diagram illustrating the principle of a joint decoding method that involves accumulating and jointly deciding on all the original bits after decoding, as provided in an embodiment of the present invention.

[0190] Figure 11 This is a schematic diagram illustrating the principle of a joint decoding method that accumulates and makes joint decisions only for bits that may be misjudged, as provided in an embodiment of the present invention.

[0191] Figure 12 This is a schematic diagram illustrating the principle of a joint decoding method based on odd-number (3) bit repetitions provided in an embodiment of the present invention.

[0192] Figure 13 This is a performance simulation diagram of a joint decoding method based on odd number (3) bit repetitions provided in an embodiment of the present invention;

[0193] Figure 14 This is a flowchart illustrating a method for inserting a short CRC-assisted leader correction according to an embodiment of the present invention;

[0194] Figure 15 This is a schematic diagram illustrating the principle of a short CRC-assisted decoding correction method provided in an embodiment of the present invention;

[0195] Figure 16 This is a flowchart illustrating an overall decoding scheme for a receiving device provided in an embodiment of the present invention;

[0196] Figure 17 This is a second schematic flowchart of a signal processing method provided in an embodiment of the present invention;

[0197] Figure 18 This is one of the structural schematic diagrams of a receiving end device provided in an embodiment of the present invention;

[0198] Figure 19 This is one of the structural schematic diagrams of a transmitting end device provided in an embodiment of the present invention;

[0199] Figure 20 This is a second schematic diagram of the structure of a receiving device provided in an embodiment of the present invention;

[0200] Figure 21 This is the second structural schematic diagram of a transmitting device provided in an embodiment of the present invention. Detailed Implementation

[0201] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0202] In related technologies, RFID protocols typically use the PIE encoding and decoding scheme, which is prone to bit misinterpretation during decoding. Current RFID is a short-range communication system using unlicensed spectrum, allowing for multiple retransmissions when data reception errors occur, making PIE codes well-suited for RFID systems. However, in cellular passive IoT systems, on the one hand, the system signal-to-noise ratio decreases with increasing communication distance, and continuing to use PIE encoding may lead to a higher system error rate. On the other hand, cellular systems typically use licensed spectrum for information transmission, limiting the maximum number of signal retransmissions. Therefore, to adapt to the long-distance transmission application scenarios of cellular passive IoT systems, this invention provides a signal processing method, device, and medium to reduce the system's receiving error rate, improve its anti-interference capability, and thus support longer transmission distances.

[0203] Specifically, this invention provides a signal processing method applied to a receiving device. Please refer to [link to relevant documentation]. Figure 1 , Figure 1 This is one of the flowcharts of a signal processing method provided in an embodiment of the present invention.

[0204] like Figure 1 As shown, the signal processing method applied to the receiving device includes the following steps:

[0205] Step 101: Receive the first signal sent by the transmitting device.

[0206] The first signal includes a preamble and a data code. The preamble carries first indication information, which is used to indicate a first target bit in the preamble. The value of the first target bit is determined by the transmitting device based on the number of logic "1"s and logic "0"s in the source signal corresponding to the first signal. The source signal is a signal that has not undergone source coding.

[0207] In this embodiment of the invention, a method for receiving and decoding with reference to a preamble instruction is provided.

[0208] In practical implementation, before source coding, the transmitting device can count the number of logic "0"s (logic0) and logic "1"s (logic1) in the source signal to be transmitted. Based on the specific number of "logic 0"s, "logic1"s, and "logic 0", a first logic value is determined, which can be represented as a flag. During preamble generation, the transmitting device can set the value of the first target bit of the preamble to the flag, providing the receiving device with prior information to help with error compensation. It should be noted that the first target bit is not limited here, such as... Figure 2 As shown, the first target bit can be the (n+1)th bit of the leading part.

[0209] Step 102: According to the first instruction information, obtain the value of the first target bit and store it as the target value.

[0210] In practice, the transmitting device uses the first indication information carried in the preamble to indicate the location of the flag to the receiving device. The receiving device decodes the flag value based on the first indication information and sets its local target value Ref_flag to flag. Subsequently, during data decoding, if a code block contains a bit error, the receiving device can identify that code block as Ref_flag.

[0211] For example, if the number of "logic 0" characters in the source signal is greater than the number of "logic 1" characters, the first logic value can be determined to be 0. That is, if the number of "logic 0" characters is greater than the number of "logic 1" characters, then flag = 0. In this case, it indicates that there are more "logic 0" characters in the source signal. If a bit error is received, the receiving device can decode flag as "logic 0" according to the first indication information, and the probability of obtaining a correct decoding result by decoding the erroneous code block as "logic 0" is higher. Conversely, if the number of "logic 0" characters in the source signal is less than the number of "logic 1" characters, flag = 1. In this case, it indicates that there are more "logic 1" characters in the source signal. If a bit error is received, the receiving device can decode flag as "logic 1" according to the first indication information, and the probability of obtaining a correct decoding result by decoding the erroneous code block as "logic 1" is higher.

[0212] Step 103: If data decoding is performed and errors are detected, the decoded value of the code block with the error is determined as the target value.

[0213] In this embodiment of the invention, the transmitting device determines a first logic value based on the number of "logic 0" and "logic 1" in the source signal. When generating the preamble, the transmitting device carries this first logic value in the preamble portion through a first target bit to provide prior information to the receiving device. If the receiving device encounters errors during data decoding, the erroneous code block can be decoded to the first logic value to compensate for the errors. Since the logic value corresponding to Ref_flag accounts for a large proportion of the source signal, decoding the code block to Ref_flag when decoding errors are possible can reduce the receiving error rate and improve decoding accuracy. For example, simulation results can be shown as follows: Figure 3 As shown.

[0214] Considering that in most scenarios of cellular passive IoT, passive tags still need to rely on radio frequency power to charge and obtain energy, in an optional implementation, the transmitting and receiving devices still use the PIE encoding and decoding scheme, retaining the characteristic that the high level accounts for a large proportion in the PIE code.

[0215] In this embodiment, optimizations can be made based on the characteristics of PIE encoding and decoding to improve the decoding accuracy of PIE encoding and decoding in cellular passive IoT scenarios. Specific details are as follows:

[0216] In one scenario, due to channel noise, the receiving device may receive coded code blocks starting with "0", a situation that should not occur in normal transmission. In an optional implementation, the receiving device can be pre-configured to change "0" to "1" upon receiving coded code blocks starting with "0", and use this as a basis for decoding subsequent bits, thereby reducing the PIE decoding error rate to some extent. For ease of understanding, consider this example: Suppose the receiving device receives the sequence "11100110101101". Under correct decoding, this sequence can be processed as "11100110 10 1101", ultimately translated as "1? 0 1". Before the optimization described above, because coded code blocks starting with "0" cannot be correctly decoded, the receiving device might process the sequence as "1110 0110101101", ultimately translated as "1??", resulting in a large number of erroneous code blocks. After optimization in the above manner, the receiving device may process the above sequence as "1110 1110 101101", which is ultimately translated as "1 1 01", thus reducing the bit error rate to some extent.

[0217] In one scenario, for PIE encoding, when the receiving device receives "1010", according to the decoding rules, it will decode "1010" as "logic 0". However, due to channel noise, the code block when the "1010" was sent from the transmitting device might be "1110". That is, the receiving device might misjudge the second bit, causing it to misdecode the code block that should have been decoded as logic 1 as logic 0. Figure 4 As shown. In an optional implementation, it can be stipulated that consecutive "logic 0"s are not allowed in the raw bits transmitted by the transmitting device, such as 00, 000, ... etc. That is, consecutive "10"s are not allowed in the code blocks transmitted by the transmitting device, such as 10, 1010, ... etc. Based on this prior information, when the receiving device receives consecutive "10"s, it should modify the consecutive "10"s to "1110".

[0218] Due to the PIE encoding specification, "logic 1" is encoded as "1110" or "110", and "logic 0" is encoded as "10" or "01". This results in "logic 0" and "logic 1" being encoded with unequal lengths. The receiving device may be unable to accurately segment the code block, potentially resulting in the translation of two original bits "logic 0, logic 0" into one original bit "logic 1", or one original bit "logic 1" into two original bits "logic 0, logic 0", leading to received bit errors.

[0219] In an optional implementation, the transmitting device can precode the source signal so that the encoding length obtained by precoding "logic 1" is equal to the encoding length obtained by precoding "logic 0". Specifically, before performing PIE encoding on the original bits of the source signal, the transmitting device first performs "10" equal-length precoding. It should be noted that the precoding method is not limited here; for example, it can be Manchester precoding or other encoding methods. Manchester precoding will be used as an example here.

[0220] like Figure 5 As shown, Manchester encoding is superimposed before PIE encoding. Each original bit after precoding should be expanded into a code block of equal length "10", for example, "logic 1" is expanded into "10" or "10 10", etc. In this way, based on the prior information of equal-length encoding, the receiving device divides the code block, which can improve the accuracy of PIE decoding to a certain extent. Figure 6 As shown.

[0221] Based on the pre-encoded "logic 0" and "logic 1" being of equal length, each 6-bit code block can typically be decoded based on the second and fourth bits. When the second and fourth bits of the code block are "10", the code block is decoded as "logic 1"; when the second and fourth bits are "01", the code block is decoded as "logic 0". When the second and fourth bits of the code block are "11" or "00", the code block cannot be correctly decoded, such as... Figure 7 As shown, the bit error situation described in step 103 occurs. In this case, the receiving device can determine that the code block is the target value Ref_flag, where Ref_flag = flag, as shown. Figure 8 As shown.

[0222] In this embodiment of the invention, determining the first logic value based on the number of "logic 0" and "logic 1" in the source signal can be understood as probability-based decoding result compensation. When there are many error bits, for example, in cases of low signal-to-interference plus noise ratio (SNR) or low modulation depth, the improvement in decoding performance is not significant. To further reduce the received bit error rate under low SNR conditions, in an optional embodiment, the method further includes:

[0223] If a data decoding is performed and a bit error is detected, a second indication information is sent to the transmitting device. The second indication information is used to instruct the transmitting device to perform an odd number of repetitions based on the source signal.

[0224] The receiver receives a second signal transmitted by the transmitting end. The second signal includes N subsequences, which are obtained by encoding the source signal, where N is an odd number.

[0225] Data decoding is performed on the N subsequences respectively, and if a bit error is detected, the decoding value of the code block with the bit error is determined as the target value, so as to obtain N first decoding sequences corresponding to the N subsequences respectively;

[0226] The N first decoding sequences are accumulated according to their corresponding bits to obtain the first joint decoding sequence;

[0227] The final decoding result is determined based on the first joint decoding sequence.

[0228] In this embodiment, a joint decoding method based on odd-number bit repetition is provided.

[0229] In practical implementation, when a decoding error occurs at the receiving end device, it can notify the sending end device through a second indication message, and the sending end device will then initiate an odd number of repetitions. For example... Figure 9 As shown, the transmitting device repeats the original bits an odd number of times to obtain a second signal comprising N sub-sequences. When the receiving device decodes the N sub-sequences, if an error occurs (i.e., the CRC check fails), the receiving device does not need to discard the erroneous code block. Instead, it can decode the code block into a Ref_flag and store the decoding result. Based on the odd number of repetitions of the original bits by the transmitting device, the receiving device can perform bit-by-bit accumulation on the N first decoding sequences corresponding to the N sub-sequences to obtain a first joint decoding sequence, and then make a decision to obtain the final decoding result.

[0230] It should be noted that due to channel noise, the second signal may be transmitted with an odd number of repetitions when sent from the transmitting device, but may not be received by the receiving device with the same number of repetitions. Therefore, in one optional embodiment, when the receiving device receives the second signal, it first determines whether the second signal is composed of an odd number of repetitions and an odd number of subsequences. If the second signal is not composed of an odd number of subsequences, some subsequences can be discarded before performing data decoding on the second signal.

[0231] The above-described implementation of accumulating the N first decoded sequences corresponding to the N subsequences according to their bits can include two methods, as detailed below:

[0232] In the first implementation method, all received bits are accumulated and then jointly decoded.

[0233] like Figure 10As shown, each bit of the first decoded sequence after an odd number of decoded bits is added together to obtain the accumulated decoded bits. Then, a joint decision is made on the accumulated decoded bits to obtain the final decoding result. Optionally, assuming N is odd and N = 2^n - 1, the value of n can be determined after determining the value of N. During the joint decision, if the accumulated result of a certain bit is greater than or equal to 2^(n - 1), the joint decoded value of that bit is determined to be 1; otherwise, the joint decoded value of that bit is determined to be 0.

[0234] In the second implementation method, only the received bits that may be misjudged are accumulated and then jointly decoded.

[0235] like Figure 11 As shown, only the bits that might be misjudged, i.e., the bits translated into Ref_flag, are added together to obtain the accumulated decoded bits. Then, a joint decision is made on the accumulated decoded bits to obtain the final decoding result. Optionally, assuming N is odd and N = 2^n - 1, the value of n can be determined after determining the value of N. When making the joint decision, if the accumulated result of a certain bit is greater than or equal to 2^(n - 1), the joint decoded value of that bit is determined to be 1; otherwise, the joint decoded value of that bit is determined to be 0.

[0236] It is understandable that the computational load of the above-described second implementation method is smaller than that of the first implementation method.

[0237] For ease of understanding, assume that the sending device repeats the odd number of times three times. The original bit generation and joint decoding process can be described as follows: Figure 12 As shown in the figure. For example, the above-mentioned joint decoding method based on odd-numbered bit repetitions is simulated and verified. The number of repetitions is set to 3, and the final decoding result is output by combining the decoding results of 3 times. The result is as follows. Figure 13 As shown, the system's anti-interference capability has been improved.

[0238] To reduce the preamble error rate and further improve the efficiency and accuracy of received decoding, in an optional embodiment, before step 102, the method further includes:

[0239] Perform a Cyclic Redundancy Check (CRC) on the preamble;

[0240] Step 102 includes:

[0241] If the preamble CRC check passes, the value of the first target bit is obtained according to the first indication information and stored as the target value.

[0242] In this embodiment, the transmitting device can insert a first CRC checksum between the preamble and the data code when generating the preamble. The first CRC checksum can be a short CRC checksum, such as CRC-4 or CRC-6. The first CRC checksum is used to verify the preamble and can verify whether there are decoding errors in the preamble.

[0243] In specific implementation, such as Figure 14 As shown, initially, Ref_flag is set to 0, and then the preamble plus the first CRC checksum is decoded. If the CRC check passes, Ref_flag is set to flag for use in determining subsequent data bits; otherwise, it is determined whether the receiving device can recognize the preamble. If the preamble cannot be recognized, it means that in addition to the flag bit error, other bits in the preamble are also incorrect, and the data can be discarded. If the preamble can be recognized, the value of flag is inverted, and the corrected preamble value is re-checked using the CRC check. If the check passes, it means that the correct preamble has been recovered, Ref_flag is set to flag for use in determining subsequent data bits, and the process ends. For ease of understanding, an example is given: assume the preamble format is "10 11 01", where the third bit is flag. If the preamble CRC check passes, it means that there is no decoding error in the preamble. If the CRC check of the preamble fails, but the receiving device can recognize the preamble, it means that there is no decoding error in other formats of the preamble, and the decoding error is locked on the third flag. In this case, the flag can be inverted to recover the correct preamble.

[0244] In an optional implementation, the data code comprises L sub-blocks, and the method further includes:

[0245] If a second CRC checksum is detected after data decoding, the i-th sub-block is subjected to CRC checksum based on the second CRC checksum, where 1≤i≤L;

[0246] If at least one of the L sub-blocks passes the CRC check, the final decoding result is determined based on the decoding result of the at least one sub-block that passed the CRC check.

[0247] If the CRC check of the L sub-blocks fails, the L second decoding sequences corresponding to the L sub-blocks are accumulated bit by bit to obtain the second joint decoding sequence, and the final decoding result is determined based on the second joint decoding sequence.

[0248] In this embodiment, the transmitting device can insert a second CRC checksum into the data code area to perform phased decoding verification of the data code area. The second CRC checksum can be a short CRC checksum, such as CRC-4 or CRC-6, and can be shorter than the first CRC checksum. If the CRC check fails, decoding stops to reduce the power consumption of the receiving device.

[0249] In specific implementation, such as Figure 15 As shown, the transmitting device can divide the original bits of the data code into L sub-blocks, and insert a second CRC checksum between any two adjacent sub-blocks. After the receiving end receives the first signal, it can first confirm the repetition count X by monitoring the downlink broadcast channel, etc. It should be noted that the method for determining the repetition count is not limited here. Figure 16 As shown, after the receiving device decodes the erroneous code block into Ref_flag, it can decode each sub-block of the data code area and the second CRC check code concatenated thereafter.

[0250] If the CRC check of the decoding result of sub-block i passes, the result is stored as "decoding result i", and i is incremented until the decoding results of all sub-blocks are decoded.

[0251] If the CRC check of the decoding result of sub-block i fails, the result is stored as "joint decoding result i", and the decoding of the CRC checksum of sub-block i+1 and its concatenated form continues. If the CRC check passes, the result is stored as "decoding result i"; otherwise, it is stored as "joint decoding result i+1", and the decoding of the CRC checksum of sub-block i+2 and its concatenated form continues, checking if the CRC check of sub-block i+2 passes. If it passes, the result is stored as "decoding result i"; otherwise, it is stored as "joint decoding result i+2", and so on.

[0252] Finally, if there is data in "decoding result i", meaning that at least one of the L sub-blocks has passed the CRC check, then the "decoding result i" of the sub-block that has passed the CRC check is directly determined as the final decoding result. If "decoding result i" is empty, meaning that the CRC check of all L sub-blocks has failed, then the joint decoding results i, i+1, i+2, ... are accumulated, and a joint decision is made for each bit. Optionally, when making a joint decision, if the accumulated result of a certain bit is greater than or equal to (X+1) / 2, then the joint decoding value of that bit is determined to be 1; otherwise, the joint decoding value of that bit is determined to be 0, until all bits have been decoded.

[0253] This invention also provides a signal processing method applied to a transmitting device. Please refer to [link to relevant documentation]. Figure 17 , Figure 17 This is a second schematic flowchart of a signal processing method provided in an embodiment of the present invention.

[0254] like Figure 17 As shown, the signal processing method applied to the transmitting device includes the following steps:

[0255] Step 201: Obtain the source signal to be transmitted;

[0256] Step 202: Determine a first logic value based on the number of logic "1"s and logic "0"s in the source signal. The first logic value is used by the receiving device to determine the decoding result of the first code block with the bit error when performing data decoding and detecting a bit error.

[0257] Step 203: Perform source encoding on the source signal to generate a preamble and a data code, and set the value of the first target bit in the preamble to the first logic value. The preamble carries first indication information, which is used to indicate the first target bit.

[0258] Step 204: Send a first signal to the receiving device, the first signal including the preamble and the data code.

[0259] Optionally, determining the first logic value based on the number of logic "1"s and logic "0"s in the source signal includes:

[0260] If the number of logic "1"s in the source signal is greater than the number of logic "0", the first logic value is determined to be 1; or, if the number of logic "1"s in the source signal is less than the number of logic "0", the first logic value is determined to be 0.

[0261] Optionally, the method further includes:

[0262] Upon receiving the second indication information sent by the receiving device, a second signal is sent to the receiving device. The second signal includes N sub-sequences, which are obtained by encoding the source signal, where N is an odd number.

[0263] Optionally, before sending the first signal to the receiving device, the method further includes:

[0264] A first CRC checksum is inserted between the preamble and the data code, wherein the first signal includes the preamble, the first CRC checksum, and the data code.

[0265] Optionally, before sending the preamble and the data code to the receiving device, the method further includes:

[0266] The data code is divided into L sub-blocks;

[0267] A second CRC checksum is inserted between any two adjacent sub-blocks in the L sub-blocks. The first signal includes the preamble, the data code, and L-1 second CRC checksums.

[0268] Optionally, neither the preamble nor the data code contains a sequence of two or more consecutive "10"s.

[0269] Optionally, the step of performing source coding on the source signal to generate a preamble and a data code includes:

[0270] The source signal is precoded to obtain a precoded signal, wherein the encoding length obtained by precoding logic "1" is equal to the encoding length obtained by precoding logic "0".

[0271] The precoded signal is subjected to Pulse Width Encoding (PIE) to generate a preamble and a data code.

[0272] It should be noted that the specific implementation of the embodiments of the present invention can refer to the description of the steps performed by the sending device in the above embodiments. To avoid repetition, it will not be repeated here.

[0273] The following is a detailed description of an exemplary implementation of this embodiment:

[0274] In this embodiment, optimization is performed based on PIE encoding and decoding rules to solve the problem of high decoding error rate of the receiving device.

[0275] Option 1: Improved PIE encoding scheme

[0276] Solution 1.1: Addressing the issue of the receiving device being unable to decode encoded code blocks starting with "0". The receiving device is configured to change the "0" to "1" upon receiving such a code block, and use this as a basis for decoding subsequent bits. This solution can reduce the PIE decoding error rate to some extent.

[0277] Solution 1.2: Addressing the issue where the receiving device, upon receiving a coded code block containing "1010," cannot determine whether to translate it as "logic 0logic 0" or "logic 1," this solution involves specifying that consecutive "logic 0"s are not allowed in the raw bits transmitted by the sending device. Specifically, consecutive "10"s are not allowed in the code block transmitted by the sending device, such as 10, 1010, etc. Based on this prior information, when the receiving device receives consecutive "10"s, it should modify them to "1110."

[0278] Option 2: Balanced PIE encoding scheme and improved balanced PIE encoding / decoding scheme

[0279] Scheme 2.1: Balanced PIE Encoding Scheme

[0280] In this embodiment, a balanced PIE encoding scheme is provided to further accommodate the charging needs of as many tags as possible with high-level / "logic 1" signals, while improving encoding efficiency and providing more decoding prior information for the receiving device.

[0281] In practice, before PIE encoding of the original bits, a "10" length pre-encoding is first performed. Taking Manchester pre-encoding as an example, ... Figure 5 As shown, Manchester encoding is superimposed before PIE encoding, and each original bit after precoding should be expanded into a code block of length "10".

[0282] Scheme 2.2: Improved Balanced PIE Encoding and Decoding Scheme

[0283] Dividing code blocks at the receiving end device based on prior information of equal code length and equal time length can improve the accuracy of PIE decoding to some extent. In the balanced PIE decoding algorithm, decoding can be performed based on the second and fourth bits of each 6-bit code block.

[0284] To address the issue that code blocks cannot be correctly decoded when the second and fourth bits are "11" or "00", this embodiment provides an improved balanced PIE encoding and decoding scheme. This scheme allows for balanced PIE decoding with reference to preamble instructions, further reducing the error rate and improving decoding accuracy.

[0285] In practice, the transmitting device can count the number of "logic 0" and "logic 1" in the source data to be transmitted. If the number of "logic 0" is greater than the number of "logic 1", then flag = 0; otherwise, flag = 1. When generating the preamble, the transmitting device sets the (n+1)th bit of the preamble as the flag and carries indication information to indicate the position of the flag to the receiving device. The receiving device decodes the flag based on the indication information and sets its local Ref_flag = flag. Subsequently, during data decoding, if the second and fourth bits of a code block contain "11" or "00", the code block can be directly decoded into Ref_flag, such as... Figure 8 As shown. Since the logical value corresponding to Ref_flag accounts for a large proportion of the information source, decoding the code block as Ref_flag can reduce the bit error rate when decoding may be incorrect.

[0286] Option 3: Joint decoding method based on odd number of bit repetitions

[0287] Since Scheme 2.2 is based on probability-based decoding result compensation, its improvement in decoding performance is not significant when there are many erroneous bits. To further reduce the receive bit error rate under low SNR conditions, this embodiment provides a joint decoding method based on odd-number bit repetition. The original bits are repeated an odd number of times by the transmitting device, such as... Figure 9 As shown, when the receiving device may misjudge the data decoding, that is, when the code block is decoded as Ref_flag and the CRC check fails, the decoding result of the code block is stored. Based on the odd number of repetitions of the original bits by the sending end, the odd number of decoded sequences are accumulated and then a joint decision is made to obtain the final decoding result.

[0288] In practice, the above-mentioned joint decoding can be implemented in ways such as Scheme 3.1 and Scheme 3.2.

[0289] Option 3.1: Perform joint decoding on all received bits.

[0290] like Figure 10 As shown, each bit of the odd number of decoded sequences is added together to obtain the accumulated decoded bits. Then, a joint decision is made on the accumulated decoded bits. If the result of the accumulation on a certain bit is greater than or equal to 2^(n-1), the joint decoded value of that bit is determined to be 1; otherwise, the joint decoded value of that bit is determined to be 0.

[0291] Scheme 3.2 performs joint decoding only on the received bits that may be misjudged.

[0292] like Figure 11 As shown, only the bits that may be misjudged, i.e. the bits that are translated into Ref_flag, are added together to obtain the accumulated decoded bits. Then, a joint decision is made on the accumulated decoded bits. If the result of the accumulation on a certain bit is greater than or equal to 2^(n-1), the joint decoded value of that bit is determined to be 1; otherwise, the joint decoded value of that bit is determined to be 0.

[0293] Scheme 3.2 has a smaller computational load compared to Scheme 3.1. When the odd number of repetitions is 3, the original bit generation and joint decoding process can be as follows: Figure 12 As shown.

[0294] Option 4: Insert multiple short CRCs into the preamble and data.

[0295] To reduce the preamble error rate and further improve the efficiency and accuracy of receiver decoding, this embodiment inserts a short CRC checksum, such as CRC-4 or CRC-6, between the original bits for preamble verification, which can probabilistically correct preamble errors. Simultaneously, a short CRC checksum is also inserted in the data area for phased decoding verification; if the CRC check fails, decoding stops to reduce the power consumption of the receiver device.

[0296] Specifically, the short CRC-assisted leader correction method is as follows: Figure 14 As shown in the diagram. First, in the initial stage, Ref_flag is set to 0, and then the preamble + CRC is decoded. If the CRC check passes, Ref_flag is set to flag for use in determining subsequent data bits. Otherwise, it is determined whether the receiving device can recognize the preamble. If the preamble cannot be recognized, it indicates that in addition to the flag bit error, other bits in the preamble are also incorrect, and the data can be discarded. If the preamble can be recognized, the value of flag is inverted, and the corrected preamble value is re-checked using the CRC. If the check passes, it indicates that the correct preamble has been recovered, Ref_flag is set to flag for use in determining subsequent data bits, and the process ends.

[0297] Based on the aforementioned short CRC-assisted preamble correction method, the overall decoding process of the system can be described as follows: Figure 16 As shown. First, the number of repetitions X is determined by monitoring the downlink broadcast channel, etc. Then, using methods such as... Figure 14 The method shown determines the value of Ref_flag. After the receiving device decodes the erroneous code block into Ref_flag, it decodes each sub-block of the data area and its subsequent concatenated CRC.

[0298] If the CRC check of the decoding result of sub-block i passes, the result is stored as "decoding result i", and i is incremented until all bits are decoded.

[0299] If the CRC check of the decoding result of sub-block i fails, the result is stored as "joint decoding result i", and the decoding of the CRC of the repeating code block sub-block i+1 and its subsequent concatenation continues. If the CRC check passes, the result is stored as "decoding result i"; otherwise, it is stored as "joint decoding result i+1", and the decoding of the CRC of the repeating code block sub-block i+2 and its subsequent concatenation continues, and so on.

[0300] Finally, if there is data in "decoding result i", then "decoding result i" is directly determined as the final decoding result. If "decoding result i" is empty, then the joint decoding results i, i+1, and i+2 are accumulated, and each bit is judged as 1 / 0. Specifically, if the accumulated result of a certain bit is greater than or equal to (X+1) / 2, then that bit is decoded as logic 1; otherwise, that bit is decoded as logic 0, until all bits have been decoded.

[0301] It should be noted that in this embodiment, schemes 1, 2, 3, and 4 are not directly related to each other and can all be implemented independently. For example, the "improved balanced PIE encoding and decoding" scheme can be combined with the "joint decoding only for potentially misjudged received bits" scheme to improve the system's noise immunity. Alternatively, the "improved balanced PIE encoding and decoding" scheme can be combined with the "joint decoding method based on odd-number bit repetition" scheme to improve the system's noise immunity. Or, the "improved balanced PIE encoding and decoding" scheme can be used alone, etc., without any limitations.

[0302] Please see Figure 18 , Figure 18 This is a receiving device provided in an embodiment of the present invention.

[0303] like Figure 18 As shown, the receiving device 1800 includes:

[0304] The first receiving module 1801 is used to receive a first signal sent by the transmitting device; the first signal includes a preamble and a data code, the preamble carries first indication information, and the first indication information is used to indicate a first target bit in the preamble.

[0305] The first acquisition module 1802 is used to acquire the value of the first target bit according to the first indication information and store it as a target value; the value of the first target bit is determined by the transmitting device according to the number of logic "1"s and logic "0"s in the source signal corresponding to the first signal, wherein the source signal is a signal that has not undergone source coding;

[0306] The first determining module 1803 is used to determine the decoded value of the code block that has an error as the target value when data decoding is performed and an error is detected.

[0307] Optionally, if the number of logic "1"s in the source signal is greater than the number of logic "0", the value of the first target bit is 1;

[0308] When the number of logic "1"s in the source signal is less than the number of logic "0", the value of the first target bit is 0.

[0309] Optionally, the receiver device 1800 also includes:

[0310] The second sending module is used to send a second indication information to the sending end device when data decoding is performed and a bit error is detected. The second indication information is used to instruct the sending end device to perform an odd number of repetitions based on the source signal.

[0311] The second receiving module is used to receive the second signal sent by the transmitting end. The second signal includes N sub-sequences, which are obtained by encoding the source signal, where N is an odd number.

[0312] The second decoding module is used to decode the data of the N sub-sequences respectively, and when an error is detected, the decoding value of the code block with the error is determined as the target value, so as to obtain the N first decoding sequences corresponding to the N sub-sequences respectively.

[0313] The first joint module is used to perform corresponding accumulation processing on the N first decoding sequences according to their bits to obtain the first joint decoding sequence;

[0314] The third decoding module is used to determine the final decoding result based on the first joint decoding sequence.

[0315] Optionally, the receiver device 1800 also includes:

[0316] The first processing module is configured to, when the second signal consists of M subsequences and M is an even number, discard k subsequences from the M subsequences to obtain the N subsequences, where k is an odd number and N = Mk;

[0317] The second processing module is used to acquire the M subsequences, N=M, when the second signal consists of M subsequences and M is an odd number.

[0318] Optionally, the first joint module is used for any of the following:

[0319] The values ​​of each bit in each of the N first decoding sequences are accumulated one by one to obtain the first joint decoding sequence;

[0320] The values ​​of the second target bits of each of the N first decoding sequences are accumulated one by one to obtain the first joint decoding sequence, where the second target bit is the bit corresponding to the code block that has an error.

[0321] Optionally, N is an odd number and N = 2^n - 1, where n is a positive integer; the third decoding module is used for:

[0322] In the first joint decoding sequence, if the value of the first bit is greater than or equal to 2^(n-1), the value of the first bit is determined to be 1;

[0323] In the first joint decoding sequence, if the value of the second bit is less than 2^(n-1), the value of the second bit is determined to be 0.

[0324] Optionally, the receiver device 1800 also includes:

[0325] The first verification module is used to perform cyclic redundancy check (CRC) on the preamble.

[0326] The first acquisition module is used for:

[0327] If the preamble CRC check passes, the value of the first target bit is obtained according to the first indication information and stored as the target value.

[0328] Optionally, the receiver device 1800 also includes:

[0329] The third acquisition module is used to acquire the value of the first target bit according to the first indication information when the CRC check of the preamble fails and the preamble can be identified, and to invert the value of the first target bit and store it as the target value.

[0330] Optionally, the first verification module includes:

[0331] If a first CRC checksum exists between the preamble and the data code, the preamble is subjected to CRC checksum verification based on the first CRC checksum.

[0332] Optionally, the data code comprises L sub-blocks, and the device further comprises:

[0333] The second verification module is used to perform CRC verification on the i-th sub-block according to the second CRC check code when the data is decoded and the existence of the second CRC check code is detected after the i-th sub-block, where 1≤i≤L;

[0334] The fourth decoding module is used to determine the final decoding result based on the decoding result of the at least one sub-block that has passed the CRC check if at least one sub-block among the L sub-blocks has passed the CRC check.

[0335] The fifth decoding module is used to perform corresponding bit-by-bit accumulation processing on the L second decoding sequences corresponding to the L sub-blocks when the CRC checks of the L sub-blocks all fail, to obtain a second joint decoding sequence, and to determine the final decoding result based on the second joint decoding sequence.

[0336] Optionally, the fifth decoding module is used for:

[0337] In the second joint decoding sequence, if the value of the third bit is greater than or equal to (X+1) / 2, the value of the third bit is determined to be 1;

[0338] In the second joint decoding sequence, if the value of the fourth bit is less than (X+1) / 2, the value of the fourth bit is determined to be 0;

[0339] Where X represents the number of repetitions.

[0340] The receiver device 1800 can achieve Figure 1 The various processes implemented in the method embodiments shown can achieve the same beneficial effects, and will not be described again here to avoid repetition.

[0341] Please see Figure 19 , Figure 19 This is a transmitting device provided in an embodiment of the present invention.

[0342] like Figure 19 As shown, the transmitting device 1900 includes:

[0343] The second acquisition module 1901 is used to acquire the source signal to be transmitted;

[0344] The second determining module 1902 is used to determine a first logic value based on the number of logic "1"s and logic "0"s in the source signal. The first logic value is used by the receiving device to determine the decoding result of the first code block with the bit error as the first logic value when performing data decoding and detecting a bit error.

[0345] The generation module 1903 is used to perform source encoding on the source signal to generate a preamble and a data code, and to set the value of the first target bit in the preamble to the first logical value. The preamble carries first indication information, which is used to indicate the first target bit.

[0346] The first transmitting module 1904 is used to transmit a first signal to the receiving device, the first signal including the preamble and the data code.

[0347] Optionally, the second determining module 1902 is used for:

[0348] If the number of logic "1"s in the source signal is greater than the number of logic "0", the first logic value is determined to be 1; or, if the number of logic "1"s in the source signal is less than the number of logic "0", the first logic value is determined to be 0.

[0349] Optionally, the transmitting device 1900 also includes:

[0350] The third transmitting module is used to transmit a second signal to the receiving device upon receiving the second indication information transmitted by the receiving device. The second signal includes N sub-sequences, which are obtained by encoding the source signal, where N is an odd number.

[0351] Optionally, the transmitting device 1900 also includes:

[0352] A first insertion module is configured to insert a first CRC checksum between the preamble and the data code, wherein the first signal includes the preamble, the first CRC checksum, and the data code.

[0353] Optionally, the transmitting device 1900 also includes:

[0354] The segmentation module is used to segment the data code into L sub-blocks;

[0355] The second insertion module is used to insert a second CRC check code between any two adjacent sub-blocks in the L sub-blocks, wherein the first signal includes the preamble, the data code, and L-1 second CRC check codes.

[0356] Optionally, neither the preamble nor the data code contains a sequence of two or more consecutive "10"s.

[0357] Optionally, the generation module 1903 is used for:

[0358] The source signal is precoded to obtain a precoded signal, wherein the encoding length obtained by precoding logic "1" is equal to the encoding length obtained by precoding logic "0".

[0359] The precoded signal is subjected to Pulse Width Encoding (PIE) to generate a preamble and a data code.

[0360] The transmitting device 1900 can achieve Figure 17 The various processes implemented in the method embodiments shown can achieve the same beneficial effects, and will not be described again here to avoid repetition.

[0361] This invention also provides a receiving device, including: a processor, a memory, and a program stored in the memory and executable on the processor. When the program is executed by the processor, it implements the various processes of the above-described signal processing method and achieves the same technical effect. To avoid repetition, it will not be described again here.

[0362] For details, see Figure 20 As shown, this embodiment of the invention also provides a receiving device, including a bus 2001, a transceiver 2002, an antenna 2003, a bus interface 2004, a processor 2005, and a memory 2006.

[0363] The transceiver 2002 is used for:

[0364] The receiver receives a first signal sent by the transmitting device; the first signal includes a preamble and a data code, the preamble carries first indication information, and the first indication information is used to indicate a first target bit in the preamble.

[0365] The processor 2005 is used for:

[0366] According to the first indication information, the value of the first target bit is obtained and stored as a target value; the value of the first target bit is determined by the transmitting device based on the number of logic "1"s and logic "0"s in the source signal corresponding to the first signal, wherein the source signal is a signal that has not undergone source coding;

[0367] If a data decoding process is performed and a bit error is detected, the decoded value of the code block containing the bit error is determined as the target value.

[0368] Optionally, if the number of logic "1"s in the source signal is greater than the number of logic "0", the value of the first target bit is 1;

[0369] When the number of logic "1"s in the source signal is less than the number of logic "0", the value of the first target bit is 0.

[0370] Optionally, the transceiver 2002 is further configured to:

[0371] If a data decoding is performed and a bit error is detected, a second indication information is sent to the transmitting device. The second indication information is used to instruct the transmitting device to perform an odd number of repetitions based on the source signal.

[0372] The receiver receives a second signal transmitted by the transmitting end. The second signal includes N subsequences, which are obtained by encoding the source signal, where N is an odd number.

[0373] The processor 2005 is also used for:

[0374] Data decoding is performed on the N subsequences respectively, and if a bit error is detected, the decoding value of the code block with the bit error is determined as the target value, so as to obtain N first decoding sequences corresponding to the N subsequences respectively;

[0375] The N first decoding sequences are accumulated according to their corresponding bits to obtain the first joint decoding sequence;

[0376] The final decoding result is determined based on the first joint decoding sequence.

[0377] Optionally, the processor 2005 is further configured to:

[0378] If the second signal consists of M subsequences and M is an even number, discard k subsequences from the M subsequences to obtain the N subsequences, where k is an odd number and N = Mk;

[0379] When the second signal consists of M subsequences and M is an odd number, the M subsequences are obtained, and N = M.

[0380] Optionally, the processor 2005 is used for:

[0381] The values ​​of each bit in each of the N first decoding sequences are accumulated one by one to obtain the first joint decoding sequence;

[0382] The values ​​of the second target bits of each of the N first decoding sequences are accumulated one by one to obtain the first joint decoding sequence, where the second target bit is the bit corresponding to the code block that has an error.

[0383] Optionally, N is an odd number and N = 2^n - 1, where n is a positive integer; the processor 2005 is used for:

[0384] In the first joint decoding sequence, if the value of the first bit is greater than or equal to 2^(n-1), the value of the first bit is determined to be 1;

[0385] In the first joint decoding sequence, if the value of the second bit is less than 2^(n-1), the value of the second bit is determined to be 0.

[0386] Optionally, the processor 2005 is further configured to:

[0387] Perform a Cyclic Redundancy Check (CRC) on the preamble;

[0388] If the preamble CRC check passes, the value of the first target bit is obtained according to the first indication information and stored as the target value.

[0389] Optionally, the processor 2005 is further configured to:

[0390] If the CRC check of the preamble fails and the preamble can be identified, the value of the first target bit is obtained according to the first indication information, and the value of the first target bit is inverted and stored as the target value.

[0391] Optionally, the processor 2005 is used for:

[0392] If a first CRC checksum exists between the preamble and the data code, the preamble is subjected to CRC checksum verification based on the first CRC checksum.

[0393] Optionally, the processor 2005 is further configured to:

[0394] If a second CRC checksum is detected after data decoding, the i-th sub-block is subjected to CRC checksum based on the second CRC checksum, where 1≤i≤L;

[0395] If at least one of the L sub-blocks passes the CRC check, the final decoding result is determined based on the decoding result of the at least one sub-block that passed the CRC check.

[0396] If the CRC check of the L sub-blocks fails, the L second decoding sequences corresponding to the L sub-blocks are accumulated bit by bit to obtain the second joint decoding sequence, and the final decoding result is determined based on the second joint decoding sequence.

[0397] Optionally, the processor 2005 is used for:

[0398] In the second joint decoding sequence, if the value of the third bit is greater than or equal to (X+1) / 2, the value of the third bit is determined to be 1;

[0399] In the second joint decoding sequence, if the value of the fourth bit is less than (X+1) / 2, the value of the fourth bit is determined to be 0;

[0400] Where X represents the number of repetitions.

[0401] exist Figure 20In this document, a bus architecture (represented by bus 2001) is used. Bus 2001 can include any number of interconnected buses and bridges, linking various circuits including one or more processors 2005 (represented by processor 2005) and memory 2006. Bus 2001 can also link various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further herein. Bus interface 2004 provides an interface between bus 2001 and transceiver 2002. Transceiver 2002 can be a single element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by processor 2005 is transmitted over a wireless medium via antenna 2003, which further receives data and transmits it to processor 2005.

[0402] Processor 2005 manages bus 2001 and general processing, and also provides various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory 2006 can be used to store data used by processor 2005 during processing.

[0403] Optionally, the processor 2005 can be a CPU, ASIC, FPGA, or CPLD.

[0404] This invention also provides a transmitting device, including: a processor, a memory, and a program stored in the memory and executable on the processor. When the program is executed by the processor, it implements the various processes of the above-described signal processing method and achieves the same technical effect. To avoid repetition, it will not be described again here.

[0405] For details, see Figure 21 As shown, this embodiment of the invention also provides a transmitting device, including a bus 2101, a transceiver 2102, an antenna 2103, a bus interface 2104, a processor 2105, and a memory 2106.

[0406] The processor 2105 is used for:

[0407] Acquire the source signal to be sent;

[0408] Based on the number of logic "1"s and logic "0"s in the source signal, a first logic value is determined. The first logic value is used by the receiving device to determine the decoding result of the first code block with the bit error when performing data decoding and detecting a bit error.

[0409] The source signal is source encoded to generate a preamble and a data code, and the value of the first target bit in the preamble is set to the first logic value. The preamble carries first indication information, which is used to indicate the first target bit.

[0410] The transceiver 2102 is used for:

[0411] A first signal is sent to the receiving device, the first signal including the preamble and the data code.

[0412] Optionally, the processor 2105 is used for:

[0413] If the number of logic "1"s in the source signal is greater than the number of logic "0", the first logic value is determined to be 1; or, if the number of logic "1"s in the source signal is less than the number of logic "0", the first logic value is determined to be 0.

[0414] Optionally, the transceiver 2102 is further configured to:

[0415] Upon receiving the second indication information sent by the receiving device, a second signal is sent to the receiving device. The second signal includes N sub-sequences, which are obtained by encoding the source signal, where N is an odd number.

[0416] Optionally, the processor 2105 is further configured to:

[0417] A first CRC checksum is inserted between the preamble and the data code, wherein the first signal includes the preamble, the first CRC checksum, and the data code.

[0418] Optionally, the processor 2105 is further configured to:

[0419] The data code is divided into L sub-blocks;

[0420] A second CRC checksum is inserted between any two adjacent sub-blocks in the L sub-blocks. The first signal includes the preamble, the data code, and L-1 second CRC checksums.

[0421] Optionally, neither the preamble nor the data code contains a sequence of two or more consecutive "10"s.

[0422] Optionally, the processor 2105 is used for:

[0423] The source signal is precoded to obtain a precoded signal, wherein the encoding length obtained by precoding logic "1" is equal to the encoding length obtained by precoding logic "0".

[0424] The precoded signal is subjected to Pulse Width Encoding (PIE) to generate a preamble and a data code.

[0425] exist Figure 21 In this document, a bus architecture (represented by bus 2101) is used. Bus 2101 may include any number of interconnected buses and bridges, linking various circuits including one or more processors 2105 (represented by processor 2105) and memory 2106. Bus 2101 may also link various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further herein. Bus interface 2104 provides an interface between bus 2101 and transceiver 2102. Transceiver 2102 may be a single element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by processor 2105 is transmitted over a wireless medium via antenna 2103, which further receives data and transmits it to processor 2105.

[0426] Processor 2105 is responsible for managing bus 2101 and general processing, and can also provide various functions, including timing, peripheral interface, voltage regulation, power management, and other control functions. Memory 2106 can be used to store data used by processor 2105 during processing.

[0427] Optionally, the processor 2105 can be a CPU, ASIC, FPGA, or CPLD.

[0428] This invention also provides a computer-readable storage medium storing a computer program. When executed by a processor, this computer program implements the various processes of the above-described signal processing method embodiments and achieves the same technical effects. To avoid repetition, further details are omitted here. The computer-readable storage medium may be, for example, ROM, RAM, a magnetic disk, or an optical disk.

[0429] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0430] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0431] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of the present invention.

Claims

1. A signal processing method, characterized by, The method is applied to a receiving end device, and comprises the following steps: Receiving a first signal sent by a sending end device, wherein the first signal comprises a preamble and a data code, the preamble carries first indication information, and the first indication information is used for indicating a first target bit in the preamble; According to the first indication information, a value of the first target bit is obtained and stored as a target value, wherein the value of the first target bit is determined according to a number of logical "1"s and a number of logical "0"s in a source signal corresponding to the first signal, and the source signal is a signal that has not been subjected to source encoding; In a case where data decoding is performed and an error code is detected, a decoding value of a code block in which the error code occurs is determined as the target value.

2. The method of claim 1, wherein, In a case where the number of logical "1"s is greater than the number of logical "0"s in the source signal, the value of the first target bit is 1; In a case where the number of logical "1"s is less than the number of logical "0"s in the source signal, the value of the first target bit is 0.

3. The method of claim 1, wherein, The method further comprises the following steps: In a case where data decoding is performed and an error code is detected, second indication information is sent to the sending end device, wherein the second indication information is used for instructing the sending end device to perform odd-numbered times of repetition processing based on the source signal; Receiving a second signal sent by the sending end device, wherein the second signal comprises N sub-sequences, the sub-sequences are obtained by encoding the source signal, and N is an odd number; Respectively performing data decoding on the N sub-sequences, and in a case where an error code is detected, a decoding value of a code block in which the error code occurs is determined as the target value, thereby obtaining N first decoding sequences respectively corresponding to the N sub-sequences; Correspondingly accumulating the N first decoding sequences according to bit positions, thereby obtaining a first joint decoding sequence; According to the first joint decoding sequence, a final decoding result is determined.

4. The method of claim 3, wherein, After the receiving of the second signal sent by the sending end device, the method further comprises the following steps: In a case where the second signal is composed of M sub-sequences and M is an even number, k sub-sequences in the M sub-sequences are discarded, thereby obtaining the N sub-sequences, k is an odd number, and N=M-k; In a case where the second signal is composed of M sub-sequences and M is an odd number, the M sub-sequences are obtained, and N=M.

5. The method of claim 3, wherein, The corresponding accumulation of the N first decoding sequences according to bit positions, thereby obtaining the first joint decoding sequence, comprises any one of the following: The values on each bit of each first decoding sequence in the N first decoding sequences are one-to-one accumulated, thereby obtaining the first joint decoding sequence; The values on a second target bit of each first decoding sequence in the N first decoding sequences are one-to-one accumulated, thereby obtaining the first joint decoding sequence, and the second target bit is a bit corresponding to a code block in which an error code occurs.

6. The method of claim 3, wherein, N is an odd number and N=2^n-1, n is a positive integer, and the determination of the final decoding result according to the first joint decoding sequence comprises the following steps: In a case where a value of a first bit in the first joint decoding sequence is greater than or equal to 2^(n-1), the value of the first bit is determined as 1. In the first joint decoding sequence, if a value of a second bit is less than 2^(n-1), it is determined that the value of the second bit is 0.

7. The method of claim 1, wherein, Before the value of the first target bit is obtained according to the first indication information and stored as a target value, the method further comprises: performing a cyclic redundancy check (CRC) on the preamble; the value of the first target bit is obtained according to the first indication information and stored as a target value, comprising: if the preamble CRC check passes, the value of the first target bit is obtained according to the first indication information and stored as a target value.

8. The method of claim 7, wherein, The method further comprises: if the preamble CRC check fails and the preamble can be identified, the value of the first target bit is obtained according to the first indication information and stored as a target value after being inverted.

9. The method according to claim 7 or 8, characterized in that, The cyclic redundancy check (CRC) on the preamble comprises: if there is a first CRC check code between the preamble and the data code, the CRC check is performed on the preamble according to the first CRC check code.

10. The method of claim 1, wherein, The data code comprises L sub-blocks, and the method further comprises: if there is a second CRC check code after the i-th sub-block is decoded and detected, the CRC check is performed on the i-th sub-block according to the second CRC check code, 1≤i≤L; if the CRC check of at least one sub-block in the L sub-blocks passes, the final decoding result is determined according to the decoding result of the at least one sub-block whose CRC check passes; if the CRC check of all the L sub-blocks fails, a second joint decoding sequence is obtained by performing corresponding accumulation processing on the L sub-blocks according to the L second decoding sequences corresponding to the L sub-blocks, respectively, and the final decoding result is determined according to the second joint decoding sequence.

11. The method of claim 10, wherein, The final decoding result is determined according to the second joint decoding sequence, comprising: if a value of a third bit in the second joint decoding sequence is greater than or equal to (X+1) / 2, it is determined that the value of the third bit is 1; if a value of a fourth bit in the second joint decoding sequence is less than (X+1) / 2, it is determined that the value of the fourth bit is 0; wherein X is a repetition number.

12. A signal processing method characterized by, The method applied to a sending end device, comprising: obtaining a source signal to be sent; determining a first logic value according to a number of logic "1"s and a number of logic "0"s in the source signal, the first logic value being used to determine a decoding result of a first code block in which an error occurs as the first logic value when the receiving end device decodes data and detects an error; performing source encoding on the source signal to generate a preamble and a data code, and setting a value of a first target bit in the preamble as the first logic value, wherein the preamble carries first indication information indicating the first target bit; sending a first signal to a receiving end device, the first signal comprising the preamble and the data code.

13. The method of claim 12, wherein, The determining the first logic value according to the number of logic "1"s and the number of logic "0"s in the source signal comprises: determining the first logic value as 1 if the number of logic "1"s is greater than the number of logic "0"s in the source signal, or determining the first logic value as 0 if the number of logic "1"s is less than the number of logic "0"s in the source signal.

14. The method of claim 12, wherein, The method further comprises: in the case of receiving the second indication information sent by the receiving end device, sending a second signal to the receiving end device, wherein the second signal comprises N sub-sequences, the sub-sequences are obtained by encoding the source signal, and N is an odd number.

15. The method of claim 12, wherein, Before sending the first signal to the receiving end device, the method further comprises: inserting a first CRC check code between the preamble and the data code, and the first signal comprises the preamble, the first CRC check code and the data code.

16. The method of claim 12, wherein, Before sending the first signal to the receiving end device, the method further comprises: dividing the data code into L sub-blocks; inserting a second CRC check code between any two adjacent sub-blocks in the L sub-blocks, and the first signal comprises the preamble, the data code and L-1 second CRC check codes.

17. The method of claim 12, wherein, There is no sequence of more than two consecutive "10"s in the preamble and the data code.

18. The method of claim 12, wherein, The source encoding of the source signal to generate the preamble and the data code comprises: performing pre-encoding processing on the source signal to obtain a pre-encoded signal, wherein the encoding length of logic "1" after the pre-encoding processing is equal to the encoding length of logic "0" after the pre-encoding processing; performing pulse width encoding (PIE) on the pre-encoded signal to generate the preamble and the data code.

19. A receiving end device, comprising: The device comprises: a first receiving module configured to receive a first signal sent by a sending end device, wherein the first signal comprises a preamble and a data code, the preamble carries first indication information, and the first indication information is used to indicate a first target bit position in the preamble; a first obtaining module configured to obtain the value of the first target bit position as a target value according to the first indication information, wherein the value of the first target bit position is determined by the sending end device according to the number of logic "1"s and the number of logic "0"s in a source signal corresponding to the first signal, and the source signal is a signal that has not been subjected to source encoding; a first decoding module configured to determine the decoding value of a code block in which an error occurs as the target value in the case of performing data decoding and detecting an error.

20. A transmitting device, comprising: The device comprises: a second obtaining module configured to obtain a source signal to be sent; a first determining module configured to determine a first logic value according to the number of logic "1"s and the number of logic "0"s in the source signal, wherein the first logic value is used by a receiving end device to determine the decoding result of a first code block in which an error occurs as the first logic value in the case of performing data decoding and detecting an error. The generating module is configured to source encode the source signal, generate a preamble and a data code, set a value of a first target bit in the preamble to the first logic value, and cause the preamble to carry first indication information, the first indication information being used to indicate the first target bit. The first sending module is configured to send a first signal to a receiving end device, the first signal comprising the preamble and the data code.

21. A receiving end device, comprising: The transceiver and the processor, The transceiver is configured to: receive a first signal sent by a sending end device, the first signal comprising a preamble and a data code, the preamble carrying first indication information, the first indication information being used to indicate a first target bit in the preamble; The processor is configured to: obtain a value of the first target bit according to the first indication information, and store the value as a target value, the value of the first target bit being determined by the sending end device according to a number of logic "1"s and a number of logic "0"s in a source signal corresponding to the first signal, the source signal being a signal that has not been source encoded; In a case where data decoding is performed and an error code is detected, a decoding value of a code block in which the error code occurs is determined as the target value.

22. A transmitting device, comprising: The transceiver and the processor, The processor is configured to: obtain a source signal to be sent; determine a first logic value according to a number of logic "1"s and a number of logic "0"s in the source signal, the first logic value being used by a receiving end device to determine a decoding result of a first code block in which an error code occurs as the first logic value in a case where data decoding is performed and the error code is detected; source encode the source signal, generate a preamble and a data code, set a value of a first target bit in the preamble to the first logic value, and cause the preamble to carry first indication information, the first indication information being used to indicate the first target bit; The transceiver is configured to: send a first signal to a receiving end device, the first signal comprising the preamble and the data code.

23. A receiving end device, comprising: The processor, the memory, and a program stored in the memory and executable on the processor, the program, when executed by the processor, implements the steps of the signal processing method according to any one of claims 1-11. The processor, the memory, and a program stored in the memory and executable on the processor, the program, when executed by the processor, implements the steps of the signal processing method according to any one of claims 12-18.

24. A transmitting device, comprising: The computer program is stored in the computer readable storage medium, and when executed by the processor, implements the steps of the signal processing method according to any one of claims 1-11, or implements the steps of the signal processing method according to any one of claims 12-18. ​ 25. A computer-readable storage medium, characterized in that, ​

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