A memory

Abstract

An embodiment of the present disclosure provides a memory, which includes a buffer unit, and the buffer unit includes multiple sub-buffer units, wherein: the wiring layer of the memory includes at least a first wiring layer and a second wiring layer, and the second wiring layer is located above the first wiring layer, a first type of signal wiring is formed in the first wiring layer, and a second type of signal wiring is formed in the second wiring layer; the multiple sub-buffer units include multiple first sub-buffer units and multiple second sub-buffer units, and the multiple first sub-buffer units are connected to the first type of signal wiring, and the multiple second sub-buffer units are connected to the second type of signal wiring, wherein every two first sub-buffer units are distributed on both sides of a second sub-buffer unit, thereby making the connection of the first type of signal wiring and the second type of signal wiring more convenient and ensuring signal integrity, thereby improving memory performance and saving memory area.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a memory. Background Art

[0002] With the continuous development of semiconductor technology, people have placed increasingly higher demands on data transmission speeds when manufacturing and using computers and other devices. To achieve faster data transmission speeds, a series of devices such as memories that can transmit data at double the data rate (DDR) have emerged.

[0003] The row decoder requires a buffer in its center to ensure signal integrity. However, since the row decoder contains many signals, each requiring a buffer for driver processing, the center area of ​​the row decoder becomes extremely crowded, making signal routing difficult and hindering memory wiring design. Summary of the Invention

[0004] An embodiment of the present disclosure provides a memory.

[0005] In a first aspect, an embodiment of the present disclosure provides a memory, the memory including a buffer unit, and the buffer unit including a plurality of sub-buffer units, wherein:

[0006] The wiring layer of the memory includes at least a first wiring layer and a second wiring layer, and the second wiring layer is located above the first wiring layer, the first wiring layer is formed with a first type of signal wiring, and the second wiring layer is formed with a second type of signal wiring;

[0007] The multiple sub-buffer units include multiple first sub-buffer units and multiple second sub-buffer units, and the multiple first sub-buffer units are connected to the first type of signal wiring, and the multiple second sub-buffer units are connected to the second type of signal wiring, wherein every two first sub-buffer units are distributed on both sides of one second sub-buffer unit.

[0008] In some embodiments, the first-type signal wiring includes a plurality of first wirings, and the second-type signal wiring includes a plurality of second wirings, wherein:

[0009] Each of the first wirings is connected to two of the first sub-buffer units;

[0010] Each of the second wirings is connected to a corresponding second sub-buffer unit.

[0011] In some embodiments, the plurality of first wirings include a target first wiring, and the plurality of second wirings include a target second wiring, wherein:

[0012] When the orthographic projections of the target first wiring and the target second wiring overlap in the first wiring layer, the two target first sub-buffer units correspondingly connected to the target first wiring are distributed on both sides of the target second sub-buffer unit correspondingly connected to the target second wiring.

[0013] In some embodiments, the target first wiring includes a first wiring segment, a second wiring segment, and a third wiring segment, wherein:

[0014] The first wiring segment and the third wiring segment are located in the first wiring layer, and the first wiring segment is connected to the first contact hole of the first target first sub-buffer unit, and the third wiring segment is connected to the second contact hole of the second target first sub-buffer unit;

[0015] The second wiring segment is located in a wiring layer other than the first wiring layer, and the second wiring segment is respectively connected to the second contact hole of the first target first sub-buffer unit and the first contact hole of the second target first sub-buffer unit.

[0016] In some embodiments, the target second wiring includes a fourth wiring segment and a fifth wiring segment, wherein:

[0017] The fourth wiring segment and the fifth wiring segment are located in the second wiring layer, and the fourth wiring segment is connected to the first contact hole of the target second sub-buffer unit, and the fifth wiring segment is connected to the second contact hole of the target second sub-buffer unit.

[0018] In some embodiments, the wiring layer of the memory further includes a third wiring layer and a fourth wiring layer, wherein:

[0019] The first wiring layer is located above the fourth wiring layer;

[0020] The fourth wiring layer is located above the third wiring layer;

[0021] The third wiring layer includes third-type signal wiring, and the fourth wiring layer includes fourth-type signal wiring.

[0022] In some embodiments, the second wiring segment is located in the third wiring layer.

[0023] In some embodiments, the first-type signal wiring, the second-type signal wiring, and the third-type signal wiring all extend along a first direction, the fourth-type signal wiring extends along a second direction, and the first direction is different from the second direction.

[0024] In some embodiments, the memory further includes an intermediate unit, and the buffer unit and the intermediate unit are located in a middle area of ​​the memory, wherein:

[0025] The buffer unit includes a first buffer unit and a second buffer unit, the first buffer unit and the second buffer unit are spaced apart along a first direction, and the middle unit is located between the first buffer unit and the second buffer unit.

[0026] In some embodiments, the first buffer unit includes the plurality of sub-buffer units, and the second buffer unit includes the plurality of sub-buffer units, wherein:

[0027] The number of sub-buffer units included in the first buffer unit is the same as the number of sub-buffer units included in the second buffer unit.

[0028] In some embodiments, the memory includes a plurality of memory arrays, wherein:

[0029] Each storage array includes a decoding circuit, and the buffer unit is located in the middle area of ​​the decoding circuit.

[0030] In some embodiments, the memory further includes a peripheral circuit, and the plurality of memory arrays are distributed on both sides of the peripheral circuit, wherein:

[0031] The peripheral circuit is used to send a signal to the decoding circuit of each storage unit.

[0032] In some embodiments, the plurality of storage arrays includes at least one first storage array and at least one second storage array, wherein:

[0033] In a first direction, the at least one first memory array and the at least one second memory array are distributed on both sides of the peripheral circuit;

[0034] In the second direction, the at least one first storage array is placed side by side, and the at least one second storage array is placed side by side.

[0035] An embodiment of the present disclosure provides a memory, which includes a buffer unit, and the buffer unit includes a plurality of sub-buffer units, wherein: the wiring layer of the memory includes at least a first wiring layer and a second wiring layer, and the second wiring layer is located above the first wiring layer, a first type of signal wiring is formed in the first wiring layer, and a second type of signal wiring is formed in the second wiring layer; the plurality of sub-buffer units include a plurality of first sub-buffer units and a plurality of second sub-buffer units, and the plurality of first sub-buffer units are connected to the first type of signal wiring, and the plurality of second sub-buffer units are connected to the second type of signal wiring, wherein every two first sub-buffer units are distributed on both sides of a second sub-buffer unit. In this way, since the second type of signal wiring is located on the upper layer of the first type of signal wiring, by placing the two first sub-buffer units connected to the first type of signal wiring on both sides of a second sub-buffer unit connected to the second type of signal wiring, the connection between the first type of signal wiring and the second type of signal wiring is made more convenient, and the signal integrity is guaranteed, thereby improving the memory performance and saving the memory area. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A schematic diagram of the composition structure of a wiring layer;

[0037] Figure 2 A schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure Figure 1 ;

[0038] Figure 3 A schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure Figure 2 ;

[0039] Figure 4 A schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure Figure 3 ;

[0040] Figure 5 A schematic diagram of the extension direction of a signal wiring provided by an embodiment of the present disclosure;

[0041] Figure 6 A schematic diagram of the composition structure of a memory;

[0042] Figure 7 A schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure Figure 4 ;

[0043] Figure 8 A schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure Figure 5 ;

[0044] Figure 9 A schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure Figure 6 . DETAILED DESCRIPTION

[0045] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It should be understood that the specific embodiments described herein are only used to explain the related applications and are not intended to limit the present disclosure. It should also be noted that for ease of description, only the portions relevant to the related applications are shown in the drawings.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0047] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0048] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0049] Before further explaining the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are explained first. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations:

[0050] Dynamic Random Access Memory (DRAM);

[0051] Double Data Rate (DDR);

[0052] Fifth-generation double data rate (DDR5);

[0053] Row decoder / X Decoder (XDEC for short);

[0054] Column decoder / Y Decoder (YDEC);

[0055] Buffer;

[0056] Buffer cell;

[0057] Chip;

[0058] Cell array;

[0059] Contact hole (Via);

[0060] Metal Oxide Semiconductor field effect transistor (MOS tube);

[0061] Peripheral circuit (PERI);

[0062] Sense Amplifier (SA).

[0063] It can be understood that for memory, a certain amount of storage space is reserved in the memory. This storage space is used to buffer input or output data. This reserved space is called a buffer. In the design of DDR5, the height of the row decoder spans the entire memory cell array area, so the signals in the row decoder need to be buffered in its middle area to ensure signal integrity. However, since there are many signals in the row decoder and each signal requires a buffer, if a buffer is added to the middle area of ​​the row decoder for driving processing, the middle area will be particularly crowded. In addition, considering the chip area, these signals cannot be laid out using the same metal layer (Floorplan), but need to be routed using different metal wiring layers (Routing). However, when connecting the upper metal wiring layer to the lower metal wiring layer, it is necessary to connect from the upper metal wiring layer to the lower metal wiring layer layer by layer. In this way, it is difficult to connect the wiring in two adjacent metal wiring layers, causing wiring difficulties and being unfavorable for the wiring design of the memory.

[0064] For example, see Figure 1 , which shows a schematic diagram of the composition structure of a wiring layer. Figure 1 As shown in (a), M1 represents the first metal layer, M2 represents the second metal layer, M3 represents the third metal layer, and M4 represents the fourth metal layer, wherein M1 is located at the bottom layer, M2 is located above M1, M3 is located above M2, and M4 is located above M3; Via1 represents the first through hole, used to connect M1 and M2; Via2 represents the second through hole, used to connect M2 and M3; Via3 represents the third through hole, used to connect M3 and M4. Figure 1As shown in (a), when M4 is connected to the lower-level M2, it needs to be connected through Via3, M3 and Via2. At this time, if M4 and M3 are overlapped for wiring, as shown in Figure 1 As shown in (b), M4 will overlap with M3, and M4 will be directly connected to M3 through Via3. M4 and the overlapping M3 will form a short circuit, resulting in M4 being unable to connect to M2 through Via3, which will cause certain difficulties in wiring layout and connection.

[0065] Based on this, an embodiment of the present disclosure provides a memory in which the second-type signal wiring is located on the upper layer of the first-type signal wiring. By placing two first sub-buffer units connected to the first-type signal wiring on both sides of a second sub-buffer unit connected to the second-type signal wiring, the connection between the first-type signal wiring and the second-type signal wiring is made more convenient, and the signal integrity is guaranteed, thereby improving the memory performance and saving the memory area.

[0066] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0067] In one embodiment of the present disclosure, see Figure 2 , which shows a schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure Figure 1 .like Figure 2 As shown, the memory 10 may include a buffer unit, and the buffer unit includes a plurality of sub-buffer units, wherein:

[0068] The wiring layer of the memory 10 includes at least a first wiring layer M3 and a second wiring layer M4, and the second wiring layer M4 is located above the first wiring layer M3. The first wiring layer M3 is formed with a first-type signal wiring m3, and the second wiring layer M4 is formed with a second-type signal wiring m4.

[0069] The multiple sub-buffer units include multiple first sub-buffer units 111 and multiple second sub-buffer units 112, and the multiple first sub-buffer units 111 are connected to the first type of signal wiring m3, and the multiple second sub-buffer units 112 are connected to the second type of signal wiring m4, wherein every two first sub-buffer units 111 are distributed on both sides of a second sub-buffer unit 112.

[0070] It should be noted that in Figure 2 In the embodiment, the memory 10 is described by taking two first sub-buffer units 111 and one second sub-buffer unit 112 as an example. However, it should be noted that the memory 10 may include multiple groups such as Figure 2 The combination of two first sub-buffer units 111 and one second sub-buffer unit 112 is shown in FIG. , and the embodiment of the present disclosure does not specifically limit this.

[0071] It should also be noted that the memory 10 may be a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDRSDRAM), etc., and no specific limitation is given here.

[0072] Furthermore, the memory 10 may be a DRAM chip. DRAM chips may not only conform to memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, and DDR6, but may also conform to memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, and LPDDR6, without specific limitations here. Furthermore, the disclosed embodiments are not limited to DRAM chips; all other chips may also adopt this design, without specific limitations here.

[0073] It should also be noted that in the embodiments of the present disclosure, the buffer unit may refer to some devices used in the layout, which are the basic components of the layout, such as MOS tubes and resistors, etc., and there is no specific limitation on this. The buffer unit may include multiple sub-buffer units, and the multiple sub-buffer units are used to drive and enhance the signals transmitted in the signal wiring. Specifically, the first sub-buffer unit 111 is connected to the first type of signal wiring m3, and can be used to drive and enhance the signals transmitted in the first type of signal wiring m3; the second sub-buffer unit 112 is connected to the second type of signal wiring m4, and can be used to drive and enhance the signals transmitted in the second type of signal wiring m4.

[0074] It should also be noted that, in the embodiment of the present disclosure, the plurality of sub-buffer units may include a plurality of sub-buffer unit combinations formed by two first sub-buffer units 111 and one second sub-buffer unit 112. For example, Figure 2 Only one group of sub-buffer unit combinations is shown. It can be understood that for each group of sub-buffer unit combinations formed by two first sub-buffer units 111 and one second sub-buffer unit 112 , every two first sub-buffer units 111 are distributed on both sides of one second sub-buffer unit 112 .

[0075] Understandably, the layout of the buffer cells needs to be comprehensively considered when designing the routing for the global bus in the disclosed embodiments. Here, a second sub-buffer cell 112 connected to the second-type signal wiring m4 is placed in the middle, and two first sub-buffer cells 111 connected to the first-type signal wiring m3 are placed on either side of the second sub-buffer cell 112. This prevents the second-type signal wiring m4 from short-circuiting with the first-type signal wiring m3 when it is connected to the bottom layer, thereby facilitating the connection between the first-type signal wiring m3 and the second-type signal wiring m4. This not only improves memory performance but also potentially reduces memory area.

[0076] Furthermore, for the wiring layer of the memory, in addition to the first wiring layer M3 and the second wiring layer M4, in some embodiments, the wiring layer of the memory may further include a third wiring layer M1 and a fourth wiring layer M2, wherein:

[0077] The first wiring layer M3 is located above the fourth wiring layer M2;

[0078] The fourth wiring layer M2 is located above the third wiring layer M1;

[0079] The third type signal wiring m1 is formed in the third wiring layer M1 , and the fourth type signal wiring m2 is formed in the fourth wiring layer M2 .

[0080] It should be noted that multiple types of signal wiring are formed in the multiple wiring layers of the memory. Specifically, the third type of signal wiring m1 is located at the bottom layer, the fourth type of signal wiring m2 is located above the third type of signal wiring m1, the first type of signal wiring m3 is located above the fourth type of signal wiring m2, and the second type of signal wiring m4 is located above the first type of signal wiring m3. The first type of signal wiring m3 and the second type of signal wiring m4 are high-level metal wiring used for global bus wiring.

[0081] It's also worth noting that because the row decoder has numerous signal traces, the first-type signal trace m3 and the second-type signal trace m4 are sometimes routed in the same direction. Both the first-type signal trace m3 and the second-type signal trace m4 need to connect to the buffer unit in the middle region of the row decoder, causing congestion. Furthermore, because both the first-type signal trace m3 and the second-type signal trace m4 need to connect to the third-type signal trace m1 at the bottom layer, the second-type signal trace m4 needs to occupy the lane of the first-type signal trace m3 when it connects downward, further causing congestion. In other words, the lane congestion in the middle region of the row decoder primarily refers to the congestion between the first-type signal trace m3 and the second-type signal trace m4.

[0082] This congestion between the first-type signal wiring m3 and the second-type signal wiring m4 causes routing difficulties for the first-type signal wiring m3 and the second-type signal wiring m4. In the disclosed embodiment, by placing two first sub-buffer units connected to the first-type signal wiring m3 on either side of a second sub-buffer unit connected to the second-type signal wiring m4, this routing difficulty for the first-type signal wiring m3 and the second-type signal wiring m4 is resolved.

[0083] In addition, the memory 10 may further include a fifth wiring layer M5, a sixth wiring layer M6, and so on, wherein the fifth wiring layer M5 is located above the second wiring layer M4, and the sixth wiring layer M6 is located above the fifth wiring layer M5. The number of wiring layers of the memory 10 can be specifically set according to actual conditions and is not limited thereto.

[0084] As for the positional relationship between the multiple wiring layers in the memory, it can be understood that the third wiring layer M1 is located at the bottom layer, the fourth wiring layer M2 is located above the third wiring layer M1, the first wiring layer M3 is located above the fourth wiring layer M2, and the second wiring layer M4 is located above the first wiring layer M3. For the convenience of illustration, the subsequent Figures 3 to 9 The multiple wiring layers are no longer shown.

[0085] In some embodiments, the first-type signal wiring m3 includes a plurality of first wirings, and the second-type signal wiring m4 includes a plurality of second wirings, wherein:

[0086] Each first wiring is connected to two first sub-buffer units; each second wiring is connected to one second sub-buffer unit.

[0087] It should be noted that in the disclosed embodiment, the first-type signal wiring m3 may be composed of one or more first wirings, and the second-type signal wiring m4 may be composed of one or more second wirings. The number of wirings included in each type of signal wiring can be set based on actual conditions and is not specifically limited here.

[0088] It can be understood that each signal requires a sub-buffer unit to drive it, that is, the wiring of each signal is connected to the corresponding sub-buffer unit. In order to facilitate wiring and avoid overlapping of the first wiring and the second wiring, for example, Figure 2 As shown, the first wiring may be connected to two first sub-buffer units 111 ; and the second wiring may be connected to one second sub-buffer unit 112 .

[0089] In some embodiments, see Figure 3 , the plurality of first wirings include a target first wiring 22, and the plurality of second wirings include a target second wiring 23, wherein:

[0090] When the orthographic projections of the target first wiring 22 and the target second wiring 23 overlap on the first wiring layer M3, the two target first sub-buffer units (211a and 211b) correspondingly connected to the target first wiring 22 are distributed on both sides of the target second sub-buffer unit 212 correspondingly connected to the target second wiring 23.

[0091] It should be noted that the target first wiring 22 is set in the first wiring layer M3, and the orthographic projection of the target second wiring 23 refers to its orthographic projection in the first wiring layer M3. In this way, when the orthographic projections of the target first wiring 22 and the target second wiring 23 overlap in the first wiring layer M3, when the target second wiring 23 located in the second wiring layer M4 is connected to other wiring layers below, a short circuit will occur between the first wiring layer M3 and the target first wiring 22. Therefore, it is necessary to disconnect the target first wiring 22 through the first target first sub-buffer unit 211a and the second target first sub-buffer unit 211b. Moreover, these two target first sub-buffer units (211a and 211b) are distributed on both sides of the target second sub-buffer unit 212, thereby avoiding a short circuit between the target first wiring 22 and the target second wiring 23, making the connection between the target first wiring 22 and the target second wiring 23 more convenient.

[0092] It should also be noted that, for the target first wiring 22, Figure 3 Based on Figure 4 , which shows a schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure Figure 3 .like Figure 4 As shown, in some embodiments, the target first wiring may include a first wiring segment 221, a second wiring segment 222, and a third wiring segment 223, wherein:

[0093] The first wiring segment 221 and the third wiring segment 223 are located in the first wiring layer M3, and the first wiring segment 221 is connected to the first contact hole 24 of the first target first sub-buffer unit 211a, and the third wiring segment 223 is connected to the second contact hole 25 of the second target first sub-buffer unit 211b;

[0094] The second wiring segment 222 is located in a wiring layer other than the first wiring layer M3 and is respectively connected to the second contact hole 26 of the first target first sub-buffer unit 211a and the first contact hole 27 of the second target first sub-buffer unit 211b.

[0095] It should be noted that the first wiring segment 221 serves as the input of the first target first sub-buffer unit 211a, and is connected to the input end of the first target first sub-buffer unit 211a through the first contact hole 24 of the first target first sub-buffer unit 211a; the second wiring segment 222 serves as the output of the first target first sub-buffer unit 211a, and is connected to the output end of the first target first sub-buffer unit 211a through the second contact hole 26 of the first target first sub-buffer unit 211a; the second wiring segment 222 serves as the input of the second target first sub-buffer unit 211b, and is connected to the input end of the second target first sub-buffer unit 211b through the first contact hole 27 of the second target first sub-buffer unit 211b; the third wiring segment 223 serves as the output of the second target first sub-buffer unit 211b, and is connected to the output end of the second target first sub-buffer unit 211b through the second contact hole 25 of the second target first sub-buffer unit 211b. That is to say, in the embodiment of the present disclosure, contact holes 24, 25, 26 and 27 may be provided here so that the target first wiring can be fully connected with the two target first sub-buffer units (211a and 211b), thereby also being able to achieve a driving enhancement effect on the target first wiring.

[0096] It should also be noted that second wiring segment 222 is located in the middle of the target first wiring. Its orthographic projection overlaps with the target second wiring on first wiring layer M3. Therefore, second wiring segment 222 needs to be located in a wiring layer other than first wiring layer M3. In other words, second wiring segment 222 can be a jumper to avoid overlapping between the target first wiring and the target second wiring. In this way, first wiring segment 221 and third wiring segment 223 are connected via second wiring segment 222 in another wiring layer.

[0097] It should also be noted that, in some embodiments, the second wiring segment 222 is located in the third wiring layer M1 .

[0098] In the disclosed embodiment, the second wiring segment 222 serves as a jumper and can be located in the third wiring layer M1, the fifth wiring layer M5, or even other wiring layers, without specific limitations. It should be noted that the jumper can be located in either the third wiring layer M1 or the fifth wiring layer M5, as long as the signal wiring located in the wiring layer extends in the same direction as the first wiring segment 221 and the third wiring segment 223, and can be used to connect the first wiring segment 221 and the third wiring segment 223, without specific limitations.

[0099] Further, for the target second wiring, in some embodiments, as Figure 4 As shown, the target second wiring may include a fourth wiring segment 231 and a fifth wiring segment 232, wherein:

[0100] The fourth wiring segment 231 and the fifth wiring segment 232 are located in the second wiring layer M4 , and the fourth wiring segment 231 is connected to the first contact hole 28 of the target second sub-buffer unit 212 , and the fifth wiring segment 232 is connected to the second contact hole 29 of the target second sub-buffer unit 212 .

[0101] It should be noted that the fourth wiring segment 231 serves as the input of the target second sub-buffer unit 212 and is connected to the input terminal of the target second sub-buffer unit 212 via the first contact hole 28 of the target second sub-buffer unit 212. The fifth wiring segment 232 serves as the output of the target second sub-buffer unit 212 and is connected to the output terminal of the target second sub-buffer unit 212 via the second contact hole 29 of the target second sub-buffer unit 212. In other words, in the embodiment of the present disclosure, contact holes 28 and 29 may be provided to ensure that the target second wiring is fully connected to the target second sub-buffer unit 212, thereby further enhancing the driving effect of the target second wiring.

[0102] That is to say, if Figure 4 As shown, the second wiring layer M4 is located above the first wiring layer M3. When the target second wiring in the second wiring layer M4 is connected to the lower wiring layer, since the target second sub-buffer unit 212 is set between the first target first sub-buffer unit 211a and the second target first sub-buffer unit 211b, and the target first wiring is divided into three sections by the first target first sub-buffer unit 211a and the second target first sub-buffer unit 211b, especially the middle section is set as a jumper in other wiring layers, so that the overlap of the target first wiring and the target second wiring can be better avoided, making wiring easier to implement.

[0103] Further, for the extension direction of the signal wiring, see Figure 5 , which shows a schematic diagram of the extension direction of a signal wiring provided by an embodiment of the present disclosure. Figure 5 As shown, in some embodiments, the first type signal wiring m3, the second type signal wiring m4 and the third type signal wiring m1 all extend along the first direction, the fourth type signal wiring m2 extends along the second direction, and the first direction is different from the second direction.

[0104] It should be noted that in the embodiments of the present disclosure, the first direction refers to the vertical direction, i.e. the longitudinal direction; the second direction refers to the horizontal direction, i.e. the transverse direction; or, the first direction refers to the horizontal direction, i.e. the transverse direction; the second direction refers to the vertical direction, i.e. the longitudinal direction; no specific limitation is given here.

[0105] For example, Figure 5As shown, taking the first direction as the vertical direction and the second direction as the horizontal direction as an example, at this time, the first type signal wiring m3, the second type signal wiring m4 and the third type signal wiring m1 all extend in the vertical direction, and the fourth type signal wiring m2 extends in the horizontal direction.

[0106] It should also be noted that extending along the first direction may include extending in a vertically upward direction or in a vertically downward direction. In the embodiment of the present disclosure, the first-type signal wiring m3, the second-type signal wiring m4, and the third-type signal wiring m1 all extend along the first direction, which may specifically mean that they all extend in the same direction of the first direction; that is, the first-type signal wiring m3, the second-type signal wiring m4, and the third-type signal wiring m1 may all extend in a vertically upward direction or in a vertically downward direction; or, the first-type signal wiring m3, the second-type signal wiring m4, and the third-type signal wiring m1 all extend along the first direction, which may specifically mean that they extend in different directions of the first direction; that is, the first-type signal wiring m3 may extend in a vertically upward direction, the second-type signal wiring m4 and the third-type signal wiring m1 may extend in a vertically downward direction, or the first-type signal wiring m3 and the second-type signal wiring m4 may extend in a vertically downward direction, and the third-type signal wiring m1 may extend in a vertically upward direction, and so on. This is not specifically limited here.

[0107] It is also understandable that in the design of DDR5, taking the row decoder as an example, the device layout of the top half (T) and the bottom half (B) of the row decoder are the same, and B can be formed by shifting T downward. However, because the row decoder is connected to the wiring starting from the peripheral circuit (PERI), the direction of the metal wiring of B and T is opposite. At this time, if the buffer unit cannot be placed in the middle, the routing of the wiring starting from PERI will be inconsistent. For example, see Figure 6 , which shows a schematic diagram of the composition structure of a memory. Figure 6 As shown in (a) in FIG, the wiring from the peripheral circuit connection T extends upward along the first direction, and the wiring from the peripheral circuit connection B extends downward along the first direction; Figure 6 As shown in (b), the middle area of ​​T and B (indicated by an ellipse) can be composed of buffer cells and other cells, and the other cells are located above the buffer cells. Since B is formed by the overall translation of T, the layout of the buffer cells and other cells of T and B are the same, and the other cells are located above the buffer cells. However, during wiring, the signal wiring directions emitted from the peripheral circuit are opposite, making the routing of these signals to the buffer cells in T inconsistent with the routing of the signals to the buffer cells in B, which is not conducive to the signal wiring in the memory.

[0108] Based on this, in some embodiments, see Figure 7 , which shows a schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure Figure 4 .like Figure 7 As shown, the memory 10 further includes an intermediate unit 12, and the buffer unit and the intermediate unit 12 are located in the middle area of ​​the memory 10, wherein:

[0109] The buffer unit includes a first buffer unit 13 and a second buffer unit 14 . The first buffer unit 13 and the second buffer unit 14 are spaced apart along a first direction, and the intermediate unit 12 is located between the first buffer unit 13 and the second buffer unit 14 .

[0110] It should be noted that the intermediate unit 12 may specifically be the aforementioned other cells (Other cells), which may refer to other cell structures that need to be placed in the middle area of ​​the memory 10 except for the buffer unit, and is not specifically limited to this.

[0111] It should also be noted that the middle area of ​​the memory 10 refers to the middle position of the memory. For example, in the embodiment of the present disclosure, it may refer to the middle position of a row decoder, which is not specifically limited.

[0112] It should also be noted that if Figure 7 As shown, the first buffer unit 13 and the second buffer unit 14 are symmetrically placed along the middle unit 12, that is, the first buffer unit 13 and the second buffer unit 14 are distributed on both sides of the middle unit 12. In addition, the spacing distance between the first buffer unit 13, the middle unit 12 and the second buffer unit 14 can be as follows Figure 7 The close connection shown may also mean that there is a certain distance between two adjacent units, which is not specifically limited.

[0113] In the embodiment of the present disclosure, the buffer units in the middle area of ​​the row decoder are split into a first buffer unit 13 and a second buffer unit 14, and the first buffer unit 13 and the second buffer unit 14 are spaced apart along the first direction and distributed on both sides of the middle unit 12; in this way, the routing of the buffer units and the middle units in the upper and lower parts of the row decoder will be completely consistent, which is beneficial to signal wiring.

[0114] Furthermore, regarding the number of buffer units, in some embodiments, the first buffer unit 13 includes multiple sub-buffer units, and the second buffer unit 14 includes multiple sub-buffer units, wherein:

[0115] The number of sub-buffer units included in the first buffer unit 13 is the same as the number of sub-buffer units included in the second buffer unit 14 .

[0116] It should be noted that if the first buffer unit 13 and the second buffer unit 14 are Figure 7 The regular shape shown may also indicate that the areas of the first buffer unit 13 and the second buffer unit 14 are equal, but this is not specifically limited.

[0117] It should also be noted that both the first buffer unit 13 and the second buffer unit 14 include the same number of sub-buffer units. For either the first buffer unit 13 or the second buffer unit 14, the multiple sub-buffer units include multiple first sub-buffer units and multiple second sub-buffer units. The multiple first sub-buffer units are connected to the first-type signal wiring m3, and the multiple second sub-buffer units are connected to the second-type signal wiring m4. Furthermore, every two first sub-buffer units are located on either side of a second sub-buffer unit. Thus, in the memory 10, both the first buffer unit 13 and the second buffer unit 14 facilitate the connection of the first-type signal wiring m3 and the second-type signal wiring m4, improving memory performance and saving memory area while also ensuring a relatively symmetrical and aesthetically pleasing overall layout.

[0118] In some embodiments, see Figure 8 The memory 10 may include a plurality of memory arrays, wherein each memory array includes a decoding circuit, and the buffer unit of the aforementioned embodiment is located in the middle area of ​​the decoding circuit.

[0119] It should be noted that the decoding circuit may be a row decoding circuit (ie, a row decoder), or a column decoding circuit (ie, a column decoder), and this is not specifically limited.

[0120] It should also be noted that if Figure 8 As shown, memory 10 may include memory array A, memory array B, memory array C, and memory array D; memory array A includes decoding circuit 31, memory array B includes decoding circuit 32, memory array C includes decoding circuit 33, and memory array D includes decoding circuit 34. In addition, a buffer unit (filled with oblique lines) is provided in the middle area of ​​each decoding circuit. The buffer units here may include a first buffer unit and a second buffer unit, which are distributed on both sides of the middle unit (filled with white).

[0121] It should also be noted that when data is to be written to a memory cell in the memory array, or when data is to be read from a memory cell, the memory cell must first be addressed. The addressing process begins by inputting the corresponding row address signal and column address signal of the memory cell to be operated into the row address buffer and column address buffer, and then selecting a specific row address line through the row decoder to activate the specific row address; wherein, each row address line is connected to multiple column address lines and multiple memory cells. In order to detect the weak activation signal on the column address line, a sense amplifier (SA) is required to amplify this signal; after the row is activated, the column address signal in the column address buffer is determined by the column decoder, and is amplified by the corresponding sense amplifier and connected to the local data line. In this way, the memory cell is activated and can be read and write operations, and the addressing is completed.

[0122] In this way, because the decoding circuit includes the buffer unit of the aforementioned embodiment, the second-type signal wiring in the decoding circuit will not be short-circuited with the first-type signal wiring when connected to the bottom layer, thereby making the connection between the first-type signal wiring and the second-type signal wiring more convenient and ensuring signal integrity, thereby improving the performance of the decoding circuit and saving the area of ​​the decoding circuit.

[0123] Furthermore, in some embodiments, Figure 8 As shown, the memory 10 may further include a peripheral circuit 35, with multiple memory arrays distributed on both sides of the peripheral circuit 35; wherein the peripheral circuit 35 is used to send a signal to the decoding circuit of each memory unit.

[0124] In the embodiment of the present disclosure, the decoding circuit includes a buffer unit, so that each signal received by the decoding circuit can be driven and enhanced by the sub-buffer unit in the buffer unit.

[0125] Furthermore, in some embodiments, Figure 8 As shown, the plurality of storage arrays may include at least one first storage array and at least one second storage array, wherein:

[0126] In a first direction, at least one first memory array and at least one second memory array are distributed on both sides of the peripheral circuit 35;

[0127] In the second direction, at least one first storage array is placed side by side, and at least one second storage array is placed side by side.

[0128] It should be noted that, in the embodiments of the present disclosure, see Figure 8, at least one first storage array can be storage array A and storage array B, and at least one second storage array can be storage array C and storage array D; however, whether it is at least one first storage array or at least one second storage array, the specific number included is set according to actual conditions and is not specifically limited here.

[0129] It should also be noted that, in the embodiments of the present disclosure, see Figure 8 Horizontally, memory arrays A and B are placed side by side, while memory arrays C and D are placed side by side. Vertically, memory arrays A and B, and memory arrays C and D, are located on either side of peripheral circuit 35. Thus, the signal routing from peripheral circuit 35 to decoding circuits 31 and 32 is vertically upward, while the signal routing from peripheral circuit 35 to decoding circuits 33 and 34 is vertically downward, with the two routing directions being opposite.

[0130] In this way, since each decoding circuit includes a buffer unit, and the buffer unit can be divided into a first buffer unit and a second buffer unit, and distributed on both sides of the middle unit; in this way, the routing between the two sides of the peripheral circuit and the buffer unit can be completely consistent, which is beneficial to signal wiring, improves the performance of the decoding circuit in the memory array, and can also save the area of ​​the decoding circuit.

[0131] In summary, the embodiment of the present disclosure provides a memory, which makes the connection of the first-class signal wiring and the second-class signal wiring more convenient by placing a second sub-buffer unit connected to the second-class signal wiring in the middle and placing two first sub-buffer units connected to the first-class signal wiring on both sides of the second sub-buffer unit, and ensures signal integrity, thereby improving memory performance and saving memory area. In addition, by splitting the buffer unit in the middle area of ​​the decoding circuit into a first buffer unit and a second buffer unit, and placing the first buffer unit and the second buffer unit at intervals along the first direction and distributed on both sides of the middle unit, the wiring between the two sides of the peripheral circuit and the buffer unit can be completely consistent, which is beneficial to wiring and improves the performance of the memory.

[0132] In another embodiment of the present disclosure, see Figure 9 , which shows a schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure Figure 6 .like Figure 9As shown in the figure, the M4 buffer unit (M4 buffer) connected to the M4 busing is located in the middle, and the two M3 buffer units (M3 buffer) connected to the M3 busing are located on both sides of the M4 buffer unit. The arrows point to the connection direction of the M4 busing and the M3 busing. In addition, the middle area of ​​the M3 busing can be connected by the M1 busing, that is, the jumper located in the M1 to avoid overlapping of M3 and M4. Figure 9 As shown, the connection of the M4 wiring is concentrated in the circle area, avoiding the M3 wiring, which makes it easier to connect M4 and M3.

[0133] Understandably, Figure 9 There are multiple M3 buffer units and M4 buffer units, the M3 buffer units are all connected to the M3 wiring, and the M4 buffer units are all connected to the M4 wiring. For each group of buffer units formed by two M3 buffer units and one M4 buffer unit, every two M3 buffer units are distributed on both sides of an M4 buffer unit.

[0134] It should be noted that the embodiments of the present disclosure mainly relate to the layout design of unit blocks and buses in integrated circuits, and specifically, can be the layout design of the middle area of ​​a row decoder. The direction of the signal wiring in two adjacent metal wiring layers will be laid out according to different actual conditions, and can be wired in the same direction or in opposite directions. However, in most cases, the signal wiring in two adjacent metal wiring layers is in a wiring situation of opposite directions. The embodiments of the present disclosure complete the signal connection without increasing the chip area and when the signal wiring in two adjacent metal wiring layers is in the same direction. In the design of DRAM, since the chip is large and there are more buses, a more reasonable unit block and busing layout is required.

[0135] It should also be noted that M1 is the bottom metal wiring layer, M2 is located above M1, M3 is located above M2, and M4 is located above M3. The memory may also include M5 located above M4, M6 located above M5, and so on, and there is no limitation on this.

[0136] It should also be noted that multiple types of signal wiring are formed in multiple wiring layers. Similarly, the signal wiring formed in M1, namely M1 wiring, is located at the bottom layer; the signal wiring formed in M2, namely M2 wiring, is located above the M1 wiring; the signal wiring formed in M3, namely M3 wiring, is located above the M2 wiring; the signal wiring formed in M4, namely M4 wiring, is located above the M3 wiring.

[0137] It should also be noted that M3 and M4 can be jumpered by M1 wiring or M5 wiring, and there is no specific limitation on this.

[0138] It should also be noted that the M1 wiring, the M3 wiring, and the M4 wiring extend in the longitudinal direction, and the M2 wiring extends in the transverse direction.

[0139] In summary, the above embodiments have been used to elaborate on the specific implementation of the aforementioned embodiments. It can be seen that in the upper and lower halves of the row decoder, the M4 buffer unit is placed in the middle, and the corresponding two M3 buffer units are placed on both sides of the M4 buffer unit. This can make the routing of the M3 wiring and the M4 wiring more convenient, ensure signal integrity, and make the device layout of the upper and lower halves of the row decoder completely consistent, which is beneficial to wiring, thereby improving memory performance and saving memory area.

[0140] Details not disclosed in the embodiments of the present disclosure may be understood by referring to the description of the aforementioned embodiments.

[0141] The above description is merely a preferred embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure.

[0142] It should be noted that, in this disclosure, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0143] The serial numbers of the above-mentioned embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments.

[0144] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0145] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0146] The features disclosed in several method or device embodiments provided in this disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0147] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A memory, characterized in that: The memory includes a buffer unit, and the buffer unit includes a plurality of sub-buffer units, wherein: The wiring layer of the memory includes at least a first wiring layer and a second wiring layer, and the second wiring layer is located above the first wiring layer, the first wiring layer is formed with a first type of signal wiring, and the second wiring layer is formed with a second type of signal wiring; The plurality of sub-buffer units include a plurality of first sub-buffer units and a plurality of second sub-buffer units, wherein the plurality of first sub-buffer units are connected to the first-type signal wiring, and the plurality of second sub-buffer units are connected to the second-type signal wiring, wherein every two first sub-buffer units are distributed on both sides of one second sub-buffer unit; The first type of signal wiring includes a plurality of first wirings, and the second type of signal wiring includes a plurality of second wirings, wherein: Each of the first wirings is connected to two of the first sub-buffer units; Each of the second wirings is connected to a corresponding second sub-buffer unit; The plurality of first wirings include a target first wiring, and the plurality of second wirings include a target second wiring, wherein: When the orthographic projections of the target first wiring and the target second wiring overlap in the first wiring layer, the two target first sub-buffer units correspondingly connected to the target first wiring are distributed on both sides of the target second sub-buffer unit correspondingly connected to the target second wiring.

2. The memory according to claim 1, wherein The target first wiring includes a first wiring segment, a second wiring segment, and a third wiring segment, wherein: The first wiring segment and the third wiring segment are located in the first wiring layer, and the first wiring segment is connected to the first contact hole of the first target first sub-buffer unit, and the third wiring segment is connected to the second contact hole of the second target first sub-buffer unit; The second wiring segment is located in a wiring layer other than the first wiring layer, and the second wiring segment is respectively connected to the second contact hole of the first target first sub-buffer unit and the first contact hole of the second target first sub-buffer unit.

3. The memory according to claim 1, wherein: The target second wiring includes a fourth wiring segment and a fifth wiring segment, wherein: The fourth wiring segment and the fifth wiring segment are located in the second wiring layer, and the fourth wiring segment is connected to the first contact hole of the target second sub-buffer unit, and the fifth wiring segment is connected to the second contact hole of the target second sub-buffer unit.

4. The memory according to claim 2, wherein: The wiring layer of the memory further includes a third wiring layer and a fourth wiring layer, wherein: The first wiring layer is located above the fourth wiring layer; The fourth wiring layer is located above the third wiring layer; The third wiring layer includes third-type signal wiring, and the fourth wiring layer includes fourth-type signal wiring.

5. The memory according to claim 4, wherein: The second wiring segment is located in the third wiring layer.

6. The memory according to claim 4, wherein: The first-type signal wiring, the second-type signal wiring, and the third-type signal wiring all extend along a first direction, and the fourth-type signal wiring extends along a second direction, and the first direction is different from the second direction.

7. The memory according to claim 1, wherein: The memory further includes an intermediate unit, and the buffer unit and the intermediate unit are located in a middle area of ​​the memory, wherein: The buffer unit includes a first buffer unit and a second buffer unit, the first buffer unit and the second buffer unit are spaced apart along a first direction, and the middle unit is located between the first buffer unit and the second buffer unit.

8. The memory according to claim 7, wherein: The first buffer unit includes the plurality of sub-buffer units, and the second buffer unit includes the plurality of sub-buffer units, wherein: The number of sub-buffer units included in the first buffer unit is the same as the number of sub-buffer units included in the second buffer unit.

9. The memory according to any one of claims 1 to 8, characterized in that The memory includes a plurality of memory arrays, wherein: Each storage array includes a decoding circuit, and the buffer unit is located in the middle area of ​​the decoding circuit.

10. The memory according to claim 9, wherein: The memory further includes a peripheral circuit, and the plurality of memory arrays are distributed on both sides of the peripheral circuit, wherein: The peripheral circuit is used to send a signal to the decoding circuit of each storage unit.

11. The memory according to claim 10, wherein: The plurality of storage arrays include at least one first storage array and at least one second storage array, wherein: In a first direction, the at least one first memory array and the at least one second memory array are distributed on both sides of the peripheral circuit; In the second direction, the at least one first storage array is placed side by side, and the at least one second storage array is placed side by side.

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