A capacitor-free dynamic random access memory and its preparation method

Abstract

The present invention discloses a capacitor-free dynamic random access memory and a preparation method thereof, belonging to the field of semiconductor technology. The memory comprises a vertically stacked write transistor and a read transistor, which respectively correspond to a group of source layer, drain layer and gate layer. Both transistors use a two-dimensional insulating material as an encapsulation layer to protect the channel layer of the two-dimensional semiconductor material, thereby improving the stability of the channel layer at high temperatures and reducing the off-state leakage current of the transistor at high temperatures, thereby extending the data retention time of the dynamic random access memory and realizing a high-temperature resistant capacitor-free dynamic random access memory. On this basis, by introducing a second insulating layer and a fourth insulating layer, the problem of too small gate capacitance between the gate and the channel caused by using the two-dimensional insulating material as the encapsulation layer, which affects the data storage time, is avoided, thereby improving the high-temperature stability of the memory while ensuring the storage performance.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and more specifically, relates to a capacitor-free dynamic random access memory and a preparation method thereof. Background Art

[0002] Since Intel invented dynamic random access memory (DRAM) in the 1970s, it has been widely used in various computing and control electronic circuit systems. With the advancement of semiconductor manufacturing technology, DRAM manufacturing has gradually evolved from using logic processes to using dedicated DRAM manufacturing processes. This has enabled DRAM to be separated from logic chips and become off-chip memory.

[0003] DRAM includes a variety of memory cells, and one of the more commonly used structures in existing memory cells is the capacitor-less dual-transistor structure. In order to overcome the difficulties of continued scaling of capacitor-less dual-transistor DRAM and overcome the short channel effect, some scholars have proposed using two-dimensional layered semiconductor materials as channels to achieve continued scaling of DRAM. However, if two-dimensional layered materials are directly used as channels, the oxidation of the two-dimensional layered semiconductor materials will cause transistor performance degradation, the off-state leakage current will increase sharply, and the data retention time of the DRAM cell will be greatly shortened. The high-temperature stability is low, which is not conducive to data preservation. Summary of the Invention

[0004] In response to the above defects or improvement needs of the prior art, the present invention provides a capacitor-free dynamic random access memory and a preparation method thereof, the purpose of which is to improve the high-temperature stability of the memory while ensuring storage performance.

[0005] In order to achieve the above objectives, in a first aspect, the present invention provides a capacitor-less dynamic random access memory, comprising:

[0006] A substrate, a first insulating layer, a first encapsulation layer and a first channel layer are sequentially arranged from bottom to top;

[0007] a first source layer and a first drain layer disposed on the first channel layer and not connected to each other; a region of the first channel layer between the first source layer and the first drain layer serving as a first channel region;

[0008] a second encapsulation layer covering the upper surfaces of the first source layer, the first channel layer and the first drain layer; the second encapsulation layer being provided with a first through hole exposing part or all of the upper surface of the first drain layer;

[0009] a second insulating layer covering the upper surface of the second encapsulation layer; the second insulating layer being provided with a second through hole penetrating the first through hole;

[0010] a first gate layer disposed on the second insulating layer, with at least a portion of the layer being located directly above the first channel region;

[0011] a third insulating layer covering the second insulating layer and the upper surface of the first gate layer; the third insulating layer being provided with a third through hole exposing part or all of the upper surface of the first gate layer, and a fourth through hole communicating with the second through hole;

[0012] a third encapsulation layer covering the upper surface of the third insulating layer; the third encapsulation layer being provided with a fifth through hole communicating with the third through hole, and a sixth through hole communicating with the fourth through hole;

[0013] a second source electrode layer and a second drain electrode layer, at least a portion of the second source electrode layer is filled in the third through hole and the fifth through hole, and at least a portion of the second drain electrode layer is filled in the first through hole, the second through hole, the fourth through hole, and the sixth through hole;

[0014] a second channel layer covering the third encapsulation layer, the second source layer, and the second drain layer; a region of the second channel layer between the second source layer and the second drain layer serving as a second channel region;

[0015] a fourth encapsulation layer and a fourth insulating layer sequentially disposed on the second channel layer;

[0016] a second gate layer disposed on the fourth insulating layer, with at least a portion of the layer being located directly above the second channel region;

[0017] The materials of the first channel layer and the second channel layer are two-dimensional semiconductor materials; the materials of the first packaging layer, the second packaging layer, the third packaging layer and the fourth packaging layer are two-dimensional insulating materials.

[0018] Further preferably, the material of the first encapsulation layer, the second encapsulation layer, the third encapsulation layer and the fourth encapsulation layer is hexagonal boron nitride.

[0019] Further preferably, the second insulating layer and the fourth insulating layer are made of insulating materials with a relative dielectric constant higher than 20.

[0020] Further preferably, the materials of the second insulating layer and the fourth insulating layer include: hafnium oxide, zirconium oxide, titanium oxide or strontium titanate.

[0021] In a second aspect, the present invention provides a method for preparing a capacitor-free dynamic random access memory, comprising:

[0022] Sequentially forming a first insulating layer, a first encapsulation layer, and a first channel layer on the substrate from bottom to top;

[0023] A first source electrode layer and a first drain electrode layer that are not connected to each other are formed on the first channel layer; wherein a region of the first channel layer between the first source electrode layer and the first drain electrode layer serves as a first channel region;

[0024] preparing a second encapsulation layer to cover upper surfaces of the first source electrode layer, the first channel layer, and the first drain electrode layer;

[0025] preparing a second insulating layer so as to cover the upper surface of the second encapsulation layer;

[0026] forming a first gate layer on the second insulating layer, and ensuring that at least a portion of the first gate layer is located directly above the first channel region;

[0027] preparing a third insulating layer so as to cover the upper surfaces of the second insulating layer and the first gate layer;

[0028] preparing a third encapsulation layer so as to cover the upper surface of the third insulating layer;

[0029] forming through holes on the second packaging layer, the second insulating layer, the third insulating layer and the third packaging layer to expose the upper surfaces of the first gate layer and the first drain layer;

[0030] preparing a second source electrode layer and a second drain electrode layer, so that at least a portion of the second source electrode layer is filled in the through hole that exposes the upper surface of the first gate electrode layer, and at least a portion of the second drain electrode layer is filled in the through hole that exposes the upper surface of the first drain electrode layer;

[0031] preparing a second channel layer so as to cover the upper surfaces of the third encapsulation layer, the second source electrode layer, and the second drain electrode layer; wherein the second channel layer region between the second source electrode layer and the second drain electrode layer serves as the second channel region;

[0032] sequentially forming a fourth encapsulation layer and a fourth insulating layer on the second channel layer;

[0033] forming a second gate layer on the fourth insulating layer, and ensuring that at least a portion of the second gate layer is located directly above the second channel region;

[0034] The materials of the first channel layer and the second channel layer are two-dimensional semiconductor materials; the materials of the first packaging layer, the second packaging layer, the third packaging layer and the fourth packaging layer are two-dimensional insulating materials.

[0035] Further preferably, the material of the first encapsulation layer, the second encapsulation layer, the third encapsulation layer and the fourth encapsulation layer is hexagonal boron nitride.

[0036] Further preferably, the second insulating layer and the fourth insulating layer are made of insulating materials with a relative dielectric constant higher than 20.

[0037] Further preferably, the materials of the second insulating layer and the fourth insulating layer include: hafnium oxide, zirconium oxide, titanium oxide or strontium titanate.

[0038] Further preferably, the first encapsulation layer, the second encapsulation layer, the third encapsulation layer, the fourth encapsulation layer, the first channel layer and the second channel layer are all prepared by a dry process or a wet process.

[0039] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects:

[0040] 1. The present invention provides a capacitor-free dynamic random access memory, comprising a vertically stacked write transistor and a read transistor, wherein one transistor comprises a first source layer, a first drain layer, and a first gate layer, and the other transistor comprises a second source layer, a second drain layer, and a second gate layer; both transistors use a two-dimensional insulating material as an encapsulation layer to protect a channel layer of a two-dimensional semiconductor material, thereby improving the stability of the channel layer at high temperatures and reducing the off-state leakage current of the transistor at high temperatures, thereby extending the data retention time of the dynamic random access memory and realizing a high-temperature resistant capacitor-free dynamic random access memory; on this basis, by introducing a second insulating layer and a fourth insulating layer, the problem of too small gate capacitance between the gate and the channel caused by using a two-dimensional insulating material as an encapsulation layer, which affects the data storage time, is avoided, thereby improving the high-temperature stability of the memory while ensuring storage performance.

[0041] 2. The capacitor-free dynamic random access memory provided by the present invention combines the dual-transistor vertical stacking technology with the bit line time-sharing multiplexing method, which not only reduces the unit area of ​​the dynamic random access memory and simplifies the circuit structure of the dynamic random access memory, but also makes it conducive to three-dimensional integration, greatly improving the integration of the dynamic random access memory.

[0042] 3. The capacitor-free dynamic random access memory provided by the present invention uses two-dimensional semiconductor materials for the transistor channels, which prevents the transistors from being affected by the short channel effect during continuous size reduction, thereby ensuring that the present invention still has excellent read and write performance during continuous size reduction.

[0043] 4. Furthermore, in the capacitor-free dynamic random access memory provided by the present invention, the materials of the second insulating layer and the fourth insulating layer are insulating materials with a relative dielectric constant higher than 20, which further increases the transistor gate capacitance, thereby further improving the data retention time and read and write speed of the capacitor-free dynamic random access memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A schematic structural diagram of a capacitor-free dynamic random access memory provided by the present invention;

[0045] Figure 2 A schematic diagram of the storage principle of a capacitor-free dynamic random access memory provided by an embodiment of the present invention;

[0046] Figure 3-17This is a schematic diagram of the structure obtained in each step of the preparation method of the capacitor-free dynamic random access memory provided by an embodiment of the present invention.

[0047] Description of reference numerals:

[0048] 100 is a substrate, 200 is a first insulating layer, 300 is a first encapsulation layer, 400 is a first channel layer, 500 is a first drain layer, 600 is a first source layer, 700 is a second encapsulation layer, 800 is a second insulating layer, 900 is a first gate layer, 1000 is a third insulating layer, 1100 is a third encapsulation layer, 1200 is a second source layer, 1300 is a second drain layer, 1400 is a second channel layer, 1500 is a fourth encapsulation layer, 1600 is a fourth insulating layer, and 1700 is a second gate layer. DETAILED DESCRIPTION

[0049] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

[0050] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present disclosure. These figures are not drawn to scale, and for the purpose of clarity, certain details are exaggerated and certain details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0051] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, it can be directly on the other layer / element or an intervening layer / element may be present therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed.

[0052] In order to achieve the above object, in a first aspect, the present invention provides a capacitor-free dynamic random access memory, such as Figure 1 Shown, including:

[0053] A substrate 100, a first insulating layer 200, a first encapsulation layer 300 and a first channel layer 400 are sequentially arranged from bottom to top;

[0054] A first source layer 500 and a first drain layer 600 are provided on the first channel layer 400 and are not connected to each other; a first channel layer region between the first source layer 500 and the first drain layer 600 serves as a first channel region;

[0055] a second encapsulation layer 700 covering the upper surfaces of the first source layer 500, the first channel layer 400 and the first drain layer 600; a first through hole is provided in the second encapsulation layer 700 to partially or completely expose the upper surface of the first drain layer 600;

[0056] a second insulating layer 800 covering the upper surface of the second encapsulation layer 700; a second through hole penetrating the first through hole is provided in the second insulating layer 800;

[0057] A first gate layer 900 is disposed on the second insulating layer 800 and at least a portion of which is located directly above the first channel region;

[0058] a third insulating layer 1000 covering the second insulating layer 800 and the upper surface of the first gate layer 900; the third insulating layer 1000 is provided with a third through hole exposing part or all of the upper surface of the first gate layer 900, and a fourth through hole communicating with the second through hole;

[0059] a third encapsulation layer 1100 covering the upper surface of the third insulating layer 1000; a fifth through hole communicating with the third through hole and a sixth through hole communicating with the fourth through hole are provided in the third encapsulation layer 1100;

[0060] A second source electrode layer 1200 and a second drain electrode layer 1300, at least part of the second source electrode layer 1200 is filled in the third through hole and the fifth through hole, and at least part of the second drain electrode layer 1300 is filled in the first through hole, the second through hole, the fourth through hole, and the sixth through hole;

[0061] a second channel layer 1400 covering the upper surfaces of the third encapsulation layer 1100 , the second source layer 1200 , and the second drain layer 1300 ; a second channel layer region between the second source layer 1200 and the second drain layer 1300 serving as a second channel region;

[0062] a fourth encapsulation layer 1500 and a fourth insulating layer 1600 sequentially disposed on the second channel layer 1400 ;

[0063] a second gate layer 1700 disposed on the fourth insulating layer 1600 , with at least a portion of the second gate layer being located directly above the second channel region;

[0064] The first channel layer 400 and the second channel layer 1400 are made of two-dimensional semiconductor materials, and the first encapsulation layer 300 , the second encapsulation layer 700 , the third encapsulation layer 1100 and the fourth encapsulation layer 1500 are made of two-dimensional insulating materials.

[0065] It should be noted that the above-mentioned two-dimensional semiconductor materials include: molybdenum disulfide, molybdenum ditelluride, tungsten selenide, etc., which are not limited here. Two-dimensional insulating materials include: hexagonal boron nitride, bismuth selenide, bismuth telluride, etc., which are not limited here.

[0066] It should be noted that the substrate 100 may be silicon, germanium, silicon germanium, gallium arsenide, or the like.

[0067] In terms of material selection of the capacitor-free dynamic random access memory of the present invention, each layer can be made of any material that can achieve its basic function. However, in order to further improve the electrical performance and use effect of the memory, each layer has its preferred material.

[0068] For example, in some optional embodiments, the substrate 100 may be made of silicon, germanium, silicon germanium, gallium arsenide, etc.

[0069] In some optional embodiments, the first channel layer 400 and the second channel layer 1400 are preferably two-dimensional layered semiconductor materials such as molybdenum disulfide and molybdenum ditelluride.

[0070] In some optional embodiments, the first packaging layer 300, the second packaging layer 700, the third packaging layer 1100 and the fourth packaging layer 1500 are preferably two-dimensional layered insulator materials such as hexagonal boron nitride, which is beneficial for encapsulating and protecting the channel layer of the two-dimensional layered semiconductor material to achieve a high-temperature resistant capacitor-free dynamic random access memory, thereby expanding the application scenarios of the memory.

[0071] The insulating layer material in the present invention can be any insulating material, such as silicon oxide, silicon oxide, aluminum oxide, and hafnium oxide. Preferably, in some optional embodiments, the first insulating layer 200 and the third insulating layer 1000 are made of silicon oxide to facilitate large-area deposition. In some optional embodiments, the second insulating layer and the fourth insulating layer are preferably made of an insulating material with a relative dielectric constant greater than 20, such as hafnium oxide, zirconium oxide, titanium oxide, and strontium titanate.

[0072] In some optional embodiments, the first drain layer 500 , the first source layer 600 , the first gate layer 900 , the second source layer 1200 , the second drain layer 1300 and the second gate layer 1700 are preferably made of metal materials with good conductive properties, including but not limited to Au, Ti and Bi.

[0073] In some optional embodiments, considering the rapidity and stability of current transmission between electrodes, in some specific embodiments, the first drain layer 500, the first source layer 600, the first gate layer 900, the second source layer 1200, the second drain layer 1300 and the second gate layer 1700 preferably use the same electrode material.

[0074] In some optional embodiments, the upper surfaces of the third encapsulation layer 1100 , the second source electrode layer 1200 , and the second drain electrode layer 1300 are flush.

[0075] The capacitor-less dynamic random access memory of the present invention can be functionally divided into three regions from bottom to top: a substrate, a first transistor, and a second transistor. The first transistor includes a first encapsulation layer 300, a first channel layer 400, a first drain layer 500, a first source layer 600, a second encapsulation layer 700, a second insulating layer 800, and a first gate layer 900. The second transistor includes a second encapsulation layer 1100, a second source layer 1200, a second drain layer 1300, a second channel layer 1400, a fourth encapsulation layer 1500, a fourth insulating layer 1600, and a second gate layer 1700.

[0076] In an optional embodiment, the first transistor is a read transistor and the second transistor is a write transistor. The working principle of the capacitor-free dynamic random access memory is as follows: Figure 2 As shown (the position of the transistors in the figure is only for the convenience of illustrating the working principle and does not represent the actual position layout), the first transistor located at the upper part of the memory is a write transistor, and the second transistor located at the lower part of the memory is a read transistor. The drain layer of the read transistor is connected to the drain layer of the write transistor as a shared bit line, and the gate layer of the read transistor is connected to the source layer of the write transistor.

[0077] In the write state, a first level is applied to the gate of the write transistor through the word line to turn on the write transistor, and a storage signal is transmitted to the drain of the write transistor of the memory cell through the bit line to write the storage signal into the storage node of the memory cell as storage data; specifically, when the write transistor is P-type, the first level is the ground voltage VSS, that is, a low level; when the write transistor is N-type: the first level is the power supply voltage VDD, that is, a high level.

[0078] Specifically, when a storage signal is transmitted to the drain of the write transistor of the memory cell through the bit line, a voltage value corresponding to the stored data is applied to the bit line; when the read transistor is N-type, the stored data 1 corresponds to a high level, and the power supply voltage VDD is applied to the bit line; the stored data 0 corresponds to a low level, and the ground voltage VSS is applied to the bit line; when the read transistor is P-type, the stored data 1 corresponds to a low level, and the ground voltage VSS is applied to the bit line; the stored data 0 corresponds to a high level, and the power supply voltage VDD is applied to the bit line.

[0079] In a read state, a second voltage level is applied to the drain of the read transistor of the memory cell via the bit line. When the read transistor receives the second voltage level, it is turned on or off according to the potential of the stored data. This causes the bit line to capture a signal indicating whether the read transistor is in the on or off state as the read data. Specifically, the second voltage level is the equalization voltage VBLQ; preferably, the voltage at the intersection of a curve showing the voltage variation over time at the storage node SN when the storage node SN stores data 0 and a curve showing the voltage variation over time at the storage node SN when the storage node SN stores data 1.

[0080] In summary, in order to protect transistors from the short channel effect, reduce cell size, and improve the integration of the memory array, the channel material in the capacitor-free dynamic random access memory of the present invention adopts a two-dimensional semiconductor material. On this basis, a two-dimensional insulating material is used as an encapsulation layer to protect the two-dimensional semiconductor material to achieve a high-temperature resistant capacitor-free dynamic random access memory; however, such a design will make the gate capacitance between the gate and the channel too small, affecting the data storage time and thus affecting the storage performance. Based on this, the present invention introduces a second insulating layer and a fourth insulating layer, which can improve the high-temperature stability of the memory while ensuring the storage performance.

[0081] In a second aspect, the present invention provides a method for preparing a capacitor-free dynamic random access memory, comprising:

[0082] Sequentially forming a first insulating layer, a first encapsulation layer, and a first channel layer on the substrate from bottom to top;

[0083] A first source electrode layer and a first drain electrode layer that are not connected to each other are formed on the first channel layer; wherein a region of the first channel layer between the first source electrode layer and the first drain electrode layer serves as a first channel region;

[0084] preparing a second encapsulation layer to cover upper surfaces of the first source electrode layer, the first channel layer, and the first drain electrode layer;

[0085] preparing a second insulating layer so as to cover the upper surface of the second encapsulation layer;

[0086] forming a first gate layer on the second insulating layer, and ensuring that at least a portion of the first gate layer is located directly above the first channel region;

[0087] preparing a third insulating layer so as to cover the upper surfaces of the second insulating layer and the first gate layer;

[0088] preparing a third encapsulation layer so as to cover the upper surface of the third insulating layer;

[0089] forming through holes on the second packaging layer, the second insulating layer, the third insulating layer and the third packaging layer to expose the upper surfaces of the first gate layer and the first drain layer;

[0090] preparing a second source electrode layer and a second drain electrode layer, so that at least a portion of the second source electrode layer is filled in the through hole that exposes the upper surface of the first gate electrode layer, and at least a portion of the second drain electrode layer is filled in the through hole that exposes the upper surface of the first drain electrode layer;

[0091] preparing a second channel layer so as to cover the upper surfaces of the third encapsulation layer, the second source electrode layer, and the second drain electrode layer; wherein the second channel layer region between the second source electrode layer and the second drain electrode layer serves as the second channel region;

[0092] sequentially forming a fourth encapsulation layer and a fourth insulating layer on the second channel layer;

[0093] forming a second gate layer on the fourth insulating layer, and ensuring that at least a portion of the second gate layer is located directly above the second channel region;

[0094] The first channel layer and the second channel layer are made of two-dimensional semiconductor materials, and the first packaging layer, the second packaging layer, the third packaging layer and the fourth packaging layer are made of two-dimensional insulating materials.

[0095] The related technical solution is the same as the capacitor-free dynamic random access memory provided in the first aspect of the present invention, and will not be described in detail here.

[0096] In order to further illustrate the specific preparation process of the above-mentioned method for preparing the capacitor-free dynamic random access memory, a specific embodiment is described in detail below:

[0097] like Figure 3-16 The specific process is as follows:

[0098] First, a substrate 100 is provided, such as Figure 3 shown.

[0099] Then, a first insulating layer 200 is formed on the upper surface of the substrate 100. The resulting structure is as follows: Figure 4 Specifically, the first insulating layer 200 may be formed by using a physical vapor deposition method or a chemical vapor deposition method.

[0100] Afterwards, a first encapsulation layer 300 is formed on the upper surface of the first insulating layer 200, and the resulting structure is as shown in FIG. Figure 5 Specifically, the first encapsulation layer 300 can be formed by dry transfer or wet transfer.

[0101] Next, a first channel layer 400 is formed to cover the upper surface of the first encapsulation layer 300. The resulting structure is as follows: Figure 6 Specifically, the first channel layer 400 can be formed by dry transfer or wet transfer.

[0102] Afterwards, a first drain layer 500 and a first source layer 600 that are not connected to each other are formed on the upper surface of the first channel layer 400. The resulting structure is as shown in FIG. Figure 7 As shown. Specifically, the first drain electrode layer 500 and the first source electrode layer 600 can be formed by photolithography, deposition, and stripping. Specifically, first, the upper surface of the first channel layer 400 is patterned by photolithography, then the first electrode material layer is deposited, and finally, the photoresist is removed and the electrode materials except the first drain electrode layer 500 and the first source electrode layer 600 are stripped.

[0103] Next, a second encapsulation layer 700 is formed to cover the exposed first channel layer 400, the first drain layer 500 and the first source layer 600. The resulting structure is as shown in FIG. Figure 8 Specifically, the second encapsulation layer 700 can be formed by dry transfer or wet transfer.

[0104] Then, a second insulating layer 800 is formed on the upper surface of the second encapsulation layer 700. The resulting structure is as shown in FIG. Figure 9 Specifically, the second insulating layer 800 can be formed by physical vapor deposition, chemical vapor deposition or atomic layer deposition.

[0105] Then, a first gate layer 900 is formed on the upper surface of the second insulating layer 800 so that at least a portion of the gate layer 900 is located above the channel region between the first drain layer 500 and the first source layer 600. The resulting structure is as shown in FIG. Figure 10 Specifically, the first gate layer 900 can be formed by photolithography, deposition, and lift-off.

[0106] Then, a third insulating layer 1000 is formed to cover the first gate layer 900 and the second insulating layer 800. The resulting structure is as shown in FIG. Figure 11 Specifically, the third insulating layer 1000 may be formed by physical vapor deposition, chemical vapor deposition or atomic layer deposition.

[0107] Next, a third encapsulation layer 1100 is formed to cover the third insulating layer 1000. The resulting structure is as follows: Figure 12 Specifically, the third encapsulation layer 1100 can be formed by dry transfer or wet transfer.

[0108] Then, through holes 1200 and 1300 are formed on the second encapsulation layer 700, the second insulating layer 800, the third insulating layer 1000 and the third encapsulation layer 1100 to expose the upper surfaces of the first drain layer 500 and the first gate layer 600. The resulting structure is as shown in FIG. Figure 13 Specifically, the through holes 1200 and 1300 can be formed by photolithography and etching. The etching can be wet etching or dry etching.

[0109] Next, a second source layer 1200 and a second drain layer 1300 that are not connected to each other are formed by photolithography, deposition, and stripping, so that at least a portion of the second source layer 1200 and the second drain layer 1300 are filled in the groove, thereby connecting the second source layer 1200 to the first gate layer 900 and the second drain layer 1300 to the first drain layer 500. The resulting structure is as shown in FIG. Figure 14 shown.

[0110] Afterwards, a second channel layer 1400 is formed to cover the second encapsulation layer 1100, the second source layer 1200 and the second drain layer 1300. The resulting structure is as shown in FIG. Figure 15 Specifically, the second channel layer 1400 can be formed by dry transfer or wet transfer.

[0111] Then, a fourth encapsulation layer 1500 is formed to completely cover the second channel layer 1400. The resulting structure is as shown in FIG. Figure 16 Specifically, the fourth encapsulation layer 1500 can be formed by dry transfer or wet transfer.

[0112] Next, a fourth insulating layer 1600 is formed to cover the fourth encapsulation layer 1500. The resulting structure is as follows: Figure 17 Specifically, the fourth insulating layer 1600 can be formed by dry transfer or wet transfer.

[0113] Finally, a second gate layer 1700 is formed on the upper surface of the fourth insulating layer 1600 by photolithography, deposition and stripping. The resulting structure is as shown in FIG. Figure 1 shown.

[0114] It will be easily understood by those skilled in the art that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A capacitor-less dynamic random access memory, characterized in that: include: A substrate, a first insulating layer, a first encapsulation layer and a first channel layer are sequentially arranged from bottom to top; a first source layer and a first drain layer disposed on the first channel layer and not connected to each other; a first channel layer region between the first source layer and the first drain layer serving as a first channel region; a second encapsulation layer covering the first source layer, the first channel layer, and the upper surface of the first drain layer; the second encapsulation layer being provided with a first through hole exposing part or all of the upper surface of the first drain layer; a second insulating layer covering the upper surface of the second encapsulation layer; the second insulating layer being provided with a second through hole penetrating the first through hole; a first gate layer disposed on the second insulating layer, with at least a portion of the first gate layer located directly above the first channel region; a third insulating layer covering the second insulating layer and the upper surface of the first gate layer; the third insulating layer being provided with a third through hole exposing part or all of the upper surface of the first gate layer, and a fourth through hole communicating with the second through hole; a third encapsulation layer covering the upper surface of the third insulating layer; the third encapsulation layer being provided with a fifth through hole communicating with the third through hole, and a sixth through hole communicating with the fourth through hole; a second source electrode layer and a second drain electrode layer, at least a portion of the second source electrode layer is filled in the third through hole and the fifth through hole, and at least a portion of the second drain electrode layer is filled in the first through hole, the second through hole, the fourth through hole, and the sixth through hole; a second channel layer covering the third encapsulation layer, the second source layer, and the second drain layer; a second channel layer region between the second source layer and the second drain layer serving as a second channel region; a fourth encapsulation layer and a fourth insulating layer sequentially disposed on the second channel layer; a second gate layer disposed on the fourth insulating layer, at least a portion of which is located directly above the second channel region; The materials of the first channel layer and the second channel layer are two-dimensional semiconductor materials; the materials of the first packaging layer, the second packaging layer, the third packaging layer and the fourth packaging layer are two-dimensional insulating materials.

2. The capacitor-less dynamic random access memory according to claim 1, wherein: The materials of the first encapsulation layer, the second encapsulation layer, the third encapsulation layer and the fourth encapsulation layer are hexagonal boron nitride.

3. The capacitor-less dynamic random access memory according to claim 1, wherein: The second insulating layer and the fourth insulating layer are made of insulating materials with a relative dielectric constant higher than 20.

4. The capacitor-less dynamic random access memory according to claim 3, wherein: The second insulating layer and the fourth insulating layer are made of hafnium oxide, zirconium oxide, titanium oxide or strontium titanate.

5. A method for preparing a capacitor-free dynamic random access memory, characterized in that: include: Sequentially forming a first insulating layer, a first encapsulation layer, and a first channel layer on the substrate from bottom to top; forming a first source electrode layer and a first drain electrode layer which are not connected to each other on the first channel layer; a first channel layer region between the first source electrode layer and the first drain electrode layer serves as a first channel region; preparing a second encapsulation layer to cover upper surfaces of the first source electrode layer, the first channel layer, and the first drain electrode layer; preparing a second insulating layer so as to cover the upper surface of the second encapsulation layer; forming a first gate layer on the second insulating layer, and ensuring that at least a portion of the first gate layer is located directly above the first channel region; preparing a third insulating layer to cover upper surfaces of the second insulating layer and the first gate layer; preparing a third encapsulation layer so as to cover the upper surface of the third insulating layer; forming a through hole on the second encapsulation layer, the second insulating layer, the third insulating layer and the third encapsulation layer to expose the upper surfaces of the first gate layer and the first drain layer; preparing a second source electrode layer and a second drain electrode layer, so that at least a portion of the second source electrode layer is filled in the through hole that exposes the upper surface of the first gate layer, and at least a portion of the second drain electrode layer is filled in the through hole that exposes the upper surface of the first drain electrode layer; preparing a second channel layer so as to cover the upper surfaces of the third encapsulation layer, the second source electrode layer, and the second drain electrode layer; a second channel layer region between the second source electrode layer and the second drain electrode layer serves as a second channel region; sequentially forming a fourth encapsulation layer and a fourth insulating layer on the second channel layer; forming a second gate layer on the fourth insulating layer, and ensuring that at least a portion of the second gate layer is located directly above the second channel region; The materials of the first channel layer and the second channel layer are two-dimensional semiconductor materials; the materials of the first packaging layer, the second packaging layer, the third packaging layer and the fourth packaging layer are two-dimensional insulating materials.

6. The method for preparing a capacitor-less dynamic random access memory according to claim 5, wherein: The materials of the first encapsulation layer, the second encapsulation layer, the third encapsulation layer and the fourth encapsulation layer are hexagonal boron nitride.

7. The method for preparing a capacitor-less dynamic random access memory according to claim 5, wherein: The second insulating layer and the fourth insulating layer are made of insulating materials with a relative dielectric constant higher than 20.

8. The method for preparing a capacitor-less dynamic random access memory according to claim 7, wherein: The second insulating layer and the fourth insulating layer are made of hafnium oxide, zirconium oxide, titanium oxide or strontium titanate.

9. The method for preparing a capacitor-less dynamic random access memory according to any one of claims 5 to 8, wherein: The first encapsulation layer, the second encapsulation layer, the third encapsulation layer, the fourth encapsulation layer, the first channel layer and the second channel layer are all prepared by a dry method or a wet method.

Images