Test system

Abstract

The present application discloses a test system, which relates to the field of chip testing. The test system is used for a chip to be tested including a memory, and the test system includes a tester and a test module, wherein the test module is arranged on the chip to be tested and coupled to the access port of the memory; wherein the tester is configured to send a control signal, and the test module is configured to receive the control signal, and switch the state according to the control signal, and the state includes an idle state and a working state; when the test module is in the working state, the tester transmits the first data to the memory or reads the second data from the memory through at least one data pin of the chip to be tested, until the test module switches the state to the idle state according to the control signal; the control signal includes a maximum address signal, and when the test module switches from the idle state to the working state, the count value in the test module starts to accumulate, and when the count value accumulates to the maximum address signal, the test module switches from the working state to the idle state. In this way, the chip testing efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to a testing system. Background Art

[0002] Testing of chips can help engineers find defects in chip manufacturing and optimize them, so that the quality and performance of the chips meet the preset requirements. The physical objects tested include but are not limited to the pins, functional modules, interfaces and memories of the chip. Among them, the test of memories is indispensable, which can be used to verify the accuracy of the read and write functions of the memories.

[0003] In the prior art, the test of the memory part of the chip to be tested has the defects of slow test speed or high test equipment cost, which leads to uncontrollable time cost or economic cost of testing the chip to be tested, resulting in low test efficiency of the chip to be tested. Therefore, how to improve the test efficiency of the chip to be tested is an urgent problem to be solved. Summary of the invention

[0004] In view of this, the present application discloses a test system to achieve rapid reading and writing of data in a memory without increasing costs, thereby improving the test efficiency of a chip to be tested.

[0005] A test system is provided for a chip to be tested, wherein the chip to be tested includes a memory, and the test system includes a test machine and a test module, wherein the test module is arranged on the chip to be tested and coupled to an access port of the memory; wherein the test machine is configured to send a control signal, and the test module is configured to receive the control signal and switch states according to the control signal, wherein the states include an idle state and a working state; when the test module is in the working state, the test machine transmits first data to the memory or reads second data from the memory through at least one data pin of the chip to be tested, until the test module switches the state to the idle state according to the control signal; the control signal includes a maximum address signal, and when the test module switches from the idle state to the working state, the count value in the test module starts to accumulate, and when the count value accumulates to the maximum address signal, the test module switches from the working state to the idle state.

[0006] Optionally, the working state includes a first working state and a second working state; when the test module is in the first working state, the test machine transmits first data to the memory through at least one data pin of the chip to be tested; when the test module is in the second working state, the test machine reads second data from the memory through at least one data pin of the chip to be tested.

[0007] Optionally, the control signal also includes an enable signal, a status signal, a start signal and a clock signal. The start signal is input into the test module through the start pin of the chip to be tested, and the clock signal is input into the test module through the clock pin of the chip to be tested. When in an idle state, the test module switches the state to a first working state or a second working state according to the enable signal, the status signal and the start signal. When in a working state, the test module switches the state to an idle state according to the clock signal and the maximum address signal.

[0008] Optionally, when in an idle state and the conversion signals of the enable signal, the status signal and the start signal are all high levels, the state of the test module is switched to a first working state; wherein, when the start signal jumps from a low level to a high level, the conversion signal of the start signal appears as a pulse signal.

[0009] Optionally, when in an idle state, the state signal is at a low level and the conversion signals of the enable signal and the start signal are both at a high level, the state of the test module is switched to a second working state; wherein, when the start signal jumps from a low level to a high level, the conversion signal of the start signal appears as a pulse signal.

[0010] Optionally, the test module includes a first rising edge detection unit and a second rising edge detection unit; the input end of the first rising edge detection unit is connected to the start pin of the chip to be tested, and is configured to receive a start signal and process the start signal into a conversion signal of the start signal; the input end of the second rising edge detection unit is connected to the clock pin of the chip to be tested, and is configured to receive a clock signal and process the clock signal into a conversion signal of the clock signal.

[0011] Optionally, when in the working state, the conversion signal of the clock signal is at a high level and the count value is accumulated to the maximum address signal, the state of the test module is switched to an idle state.

[0012] Optionally, when in the second working state, the tester reads a valid signal output by a valid signal pin of the chip under test; when the valid signal is at a high level, the tester reads second data from the memory through at least one data pin of the chip under test.

[0013] Optionally, the test module includes several selection units; the several selection units are arranged between the test module and the memory and between the test module and the pins of the chip to be tested, and are configured to receive a control signal and adjust the mode of the chip to be tested according to the level state of the control signal; wherein the mode of the chip to be tested includes a test mode and a non-test mode.

[0014] Optionally, the chip to be tested is a mixed analog-digital chip, and the memory is a data acquisition memory; the test module includes a finite state machine, and the finite state machine is configured to set the state of the test module according to a control signal; the access port of the memory includes a chip select port, a status port, an address port, a first data port, and a second data port; when the test module is in a working state, the chip select port is configured to receive a high-level signal, and the address port is configured to receive a count value; when the test module is in a first working state, the status port is configured to receive a high-level signal, and the first data port is configured to receive and store first data; when the test module is in a second working state, the status port is configured to receive a low-level signal, and the second data port is configured to output second data to at least one data pin of the chip to be tested.

[0015] In summary, the test system disclosed in this application has at least the following beneficial effects:

[0016] (1) By setting the test module directly on the chip to be tested, the dependence on external test equipment can be reduced to a certain extent, thereby reducing the cost of chip testing;

[0017] (2) Compared with the prior art that uses a serial peripheral interface (SPI) to read and write data, the test system of the present application can transmit multiple data in parallel in each clock cycle according to the number of pins of the chip to be tested, thereby reducing the test time and increasing the test efficiency;

[0018] (3) The test system of the present application does not require any additional high-cost test equipment, such as automatic test equipment (ATE) high-speed boards, thereby reducing the test cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The following is a brief introduction to the drawings used in describing the embodiments of the present application:

[0020] Figure 1 It is a structural schematic diagram of an analog-to-digital conversion chip in the prior art.

[0021] Figure 2 It is a structural schematic diagram of a digital-to-analog conversion chip in the prior art.

[0022] Figure 3 It is a structural schematic diagram of a test system in the prior art.

[0023] Figure 4 It is a structural schematic diagram of another test system in the prior art.

[0024] Figure 5It is a structural schematic diagram of a test system provided in an embodiment of the present application.

[0025] Figure 6 This is a state switching schematic diagram provided in an embodiment of the present application.

[0026] Figure 7 It is a signal timing diagram of a working state provided by an embodiment of the present application.

[0027] Figure 8 This is a signal timing diagram of another working state provided by an embodiment of the present application. DETAILED DESCRIPTION

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the specific implementation methods of the present application will be described below with reference to the accompanying drawings. The accompanying drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other accompanying drawings and other implementation methods can be obtained based on these drawings without creative work. Adjustments and improvements made without departing from the concept of the present application are all within the scope of protection of the present application.

[0029] In order to simplify the drawings, only the parts related to the corresponding embodiments are schematically shown in each figure, and they do not represent the actual structure of the product. In addition, in order to simplify the drawings and facilitate understanding, only part of the components with the same structure or function in some figures are schematically drawn, and there may be more or fewer components with the same structure or function in reality.

[0030] In this application, unless otherwise clearly specified and limited, ordinal numbers, such as "first", "second", etc., are only used to distinguish and describe associated objects, and cannot be understood as indicating or implying the relative importance or order between associated objects; in addition, they do not represent the number of associated objects. "Multiple" includes two or more, and other quantifiers are similar. " / " is used to describe the relationship between associated objects, which indicates the "or" relationship between associated objects. "And / or" is used to describe the relationship between associated objects, which includes any combination relationship between associated objects, such as "a and / or b" includes: "alone a", "alone b", or "a and b". "One or more" or "at least one" in multiple objects refers to any object or any combination of multiple objects, such as "one or more of a1, a2, a3" or "at least one of a1, a2, a3" includes: "alone a1", "alone a2", "alone a3", "a1 and a2", "a1 and a3", "a2 and a3", or "a1, a2 and a3".

[0031] Testing of chips is a crucial part of the chip development and manufacturing process. Through comprehensive testing, engineers can effectively discover defects in the chip manufacturing process and take timely measures to repair and optimize them. This test not only helps to identify defects in manufacturing, but also deeply analyzes and improves potential problems in the design, thereby improving the quality and performance of the chip in the final product so that it can meet the preset strict standards. The physical objects of the test include but are not limited to various aspects of the chip, which may cover key parts such as the chip's pins, functional modules, interfaces, and memory. Through the testing of these objects, engineers can comprehensively evaluate the performance of the chip under different working conditions. For example, the chip's pin test can ensure the reliability of signal transmission and connection of all input and output ports; the functional module test is used to verify the correctness and stability of each functional unit inside the chip; the interface test focuses on compatibility with external devices and the integrity of data transmission. Among them, the test of memory is indispensable. As a key component in the chip, the quality and performance of the memory plays a decisive role in the function of the entire chip. Memory testing is mainly used to verify the accuracy of the memory's read and write functions, so that it can reliably store and read data under various operating environments. Through these tests, engineers can detect possible read and write errors, data corruption and other problems, and optimize the design and manufacturing process of the memory. In addition, memory testing can also help evaluate its performance under different temperature and power consumption conditions, so that the memory can operate stably in various complex environments.

[0032] The chip under test can be an analog-to-digital conversion chip, a digital-to-analog conversion chip, or a digital-to-analog hybrid chip that has both analog-to-digital conversion and digital-to-analog conversion functions. In the above chips under test, the memory located on the chip can be a data acquisition memory (abbreviated as data acquisition memory). Please refer to Figure 1 , which shows a schematic diagram of the structure of an analog-to-digital conversion chip in the prior art. Figure 1 As shown, the analog-to-digital conversion chip 10 includes an analog-to-digital converter 110, a digital signal processing circuit 120, and a serial deserializer transmitter 130. After the first analog signal A1 enters the analog-to-digital conversion chip 10, it is converted into a first digital signal D1 by the analog-to-digital converter 110. The first digital signal D1 is input into the digital signal processing circuit 120 and processed into a second digital signal D2. The second digital signal D2 is output to the target chip through the serial deserializer transmitter 130 through a high-speed interface. In order to enable the analog-to-digital conversion chip 10 to support the debugging function, a data acquisition memory 140 can be added to the chip to store the original digital signal (i.e., the first digital signal D1) or the processed digital signal (i.e., the second digital signal D2). The host computer can read the data in the data acquisition memory 140 through an interface such as SPI for analysis and debugging. Please refer to Figure 2 , which shows a schematic diagram of the structure of a digital-to-analog conversion chip in the prior art. Figure 2 As shown, the digital-to-analog conversion chip 20 includes a serial deserializer receiving end 210, a digital signal processing circuit 220 and a digital-to-analog converter 230. The serial deserializer receiving end 210 of the digital-to-analog conversion chip 20 receives data (i.e., the third digital signal D3) from the high-speed interface, and after being processed into the fourth digital signal D4 by the digital signal processing circuit 220, it is output to the digital-to-analog converter 230 and converted into the second analog signal A2 and output to the next level circuit. In order to enable the digital-to-analog conversion chip 20 to support the debugging function, a data acquisition memory 240 can be added to the digital-to-analog conversion chip 20. The user writes the test data (i.e., the fifth digital signal D5) into the data acquisition memory 240 through the SPI interface, and the digital-to-analog converter 230 can read the data conversion output from the data acquisition memory 240, and then observe whether the output signal meets expectations.

[0033] When the chip under test is a mixed-signal chip, a complete test system can be used to test the chip under test. Figure 3 , which shows a schematic diagram of the structure of a test system in the prior art. Figure 3 As shown, the digital-analog hybrid chip includes both the analog-to-digital conversion chip 10 and the digital-to-analog conversion chip 20 involved in the above prior art. Their internal structures can refer to the above content and will not be repeated here. The test system is a test machine including a radio frequency signal board (i.e., the RF board in the figure) and a digital board. The test machine accesses the SPI interface of the chip to be tested through the digital board. When testing the analog-to-digital conversion logic (i.e., the analog-to-digital conversion chip 10 in the figure), the radio frequency signal board of the test machine sends the analog signal to be tested, which is collected by the analog-to-digital conversion logic and written into the data acquisition memory 140. The test machine sends an SPI read command to read the collected data from the data acquisition memory 140, and then processes the data through fast Fourier transformation (FFT) to determine whether the performance of the analog-to-digital conversion chip 10 meets the standard. When testing the digital-to-analog conversion logic (i.e., the digital-to-analog conversion chip 20 in the figure), the test machine writes the test data into the data acquisition memory 240 by sending an SPI write command, and the digital-to-analog conversion logic reads the data from the data acquisition memory 240 and converts it into an analog signal. Finally, the RF signal board of the test machine captures and analyzes the data to determine whether the performance of the digital-to-analog conversion chip 20 meets the standard. In this prior art solution, since the speed of SPI is generally only 20MHz, each clock only accesses 1 bit of data in the data acquisition memory, resulting in a very long test time, which increases the test cost of the chip.

[0034] Please refer to Figure 4 , which shows a schematic diagram of the structure of another test system in the prior art. Figure 4As shown, the digital-analog hybrid chip includes both the analog-to-digital conversion chip 10 and the digital-to-analog conversion chip 20 involved in the above prior art. Their internal structures can refer to the above content and will not be repeated here. The test system is a test machine including a radio frequency signal board (i.e., the RF board in the figure) and a high-speed interface board. The test machine accesses the data in the chip through the high-speed interface board. When testing the analog-to-digital conversion chip 10, the radio frequency signal board of the test machine sends the analog signal to be tested, which is collected by the analog-to-digital conversion chip 10 and sent to the interface of the serial deserializer transmitting end 130. The test machine receives the data through the serial deserializer receiving end of the high-speed interface board, and then processes the data through fast Fourier transform and determines whether the performance of the analog-to-digital conversion chip 10 meets the standard. When testing the digital-to-analog conversion chip 20, the test machine sends test data to the digital-to-analog conversion chip 20 through the interface of the serial deserializer transmitting end of the high-speed interface board. The digital-to-analog conversion chip 20 reads the data from the data acquisition memory 240 and converts it into an analog signal. Finally, the RF signal board of the test machine captures and analyzes it to determine whether the performance of the digital-to-analog conversion chip 20 meets the standard. The test machine needs to add a high-speed interface board, which will increase the test cost exponentially. In this case, the analog part of the chip and the SERDES are tested at the same time, and it is difficult to locate the specific cause when a problem occurs. In this prior art solution, the test machine adds an additional high-speed interface board, thereby increasing the test cost exponentially. In this case, the analog part of the digital-to-analog hybrid chip and the serial deserializer are tested at the same time, and it is difficult to locate the specific cause when a problem occurs.

[0035] From the above, it can be seen that the test of the memory part of the chip under test in the prior art has the defects of slow test speed or high test equipment cost, which leads to uncontrollable time cost or economic cost of testing the chip under test, making the test efficiency of the chip under test low. Therefore, how to improve the test efficiency of the chip under test is an urgent problem to be solved.

[0036] Please refer to Figure 5 , which shows a schematic diagram of the structure of a test system provided by an embodiment of the present application. Figure 5As shown, the test system is used for a chip to be tested, the chip to be tested includes a memory, the test system includes a test machine and a test module, the test module is arranged on the chip to be tested and coupled to the access port of the memory; wherein the test machine is configured to send a control signal, the test module is configured to receive the control signal, and switch states according to the control signal, the states including an idle state and a working state; when the test module is in the working state, the test machine transmits the first data to the memory or reads the second data from the memory through at least one data pin of the chip to be tested, until the test module switches the state to the idle state according to the control signal; the control signal includes a maximum address signal, when the test module switches from the idle state to the working state, the count value in the test module starts to accumulate, and when the count value accumulates to the maximum address signal, the test module switches from the working state to the idle state.

[0037] The test machine of the present application is not shown in the figure, and the test machine in the above prior art can be referred to, but the test machine of the present application does not add an additional high-speed interface board to reduce the cost. The test module includes the DFT logic module and the ate_mem_access module in the figure. The DFT logic module is a logic module of the testability design, and the ate_mem_access module is a module for the interaction between ATE and memory. By designing the ate_mem_access module and the DFT Logic module together on the chip, an integrated test module is formed. This test module can perform test tasks related to the memory of the chip under test inside the chip under test. The integrated test module can perform on-chip testing quickly and efficiently, greatly improving the test coverage and reducing the time and resources required for external testing; especially in mass production, this advantage is very obvious. Integrating the ate_mem_access module and the DFT Logic module on the chip under test to form an on-chip test module is an advanced and effective test strategy. This design not only improves the test efficiency and coverage of the chip under test, but also reduces the dependence on external devices. Since the test system disclosed in the present application is mainly used to test the memory of the chip under test, the test module can be coupled to the access port of the memory. The test machine sends a control signal, the test module receives the control signal, and switches the state (i.e., the state in the figure) according to the control signal, and the state includes an idle state and a working state. When the test module is in an idle state, the test system does not test the chip under test, and the chip under test can be used normally at this time; when the test module is in a working state, the test system tests the memory function of the chip under test. The control signal sent by the test machine can be sent to the DFT logic module first, and then sent to the ate_mem_access module by the DFT logic module; the control signal can also be directly sent to some pins of the chip under test, and the control signal is sent to the ate_mem_access module through these pins. In this way, by multiplexing some pins in the chip under test, the structure is clear and simple, and the test cost is reduced. The pins of the chip under test include data pins and other control pins; the data pin is the PAD (pin) corresponding to ATE_DATA in the figure, and the number of data pins is DW, and DW is the data width. When the test module is in working state, the test machine transmits the first data to the memory or reads the second data from the memory through at least one data pin of the chip under test until the state of the test module is switched from the working state to the idle state. The first data is ate_wdata[DW-1:0] in the figure, and the second data is ate_rdata[DW-1:0] in the figure. The first data can be the same as or different from the second data.For example, the memory is empty in the initial state, and the tester transmits the first data to the memory. If the write function of the memory is normal, the first data is stored in the memory at this time; if the read function of the memory is also normal, when the tester reads data from the memory, the second data read is the same as the first data in content. If the write function or read function of the memory is abnormal, the content of the first data and the second data are different. When the test module switches from the idle state to the working state, the count value of the register in the test module begins to accumulate through the accumulator until the count value is equal to the value of the maximum address signal in the control signal, which means that a test (read test or write test) is completed, and the test module switches its state from the working state to the idle state. The maximum address signal is max_addr[AW-1:0] in the figure, and AW is the address width. Exemplarily, the initial value of the count value is 0.

[0038] The test system disclosed in the present application can reduce the dependence on external test equipment to a certain extent by directly setting the test module on the chip to be tested, thereby reducing the cost of chip testing; compared with the SPI interface in the prior art for reading and writing data, the test system of the present application can transmit multiple data in parallel in each clock cycle according to the number of pins of the chip to be tested, thereby reducing the test time and increasing the test efficiency; moreover, the test system of the present application does not add additional high-cost test equipment, thereby reducing the test cost.

[0039] In some embodiments of the present application, the working state includes a first working state and a second working state; when the test module is in the first working state, the test machine transmits first data to the memory through at least one data pin of the chip to be tested; when the test module is in the second working state, the test machine reads second data from the memory through at least one data pin of the chip to be tested.

[0040] Please continue to refer to Figure 5 , the first working state (i.e. WRITE in the figure) is the "write" state. When the test module is in the first working state, the test machine transmits the first data to the memory through at least one data pin of the chip under test; the second working state (i.e. READ in the figure) is the "read" state. When the test module is in the second working state, the test machine reads the second data from the memory through at least one data pin of the chip under test. The state of the test module can be switched between the idle state, the first working state and the second working state.

[0041] Optionally, the first working state cannot be directly switched to the second working state. After the write test corresponding to the first working state is completed, the test module first switches to the idle state, and then switches from the idle state to the second working state, or switches to the first working state again. The setting of the idle state plays a buffering role, which allows the test module to be idle for a certain period of time after each test, avoiding errors caused by frequent mode switching of the test module.

[0042] Please continue to refer to Figure 5 In some embodiments of the present application, the chip to be tested is a mixed analog-digital chip, and the memory is a data acquisition memory; the test module includes a finite state machine, and the finite state machine is configured to set the state of the test module according to a control signal; the access port of the memory includes a chip select port, a status port, an address port, a first data port, and a second data port; when the test module is in a working state, the chip select port is configured to receive a high-level signal, and the address port is configured to receive a count value; when the test module is in a first working state, the status port is configured to receive a high-level signal, and the first data port is configured to receive and store first data; when the test module is in a second working state, the status port is configured to receive a low-level signal, and the second data port is configured to output second data to at least one data pin of the chip to be tested.

[0043] In fact, the chip to be tested targeted by the test system of the present application is not limited to the analog-to-digital conversion chip, digital-to-analog conversion chip or digital-to-analog hybrid chip mentioned in the above content, and any chip to be tested that includes a memory can be tested using the test system disclosed in the present application. In the embodiments of the following text application, the chip to be tested is a digital-to-analog hybrid chip as an example for explanation. If the chip to be tested is a separate analog-to-digital conversion chip or a digital-to-analog conversion chip, some of its functions can be discarded according to requirements.

[0044] In the mixed-analog chip, the type of memory is a data acquisition memory, and the test module includes a finite state machine (FSM), that is, the FSM module in the figure; the finite state machine sets the state of the test module according to the control signal. The access port of the memory includes a chip select port (cs in the figure), a state port (we in the figure), an address port (addr[AW-1:0] in the figure), a first data port (wdata[DW-1:0] in the figure), and a second data port (rdata[DW-1:0] in the figure). The first data port is used to receive the first data from the outside, and the first data is written into the memory through the first data port; when the second data of the memory is read externally, the second data is output through the second data port. In layman's terms, the first data port and the second data port serve as the "write" port and the "read" port of the memory, respectively. When the test module is in the working state, the chip select port receives the signal from the test module, that is, men_cs in the figure, and the level state of men_cs can be determined by the judgment module composed of the comparator and register in the test module. The working principle of the judgment module is to compare whether the current state of the test module (i.e., state in the figure) is the first working state (i.e., WRITE in the figure) or the second working state (i.e., READ in the figure): if state is equal to WRITE or state is equal to READ, mem_cs is high level, otherwise it is low level. Through the mem_cs signal, the test module can let the memory know whether the test is currently being performed. Similarly, the signal mem_we received by the state port of the memory is determined according to whether the current state of the test module is the first working state. When the test module is in the first working state, the state port is configured to receive a high level signal; when the test module is in the second working state, the state port is configured to receive a low level signal.

[0045] The address port is configured to receive a count value (i.e., mem_addr[AW-1:0] in the figure). The count value is not only used to determine whether the state of the test module is switched, but also used to indicate which unit in the memory the current operation (read or write) is performed on. For example, in the first clock cycle, the count value is 0, which indicates the unit with address 0 in the memory, the first data port of the memory receives the first data, and stores the first data in the unit with address 0 in the memory. In the second clock cycle, the count value is 1, which indicates the unit with address 1 in the memory, the first data port of the memory receives the first data, and stores the first data in the unit with address 1 in the memory, and so on, until the count value is equal to the maximum address signal in the control signal. For example, in the first clock cycle, the count value is 0, which indicates the unit with address 0 in the memory. The second data port of the memory outputs the second data corresponding to the unit with address 0 in the memory to at least one data pin of the chip to be tested. In the second clock cycle, the count value is 1, and the second data port of the memory outputs the second data corresponding to the unit with address 1 in the memory to at least one data pin of the chip to be tested, and so on, until the count value is equal to the maximum address signal in the control signal.

[0046] In this way, by designing corresponding processing logic for each access port of the memory, the test module can flexibly test the function of the memory according to the current state.

[0047] Please continue to refer to Figure 5 In some embodiments of the present application, the control signal also includes an enable signal, a status signal, a start signal and a clock signal. The start signal is input into the test module through the start pin of the chip to be tested, and the clock signal is input into the test module through the clock pin of the chip to be tested; when in an idle state, the test module switches the state to the first working state or the second working state according to the enable signal, the status signal and the start signal; when in a working state, the test module switches the state to an idle state according to the clock signal and the maximum address signal.

[0048] The enable signal is the enable in the figure, the status signal is the write in the figure, the start signal is the ate_start in the figure, the clock signal is the ate_clock in the figure, the start pin of the chip under test is the ATE_START in the figure, and the clock pin of the chip under test is the ATE_CLOCK in the figure. The conversion signal of the start signal is the start in the figure, and the conversion signal of the clock signal is the clock_valid in the figure. The enable signal, the status signal, and the maximum address signal are derived from the DFT logic module, that is, the tester controls the ate_mem-access module by controlling the DFT logic module; the clock signal and the start signal are directly derived from the tester, that is, the tester sends the clock signal and the start signal to the corresponding pins of the chip under test.

[0049] Please refer to Figure 6 , which shows a schematic diagram of state switching provided by an embodiment of the present application. Figure 6 As shown, the state of the test module can be switched between an idle state, a first working state and a second working state. When in an idle state, the test module determines whether the state to be switched is the first working state or the second working state according to the level states of the above enable signal, the conversion signal of the start signal and the state signal. When in an idle state, and the conversion signals of the enable signal, the state signal and the start signal are all high, the state of the test module is switched to the first working state; when in an idle state, the state signal is low and the conversion signals of the enable signal and the start signal are both high, the state of the test module is switched to the second working state. When in a working state, the conversion signal of the clock signal is high and the count value is accumulated to the maximum address signal, the state of the test module is switched to an idle state.

[0050] Among them, the start signal is processed into a conversion signal of the start signal by the first rising edge detection unit in the test module: when the start signal jumps from a low level to a high level, the conversion signal of the start signal is expressed as a pulse signal. That is to say, when the first rising edge detection unit detects a rising edge in the start signal, the level of the conversion signal of the start signal will be pulled up. Similarly, the clock signal is processed into a conversion signal of the clock signal by the second rising edge detection unit in the test module: when the clock signal jumps from a low level to a high level, the conversion signal of the clock signal is expressed as a pulse signal. That is to say, when the second rising edge detection unit detects a rising edge in the clock signal, the level of the conversion signal of the clock signal will be pulled up. In terms of connection mode, the input end of the first rising edge detection unit is connected to the start pin of the chip to be tested, is configured to receive the start signal, and processes the start signal into a conversion signal of the start signal, and the output end of the first rising edge detection unit is connected to a finite state machine; the input end of the second rising edge detection unit is connected to the clock pin of the chip to be tested, is configured to receive the clock signal, and processes the clock signal into a conversion signal of the clock signal, and the output end of the second rising edge detection unit is connected to a finite state machine. Since the clock of the signal output by the tester is asynchronous with the clock clk_mem used to access the memory inside the chip under test, and the memory access clock is much higher than the tester signal clock, a rising edge detector is added to the ate_start and ate_clock signals to synchronize the tester signal to the start and clock_valid of the clk_mem clock domain. In this way, the internal and external clocks can be synchronized. The first rising edge detection unit and the second rising edge detection unit are represented as posedge_detector in the figure.

[0051] Please continue to refer to Figure 5 In some embodiments of the present application, when in the second working state, the tester reads the valid signal output by the valid signal pin of the chip under test; when the valid signal is at a high level, the tester reads the second data from the memory through at least one data pin of the chip under test.

[0052] The valid signal pin of the chip under test is ATE_VALID in the figure, and the valid signal is ate_valid in the figure. ate_valid is used to indicate when ate_rdata is valid, so that the tester can determine the timing of reading ate_rdata data.

[0053] Please refer to Figure 7 , which shows a signal timing diagram of a working state provided by an embodiment of the present application. The names of each signal are marked in Figure 7 On the left, each name can be Figure 5 The names in correspondence. Figure 7As shown, the corresponding working state is the first working state, that is, testing the "write" function of the memory.

[0054] In a complete write operation, the DFT logic module pulls up the enable and write signals, and sets max_addr to a preset value. The tester gives ATE_CLOCK a clock signal of appropriate frequency (which can be a lower frequency, such as 10MHz~50MHz), then pulls up the ATE_START signal, and gives ATE_DATA the value expected to be written on the falling edge of ATE_CLOCK. The ate_mem_access module will enter the WRITE state and write the data to the data acquisition memory in sequence. Among them, the tester puts the data to be written to the memory on the ATE_DATA pin of the chip under test in sequence, and places DW bits of data for each ATE_CLOCK clock.

[0055] Please refer to Figure 8 , which shows a signal timing diagram of another working state provided by an embodiment of the present application. The names of the various signals are marked in Figure 8 On the left, each name can be Figure 5 The names in correspondence. Figure 8 As shown, the corresponding working state is the second working state, that is, testing the "read" function of the memory.

[0056] In a complete read operation, the DFT logic module pulls the enable signal high, pulls the write signal low, and sets max_addr to a preset value. The tester gives ATE_CLOCK a clock signal of appropriate frequency (can be a lower frequency such as 10MHz~50MHz), and then pulls the ATE_START signal high. The ate_mem_access module will enter the READ state, read the data from the acquisition memory and output it to ATE_DATA, and pull ATE_VALID high to indicate the validity of the data. ATE collects the data of ATE_DATA when ATE_CLOCK rises and ATE_VALID is 1.

[0057] Please continue to refer to Figure 5 In some embodiments of the present application, the test module includes a plurality of selection units; the plurality of selection units are arranged between the test module and the memory and between the test module and the pins of the chip to be tested, and are configured to receive a control signal and adjust the mode of the chip to be tested according to the level state of the control signal; wherein the mode of the chip to be tested includes a test mode and a non-test mode.

[0058] Exemplarily, the selection unit may be Figure 5The multiplexer (MUX) shown in the figure, when the enable signal enable in the control signal is at a high level, the chip under test is set to the test mode, so that the access port of the memory and the pins of some of the chips under test receive signals or data from the test module. When the enable signal enable in the control signal is at a low level, the chip under test is set to the non-test mode, at which time the access port of the memory and the pins of some of the chips under test receive regular functional signals or data, such as func_cs, func_we, func_addr, func_wdata and from function logic in the figure.

[0059] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments. In addition, the above embodiments can be freely combined as needed.

Claims

1. A testing system, characterized in that: For a chip to be tested, the chip to be tested includes a memory, the test system includes a test machine and a test module, the test module is arranged on the chip to be tested and coupled to an access port of the memory; wherein, The test machine is configured to send a control signal, and the test module is configured to receive the control signal and switch states according to the control signal, wherein the states include an idle state and a working state; When the test module is in the working state, the test machine transmits first data to the memory or reads second data from the memory through at least one data pin of the chip to be tested, until the test module switches the state to the idle state according to the control signal; The control signal includes a maximum address signal, and when the test module switches from the idle state to the working state, the count value in the test module starts to accumulate, and when the count value accumulates to the maximum address signal, the test module switches from the working state to the idle state; The control signal also includes an enable signal, a status signal, a start signal and a clock signal, wherein the start signal is input into the test module through the start pin of the chip under test, and the clock signal is input into the test module through the clock pin of the chip under test; The test module includes a first rising edge detection unit and a second rising edge detection unit; The input end of the first rising edge detection unit is connected to the start pin of the chip to be tested, and is configured to receive the start signal and process the start signal into a conversion signal of the start signal; The input end of the second rising edge detection unit is connected to the clock pin of the chip to be tested, and is configured to receive the clock signal and process the clock signal into a conversion signal of the clock signal; Wherein, the test module realizes the switching of the state according to the control signal.

2. The test system according to claim 1, characterized in that: The working state includes a first working state and a second working state; When the test module is in the first working state, the test machine transmits the first data to the memory through at least one data pin of the chip to be tested; When the test module is in the second working state, the test machine reads the second data from the memory through at least one data pin of the chip under test.

3. The test system according to claim 2, characterized in that: When in the idle state, the test module switches the state to the first working state or the second working state according to the enable signal, the state signal and the start signal; When in the working state, the test module switches the state to the idle state according to the clock signal and the maximum address signal.

4. The test system according to claim 3, characterized in that: When in the idle state, and the conversion signals of the enable signal, the state signal, and the start signal are all at high levels, the state of the test module is switched to the first working state; When the start signal changes from a low level to a high level, the conversion signal of the start signal is expressed as a pulse signal.

5. The test system according to claim 3, characterized in that: When in the idle state, the state signal is at a low level and the conversion signals of the enable signal and the start signal are both at high levels, the state of the test module is switched to the second working state; When the start signal changes from a low level to a high level, the conversion signal of the start signal is expressed as a pulse signal.

6. The test system according to claim 1, characterized in that: When in the working state, the conversion signal of the clock signal is at a high level and the count value is accumulated to the maximum address signal, the state of the test module is switched to the idle state.

7. The test system according to claim 2, characterized in that: When in the second working state, the tester reads the valid signal output by the valid signal pin of the chip to be tested; When the valid signal is at a high level, the tester reads the second data from the memory through at least one data pin of the chip under test.

8. The test system according to claim 1, characterized in that: The test module includes a plurality of selection units; The plurality of selection units are arranged between the test module and the memory and between the test module and the pins of the chip to be tested, and are configured to receive the control signal and adjust the mode of the chip to be tested according to the level state of the control signal; The modes of the chip to be tested include a test mode and a non-test mode.

9. The test system according to claim 2, characterized in that: The chip to be tested is a digital-analog hybrid chip, and the memory is a data acquisition memory; The test module comprises a finite state machine configured to set a state of the test module according to the control signal; The access port of the memory includes a chip selection port, a status port, an address port, a first data port and a second data port; When the test module is in the working state, the chip select port is configured to receive a high level signal, and the address port is configured to receive the count value; When the test module is in the first working state, the state port is configured to receive a high level signal, and the first data port is configured to receive and store the first data; When the test module is in the second working state, the state port is configured to receive a low level signal, and the second data port is configured to output the second data to at least one data pin of the chip under test.

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