Display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device. The display panel comprises a substrate, a plurality of pixel circuits and a plurality of sub-pixels located on one side of the substrate, the sub-pixels are connected with the pixel circuits, the pixel circuits comprise a driving transistor; the sub-pixels comprise a first sub-pixel and a second sub-pixel, the pixel circuits comprise a first pixel circuit, the first sub-pixel is connected with the first pixel circuit; the minimum distance between the orthographic projection of the first sub-pixel on the substrate and the orthographic projection of the driving transistor in the first pixel circuit on the substrate is greater than the minimum distance between the orthographic projection of the second sub-pixel on the substrate and the orthographic projection of the driving transistor in the first pixel circuit on the substrate. The present application can improve the white picture color deviation problem and improve the display effect.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] LEDs (light-emitting diodes) efficiently convert electrical energy into light energy, featuring small size, long lifespan, high efficiency, energy saving, and rich colors. With continuous technological advancements, LEDs have been widely used in fields such as photography, flat panel displays, and medical devices. In display applications, temperature affects the luminous efficiency of LEDs within sub-pixels, and the degree of temperature impact on LED efficiency varies across different color sub-pixels. This affects the display's color accuracy, leading to color distortion in white areas. Summary of the Invention

[0003] This invention provides a display panel and a display device to improve the problem of color deviation in white screens in the prior art.

[0004] In a first aspect, embodiments of the present invention provide a display panel, the display panel including a substrate, a plurality of pixel circuits located on one side of the substrate and a plurality of sub-pixels, the sub-pixels being connected to the pixel circuits, the pixel circuits including driving transistors; the sub-pixels including first sub-pixels and second sub-pixels, the pixel circuits including first pixel circuits, the first sub-pixels being connected to the first pixel circuits;

[0005] Wherein, the minimum distance between the orthographic projection of the first sub-pixel on the substrate and the orthographic projection of the driving transistor in the first pixel circuit on the substrate is greater than the minimum distance between the orthographic projection of the second sub-pixel on the substrate and the orthographic projection of the driving transistor in the first pixel circuit on the substrate.

[0006] Secondly, based on the same inventive concept, embodiments of the present invention also provide a display device, including the display panel provided in any embodiment of the present invention.

[0007] The display panel and display device provided in this embodiment of the invention have the following beneficial effects: In the display panel provided in this embodiment of the invention, compared with the second sub-pixel, the distance between the orthogonal projection of the first sub-pixel on the substrate and the orthogonal projection of the driving transistor in the first pixel circuit on the substrate is larger, that is, the first sub-pixel is set far away from the driving transistor in the first pixel circuit. When the luminous efficiency of the first sub-pixel is more affected by temperature than that of the second sub-pixel, the design of this embodiment of the invention can reduce the influence of heat emitted by the driving transistor in the first pixel circuit on the luminous efficiency of the first sub-pixel, thereby improving the color shift problem of white screen and enhancing the display effect. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 A schematic diagram of a display panel provided in an embodiment of the present invention;

[0010] Figure 2 for Figure 1 A partial schematic diagram of the central region at location Q1;

[0011] Figure 3 A schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0012] Figure 4 Another pixel circuit schematic diagram provided in an embodiment of the present invention;

[0013] Figure 5 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention;

[0014] Figure 6 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention;

[0015] Figure 7 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention;

[0016] Figure 8 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention;

[0017] Figure 9 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention;

[0018] Figure 10 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention;

[0019] Figure 11 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention;

[0020] Figure 12 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention;

[0021] Figure 13 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention;

[0022] Figure 14 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention;

[0023] Figure 15 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention;

[0024] Figure 16 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention;

[0025] Figure 17 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0028] It should be understood that although the terms "first" and "second" may be used to describe XX in the embodiments of the present invention, these XX should not be limited to these terms. These terms are only used to distinguish XX from each other. For example, without departing from the scope of the embodiments of the present invention, the first XX may also be referred to as the second XX, and similarly, the second XX may also be referred to as the first XX.

[0029] In related technologies, the simplest panel design involves distributing multiple LEDs on a substrate and placing pixel circuits below each LED. The driving transistors in the pixel circuits generate driving current, which drives the LEDs to emit light. The LEDs are located close to the driving transistors in their connected pixel circuits; for example, red LEDs are close to the driving transistors in red pixel circuits, green LEDs are close to the driving transistors in green pixel circuits, and the same applies to blue LEDs. This causes the LEDs to be affected by the heat generated by the driving transistors, leading to an increase in LED temperature and a decrease in luminous efficiency. Since the three colors of LEDs use different light-emitting materials, the degree to which their efficiency decreases due to temperature varies, thus affecting the display's color accuracy and causing color distortion in white areas.

[0030] To address the problems existing in related technologies, embodiments of the present invention provide a display panel that designs the relative position of the first sub-pixel, whose luminous efficiency is significantly affected by temperature, and the driving transistor. This aims to weaken the impact of heat emitted by the driving transistor on the luminous efficiency of the first sub-pixel, thereby improving the color shift problem in white screens and enhancing the display effect. Furthermore, considering that different colored sub-pixels have different driving current requirements, the heat generated by the driving transistors in the pixel circuits corresponding to different colored sub-pixels varies, resulting in different degrees of impact of the heat generated by the driving transistors in different pixel circuits on the luminous efficiency of the sub-pixels. For example, the luminous efficiency of red LEDs is significantly affected by temperature, while the luminous efficiency of blue and green LEDs is relatively less affected. In some embodiments, blue LEDs and / or green LEDs can be placed closer to the driving transistors corresponding to red LEDs, and red LEDs can be placed further away from their corresponding driving transistors. This makes the luminous efficiency of blue and / or green LEDs more susceptible to temperature influence, while reducing the influence of temperature on the luminous efficiency of red LEDs. This reduces the decrease in luminous efficiency of red LEDs and increases the decrease in luminous efficiency of blue and / or green LEDs, resulting in a more even distribution of luminous efficiency decrease due to temperature among red, blue, and green LEDs. The overall brightness of the display panel decreases somewhat, but the color shift is small, resulting in a good display effect. The above is an overview of the technical concept of this invention. Specific embodiments are described below to illustrate the technical solution of this invention.

[0031] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of the present invention. Figure 2 for Figure 1 A partial schematic diagram of the central region at location Q1. Figure 1 The illustration shows that the display panel includes multiple sub-pixels (sp), each sub-pixel (sp) comprising a first sub-pixel (sp1), a second sub-pixel (sp2), and a third sub-pixel (sp3) of different colors. For example, the first sub-pixel (sp1) is red, the second sub-pixel (sp2) is green, and the third sub-pixel (sp3) is blue. These three sub-pixels (sp1, sp2, and sp3) together form a single pixel, capable of displaying white. Each sub-pixel (sp) includes one LED, or two or more LEDs. The LEDs can be Micro-LEDs or Mini-LEDs. Figure 1 The diagram illustrates a sub-pixel sp that includes an LED.

[0032] Figure 2 This is a simplified schematic diagram of a portion of the display panel. Figure 2 The diagram illustrates the area in the display panel where the pixel circuitry is located. For example... Figure 2As shown, the display panel includes multiple pixel circuits 10, each including a first pixel circuit 11, a second pixel circuit 12, and a third pixel circuit 13. Specifically, the first sub-pixel sp1 is connected to the first pixel circuit 11, the second sub-pixel sp2 is connected to the second pixel circuit 12, and the third sub-pixel sp3 is connected to the third pixel circuit 13. Figure 2 The diagram is simplified and the connection lines between each sub-pixel sp and the pixel circuit 10 are not shown. Figure 2 The diagram illustrates the location of the driving transistor Tm in each pixel circuit 10. However, the location of the driving transistor Tm is merely illustrative and not intended to limit the scope of this invention. The driving transistor Tm is used to generate driving current. Figure 2 The illustration is only for comparison to illustrate the relationship between the distance and position of different sub-pixels sp and the driving transistor Tm. Figure 2 The diagram uses different patterns to illustrate pixel circuits that connect sub-pixels of different colors.

[0033] In this embodiment of the invention, the pixel circuit 10 has an aTbC structure, where T represents a transistor, C represents a capacitor, and a and b are both positive integers. That is, the pixel circuit 10 includes a transistors and b capacitors.

[0034] Figure 3 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention, illustrating a pixel circuit with a 7T1C structure. For example... Figure 3As shown, the pixel circuit includes a driving transistor Tm, a data writing transistor M1, a gate reset transistor M3, a threshold compensation transistor M4, an electrode reset transistor M7, a first light-emitting control transistor M5, a second light-emitting control transistor M6, and a storage capacitor Cst. The gates of the data writing transistor M1 and the threshold compensation transistor M4 are connected to the first scan signal S1, the gate of the gate reset transistor M3 is connected to the second scan signal S2, and the gates of the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are connected to the light-emitting control signal Emit. Additionally, the gate reset transistor M3 and the electrode reset transistor M7 are respectively connected to the reset signal Ref. The driving transistor Tm is connected in series between the first light-emitting control transistor M5 and the second light-emitting control transistor M6. One electrode of the first light-emitting control transistor M5 is connected to the first power supply voltage VDD, and one electrode of the light-emitting element LED is connected to the second light-emitting control transistor M6, while the other electrode is connected to the second power supply voltage VEE. The operation of the pixel circuit includes at least a reset stage, a writing stage, and a light-emitting stage. During the reset phase, gate reset transistor M3 is turned on under the control of the second scan signal S2 to write the reset signal Ref to the gate of the driving transistor Tm, and electrode reset transistor M7 is turned on under the control of the second scan signal S2 to write the reset signal Ref to the electrode of the light-emitting device LED. During the writing phase, data writing transistor M1 and threshold compensation transistor M4 are turned on under the control of the first scan signal S1 to write the data voltage Data to the gate of the driving transistor Tm and perform self-testing and compensation on the threshold voltage of the driving transistor Tm. During the light-emitting phase, the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are turned on under the control of the light-emitting control signal Emit, and the driving transistor Tm generates a driving current under the control of its gate voltage and provides the driving current to the light-emitting element LED.

[0035] Figure 4 Another pixel circuit schematic diagram provided in an embodiment of the present invention, such as... Figure 4 As shown, the pixel circuit includes a first driving circuit 01 and a second driving circuit 02. The first driving circuit 01 is configured to control the duration of providing driving current to the light-emitting element LED based on a first data voltage PWM-data, and the second driving circuit 02 is configured to control the amplitude of providing driving current to the light-emitting element LED based on a second data voltage PAM-data.

[0036] The first driving circuit 01 includes a first driving transistor M1, a first gate reset transistor M2, a first data write transistor M3, a first compensation transistor M4, a first control transistor M6, a second control transistor M5, and a first capacitor C1. The first capacitor C1 is the storage capacitor in the first driving circuit 01, and can also be referred to as the first storage capacitor in the pixel circuit. The second control transistor M5 is connected between the first power supply voltage PWM-Vdd and the first terminal of the second driving transistor M1. The first control transistor M6 is connected between the second terminal of the first driving transistor M1 and the first node N1. The first data write transistor M3 is connected to the first terminal of the first driving transistor M1. The first compensation transistor M4 is connected to the second terminal and the gate of the first driving transistor M1. The first gate reset transistor M2 is connected to the gate of the first driving transistor M1. The first plate of the first capacitor C1 is connected to the gate of the first driving transistor M1, and the second plate of the first capacitor C1 is connected to the sweep frequency signal SWEEP. The gate of the first gate reset transistor M2 is connected to the third scan signal PWM-S1, and the gates of the first data write transistor M3 and the first compensation transistor M4 are connected to the fourth scan signal PWM-S2. The gates of the first control transistor M6 and the second control transistor M5 are connected to the first light-emitting control signal PWM-EM.

[0037] The second driving circuit 02 includes a second driving transistor M7, a second gate reset transistor M8, a second data write transistor M9, a second compensation transistor M10, a third control transistor M11, a fourth control transistor M12, an electrode reset transistor M13, and a second capacitor C2. The second capacitor C2 is the second storage capacitor in the pixel circuit. The third control transistor M11 is connected between the second power supply voltage PAM-Vdd and the first electrode of the second driving transistor M7, and the fourth control transistor M12 is connected between the second electrode of the second driving transistor M7 and the light-emitting element LED. The second driving transistor M7 is configured to generate a driving current under the control of its gate voltage, and the gate of the second driving transistor M7 is connected to the first node N1. The second data write transistor M9 is connected to the first electrode of the second driving transistor M7, the second compensation transistor M10 is connected to the second electrode and the gate of the second driving transistor M7, the second gate reset transistor M8 is connected to the gate of the second driving transistor M7, the electrode reset transistor M13 is connected to the first electrode of the light-emitting element LED, the fourth control transistor M12 is also connected to the first electrode of the light-emitting element LED, and the second electrode of the light-emitting element LED is connected to the third power supply voltage VEE. Specifically, the gate of the second gate reset transistor M8 is connected to the first scan signal PAM-S1; the gates of the second data write transistor M9, the second compensation transistor M10, and the electrode reset transistor M13 are connected to the second scan signal PAM-S2. The gates of the third control transistor M11 and the fourth control transistor M12 are connected to the second light emission control signal PAM-EM.

[0038] Figure 4 The pixel circuit provided in the embodiment includes at least a writing stage and a light-emitting stage. The writing stage further includes a first writing stage and a second writing stage.

[0039] In the first writing phase, the second driving circuit 02 sequentially executes the gate reset phase and the data writing phase. In the gate reset phase, the first scan signal PAM-S1 controls the second gate reset transistor M8 to turn on, writing the second reset signal PAM-REF to the gate of the second driving transistor M7, thus resetting the gate of the second driving transistor M7. In the data writing phase, the second scan signal PAM-S2 controls the second data writing transistor M9 and the second compensation transistor M10 to turn on, writing the second data signal PAM-Data to the gate of the second driving transistor M7 and performing threshold compensation; during this phase, the electrode reset transistor M13 turns on to reset the electrodes of the light-emitting element LED.

[0040] In the second write phase, the first driving circuit 01 sequentially executes the gate reset phase and the data write phase. In the gate reset phase, the third scan signal PWM-S1 controls the first gate reset transistor M2 to turn on and writes the third reset signal PWM-REF to the gate of the second driving transistor M1, thus resetting the gate of the first driving transistor M1. In the data write phase, the fourth scan signal PWM-S2 controls the first data write transistor M3 and the first compensation transistor M4 to turn on, writing the first data signal PWM-Data to the gate of the first driving transistor M1 and performing threshold compensation.

[0041] During the light-emitting phase, the second light-emitting control signal PAM-EM controls the third control transistor M11 and the fourth control transistor M12 to turn on. The second driving transistor M7 generates a driving current under the control of its gate voltage, thus the second driving circuit 20 provides driving current to the light-emitting element LED. The first light-emitting control signal PWM-EM controls the first control transistor M6 and the second control transistor M5 to turn on. Simultaneously, the voltage value of the sweep frequency signal SWEEP gradually changes, and due to the coupling effect of the first capacitor C1, the gate voltage of the first driving transistor M1 changes. When the gate voltage of the first driving transistor M1 is equal to (or less than) the absolute value of its source voltage and threshold voltage, the first driving transistor M1 turns on. The first driving circuit 10 gradually raises the potential of the first node N1. Finally, the second driving transistor M1 turns on, supplying the first power supply voltage PWM-vdd to the first node N1 via the first control transistor M6. This causes a change in the gate voltage of the first driving transistor M7, causing the second driving transistor M7 to turn off, thereby stopping the supply of driving current to the light-emitting element LED. The period during which the second driving transistor M7 provides driving current to the light-emitting element LED during the light-emitting phase is the effective light-emitting period. In this embodiment, the second driving transistor M7 is a driving transistor capable of generating driving current. Figure 2 The driving transistor Tm is shown in the diagram.

[0042] The pixel circuit 10 in the display panel provided in this embodiment of the invention includes, but is not limited to, Figure 3 and Figure 4 The schematic structure illustrates this. It can be understood that the display panel includes a substrate, multiple pixel circuits 10, and multiple sub-pixels sp located on the same side of the substrate. A semiconductor layer, a metal layer, and an insulating layer are fabricated on the substrate. The active layer of the transistor and some wiring are fabricated using the semiconductor layer, and the gate, source, drain, and some wiring of the transistor are fabricated using the metal layer. The insulating layer is disposed between the semiconductor layer and the metal layer, and between adjacent metal layers. The pixel circuits 10 and other driving lines are fabricated using the semiconductor layer, metal layer, and insulating layer. Then, a light-emitting element is fixed as a sub-pixel sp on the side of the pixel circuit 10 away from the substrate.

[0043] Figure 2 This is a partial top view of the display panel. Since the top view direction is the same as the direction of the orthographic projection onto the substrate, it can be understood that in the top view, the first sub-pixel sp1 and its orthographic projection onto the substrate coincide, as does the first pixel circuit 11 and its orthographic projection onto the substrate, and so on for other structures. The parts in the following embodiments involving the orthographic projection of sub-pixels onto the substrate and the orthographic projection of pixel circuits onto the substrate can be understood with reference to this description.

[0044] Depend on Figure 2It can be seen that the minimum distance between the orthographic projection of the first sub-pixel sp1 onto the substrate and the minimum distance between the orthographic projection of the first sub-pixel sp2 onto the substrate and the minimum distance between the orthographic projection of the second sub-pixel sp2 onto the substrate and the minimum distance between the orthographic projection of the second sub-pixel sp2 onto the substrate and the minimum distance between the first sub-pixel sp1 and the minimum distance between the second sub-pixel sp2 and the minimum distance between the first sub-pixel sp1 and the minimum distance between the second sub-pixel sp2 and the minimum distance between the second sub-pixel sp1 ...

[0045] The driving transistor Tm comprises an active layer, a gate, a source, and a drain. In actual products, the driving transistor Tm has a larger area compared to other switching transistors in the pixel circuit. In the actual product structure, the overlapping region between the active layer and the gate of the driving transistor Tm forms a channel. The position and shape of the channel are relatively easy to determine. Therefore, the orthographic projection position of the driving transistor Tm can be located by the orthographic projection of the channel onto the substrate. When calculating the minimum distance between the orthographic projection of the sub-pixel onto the substrate and the orthographic projection of the driving transistor Tm onto the substrate, this minimum distance is used. Furthermore, the minimum distance between two structures is calculated as the minimum distance between the outer contours of the two structures.

[0046] In the display panel provided by this embodiment of the invention, the first sub-pixel sp1 is connected to the first pixel circuit 11. Compared to the second sub-pixel sp2, the distance between the orthogonal projection of the first sub-pixel sp1 onto the substrate and the orthogonal projection of the driving transistor Tm in the first pixel circuit 11 onto the substrate is greater. In other words, the first sub-pixel sp1 is positioned further away from the driving transistor Tm in the first pixel circuit 11. When the luminous efficiency of the first sub-pixel sp1 is more significantly affected by temperature compared to the second sub-pixel sp2, the design of this embodiment of the invention can reduce the impact of heat emitted by the driving transistor Tm in the first pixel circuit 11 on the luminous efficiency of the first sub-pixel sp1, thereby improving the color shift problem of white screens and enhancing the display effect.

[0047] In some implementations, the red sub-pixel requires a greater driving current than the blue and green sub-pixels, meaning the driving transistor in the pixel circuit connected to the red sub-pixel generates the most heat. Correspondingly, the green and blue sub-pixels require relatively smaller driving currents, resulting in relatively less heat generation in the driving transistors of their pixel circuits. Furthermore, the luminous efficiency of the red LED is significantly affected by temperature, while the luminous efficiency of the blue and green LEDs is less affected. Therefore, the first sub-pixel sp1 is configured to include a red sub-pixel, and the second sub-pixel sp2 is either a blue or green sub-pixel. The minimum distance between the orthographic projection of the red LED onto the substrate and the orthographic projection of the driving transistor in the red pixel circuit onto the substrate is set to be greater than the minimum distance between the orthographic projection of the blue / green LED onto the substrate and the orthographic projection of the driving transistor in the red pixel circuit onto the substrate. This reduces the degree of luminous efficiency degradation of the red LED, which is beneficial for improving color shift issues in white images and enhancing the display effect.

[0048] In some implementations... Figure 5 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention. Figure 5 This is a partial top view of the display panel. Figure 5 It can be seen that the minimum distance between the orthographic projection of the first sub-pixel sp1 on the substrate and the minimum distance between the orthographic projection of the driving transistor Tm in the first pixel circuit 11 and the orthographic projection of the second sub-pixel sp2 on the substrate and the minimum distance between ... driving transistor Tm in the second pixel circuit 12 and the orthographic projection of the second sub-pixel sp2 on the substrate. Figure 2 As can be seen from the embodiments, in the direction parallel to the plane where the substrate is located, the minimum distance between the first sub-pixel sp1 and the driving transistor Tm in the first pixel circuit 11 is greater than the minimum distance between the second sub-pixel sp2 and the driving transistor Tm in the second pixel circuit 12. In the display panel, the heat emitted by the driving transistor Tm in the first pixel circuit 11 affects the luminous efficiency of the first sub-pixel sp1, and the heat emitted by the driving transistor Tm in the second pixel circuit 12 also affects the luminous efficiency of the second sub-pixel sp2. In this embodiment, the distance between the first sub-pixel sp1 and the driving transistor Tm in the first pixel circuit 11 is set to be greater than the distance between the second sub-pixel sp2 and the driving transistor Tm in the second pixel circuit 12. Therefore, the luminous efficiency of the first sub-pixel sp1 is less affected by the heat of the driving transistor Tm in the first pixel circuit 11 than the luminous efficiency of the second sub-pixel sp2 is affected by the heat of the driving transistor Tm in the second pixel circuit 12. This balances the differences in luminous efficiency between different color sub-pixels, improves the color shift problem of white screen, and enhances the display effect.

[0049] Figure 5In this embodiment, for the second sub-pixel sp2, the distance between the second sub-pixel sp2 and the driving transistor Tm in the second pixel circuit 12 is less than its distance from the driving transistor Tm in the first pixel circuit 11. In other words, the second sub-pixel sp2 is closest to the driving transistor Tm of the pixel circuit 10 to which it is connected.

[0050] In some implementations, such as Figure 5 As shown, the minimum distance between the orthographic projection of the first sub-pixel sp1 on the substrate and the minimum distance between the orthographic projection of its nearest driving transistor Tm on the substrate is greater than the minimum distance between the orthographic projection of the second sub-pixel sp2 on the substrate and the minimum distance between the orthographic projection of its nearest driving transistor Tm on the substrate. In all three pixel circuits of the display panel, the driving transistor Tm generates heat during operation, which affects surrounding sub-pixels. In this embodiment, the driving transistor Tm closest to the first sub-pixel sp1 can belong to the first pixel circuit 11, the second pixel circuit 12, or the third pixel circuit 13. Similarly, the driving transistor Tm closest to the second sub-pixel sp2 can belong to the second pixel circuit 12, the first pixel circuit 11, or the third pixel circuit 13. This implementation ensures that the first sub-pixel sp1 is farther from the driving transistor Tm than the second sub-pixel sp2, thus reducing the impact of the heat generated by the driving transistor Tm on the luminous efficiency of the first sub-pixel sp1. This balances the differences in luminous efficiency between different color sub-pixels, improves the color shift problem in white images, and enhances the display effect.

[0051] like Figure 5 As shown, the minimum distance between the first sub-pixel sp1 and its projection onto the substrate, and the minimum distance between its projection onto the substrate and the projection onto the nearest driving transistor Tm, is greater than the minimum distance between the third sub-pixel sp3 and its projection onto the substrate and the projection onto the nearest driving transistor Tm. In other words, among the three color sub-pixels sp, the first sub-pixel sp1 has the smallest distance to the driving transistor Tm. Optionally, the first sub-pixel sp1 is a red sub-pixel, and one of the second sub-pixels sp2 and the third sub-pixel sp3 is a green sub-pixel and the other is a blue sub-pixel. The design of this embodiment reduces the impact of heat emitted by the driving transistor Tm on the luminous efficiency of the red sub-pixel, thereby balancing the differences in luminous efficiency among the red, green, and blue sub-pixels, improving the color shift problem in white images, and enhancing the display effect.

[0052] In other implementations, Figure 6 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention. Figure 6 This is a partial top view of the display panel. Figure 6It can be seen that the minimum distance between the orthogonal projection of the second sub-pixel sp2 on the substrate and the orthogonal projection of the driving transistor Tm in the first pixel circuit 11 on the substrate is smaller than the minimum distance between the second sub-pixel sp2 and the orthogonal projection of the driving transistor Tm in the second pixel circuit 12 on the substrate. In this embodiment, the first sub-pixel sp1 is set far away from the driving transistor Tm in the first pixel circuit 11, while the second sub-pixel sp2 is set close to the driving transistor Tm in the first pixel circuit 11. This reduces the impact of the heat emitted by the driving transistor Tm on the luminous efficiency of the first sub-pixel sp1, while appropriately increasing the impact of the heat emitted by the driving transistor Tm on the luminous efficiency of the second sub-pixel sp2. That is, it reduces the decrease in the luminous efficiency of the first sub-pixel sp1 and appropriately increases the decrease in the luminous efficiency of the second sub-pixel sp2, so as to balance the difference in luminous efficiency of different color sub-pixels, resulting in a smaller color shift of the display panel, which can improve the color deviation of the white screen and enhance the display effect.

[0053] In some embodiments, the display panel includes multiple circuit groups, each circuit group comprising N pixel circuits 10, where N is an integer and N≥2. The multiple circuit groups are arranged in an array within the display panel, and one electrode group is used to drive N sub-pixels within a single pixel. Figure 6 The example uses N=3 as an example, such as... Figure 6 As shown, three pixel circuits 10 form a circuit group 10Z. The spacing between two pixel circuits 10 within a circuit group 10Z is smaller than the spacing between adjacent circuit groups 10Z. At least one first sub-pixel sp1 is located within the area enclosed by four driving transistors Tm in four adjacent pixel circuits 10, which belong to four adjacent circuit groups 10Z. This arrangement allows the first sub-pixel sp1 to be located away from the driving transistors Tm in the first pixel circuit 10, and also ensures that the first sub-pixel sp1 is not too close to its surrounding driving transistors Tm. By designing the position of the first sub-pixel sp1, the influence of heat emitted by the driving transistors Tm on the luminous efficiency of the first sub-pixel sp1 can be reduced, thereby balancing the differences in luminous efficiency between different color sub-pixels, improving the color shift problem in white images, and enhancing the display effect.

[0054] Figure 6 Taking N=3 as an example, in other implementations, N=2, Figure 7 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention. Figure 7As shown, the display panel includes multiple pixels P, each pixel P including two sub-pixels. A portion of pixels P includes a first sub-pixel sp1 and a second sub-pixel sp2, and the remaining pixels P include a third sub-pixel sp3 and a second sub-pixel sp2. Optionally, the first sub-pixel sp1 is a red sub-pixel, the second sub-pixel sp2 is a green sub-pixel, and the third sub-pixel sp3 is a blue sub-pixel. The circuit group 10Z corresponds to the pixels P, and the circuit group 10Z includes two pixel circuits 10. Figure 7 The diagram shows that the first sub-pixel sp1 is far away from the driving transistor Tm in the first pixel circuit 10. At least one first sub-pixel sp1 is located in the area enclosed by the four driving transistors Tm in four adjacent pixel circuits 10, which belong to four adjacent circuit groups 10Z respectively. Figure 7 The display panel provided in the embodiment can be displayed using a subpixel rendering method.

[0055] In some implementations... Figure 8 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention, such as... Figure 8 As shown, in a circuit group 10Z, the three pixel circuits arranged from left to right are the first pixel circuit 11, the third pixel circuit 13, and the second pixel circuit 12. At least one first sub-pixel sp1 is located within the area enclosed by four driving transistors Tm in four adjacent pixel circuits 10, belonging to four adjacent circuit groups 10Z, and the four adjacent pixel circuits 10 include the first pixel circuit 11 and the second pixel circuit 12. The minimum distance between the orthographic projection of the first sub-pixel sp1 on the substrate and the orthographic projection of the driving transistor Tm in the first pixel circuit 11 on the substrate is d1, and the minimum distance between the orthographic projection of the first sub-pixel sp1 on the substrate and the orthographic projection of the driving transistor Tm in the second pixel circuit 12 on the substrate is d2, where d1 is greater than d2. That is, among the four driving transistors Tm surrounding the first sub-pixel sp1, the distance between the first sub-pixel sp1 and the driving transistor Tm in the first pixel circuit 11 is set to be relatively far. This configuration can balance the influence of the driving transistors Tm in the different pixel circuits around the first sub-pixel sp1 on its luminous efficiency, and minimize the influence of the heat emitted by the driving transistors Tm in the first pixel circuit 11 on the first sub-pixel sp1.

[0056] In this embodiment of the invention, the second pixel circuit 12 is connected to the second sub-pixel sp2, which can be either a blue sub-pixel or a green sub-pixel. Figure 8 The diagram illustrates three pixel circuits arranged from left to right in a circuit group 10Z: the first pixel circuit 11, the third pixel circuit 13, and the second pixel circuit 12. Of the four driving transistors Tm surrounding the first sub-pixel sp1, two belong to the first pixel circuit 11 and the other two belong to the second pixel circuit 12. Figure 6 The diagram illustrates three pixel circuits arranged from left to right in a circuit group 10Z: the first pixel circuit 11, the second pixel circuit 12, and the third pixel circuit 13. Of the four driving transistors Tm surrounding the first sub-pixel sp1, two belong to the first pixel circuit 11 and the other two belong to the third pixel circuit 13.

[0057] Figure 6 and Figure 8 The color of light emitted by the second sub-pixel sp2 and the third sub-pixel sp3 is not specifically defined, therefore Figure 6 Implementation examples can also be adopted Figure 8 The design of the embodiment is such that the four adjacent pixel circuits 10, which belong to four adjacent circuit groups 10Z respectively, include a first pixel circuit 11 and a third pixel circuit 13; the minimum distance between the orthogonal projection of the first sub-pixel sp1 on the substrate and the orthogonal projection of the driving transistor Tm in the first pixel circuit 11 on the substrate is greater than the minimum distance between the orthogonal projection of the first sub-pixel sp1 on the substrate and the orthogonal projection of the driving transistor Tm in the third pixel circuit 13 on the substrate.

[0058] In some embodiments, the display panel includes multiple pixels, each pixel including N sub-pixels sp of different colors, where N is an integer and N≥2; at least one pixel sp includes a first sub-pixel sp1 and a second sub-pixel sp2; the arrangement of the sub-pixels sp in at least one pixel is different from the arrangement of its corresponding N pixel circuits 10. Here, the arrangement refers to the different color order in which the N sub-pixels sp and the N pixel circuits 10 are arranged, and / or the N pixel circuits 10 are arranged at equal intervals while the N sub-pixels sp are arranged non-intervals. This embodiment designs the arrangement of the N sub-pixels sp within a pixel, setting the arrangement of the N sub-pixels sp to be different from the arrangement of its corresponding N pixel circuits 10, so as to move the first sub-pixel sp1 away from the driving transistor Tm in the first pixel circuit 11, reducing the impact of heat emitted by the driving transistor Tm in the first pixel circuit 11 on the luminous efficiency of the first sub-pixel sp1.

[0059] In some implementations, N = 3. Figure 9 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention, such as... Figure 9 As shown, a pixel P includes three sub-pixels sp, and a circuit group 10Z includes three pixel circuits 10. The three pixel circuits 10 corresponding to pixel P are arranged at equal intervals, and the distance from the first sub-pixel sp1 to its adjacent sub-pixel sp in pixel P is greater than the distance between the other two sub-pixels sp. In this embodiment, by increasing the distance between the first sub-pixel sp1 and other sub-pixels sp within a pixel P, the first sub-pixel sp1 is moved further away from the driving transistor Tm in the first pixel circuit 11.

[0060] Figure 9 The diagram illustrates that the first sub-pixel sp1, the second sub-pixel sp2, and the third sub-pixel sp3 located to its right form a pixel P. The three sub-pixels sp within pixel P are arranged in the same color order as the three pixel circuits 10 within circuit group 10Z. Figure 9 In the embodiment, the first sub-pixel sp1 and the second sub-pixel sp2 and the third sub-pixel sp3 located to its left can also be combined into a pixel P, which also increases the spacing between the first sub-pixel sp1 and other sub-pixels sp within pixel P.

[0061] In some implementations... Figure 10 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention, such as... Figure 10 As shown, the three pixel circuits 10 corresponding to pixel P are arranged along the first direction x; along the first direction x, the first sub-pixel sp1 and the other two sub-pixels sp in its pixel P are misaligned. In other words, in the second direction y, the first sub-pixel sp1 is offset relative to the second sub-pixel sp2 / third sub-pixel sp3, and the second direction y intersects with the first direction x. Figure 10 The diagram illustrates that the first sub-pixel sp1 is offset upwards along the second direction y relative to the second sub-pixel sp2 / third sub-pixel sp3. In other words, the second sub-pixel sp2 and the third sub-pixel sp3 are located in the same row, while the first sub-pixel sp1 is located in a separate row; that is, the first sub-pixel sp1 and the second sub-pixel sp2 / third sub-pixel sp3 are located in different rows. This arrangement increases the distance between the first sub-pixel sp1 and the driving transistor Tm in the first pixel circuit 11 to which it is connected, thereby reducing the impact of heat emitted by the driving transistor Tm in the first pixel circuit 11 on the luminous efficiency of the first sub-pixel sp1.

[0062] In some implementations, the color order of subpixels sp in at least one pixel P is different from the color order of its corresponding pixel circuit 10. Figure 11 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention. Figure 11 Taking N=3 as an example, such as Figure 11As shown, in pixel P, the three sub-pixels sp are arranged from left to right as second sub-pixel sp2, third sub-pixel sp3, and first sub-pixel sp1. In circuit group 10Z, the three pixel circuits 10 are arranged from left to right as first pixel circuit 11, second pixel circuit 12, and third pixel circuit 13. Taking first sub-pixel sp1 as a red sub-pixel, second sub-pixel sp2 as a green sub-pixel, and third sub-pixel sp3 as a blue sub-pixel as an example, the color arrangement order in pixel P is green, blue, and red, while the color arrangement order in circuit group 10Z is red, green, and blue. The color arrangement orders are different. In related technologies, a simple design is to have the color arrangement order of sub-pixels sp in pixel P be the same as the color arrangement order of their corresponding pixel circuits 10, thus facilitating the corresponding connection between sub-pixels sp and pixel circuits 10. The driving current required by the three color sub-pixels differs, resulting in different heat generation of the driving transistors in the pixel circuits corresponding to different color sub-pixels. For example, the first sub-pixel sp1 requires the largest driving current, and its corresponding pixel circuit generates the most heat. In this embodiment of the invention, by adjusting the arrangement order of sub-pixels sp within pixel P, the color arrangement order of sub-pixels sp in pixel P is different from the color arrangement order of its corresponding pixel circuit 10. This enables the first sub-pixel sp1 to be moved away from the driving transistor Tm in the first pixel circuit 11. Even if the first sub-pixel sp1 is close to the driving transistor Tm in other pixel circuits, the luminous efficiency of the first sub-pixel sp1 can be reduced from being affected by the heat emitted by the driving transistor Tm.

[0063] Figure 11 As illustrated, in pixel P, the three sub-pixels sp are arranged from left to right as second sub-pixel sp2, third sub-pixel sp3, and first sub-pixel sp1; and in circuit group 10Z, the three pixel circuits 10 are arranged from left to right as first pixel circuit 11, second pixel circuit 12, and third pixel circuit 13. In other embodiments, in pixel P, the three sub-pixels sp are arranged from left to right as second sub-pixel sp2, first sub-pixel sp1, and third sub-pixel sp3; and in circuit group 10Z, the three pixel circuits 10 are arranged from left to right as first pixel circuit 11, second pixel circuit 12, and third pixel circuit 13.

[0064] In some implementations, such as Figure 11As shown, N=3; the color-ordered arrangement of sub-pixels sp in pixel P differs from the color-ordered arrangement of their corresponding pixel circuits 10. Furthermore, the three sub-pixels sp in pixel P are arranged at equal intervals. This implementation essentially changes the arrangement of sub-pixels sp within pixel P, but essentially does not change the spacing between adjacent sub-pixels sp within pixel P. If the sub-pixels sp include LEDs, then a first electrode and a second electrode need to be fabricated on the display panel. The positive electrode of the LED is connected to the first electrode, and the negative electrode is connected to the second electrode. The pixel circuit is connected to the first electrode. By essentially not changing the spacing between adjacent sub-pixels sp within pixel P, the distribution regularity of the first and second electrodes in the display panel is stronger, making it easier to manufacture. Moreover, pixel P also has a better display effect.

[0065] In other implementations, N = 2. Figure 12 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention, such as... Figure 12 As shown, each pixel P includes two sub-pixels. The first pixel P1 includes a first sub-pixel sp1 and a second sub-pixel sp2, and the second pixel P2 includes a third sub-pixel sp3 and a second sub-pixel sp2. The circuit group 10Z includes two pixel circuits 10. Part of the circuit group 10 includes a first pixel circuit 11 and a second pixel circuit 12, and part of the circuit group 10 includes a third pixel circuit 13 and a second pixel circuit 12. The orthographic projection distance of the first sub-pixel sp1 onto the substrate is less than the minimum distance between the orthographic projection distance of the first sub-pixel sp1 onto the substrate and the minimum distance between the orthographic projection distance of the third sub-pixel sp3 ... In related technologies, to facilitate the connection between sub-pixels and pixel circuits, the first sub-pixel sp1 is typically positioned closer to the first pixel circuit 11, the second sub-pixel sp2 closer to the second pixel circuit 12, and the third sub-pixel sp3 closer to the third pixel circuit 13. However, in this embodiment of the invention, the first sub-pixel sp1 is positioned even closer to the third pixel circuit 13, and the third sub-pixel sp3 is positioned even closer to the first pixel circuit 11. This embodiment can move the first sub-pixel sp1 away from the driving transistor Tm in the first pixel circuit 11, and position the third sub-pixel sp3 closer to the driving transistor Tm in the first pixel circuit 11. This reduces the impact of heat emitted by the driving transistor Tm in the first pixel circuit 11 on the luminous efficiency of the first sub-pixel sp1, while appropriately increasing the impact of heat emitted by the driving transistor Tm in the first pixel circuit 11 on the luminous efficiency of the third sub-pixel sp3. This can balance the differences in luminous efficiency between sub-pixels of different colors, improve the color shift problem in white images, and enhance the display effect.

[0066] In some implementations, such as Figure 12 As shown in the top view, along the plane perpendicular to the substrate, the first sub-pixel sp1 and the third pixel circuit 13 overlap, and the third sub-pixel sp3 overlaps with the first pixel circuit 11. Here, "overlap" refers to partial overlap; any overlap between a sub-pixel sp and any transistor in the pixel circuit 10 can be considered as overlap. In related designs, the first sub-pixel sp1 overlaps with the first pixel circuit 11, and the third sub-pixel sp3 overlaps with the third pixel circuit 13. This embodiment of the invention is equivalent to swapping the positions of the first sub-pixel sp1 and the third sub-pixel sp3, while the position of the second sub-pixel sp2 can remain unchanged. The arrangement of the pixel circuits 10 in the display panel can remain unchanged. By designing the connection lines between the pixel circuits 10 and the sub-pixels sp, the swapped first sub-pixels sp1 and sp3 are connected to their respective pixel circuits 10.

[0067] In other implementations, N = 2. Figure 13 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention, such as... Figure 13As shown, each pixel P includes two sub-pixels. The first pixel P1 includes a first sub-pixel sp1 and a second sub-pixel sp2, and the second pixel P2 includes a third sub-pixel sp3 and a second sub-pixel sp2. The circuit group 10Z includes two pixel circuits 10. Part of the circuit group 10 includes a first pixel circuit 11 and a second pixel circuit 12, and part of the circuit group 10 includes a third pixel circuit 13 and a second pixel circuit 12. The orthographic projection distance of the first sub-pixel sp1 on the substrate is less than the minimum distance between the orthographic projection distance of the first sub-pixel sp1 on the substrate and the minimum distance between the orthographic projection distance of the nearest second pixel circuit 12 on the substrate and the minimum distance between the orthographic projection distance of the second sub-pixel sp2 in the first pixel P1 and the minimum distance between the orthographic projection distance of the nearest first pixel circuit 11 on the substrate and the minimum distance between the orthographic projection distance of the second sub-pixel sp2 on the substrate and the minimum distance between the orthographic projection distance of the second sub-pixel sp2 on the substrate and the minimum distance between the orthographic projection distance of the second sub-pixel sp2 on the substrate and the minimum distance between the orthographic projection distance of the second sub-pixel circuit 12 on the substrate. In related technologies, to facilitate the connection between sub-pixels and pixel circuits, the first sub-pixel sp1 is typically positioned closer to the first pixel circuit 11, the second sub-pixel sp2 closer to the second pixel circuit 12, and the third sub-pixel sp3 closer to the third pixel circuit 13. That is, in related technologies, the first pixel P1 corresponds to the positions of the first pixel circuit 11 and the second pixel circuit 12, and the second pixel P2 corresponds to the positions of the third pixel circuit 13 and the second pixel circuit 12. However, in the embodiment of this invention, the first sub-pixel sp1 is positioned even closer to the second pixel circuit 12, and the second sub-pixel sp2 within the first pixel P1 is positioned even closer to the first pixel circuit 11. Essentially, this involves swapping the positions of the first pixel circuit 11 and the second pixel circuit 12 corresponding to the first pixel P1. This moves the first sub-pixel sp1 away from the driving transistor Tm in the first pixel circuit 11, and moves the second sub-pixel sp2 closer to it. This reduces the impact of heat from the driving transistor Tm on the luminous efficiency of the first sub-pixel sp1, while appropriately increasing the impact of heat on the driving transistor Tm on the luminous efficiency of the second sub-pixel sp2. This balances the differences in luminous efficiency between different color sub-pixels, improves color cast in white images, and enhances the display effect.

[0068] In some implementations... Figure 14 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention, such as... Figure 14As shown, the orthographic projection distance of the first sub-pixel sp1 on the substrate is less than the minimum distance of the orthographic projection of its nearest second pixel circuit 12 on the substrate. Similarly, the orthographic projection distance of the second sub-pixel sp2 in the first pixel P1 is less than the minimum distance of the orthographic projection of its nearest first pixel circuit 11 on the substrate. The orthographic projection distance of the second sub-pixel sp2 in the first pixel P1 is also less than the minimum distance of the orthographic projection of its nearest first pixel circuit 11 on the substrate. The orthographic projection distance of the third sub-pixel sp3 on the substrate is also less than the minimum distance of the orthographic projection of its nearest third pixel circuit 13 on the substrate. Similarly, the orthographic projection distance of the second sub-pixel sp2 in the second pixel P2 is less than the minimum distance of the orthographic projection of its nearest second pixel circuit 12 on the substrate. Figure 14 Implementation examples in Figure 13 Based on the previous embodiment, the positions of the third pixel circuit 13 and the second pixel circuit 12 corresponding to the second pixel P2 are further interchanged. This arrangement allows multiple second pixel circuits 12 to be arranged in a column in the second direction y (i.e., the column direction), while the first pixel circuit 11 and the third pixel circuit 13 are alternately arranged in a column. Then, a first data line 31 and a second data line 32 can be provided in the display panel. The first data line 31 is connected to multiple second pixel circuits 12, and the second data line 32 is connected to the first pixel circuit 11 and the third pixel circuit 13. In this embodiment, the data lines do not need to be wound, and the signal transmission method of the display driver chip to the data lines remains basically unchanged, making the driving process simpler. Figure 14 The first data line 31 and the second data line 32 are only shown as dashed lines for illustrative purposes and are not intended to limit the scope of the invention.

[0069] In other implementations, Figure 15 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention, such as... Figure 15As shown, each pixel P includes two sub-pixels. The first pixel P1 includes a first sub-pixel sp1 and a second sub-pixel sp2, and the second pixel P2 includes a third sub-pixel sp3 and a second sub-pixel sp2. The circuit group 10Z includes two pixel circuits 10. Part of the circuit group 10 includes a first pixel circuit 11 and a second pixel circuit 12, and part of the circuit group 10 includes a third pixel circuit 13 and a second pixel circuit 12. The spacing between the two sub-pixels sp1 in the first pixel P1 is greater than the spacing between the two sub-pixels sp2 in the second pixel P2. This embodiment increases the spacing between the first sub-pixels sp1 and sp2 in the first pixel P1, causing the first sub-pixel sp1 to move further away from the driving transistor Tm in the first pixel circuit 11. This reduces the impact of heat generated by the driving transistor Tm on the luminous efficiency of the first sub-pixel sp1, improves the color shift problem in white images, and enhances the display effect.

[0070] In other implementations, Figure 16 A partial schematic diagram of another display panel provided in an embodiment of the present invention, as shown below. Figure 16 As shown, taking a pixel P that includes 3 sub-pixels as an example, the circuit group 10Z corresponds to the pixel P and includes 3 pixel circuits 10. Figure 16 The diagram illustrates that the first sub-pixel sp1, the second sub-pixel sp2, and the third sub-pixel sp3 are all located far from the area where the circuit group 10Z is located. In other words, the distance between the three color sub-pixels and the driving transistor Tm is increased. This reduces the impact of heat generated by the driving transistor Tm on the luminous efficiency of the three color sub-pixels, improves the color shift of the white screen, enhances the display effect, and also prevents a decrease in the overall brightness of the display panel.

[0071] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 17 This is a schematic diagram of a display device provided in an embodiment of the present invention, such as... Figure 17 As shown, the display device includes a display panel 100 provided in any embodiment of the present invention. The structure of the display panel 100 has been described in the above embodiments and will not be repeated here. The display device provided in the embodiments of the present invention can be, for example, an electronic device with display function such as a mobile phone, tablet, computer, television, or smart wearable product.

[0072] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0073] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, The display panel includes a substrate, a plurality of pixel circuits located on one side of the substrate, and a plurality of sub-pixels. The sub-pixels are connected to the pixel circuits. Each sub-pixel includes at least one LED, and each pixel circuit includes a driving transistor. Each sub-pixel includes a first sub-pixel and a second sub-pixel. Each pixel circuit includes a first pixel circuit and a second pixel circuit. The first sub-pixel is connected to the first pixel circuit, and the second sub-pixel is connected to the second pixel circuit. At least one first pixel circuit and at least one second pixel circuit are adjacent to each other. The display panel includes a plurality of pixels, and each pixel includes N sub-pixels of different colors, where N is an integer and N≥2; at least one pixel includes a first sub-pixel and a second sub-pixel; the first sub-pixel is a red sub-pixel; The minimum distance between the orthographic projection of the first sub-pixel on the substrate and the orthographic projection of the driving transistor in the first pixel circuit on the substrate is greater than the minimum distance between the orthographic projection of the second sub-pixel on the substrate and the orthographic projection of the driving transistor in the first pixel circuit on the substrate. in, The minimum distance between the orthographic projection of the first sub-pixel on the substrate and the orthographic projection of the driving transistor in the first pixel circuit on the substrate is greater than the minimum distance between the orthographic projection of the second sub-pixel on the substrate and the orthographic projection of the driving transistor in the second pixel circuit on the substrate.

2. The display panel according to claim 1, characterized in that, The minimum distance between the orthographic projection of the first sub-pixel on the substrate and the orthographic projection of its nearest driving transistor on the substrate is greater than the minimum distance between the orthographic projection of the second sub-pixel on the substrate and the orthographic projection of its nearest driving transistor on the substrate.

3. The display panel according to claim 2, characterized in that, The sub-pixel also includes a third sub-pixel, and the colors of the first sub-pixel, the second sub-pixel and the third sub-pixel are different from each other; The minimum distance between the orthographic projection of the first sub-pixel on the substrate and the orthographic projection of its nearest driving transistor on the substrate is greater than the minimum distance between the orthographic projection of the third sub-pixel on the substrate and the orthographic projection of its nearest driving transistor on the substrate.

4. The display panel according to claim 1, characterized in that, The minimum distance between the orthographic projection of the second sub-pixel on the substrate and the orthographic projection of the driving transistor in the first pixel circuit on the substrate is less than the minimum distance between the second sub-pixel and the orthographic projection of the driving transistor in the second pixel circuit on the substrate.

5. The display panel according to claim 1, characterized in that, The display panel includes multiple circuit groups, and each circuit group includes N pixel circuits; At least one of the first sub-pixels is located within the area enclosed by the four driving transistors in four adjacent pixel circuits, which respectively belong to four adjacent circuit groups.

6. The display panel according to claim 5, characterized in that, The four adjacent pixel circuits belong to four adjacent circuit groups and include the first pixel circuit and the second pixel circuit. The minimum distance between the orthographic projection of the first sub-pixel on the substrate and the orthographic projection of the driving transistor in the first pixel circuit on the substrate is greater than the minimum distance between the orthographic projection of the first sub-pixel on the substrate and the orthographic projection of the driving transistor in the second pixel circuit on the substrate.

7. The display panel according to claim 1, characterized in that, The arrangement of the sub-pixels in at least one pixel is different from the arrangement of the corresponding N pixel circuits.

8. The display panel according to claim 7, characterized in that, N=3； The three pixel circuits corresponding to the pixel are arranged at equal intervals, and the distance between the first sub-pixel and its adjacent sub-pixel is greater than the distance between the other two sub-pixels.

9. The display panel according to claim 8, characterized in that, The three pixel circuits corresponding to the pixel are arranged along the first direction; Along the first direction, the first sub-pixel and the other two sub-pixels in the pixel are misaligned.

10. The display panel according to claim 7, characterized in that, At least one of the pixels has a different color order for its subpixels than for its corresponding pixel circuits.

11. The display panel according to claim 10, characterized in that, N=3; in the pixel, the three sub-pixels are arranged at equal intervals.

12. The display panel according to claim 10, characterized in that, N=2; the sub-pixel further includes a third sub-pixel, and the pixel circuit includes a third pixel circuit; the third sub-pixel and the third pixel circuit are connected; The pixel includes a first pixel and a second pixel, the first pixel includes a first sub-pixel and a second sub-pixel, and the second pixel includes a second sub-pixel and a third sub-pixel; Wherein, the orthographic projection distance of the first sub-pixel on the substrate is less than the minimum distance of the orthographic projection distance of the first sub-pixel on the substrate and the minimum distance of the orthographic projection distance of the third ...

13. The display panel according to claim 12, characterized in that, Along a plane perpendicular to the substrate, the first sub-pixel and the third pixel circuit overlap.

14. The display panel according to claim 7, characterized in that, N=2; the sub-pixel further includes a third sub-pixel, and the pixel circuit includes a third pixel circuit; the third sub-pixel and the third pixel circuit are connected; The pixel includes a first pixel and a second pixel, the first pixel includes a first sub-pixel and a second sub-pixel, and the second pixel includes a second sub-pixel and a third sub-pixel; Wherein, the distance between two sub-pixels in the first pixel is greater than the distance between two sub-pixels in the second pixel.

15. The display panel according to claim 1, characterized in that, The display panel includes a circuit group, which includes N pixel circuits, and the multiple circuit groups are arranged in an array.

16. A display panel, characterized in that, The display panel includes a substrate, a plurality of pixel circuits located on one side of the substrate, and a plurality of sub-pixels. The sub-pixels are connected to the pixel circuits. Each sub-pixel includes at least one LED, and each pixel circuit includes a driving transistor. Each sub-pixel includes a first sub-pixel and a second sub-pixel. Each pixel circuit includes a first pixel circuit and a second pixel circuit. The first sub-pixel is connected to the first pixel circuit, and the second sub-pixel is connected to the second pixel circuit. At least one first pixel circuit and at least one second pixel circuit are adjacent to each other. The display panel includes a plurality of pixels, and each pixel includes N sub-pixels of different colors, where N is an integer. At least one pixel includes a first sub-pixel and a second sub-pixel; the first sub-pixel is a red sub-pixel. The minimum distance between the orthographic projection of the first sub-pixel on the substrate and the orthographic projection of the driving transistor in the first pixel circuit on the substrate is greater than the minimum distance between the orthographic projection of the second sub-pixel on the substrate and the orthographic projection of the driving transistor in the first pixel circuit on the substrate. N=2, the pixel includes a first pixel, the first pixel includes a first sub-pixel and a second sub-pixel, the orthographic projection distance of the first sub-pixel on the substrate is less than the minimum distance of the orthographic projection distance of the first sub-pixel on the substrate to the minimum distance of the orthographic projection of the nearest second pixel circuit on the substrate, and the orthographic projection distance of the second sub-pixel in the first pixel on the substrate to the minimum distance of the orthographic projection of the nearest first pixel circuit on the substrate is less than the minimum distance of the orthographic projection distance of the second sub-pixel on the substrate to the minimum distance of the orthographic projection of the nearest second pixel circuit on the substrate.

17. The display panel according to claim 16, characterized in that, The sub-pixel further includes a third sub-pixel, and the pixel circuit includes a third pixel circuit; the third sub-pixel and the third pixel circuit are connected; the pixel includes a second pixel, and the second pixel includes the second sub-pixel and the third sub-pixel; The orthographic projection distance of the third sub-pixel on the substrate is greater than the minimum distance of the orthographic projection distance of the third sub-pixel on the substrate and the minimum distance of the orthographic projection distance of the nearest third pixel circuit on the substrate. The orthographic projection distance of the second sub-pixel in the second pixel on the substrate is greater than the minimum distance of the orthographic projection distance of the second sub-pixel on the substrate and the minimum distance of the orthographic projection distance of the nearest second pixel circuit on the substrate.

18. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 17.

Images