Semiconductor structure and method for manufacturing the same

Abstract

The present application relates to a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a substrate and a dielectric layer; the substrate includes a device region and a peripheral region; the device region includes at least two transistors arranged at intervals; the peripheral region includes a resistor structure; the dielectric layer is located on the top surface of the substrate, and the gate structures of at least two transistors penetrate the dielectric layer; the resistor structure penetrates the dielectric layer; the resistor structure includes a conductive structure, and a resistor with a preset resistance value located between the bottom surface of the conductive structure and the substrate; the sum of the preset resistance value and the impedance value of the conductive structure is greater than a preset threshold value; the conductive structure and at least part of the gate conductive layer of the gate structure are prepared synchronously in the same process step. The present application is beneficial to improving the filling capacity of the contact hole and shortening the current flow path under the premise of forming a resistor structure with adjustable resistance, thereby improving the performance of the semiconductor structure.

Description

Technical Field

[0001] The present application relates to the semiconductor field, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] In current semiconductor structures, a high-resistivity (HIR) layer is usually used to form a resistor structure. Taking the high-K Metal Gate (HKMG) device as an example, the HIR resistor structure is usually composed of two film layers (such as TiN and SiN) and is connected to them through an embolization structure to achieve the functions of voltage division, current limiting and leakage prevention.

[0003] However, in the process of forming the HIR resistor structure in the related art, since an additional dielectric layer needs to be added to form the HIR resistor structure and the embolization structure separately, the thickness of the dielectric layer is increased, which easily causes the contact hole in the semiconductor structure to be too long, resulting in a decrease in the contact hole filling ability and a contact hole (contact open) defect, which in turn has an adverse effect on the performance of the semiconductor structure. Summary of the invention

[0004] Based on this, the embodiments of the present application provide a semiconductor structure and a method for preparing the same, which are beneficial for improving the filling capacity of the contact holes and shortening the current flow path while forming a resistor structure with adjustable resistance, thereby improving the performance of the semiconductor structure.

[0005] In order to achieve the above-mentioned purpose, on the one hand, some embodiments of the present application provide a semiconductor structure. The semiconductor structure includes a substrate and a dielectric layer; the substrate includes a device area and a peripheral area distributed along a first direction; the device area includes at least two transistors arranged at intervals along the first direction; the peripheral area includes a resistor structure; the dielectric layer is located on the top surface of the substrate, and the gate structures of at least two transistors penetrate the dielectric layer along a second direction away from the substrate; the resistor structure penetrates the dielectric layer along the second direction; wherein the second direction intersects with the first direction; the resistor structure includes a conductive structure, and a resistor with a preset resistance value located between the bottom surface of the conductive structure and the substrate; the sum of the preset resistance value and the impedance value of the conductive structure is greater than a preset threshold value; the conductive structure and At least part of the gate conductive layer of the gate structure is prepared synchronously in the same process step; by making the sum of the preset resistance value of the resistor structure and the impedance value of the conductive structure greater than the preset threshold value, a high-resistance resistor structure with adjustable resistance is formed to achieve voltage division, current limiting and leakage prevention; by forming the resistor structure in a non-device area next to the device area, and using the same process steps to synchronously prepare at least part of the conductive structure and the gate conductive layer, so that the conductive structure and the gate conductive layer are formed in the same dielectric layer, the thickness of the dielectric layer is effectively reduced, thereby improving the hole filling ability of the contact hole to improve the contact hole (contact open) defect problem, and shortening the current flow path in the structure to improve the resistance and capacitance (RC) delay problem in the semiconductor structure, effectively improving the performance of the semiconductor device; in addition, by using the same process steps to synchronously prepare at least part of the conductive structure and the gate conductive layer, the process integration can also be improved, so that the manufacturing steps of the resistor structure are compatible with the manufacturing steps of the transistor, saving costs while shortening the process cycle.

[0006] In some embodiments, the conductive structure includes a first metal layer, a second metal layer and a third metal layer stacked in sequence from outside to inside; the third metal layer is located in the first metal layer; the second metal layer is located between the first metal layer and the third metal layer, as well as the side wall and bottom surface of the third metal layer.

[0007] In some embodiments, the resistor includes doped polysilicon; the preset resistance value is associated with the doping concentration and / or the doping element type of the doped polysilicon; the resistance value of the resistor is set by adjusting the doping concentration and / or the doping element type of the doped polysilicon, thereby achieving adjustable resistance of the resistor structure.

[0008] In some embodiments, the device area includes a first-type transistor and a second-type transistor arranged at intervals along a first direction; the gate structures of the first-type transistor and the second-type transistor both include a gate conductive layer located on the substrate, and a sidewall located at least on the sidewall of the gate conductive layer; the first-type transistor also includes a stress layer, a contact layer, a first sigma groove distributed in sequence along the first direction, a gate structure, and a second sigma groove; the first sigma groove and the second sigma groove are both partially located in the substrate directly below the sidewall; the first sigma groove and the second sigma groove are both filled with a stress layer; the contact layer is located between the bottom surface of part of the sidewall and the stress layer.

[0009] In some embodiments, the semiconductor structure further includes a gate extraction electrode and an embolization structure. The gate extraction electrode is located on the side of the gate structure away from the substrate and is electrically connected to the gate structure; the embolization structure is located on the side of the resistor structure away from the substrate and is electrically connected to the resistor structure; wherein the gate extraction electrode and the embolization structure are simultaneously prepared in the same process step, which saves costs while improving process integration, and is conducive to enhancing the interconnection between the gate extraction electrode and the embolization structure and the pad layer in the upper structure, avoiding short circuit problems caused by bridging effects, etc., thereby improving the performance stability of the semiconductor structure.

[0010] On the other hand, the present disclosure also provides a method for manufacturing a semiconductor structure according to some embodiments; the manufacturing method includes: providing a substrate; the substrate includes a device area and a peripheral area distributed along a first direction; the top surface of the substrate includes a dielectric layer, the dielectric layer includes at least two gate trenches located in the device area and arranged at intervals along the first direction, and a groove located in the peripheral area; at least two gate trenches are filled with a sacrificial layer; a resistor with a preset resistance value is formed at the bottom of the groove; the sacrificial layer in at least two gate trenches is removed; during the formation of a gate conductive layer in at least two gate trenches, a conductive structure is formed on the resistor in the groove, and the sum of the preset resistance value and the impedance value of the conductive structure is greater than a preset threshold.

[0011] In some embodiments, during the formation of the gate conductive layer in at least two gate trenches, a conductive structure is formed on the resistor in the groove, including: forming a first metal material layer, the first metal material layer at least covers the inner surface of at least two gate trenches and the groove; forming a second metal material layer, the second metal material layer covers the exposed surface of the first metal material layer; forming a third metal material layer in at least the remaining space in at least two gate trenches and the groove; at least removing the first metal material layer, the second metal material layer and the third metal material layer located outside the at least two gate trenches and the groove, the first metal material layer retained in the groove is used to constitute the first metal layer, the second metal material layer retained in the groove is used to constitute the second metal layer, and the third metal material layer retained in the groove is used to constitute the third metal layer; the first metal material layer, the second metal material layer and the third metal material layer retained in at least two gate trenches are used to constitute at least part of the gate conductive layer.

[0012] In some embodiments, the resistor with a preset resistance value formed at the bottom of the groove includes: filling at least a semiconductor material layer in the groove; performing ion implantation on the semiconductor material layer in the groove so that the semiconductor material layer after ion implantation has a preset resistance value; and etching back the semiconductor material layer in the groove, and retaining the semiconductor material layer at the bottom of the groove to form a resistor.

[0013] In some embodiments, during the process of ion implantation into the semiconductor material layer in the groove, the concentration, dosage and / or element type of the ions implanted are controlled so that the semiconductor material layer after ion implantation has a preset resistance value.

[0014] In some embodiments, providing a substrate comprises: providing an initial substrate, the initial substrate comprising a device region and a peripheral region distributed along a first direction; the top surface of the initial substrate comprising a dielectric layer, the dielectric layer comprising a first gate trench and a second gate trench located in the device region and arranged at intervals along the first direction; the inner surfaces of the first gate trench and the second gate trench both comprise a gate dielectric layer and an initial gate conductive layer at least covering the gate dielectric layer; forming a work function layer, the work function layer exposing an opening of the initial gate conductive layer in the second gate trench, the work function layer covering the exposed surface of the initial gate conductive layer in the first gate trench and the top surface of the dielectric layer; forming a sacrificial layer that at least fills the remaining gaps in the first gate trench and the second gate trench; forming a patterned mask layer covering the sacrificial layer, the patterned mask layer comprising a pattern for defining a groove; using the patterned mask layer as a mask, etching the dielectric layer to form a groove located in the peripheral region, and the remaining initial substrate is used to constitute a substrate.

[0015] In summary, the unexpected technical effects that can be produced by the embodiments of the present application include at least:

[0016] By making the sum of the preset resistance value of the resistor structure and the impedance value of the conductive structure greater than the preset threshold value, a high-resistance resistor structure with adjustable resistance is formed to achieve voltage division, current limiting and leakage prevention effects; by forming the resistor structure in a non-device area next to the device area, and using the same process steps to simultaneously prepare at least part of the conductive structure and the gate conductive layer, so that the conductive structure and the gate conductive layer are formed in the same dielectric layer, the thickness of the dielectric layer is effectively reduced, thereby improving the hole filling ability of the contact hole to improve the contact hole (contact open) defect problem, and shortening the current flow path in the structure to improve the resistance and capacitance (RC) delay problem in the semiconductor structure, effectively improving the performance of the semiconductor device; in addition, by using the same process steps to simultaneously prepare at least part of the conductive structure and the gate conductive layer, the process integration can also be effectively improved, so that the manufacturing steps of the resistor structure are compatible with the manufacturing steps of the transistor, saving costs while shortening the process cycle.

[0017] The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 A schematic diagram of a semiconductor structure provided in some embodiments;

[0020] Figure 2 A schematic diagram of a resistor structure provided in some embodiments;

[0021] Figure 3 is a schematic structural diagram of a gate structure provided in some embodiments;

[0022] Figure 4 A schematic diagram of another semiconductor structure provided in some embodiments;

[0023] Figure 5 is a schematic structural diagram of another semiconductor structure provided in some embodiments;

[0024] Figure 6 A schematic diagram of a flow chart of a method for manufacturing a semiconductor structure provided in some embodiments;

[0025] Figure 7is a schematic diagram of a flowchart of step S100 provided in some embodiments;

[0026] Figure 8 is a schematic diagram of a flowchart of step S200 provided in some embodiments;

[0027] Fig. 9 is a schematic diagram of a flowchart of step S400 provided in some embodiments;

[0028] Fig.10 A schematic diagram of the structure of an initial substrate provided in some embodiments;

[0029] Fig.11 A schematic diagram of a structure obtained after forming a work function layer provided in some embodiments;

[0030] Fig.12 A schematic diagram of a structure obtained after forming a sacrificial layer provided in some embodiments;

[0031] Fig.13 A schematic diagram of a structure obtained after forming a patterned mask layer and etching a dielectric layer provided in some embodiments;

[0032] Fig.14 A schematic diagram of a structure obtained after forming a semiconductor material layer provided in some embodiments;

[0033] Fig.15 A schematic diagram of a structure obtained after grinding a semiconductor material layer provided in some embodiments;

[0034] Fig.16 A schematic diagram of a structure obtained after etching back a semiconductor material layer provided in some embodiments;

[0035] Fig.17 A schematic diagram of a structure obtained after removing a sacrificial layer provided in some embodiments.

[0036] Description of reference numerals:

[0037] 1. Substrate, A. Device region, B. Peripheral region, STI, shallow trench isolation structure, T. Transistor, T1, first type transistor, T2, second type transistor, 21. Gate structure, 211. Gate conductive layer, 2110. Initial gate conductive layer, 211a. First gate conductive stack, 211b. Second gate conductive stack, 212. Gate dielectric layer, S. Sidewall, 22. Stress layer, 23. Contact layer, 23a. Source contact layer, 23b. Drain contact layer, 241. First sigma groove, 242. Second sigma groove, 25. Source region, 26. Drain region, 3. Resistor structure, 31. Conductive structure, M1. First metal layer, M2. Second metal layer, M3. Third metal layer, M4, barrier layer, M5, fourth metal layer, M6, work function layer, 32, resistor, 4, dielectric layer, 5, nitride layer, 61, gate lead electrode, 62, source lead electrode, 63, drain lead electrode, 7, embolism structure, 8, isolation layer, H1, gate trench, H11, first gate trench, H12, second gate trench, H2, groove, H3, gate contact hole, H4, source contact hole, H5, drain contact hole, H6, resistor contact hole, 9, first protective layer, 10, second protective layer, 111, first metal wire, 112, second metal wire, 12, interlayer dielectric layer, 13, sacrificial layer, P, patterned mask layer, 14, semiconductor material layer. DETAILED DESCRIPTION

[0038] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0040] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0041] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0042] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments (and intermediate structures) of the present application, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include deviations in shapes due to, for example, manufacturing techniques. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present application.

[0043] The embodiment of the present application provides a semiconductor structure and a method for preparing the same, so as to improve the filling capacity of the contact hole and shorten the flow path of the current while forming a resistor structure with adjustable resistance, thereby improving the performance of the semiconductor structure.

[0044] In order to achieve the above objectives, on the one hand, some embodiments of the present application provide a semiconductor structure.

[0045] In some embodiments, see Figure 1The semiconductor structure includes a substrate 1 and a dielectric layer 4; the substrate 1 includes a device area A and a peripheral area B distributed along a first direction; the device area A includes at least two transistors T arranged at intervals along a first direction (for example, an X direction); the peripheral area B includes a resistor structure 3; the dielectric layer 4 is located on the top surface of the substrate 1, and the gate structures 21 of at least two transistors T penetrate the dielectric layer 4 along a second direction (for example, a Y direction) away from the substrate 1; wherein the second direction intersects with the first direction; the resistor structure 3 penetrates the dielectric layer 4 along the second direction; the resistor structure 3 includes a conductive structure 31, and a resistor 32 with a preset resistance value located between the bottom surface of the conductive structure 31 and the substrate 1; the sum of the preset resistance value and the impedance value of the conductive structure 31 is greater than a preset threshold value; the conductive structure 31 and at least a portion of the gate conductive layer 211 of the gate structure 21 are synchronously prepared in the same process step.

[0046] By way of example, the semiconductor structure includes but is not limited to a high-K Metal Gate (HKMG) device and the like.

[0047] By way of example, the resistor structure 3 includes but is not limited to a high resistance (HIR) resistor and the like.

[0048] It should be supplemented that the dielectric layer 4 includes at least two gate trenches H1 arranged in a first direction (for example, X direction) in the device area A, and a groove H2 in the peripheral area B; wherein the gate structure 21 is embedded in the gate trench H1; and the resistor structure 3 is embedded in the groove H2.

[0049] For example, the material of the dielectric layer 4 includes but is not limited to insulating materials; the insulating materials include but are not limited to oxides, and the material of the dielectric layer 4 may be, for example, silicon oxide (SiO) or silicon dioxide (SiO 2 ).

[0050] Please refer to Figure 1 , the surface of the gate structure 21 facing away from the substrate 1 is flush with the surface of the dielectric layer 4 facing away from the substrate 1; the surface of the resistor structure 3 facing away from the substrate 1 is flush with the surface of the dielectric layer 4 facing away from the substrate 1, and the size of the resistor structure 3 in the second direction is equal to the size of the gate structure 21 in the second direction.

[0051] In some embodiments, please refer to Figure 1 The semiconductor structure further includes a nitride layer 5 ; the nitride layer 5 is located between the dielectric layer 4 and the substrate 1 . It should be noted that the resistor structure 3 is located on the surface of the nitride layer 5 away from the substrate 1 ; the gate structure 21 penetrates the nitride layer 5 .

[0052] By way of example, the material of the nitride layer 5 includes, but is not limited to, silicon nitride (SiN) and the like.

[0053] In some embodiments, please refer to Figure 1 The semiconductor structure also includes a shallow trench isolation structure STI; the shallow trench isolation structure STI is embedded in the substrate 1 between the transistors T and between the device area A and the peripheral area B; the size of the shallow trench isolation structure STI in the second direction (for example, the Y direction) is larger than the size of the transistor T in the second direction (for example, the Y direction).

[0054] By way of example, the material of the shallow trench isolation structure STI includes but is not limited to oxide (GOX) and the like.

[0055] For example, the substrate 1 can be made of semiconductor material, insulating material, conductor material or any combination thereof. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrate 1 or II / VI semiconductor substrate. Or, for example, the substrate 1 can be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator. Therefore, the type of substrate 1 should not limit the scope of protection of the present application.

[0056] By way of example, the material of the conductive structure 31 includes, but is not limited to, conductive metals and alloys thereof.

[0057] It should be noted that please combine Figure 1 and Figure 2 It is understood that the resistance structure 3 includes a conductive structure 31 and a resistor 32 ; wherein the resistor 32 is located on a side of the nitride layer 5 facing away from the substrate 1 .

[0058] In some embodiments, please refer to Figure 2 The conductive structure 31 includes a first metal layer M1, a second metal layer M2 and a third metal layer M3 stacked in sequence from the outside to the inside; the third metal layer M3 is located in the first metal layer M1; the second metal layer M2 is located between the first metal layer M1 and the third metal layer M3, as well as the side wall and bottom surface of the third metal layer M3.

[0059] By way of example, the material of the first metal layer M1 includes, but is not limited to, titanium aluminum alloy (TiAl) and the like.

[0060] By way of example, the material of the second metal layer M2 includes, but is not limited to, titanium (Ti) or titanium nitride (TiN).

[0061] By way of example, the material of the third metal layer M3 includes, but is not limited to, a conductive metal; the material of the third metal layer M3 may be, for example, aluminum (Al).

[0062] Please refer to Figure 2 The first metal layer M1 covers the bottom surface and sidewalls of the groove H2; the second metal layer M2 covers the first metal layer M1; and the third metal layer M3 covers the second metal layer M2 and fills the remaining space of the groove H2.

[0063] In some embodiments, the resistor 32 includes doped polysilicon (Adulterated Poly Si); the predetermined resistance value is associated with the doping concentration and / or doping element type of the doped polysilicon.

[0064] It should be noted that in the embodiment of the present disclosure, the resistance of the resistor 32 is set by adjusting the doping concentration and / or the type of doping elements of the doped polysilicon, thereby achieving adjustable resistance of the resistor structure 3 .

[0065] In some embodiments, see Figure 1 The device region A includes first-type transistors T and second-type transistors T arranged at intervals along a first direction; the gate structures 21 of the first-type transistors T and the second-type transistors T both include a gate conductive layer 211 located on the substrate 1, and a sidewall S located at least on the sidewall of the gate conductive layer 211;

[0066] In some embodiments, please refer to Figure 1 The gate structure 21 further includes a gate dielectric layer 212 ; the gate dielectric layer 212 is located between the gate conductive layer 211 and the substrate 1 .

[0067] By way of example, the material of the gate dielectric layer 212 includes, but is not limited to, a high dielectric constant (High-K, HK for short) material.

[0068] For example, the first-type transistor T1 is, for example, a P-type metal oxide semiconductor (PMOS); and the second-type transistor T2 is, for example, an N-type metal oxide semiconductor (NMOS).

[0069] It should be noted that please combine Figure 1 and Figure 3 It is understood that the gate conductive layer 211 includes a first gate conductive stack 211a and a second gate conductive stack 211b stacked in sequence from outside to inside; the first gate conductive stack 211a is located at the bottom and sidewall of the gate trench H1; the second gate conductive stack 211b is located inside the first gate conductive stack 211a and fills the gate trench H1.

[0070] It should be noted that, for example, please refer to Figure 3In Figure (a), the first gate conductive stack 211a of the first type transistor T1 (for example, PMOS) includes a barrier layer M4 located on the side of the gate dielectric layer 212 away from the substrate 1, and a fourth metal layer M5 and a work function layer M6 stacked in sequence from the outside to the inside and located on the side of the barrier layer M4 away from the gate dielectric layer 212; the work function layer M6 is located between the first gate conductive stack 211a and the fourth metal layer M5.

[0071] For example, see Figure 3 In FIG. 5( b ), the first gate conductive stack 211 a of the second-type transistor T2 (eg, NMOS) includes a barrier layer M4 located on the side of the gate dielectric layer 212 away from the substrate 1 , and a fourth metal layer M5 located on the side of the barrier layer M4 away from the gate dielectric layer 212 and on the sidewall of the gate trench H1 .

[0072] It should be explained that the work function required by the first-type transistor T1 (for example, PMOS) is greater than that of the second-type transistor T2 (for example, NMOS). In the embodiment of the present disclosure, the first gate conductive stack 211a of the first-type transistor T1 (for example, PMOS) is provided with a work function layer M6 more than the first gate conductive stack 211a of the second-type transistor T2 (for example, NMOS) in order to increase the work function of the first-type transistor T1 (for example, PMOS) and make it greater than the work function of the second-type transistor T2 (for example, NMOS), so as to ensure that the work function difference between the first-type transistor T1 and meets the process manufacturing requirements of the transistor T.

[0073] By way of example, the material of the barrier layer M4 includes, but is not limited to, at least one of tantalum nitride (TaN) or titanium nitride (TiN).

[0074] By way of example, the material of the fourth metal layer M5 includes, but is not limited to, at least one of tantalum nitride (TaN) or titanium nitride (TiN).

[0075] By way of example, the material of the work function layer M6 includes, but is not limited to, at least one of tantalum nitride (TaN) or titanium nitride (TiN).

[0076] It should be noted that the barrier layer M4 and the work function layer M6 may be made of the same material.

[0077] It is worth mentioning that see Figure 3The second gate conductive stack 211b includes a first metal layer M1, a second metal layer M2 and a third metal layer M3 stacked in sequence from the outside to the inside; the third metal layer M3 is located in the first metal layer M1; the second metal layer M2 is located between the first metal layer M1 and the third metal layer M3, as well as the side wall and bottom surface of the third metal layer M3; it should be noted that the second gate conductive stack 211b and the conductive structure 31 have the same or similar stacking structure; the second gate conductive stack 211b can be prepared simultaneously with the conductive structure 31 in the same process steps.

[0078] In some examples, the sidewall spacer S may be a stacked structure stacked along a first direction (e.g., X direction); illustratively, the material of the sidewall spacer S includes, but is not limited to, an insulating material, such as titanium nitride (TiN) and / or oxide (GOX), etc.; the sidewall spacer S may be, for example, a stacked structure in which titanium nitride (TiN) and oxide (GOX) are sequentially stacked along a first direction (e.g., X direction).

[0079] In some embodiments, see Figure 1 The gate structures 21 of the first-type transistor T1 and the second-type transistor T2 further include a source region 25 and a drain region 26 located in the substrate 1 below the left and right sides of the gate structure 21 .

[0080] For some examples, see Figure 1 The first-type transistor T further includes a stress layer 22, a contact layer 23, a first sigma groove 241, a gate structure 21, and a second sigma groove 242 sequentially distributed along a first direction; the first sigma groove 241 and the second sigma groove 242 are both partially located in the substrate 1 directly below the sidewall S; the first sigma groove 241 and the second sigma groove 242 are both filled with the stress layer 22; the contact layer 23 is located between the bottom surface of a portion of the sidewall S and the stress layer 22;

[0081] For example, the first sigma groove 241 and the second sigma groove 242 both include, but are not limited to, a rectangular groove H2, a diamond groove H2, a pentagonal groove H2, or a hexagonal groove H2, etc.

[0082] By way of example, the material of the stress layer 22 includes, but is not limited to, silicon germanium alloy (SiGe) and the like.

[0083] By way of example, the material of the contact layer 23 includes, but is not limited to, metal silicide and the like.

[0084] Please refer to Figure 1 The top surface of the contact layer 23 facing away from the stress layer 22 is higher than the surface of the substrate 1 , and at least a portion of the contact layer 23 that is higher than the surface of the substrate 1 is located within the sidewall S.

[0085] In some examples, the contact layer 23 includes a source contact layer 23 a and a drain contact layer 23 b ; at least a portion of the source contact layer 23 a is located in the source region 25 and is electrically connected to the source region 25 , and at least a portion of the drain contact layer 23 b is located in the drain region 26 and is electrically connected to the drain region 26 .

[0086] In some embodiments, see Figure 4 The semiconductor structure further includes an isolation layer 8 ; the isolation layer 8 is located on a side of the dielectric layer 4 facing away from the substrate 1 .

[0087] For example, the material of the isolation layer 8 includes but is not limited to insulating materials; the insulating materials include but are not limited to oxides, and the material of the dielectric layer 4 may be, for example, silicon oxide (SiO) or silicon dioxide (SiO 2 ).

[0088] In some embodiments, please refer to Figure 4 The isolation layer 8 includes a gate contact hole H3, a source contact hole H4, a drain contact hole H5 and a resistor contact hole H6.

[0089] It should be noted that the gate contact hole H3 exposes the top surface of the gate conductive layer 211 away from the substrate 1, the source contact hole H4 exposes the top surface of the source contact layer 23a away from the substrate 1, the drain contact hole H5 exposes the top surface of the drain contact layer 23b away from the substrate 1, and the resistor contact hole H6 exposes the top surface of the conductive structure 31 away from the substrate 1. The size of the gate contact hole H3 in the second direction (for example, the Y direction) is equal to the size of the resistor contact hole H6 in the second direction (for example, the Y direction).

[0090] In some embodiments, please refer to Figure 4 The semiconductor structure further includes a gate extraction electrode 61 and an embolization structure 7. The gate extraction electrode 61 is located on the side of the gate structure 21 away from the substrate 1 and is electrically connected to the gate structure 21; the embolization structure 7 is located on the side of the resistor structure 3 away from the substrate 1 and is electrically connected to the resistor structure 3; wherein the gate extraction electrode 61 and the embolization structure 7 are simultaneously prepared in the same process steps.

[0091] In some embodiments, please refer to Figure 4 The semiconductor structure further includes a source extraction electrode 62 and a drain extraction electrode 63. The source extraction electrode 62 is located on the side of the source contact layer 23a away from the substrate 1 and is electrically connected to the source contact layer 23a; the drain extraction electrode 63 is located on the side of the drain contact layer 23b away from the substrate 1 and is electrically connected to the drain contact layer 23b.

[0092] In some examples, the gate lead electrode 61, the source lead electrode 62, the drain lead electrode 63 and the plug structure 7 all include a stacked structure; the stacked structure includes a seed layer covering the bottom and sidewalls of the contact hole and a conductive metal covering the seed layer and filling the contact hole.

[0093] For example, the materials of the gate lead electrode 61 , the source lead electrode 62 , the drain lead electrode 63 and the plug structure 7 include but are not limited to conductive metals; for example, they may be copper (Cu), aluminum (Al) and their alloy materials (such as copper-aluminum alloy CuAl).

[0094] It should be noted that the size of the gate extraction electrode 61 in the second direction (eg, the Y direction) is equal to the size of the plug structure 7 in the second direction (eg, the Y direction).

[0095] For example, the size of the embolic structure 7 in the second direction (eg, Y direction) ranges from 500A to 1000A; the size of the embolic structure 7 in the second direction (eg, Y direction) may be, for example, 500A, 600A, 700A, 800A, 900A, 1000A, etc.

[0096] In some embodiments, see Figure 5 The semiconductor structure also includes a first protective layer 9, a second protective layer 10, a first metal wire 111, a second metal wire 112 and an interlayer dielectric layer 12; the first protective layer 9 is located on the side of the isolation layer 8 away from the dielectric layer 4; the second protective layer 10 is located on the side of the first protective layer 9 away from the isolation layer 8; the first metal wire 111 penetrates at least part of the first protective layer 9 and the second protective layer 10, and is electrically connected to any adjacent source lead-out electrode 62 and drain lead-out electrode 63 located in different transistors T; the second metal wire 112 penetrates at least part of the first protective layer 9 and the second protective layer 10, and is electrically connected to the embolization structure 7; the interlayer dielectric layer 12 is located between any two adjacent metal wires on the side of the second protective layer 10 away from the first protective layer 9.

[0097] On the other hand, the present application also provides a method for manufacturing a semiconductor structure according to some embodiments, and the method for manufacturing a semiconductor structure is used to prepare the semiconductor structure in some of the above embodiments. The method for manufacturing the semiconductor structure also has the technical advantages of the above semiconductor structure. It should be noted that the parts that are the same or corresponding to the above embodiments can refer to the corresponding description of the above embodiments, and will not be described in detail below.

[0098] In some embodiments, see Figure 6 , the manufacturing method of the semiconductor structure includes the following steps S100~S400.

[0099] S100, providing a substrate; the substrate includes a device area and a peripheral area distributed along a first direction; the top surface of the substrate includes a dielectric layer, the dielectric layer includes at least two gate trenches located in the device area and arranged at intervals along the first direction, and a groove located in the peripheral area; at least two gate trenches are filled with a sacrificial layer.

[0100] In some embodiments, see Figure 7 , step S100 includes the following steps S110~S150.

[0101] S110, providing an initial substrate, the initial substrate comprising a device region and a peripheral region distributed along a first direction; the top surface of the initial substrate comprises a dielectric layer, the dielectric layer comprises a first gate trench and a second gate trench located in the device region and arranged at intervals along the first direction; the inner surfaces of the first gate trench and the second gate trench both comprise a gate dielectric layer and an initial gate conductive layer at least covering the gate dielectric layer.

[0102] S120, forming a work function layer, wherein the work function layer exposes the opening of the initial gate conductive layer in the second gate trench, and the work function layer covers the exposed surface of the initial gate conductive layer in the first gate trench and the top surface of the dielectric layer.

[0103] In some examples, step S120 includes: forming a work function material layer, the work function material layer covering the first gate trench, the second gate trench, the dielectric layer and the initial gate conductive layer; etching at least the work function material layer in the second gate trench to expose the opening of the initial gate conductive layer in the second gate trench to obtain the work function layer.

[0104] S130, forming a sacrificial layer that at least fills the remaining gaps in the first gate trench and the second gate trench.

[0105] S140, forming a patterned mask layer covering the sacrificial layer, wherein the patterned mask layer includes a pattern for defining a groove.

[0106] S150, using the patterned mask layer as a mask, etching the dielectric layer to form a groove in the peripheral area, and the remaining initial substrate is used to form a substrate.

[0107] S200, forming a resistor with a preset resistance at the bottom of the groove.

[0108] In some embodiments, see Figure 8 , step S200 includes the following steps S210~S230.

[0109] S210, filling a semiconductor material layer at least in the groove.

[0110] S220, performing ion implantation on the semiconductor material layer in the groove, so that the semiconductor material layer after the ion implantation has a preset resistance value.

[0111] In some embodiments, during the process of ion implantation into the semiconductor material layer in the groove, the concentration, dosage and / or element type of the ions implanted are controlled so that the semiconductor material layer after ion implantation has a preset resistance value.

[0112] In some examples, after step S220 , step S200 further includes: grinding the semiconductor material layer after ion implantation to remove the semiconductor material layer outside the groove and make the semiconductor material layer in the groove flush with the surface of the dielectric layer.

[0113] S230, etching back the semiconductor material layer in the groove, and the semiconductor material layer retained at the bottom of the groove is used to form a resistor.

[0114] S300, removing the sacrificial layer in at least two gate trenches.

[0115] In some examples, step S300 further includes: grinding the initial gate conductive layer and the work function layer to remove the initial gate conductive layer and the work function layer outside the first gate trench, the second gate trench and the groove, and exposing the top surface of the dielectric layer facing away from the substrate.

[0116] S400, during the formation of gate conductive layers in at least two gate trenches, a conductive structure is formed on the resistor in the groove, and the sum of a preset resistance value and an impedance value of the conductive structure is greater than a preset threshold.

[0117] In some embodiments, see Fig. 9 , step S400 includes the following steps S410~S440.

[0118] S410, forming a first metal material layer, wherein the first metal material layer at least covers inner surfaces of at least two gate trenches and recesses.

[0119] S420, forming a second metal material layer, wherein the second metal material layer covers the exposed surface of the first metal material layer.

[0120] S430, forming a third metal material layer at least in the remaining space in the at least two gate trenches and the recess.

[0121] S440, at least the first metal material layer, the second metal material layer and the third metal material layer located outside at least two gate trenches and outside the groove are removed, the first metal material layer retained in the groove is used to constitute the first metal layer, the second metal material layer retained in the groove is used to constitute the second metal layer, and the third metal material layer retained in the groove is used to constitute the third metal layer; the first metal material layer, the second metal material layer and the third metal material layer retained in at least two gate trenches are used to constitute at least part of the gate conductive layer.

[0122] It should be understood that although Figure 6~Figure 9 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 6~Figure 9 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0123] In order to more clearly illustrate the chip packaging method in some of the above embodiments, the following embodiments are combined with Figure 10~Figure 17 Understand.

[0124] In some embodiments, the method for manufacturing a semiconductor structure includes steps S100 to S400.

[0125] In step S100, a substrate 1 is provided; the substrate 1 includes a device area A and a peripheral area B distributed along a first direction; the top surface of the substrate 1 includes a dielectric layer 4, the dielectric layer 4 includes at least two gate trenches H1 located in the device area A and arranged at intervals along the first direction, and a groove H2 located in the peripheral area B; at least two gate trenches H1 are filled with a sacrificial layer 13.

[0126] In some embodiments, step S100 includes steps S110 to S150.

[0127] In step S110, refer to Fig.10 , providing an initial substrate, the initial substrate comprising a device region A and a peripheral region B distributed along a first direction; the top surface of the initial substrate comprises a dielectric layer 4, the dielectric layer 4 comprises a first gate trench H11 and a second gate trench H12 located in the device region A and arranged at intervals along the first direction; the inner surfaces of the first gate trench H11 and the second gate trench H12 both comprise a gate dielectric layer 212 and an initial gate conductive layer 2110 at least covering the gate dielectric layer 212.

[0128] It should be noted that the initial gate conductive layer 2110 refers to an intermediate structure used for continuing deposition on an upper layer thereof in subsequent steps to form a gate conductive layer 211 .

[0129] In step S120, refer to Fig.11 , a work function layer M6 is formed, the work function layer M6 exposes the opening of the initial gate conductive layer 2110 in the second gate trench H1, and the work function layer M6 covers the exposed surface of the initial gate conductive layer 2110 in the first gate trench H11 and the top surface of the dielectric layer 4.

[0130] In some examples, step S120 includes: forming a work function material layer, the work function material layer covering the first gate trench H11, the second gate trench H12, the dielectric layer 4 and the initial gate conductive layer 2110; etching at least the work function material layer in the second gate trench H12 to expose the opening of the initial gate conductive layer 2110 in the second gate trench H12 to obtain the work function layer M6.

[0131] By way of example, the material of the work function material layer includes, but is not limited to, at least one of tantalum nitride (TaN) or titanium nitride (TiN).

[0132] By way of example, the process for forming the work function material layer includes, but is not limited to, a deposition process.

[0133] By way of example, the etching process of the work function layer M6 includes but is not limited to a photolithography process.

[0134] In step S130, refer to Fig.12 , forming a sacrificial layer 13 that at least fills the remaining gaps in the first gate trench H11 and the second gate trench H12.

[0135] In step S140, refer to Fig.13 , a patterned mask layer covering the sacrificial layer 13 is formed, and the patterned mask layer includes a pattern for defining the groove H2.

[0136] By way of example, the patterned mask layer includes but is not limited to a photoresist layer and the like.

[0137] For example, the process for forming the patterned mask layer includes but is not limited to a coating process, and may be a spin coating process, for example.

[0138] In step S150, please continue to refer to Fig.13 , using the patterned mask layer as a mask, the dielectric layer 4 is etched to form a groove H2 located in the peripheral area B, and the remaining initial substrate is used to form the substrate 1.

[0139] By way of example, the etching process of the dielectric layer 4 includes, but is not limited to, a photolithography process.

[0140] It should be noted that the etching of the dielectric layer 4 stops at the nitride layer 5 , so that the groove H2 exposes the top surface of the nitride layer 5 facing away from the substrate 1 .

[0141] In step S200 , a resistor 32 with a predetermined resistance is formed at the bottom of the recess H2 .

[0142] In some embodiments, step S200 includes steps S210 to S230.

[0143] In step S210, refer to Fig.14 , at least the groove H2 is filled with the semiconductor material layer 14 .

[0144] By way of example, the material of the semiconductor material layer 14 includes, but is not limited to, polysilicon (poly).

[0145] By way of example, the formation process of the semiconductor material layer 14 includes, but is not limited to, a deposition process.

[0146] In step S220 , ions are implanted into the semiconductor material layer 14 in the groove H2 , so that the semiconductor material layer 14 after the ion implantation has a preset resistance value.

[0147] In some embodiments, during the process of ion implantation into the semiconductor material layer 14 in the groove H2 , the concentration, dosage and / or element type of the ions implanted are controlled so that the semiconductor material layer 14 after ion implantation has a preset resistance value.

[0148] For some examples, see Fig.15 After step S220 , step S200 further includes: grinding the semiconductor material layer 14 after ion implantation to remove the semiconductor material layer 14 and the patterned mask layer P outside the groove H2 , and making the semiconductor material layer 14 in the groove H2 flush with the surface of the dielectric layer 4 .

[0149] For example, the polishing process of the semiconductor material layer 14 includes but is not limited to a chemical mechanical polishing process (CMP for short).

[0150] In step S230, refer to Fig.16 The semiconductor material layer 14 in the groove H2 is etched back, and the semiconductor material layer 14 retained at the bottom of the groove H2 is used to form the resistor 32.

[0151] By way of example, the etch-back process of the semiconductor material layer 14 includes, but is not limited to, a wet etching process.

[0152] In step S300, refer to Fig.17 , removing the sacrificial layer 13 in at least two gate trenches H1.

[0153] In some examples, step S300 further includes: grinding the initial gate conductive layer 2110 and the work function layer M6 to remove the initial gate conductive layer 2110 and the work function layer M6 outside the first gate trench H1, the second gate trench H1 and the recess H2, and exposing the top surface of the dielectric layer 4 facing away from the substrate 1.

[0154] For example, the polishing process of the initial gate conductive layer 2110 and the work function layer M6 includes but is not limited to a chemical mechanical polishing (CMP) process.

[0155] In step S400 , while the gate conductive layer 211 is formed in at least two gate trenches H1 , a conductive structure 31 is formed on the resistor 32 in the recess H2 , and the sum of a preset resistance value and the impedance value of the conductive structure 31 is greater than a preset threshold.

[0156] In some embodiments, step S400 includes steps S410 to S440.

[0157] In step S410 , a first metal material layer is formed, and the first metal material layer at least covers inner surfaces of at least two gate trenches H1 and recess H2 .

[0158] By way of example, the formation process of the first metal material layer includes, but is not limited to, a deposition process.

[0159] In step S420 , a second metal material layer is formed, and the second metal material layer covers the exposed surface of the first metal material layer.

[0160] By way of example, the formation process of the second metal material layer includes, but is not limited to, a deposition process.

[0161] In step S430 , a third metal material layer is formed at least in the remaining space in the at least two gate trenches H1 and the recess H2 .

[0162] By way of example, the formation process of the third metal material layer includes, but is not limited to, a deposition process.

[0163] In step S440, please combine Figure 1 , Figure 2 and Figure 3 It is understood that at least the first metal material layer, the second metal material layer and the third metal material layer located outside the at least two gate trenches H1 and outside the groove H2 are removed, and the first metal material layer retained in the groove H2 is used to constitute the first metal layer M1, the second metal material layer retained in the groove H2 is used to constitute the second metal layer M2, and the third metal material layer retained in the groove H2 is used to constitute the third metal layer M3; the first metal material layer, the second metal material layer and the third metal material layer retained in at least two gate trenches H1 are used to constitute at least part of the gate conductive layer 211.

[0164] For example, the removal process of the first metal material layer, the second metal material layer and the third metal material layer includes but is not limited to a chemical mechanical polishing (CMP) process.

[0165] In summary, the unexpected technical effects that can be produced by the embodiments of the present application include at least:

[0166] By making the sum of the preset resistance value of the resistor structure and the impedance value of the conductive structure greater than the preset threshold value, a high-resistance resistor structure with adjustable resistance is formed to achieve voltage division, current limiting and leakage prevention effects; by forming the resistor structure in a non-device area next to the device area, and using the same process steps to simultaneously prepare at least part of the conductive structure and the gate conductive layer, so that the conductive structure and the gate conductive layer are formed in the same dielectric layer, the thickness of the dielectric layer is effectively reduced, thereby improving the hole filling ability of the contact hole to improve the contact hole (contact open) defect problem, and shortening the current flow path in the structure to improve the resistance and capacitance (RC) delay problem in the semiconductor structure, effectively improving the performance of the semiconductor device; in addition, by using the same process steps to simultaneously prepare at least part of the conductive structure and the gate conductive layer, the process integration can also be effectively improved, so that the manufacturing steps of the resistor structure are compatible with the manufacturing steps of the transistor, saving costs while shortening the process cycle.

[0167] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0168] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; The substrate comprises a device region and a peripheral region distributed along a first direction; the top surface of the substrate comprises a dielectric layer, the dielectric layer comprises at least two gate trenches located in the device region and arranged at intervals along the first direction, and a groove located in the peripheral region; the at least two gate trenches are filled with a sacrificial layer; forming a resistor with a preset resistance at the bottom of the groove; removing the sacrificial layer in the at least two gate trenches; During the formation of the gate conductive layer in the at least two gate trenches, a conductive structure is formed on the resistor in the groove, and the sum of the preset resistance value and the impedance value of the conductive structure is greater than a preset threshold.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: During the formation of the gate conductive layer in the at least two gate trenches, a conductive structure is formed on the resistor in the groove, comprising: Forming a first metal material layer, wherein the first metal material layer at least covers the inner surface of the at least two gate trenches and the groove; forming a second metal material layer, wherein the second metal material layer covers the exposed surface of the first metal material layer; forming a third metal material layer at least in the at least two gate trenches and in the remaining space in the groove; At least the first metal material layer, the second metal material layer and the third metal material layer located outside the at least two gate trenches and outside the groove are removed, the first metal material layer retained in the groove is used to constitute the first metal layer, the second metal material layer retained in the groove is used to constitute the second metal layer, and the third metal material layer retained in the groove is used to constitute the third metal layer; the first metal material layer, the second metal material layer and the third metal material layer retained in the at least two gate trenches are used to constitute at least part of the gate conductive layer.

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: A resistor with a preset resistance is formed at the bottom of the groove, comprising: Filling a semiconductor material layer at least in the groove; Performing ion implantation on the semiconductor material layer in the groove, so that the semiconductor material layer after the ion implantation has a preset resistance value; The semiconductor material layer in the groove is etched back, and the semiconductor material layer retained at the bottom of the groove is used to form the resistor.

4. The method for manufacturing a semiconductor structure according to claim 3, characterized in that: During the process of ion implantation into the semiconductor material layer in the groove, the concentration, dosage and / or element type of the ions implanted are controlled so that the semiconductor material layer after ion implantation has a preset resistance value.

5. The method for manufacturing a semiconductor structure according to claim 1, wherein: The providing of a substrate comprises: Providing an initial substrate, the initial substrate comprising a device region and a peripheral region distributed along a first direction; the top surface of the initial substrate comprising a dielectric layer, the dielectric layer comprising a first gate trench and a second gate trench located in the device region and arranged at intervals along the first direction; the inner surfaces of the first gate trench and the second gate trench both comprising a gate dielectric layer and an initial gate conductive layer at least covering the gate dielectric layer; forming a work function layer, wherein the work function layer exposes an opening of the initial gate conductive layer in the second gate trench, and the work function layer covers an exposed surface of the initial gate conductive layer in the first gate trench and a top surface of the dielectric layer; forming a sacrificial layer that at least fills the remaining gaps in the first gate trench and the second gate trench; forming a patterned mask layer covering the sacrificial layer, wherein the patterned mask layer includes a pattern for defining the groove; The dielectric layer is etched using the patterned mask layer as a mask to form a groove in the peripheral area, and the remaining initial substrate is used to form the substrate.

6. A semiconductor structure, characterized in that: The semiconductor structure is prepared by the manufacturing method of any one of claims 1 to 5; the semiconductor structure comprises: A substrate, comprising a device region and a peripheral region distributed along a first direction; the device region comprises at least two transistors arranged at intervals along the first direction; the peripheral region comprises a resistor structure; A dielectric layer is located on the top surface of the substrate, the gate structures of the at least two transistors penetrate the dielectric layer along a second direction away from the substrate; the resistance structure penetrates the dielectric layer along the second direction; wherein the second direction intersects with the first direction; The resistance structure includes a conductive structure, and a resistor with a preset resistance value located between the bottom surface of the conductive structure and the substrate; the sum of the preset resistance value and the impedance value of the conductive structure is greater than a preset threshold; The conductive structure and at least a portion of the gate conductive layer of the gate structure are simultaneously prepared in the same process step.

7. The semiconductor structure according to claim 6, characterized in that: The conductive structure includes a first metal layer, a second metal layer and a third metal layer stacked in sequence from outside to inside; The third metal layer is located within the first metal layer; The second metal layer is located between the first metal layer and the third metal layer, and on the sidewall and bottom surface of the third metal layer.

8. The semiconductor structure according to claim 6, characterized in that: The resistor comprises doped polysilicon; The preset resistance value is associated with the doping concentration and / or the doping element type of the doped polysilicon.

9. The semiconductor structure according to claim 6, characterized in that: The device area includes first-type transistors and second-type transistors arranged at intervals along a first direction; the gate structures of the first-type transistors and the second-type transistors each include a gate conductive layer located on the substrate, and a sidewall at least located on a sidewall of the gate conductive layer; The first-type transistor further includes a stress layer, a contact layer, a first sigma groove, a gate structure, and a second sigma groove sequentially distributed along the first direction; The first sigma groove and the second sigma groove are both partially located in the substrate directly below the sidewall; The first sigma groove and the second sigma groove are both filled with the stress layer; The contact layer is located between a bottom surface of a portion of the sidewall and the stress layer.

10. The semiconductor structure according to claim 6, characterized in that: The semiconductor structure further comprises: A gate extraction electrode, located at a side of the gate structure away from the substrate and electrically connected to the gate structure; an embolization structure, located on a side of the resistor structure away from the substrate and electrically connected to the resistor structure; Wherein, the gate lead-out electrode and the plug structure are simultaneously prepared in the same process step.

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