Light emitting device and method of manufacturing

Abstract

The application relates to the technical field of semiconductor photoelectric devices, and discloses a light-emitting device and a preparation method, the light-emitting device comprising a substrate layer, a buffer layer, a porous structure and a light-emitting structure layer, the buffer layer being located on one side surface of the substrate layer, and the buffer layer having a target region; the porous structure being embedded in the target region, the porous structure comprising a gallium nitride column, and the gallium nitride column having nanopores; the light-emitting structure layer being located on one side surface of the gallium nitride column away from the substrate layer, the light-emitting structure layer comprising a first doped semiconductor layer, a light-emitting layer and a second doped semiconductor layer, the first doped semiconductor layer being located on one side surface of the gallium nitride column away from the substrate layer, the light-emitting layer being located between the first doped semiconductor layer and the second doped semiconductor layer, and the conduction type of the first doped semiconductor layer being opposite to that of the second doped semiconductor layer. The application reduces the non-uniformity of pore diameters caused by large-area poration, and further reduces the non-uniformity of stress relaxation degrees.

Description

Technical Field

[0001] This invention relates to the field of semiconductor optoelectronic device technology, specifically to a light-emitting device and its fabrication method. Background Technology

[0002] In recent years, third-generation semiconductor materials, represented by silicon carbide and gallium nitride, have been widely used in optoelectronic devices. Among them, gallium nitride has been widely used in the field of light-emitting devices due to its advantages such as wide bandgap, good stability, strong radiation resistance, and high temperature resistance.

[0003] For optoelectronic semiconductor devices, changing the indium content in gallium nitride-based ternary alloy materials can alter the bandgap width of the material and thus modulate the wavelength of light emission. To achieve red light wavelengths, the indium content of the semiconductor needs to be increased. However, increasing the indium content of the semiconductor will affect the in-plane lattice constant of the semiconductor and cause a large lattice mismatch between indium nitride and gallium nitride in the semiconductor material. The lattice mismatch strain will also reduce the indium content through the composition pulling effect, making it difficult to obtain high-quality gallium indium nitride.

[0004] To obtain high-quality gallium indium nitride epitaxial materials with high indium content, existing techniques involve etching one or more planar layers in the device into porous layers. These porous layers facilitate stress relaxation and reduce lattice mismatch strain. However, large-area porous structures suffer from uneven porosity due to differences in contact time with the electrolyte used in electrochemical etching, which in turn leads to uneven relaxation. Summary of the Invention

[0005] In view of this, the present invention provides a light-emitting device and a method for fabricating it, so as to solve the problems of uneven porosity and uneven relaxation degree in the porous structure of existing light-emitting devices.

[0006] In a first aspect, the present invention provides a light-emitting device, comprising:

[0007] Substrate layer;

[0008] A buffer layer located on one side surface of the substrate layer, the buffer layer having one or more target regions;

[0009] A porous structure is embedded in the target region, the porous structure comprising gallium nitride pillars arranged in an array, and the gallium nitride pillars having nanopores;

[0010] A light-emitting structure layer is located on the side surface of the gallium nitride column away from the substrate layer, and the light-emitting structure layer comprises a first doped semiconductor layer, a light-emitting layer and a second doped semiconductor layer, the first doped semiconductor layer is located on the side surface of the gallium nitride column away from the substrate layer, the light-emitting layer is located on the side surface of the first doped semiconductor away from the gallium nitride column, and the second doped semiconductor layer is located on the side surface of the light-emitting layer away from the first doped semiconductor layer, and the conductive type of the first doped semiconductor layer is opposite to that of the second doped semiconductor layer.

[0011] Beneficial effects: the nanopores on the gallium nitride column can reduce the mismatch stress caused by the mismatch of the lattice constant of gallium nitride and the lattice constant of indium nitride; secondly, the nanopores in the gallium nitride column are beneficial to stress relaxation and, due to the composition pulling effect, more indium is incorporated into the light-emitting structure layer; thirdly, the porous structure is embedded only in the target area, reducing the area of the porous structure and thus reducing the non-uniformity of the pore size caused by large-area porosity, and further reducing the non-uniformity of the stress relaxation degree. At the same time, the part of the buffer layer outside the target area can provide support between the buffer layer and the light-emitting structure layer, so that a greater degree of porosity can be achieved in the target area to form an air gap and achieve the effect of a mirror.

[0012] In an optional embodiment, the depth of the gallium nitride column in the buffer layer is 0.1 μm-0.8 μm, the maximum width of the gallium nitride column is 5 μm-100 μm, and the spacing between adjacent two gallium nitride columns is 1 μm-100 μm.

[0013] Beneficial effects: when the depth of the gallium nitride column in the buffer layer is less than 0.1 μm, the stress relaxation effect cannot be achieved, and when the depth of the gallium nitride column in the buffer layer is greater than 0.8 μm, the crystal damage caused by the formation of gallium nitride is avoided. The width of the gallium nitride should meet the size of the light-emitting device, and the spacing of each gallium nitride column should meet the spacing of the light-emitting device.

[0014] In an optional embodiment, the material of the light-emitting layer comprises a mixture formed by gallium nitride, aluminum element and indium element.

[0015] The incorporation of indium element and aluminum element in the light-emitting layer can form gallium aluminum nitride and gallium indium nitride alloy. By changing the composition of aluminum and indium in the alloy, the wavelength range of light emission can be 200 nm-1771 nm, so that the spectral variation range corresponding to the band gap variation of gallium nitride-based semiconductor material can be from infrared light to ultraviolet light wave region, so as to be applied to multiple illumination fields with different wavelength requirements.

[0016] In an optional embodiment, the area of the light-emitting structure layer is less than or equal to the area of the target area.

[0017] The light-emitting structure layer is less than or equal to the area of the target region, i.e. the light-emitting structure layer is completely located on the gallium indium nitride column with nanopores, and the nanopores on the gallium indium nitride can improve light scattering, thereby facilitating the improvement of the light extraction efficiency of the light-emitting device.

[0018] In an alternative embodiment, a non-porous layer is further included, which is located between the gallium nitride column and the first doped semiconductor layer, and the material of the non-porous layer comprises gallium nitride.

[0019] The non-porous layer is used to provide a smooth surface for the growth of the light-emitting structure layer, thereby facilitating the guarantee of the epitaxial crystallization quality of the light-emitting structure layer.

[0020] In an alternative embodiment, a stress regulation layer is further included, which is located between the substrate and the buffer layer, the material of the stress regulation layer comprises gallium nitride, and the thickness of the stress regulation layer is less than the thickness of the buffer layer.

[0021] The stress regulation layer is used to regulate the lattice mismatch stress and thermal stress caused by the difference in the coefficient of thermal expansion during the subsequent preparation and growth of the structure layer of the light-emitting device; and the stress regulation layer is used to regulate the large thermal stress generated by the large difference in the coefficient of thermal expansion between the silicon substrate and the gallium nitride material during the substantial cooling process after the preparation and growth of the material.

[0022] In a second aspect, the present application provides a preparation method of a light-emitting device, comprising the following steps:

[0023] providing a substrate layer;

[0024] forming a buffer layer on one side surface of the substrate layer, and the buffer layer has one or more target regions;

[0025] forming a porous structure in the target region, and the porous structure comprises gallium nitride columns embedded in the target region in an array form, and the gallium nitride columns have nanopores;

[0026] forming a light-emitting structure layer on the side surface of the gallium nitride column away from the substrate layer, and the light-emitting structure layer comprises a first doped semiconductor layer, a light-emitting layer and a second doped semiconductor layer, the first doped semiconductor layer is located on the side surface of the gallium nitride column away from the substrate layer, the light-emitting layer is located on the side surface of the first doped semiconductor away from the gallium nitride column, and the second doped semiconductor layer is located on the side surface of the light-emitting layer away from the first doped semiconductor layer, and the conductive type of the first doped semiconductor layer and the conductive type of the second doped semiconductor layer are opposite.

[0027] Beneficial effects: the luminescent device prepared by the above method, the nanopores in the gallium nitride column can reduce the mismatch stress caused by the mismatch of the lattice constant of gallium nitride and the lattice constant of indium nitride; secondly, the nanopores in the gallium nitride column are beneficial to stress relaxation, and due to the composition pulling effect, more indium is incorporated into the luminescent structure layer; thirdly, the porous structure is embedded only in the target area, reducing the area of the porous structure, thereby reducing the non-uniformity of the pore size caused by large-area porosity, and further reducing the non-uniformity of the stress relaxation degree.

[0028] In an optional embodiment, forming a porous structure in a target area on the buffer layer comprises:

[0029] Providing a dielectric layer on the side surface of the buffer layer away from the substrate layer, the dielectric layer having a preset pattern, the preset pattern comprising a pore array composed of a plurality of through holes;

[0030] Using the dielectric layer as a mask, ions are injected into the buffer layer through the through holes in the pore array to form a gallium nitride column;

[0031] Carrying out a porosity treatment on the gallium nitride column to form nanopores;

[0032] Wherein, the material of the buffer layer comprises one or more of gallium nitride, indium nitride, gallium indium nitride, and the ions comprise one or more of silicon ions, germanium ions, boron ions, tellurium ions, iodine ions, carbon ions, phosphorus ions, arsenic ions, sulfur ions, antimony ions, and tin ions.

[0033] In an optional embodiment, the gallium nitride column is formed by using a local ion implantation process, the depth of ion implantation is 0.1-0.8 μm, and the ion concentration of the local ion implantation process is 10 18 orders of magnitude.

[0034] In an optional embodiment, the porosity treatment on the gallium nitride column is carried out by using an electrochemical etching process;

[0035] The parameters of the electrochemical etching process include: the electrolyte used includes oxalic acid, hydrofluoric acid or nitric acid, the concentration of the electrolyte is 0.1-0.3 M, the etching voltage is 8-15 V, and the negative electrode used includes a platinum electrode or a gold electrode.

[0036] In an optional embodiment, it further comprises: after forming the luminescent structure layer, removing the mask to the first doped semiconductor layer, and forming an electrode on the luminescent structure layer after removing part of the mask. BRIEF DESCRIPTION OF DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or prior art description. Obviously, the drawings described below are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative effort based on these drawings.

[0038] Figure 1 is a flowchart of a preparation method of a light emitting device according to an embodiment of the present application;

[0039] Figure 2 is a structural diagram of a light emitting device according to an embodiment of the present application;

[0040] Figure 3 is a structural diagram of a substrate layer in the preparation of a light emitting device according to an embodiment of the present application;

[0041] Figure 4 is a structural diagram of a substrate layer and a stress control layer in the preparation of a light emitting device according to an embodiment of the present application;

[0042] Figure 5 is a structural diagram of a substrate layer, a stress control layer and a buffer layer in the preparation of a light emitting device according to an embodiment of the present application;

[0043] Figure 6 is a structural diagram of a substrate layer, a stress control layer, a buffer layer and a dielectric layer in the preparation of a light emitting device according to an embodiment of the present application;

[0044] Figure 7 is a structural diagram of a substrate layer, a stress control layer, a buffer layer, a dielectric layer and a gallium nitride column in the preparation of a light emitting device according to an embodiment of the present application;

[0045] Figure 8 is a structural diagram of a substrate layer, a stress control layer, a buffer layer, a dielectric layer, a gallium nitride column with nanopores in the preparation of a light emitting device according to an embodiment of the present application;

[0046] Figure 9 is a structural diagram of a substrate layer, a stress control layer, a buffer layer, a dielectric layer, a gallium nitride column with nanopores and a non-porous layer in the preparation of a light emitting device according to an embodiment of the present application;

[0047] Figure 10 is a structural diagram of a substrate layer, a stress control layer, a buffer layer, a dielectric layer, a gallium nitride column with nanopores, a non-porous layer and a first doped semiconductor layer in the preparation of a light emitting device according to an embodiment of the present application;

[0048] Figure 11is a structure schematic diagram of a substrate layer, a stress regulation layer, a buffer layer, a dielectric layer, a gallium nitride column with nano-pores, a non-porous layer, a first doped semiconductor layer, and a light emitting layer in preparation of a light emitting device according to an embodiment of the present application;

[0049] Figure 12 is a structure schematic diagram of a substrate layer, a stress regulation layer, a buffer layer, a dielectric layer, a gallium nitride column with nano-pores, a non-porous layer, a first doped semiconductor layer, a light emitting layer, and a second doped semiconductor layer in preparation of a light emitting device according to an embodiment of the present application;

[0050] Figure 13 is a structure schematic diagram of a substrate layer, a stress regulation layer, a buffer layer, a partial dielectric layer, a gallium nitride column with nano-pores, a non-porous layer, and a partial light emitting structure layer in preparation of a light emitting device according to an embodiment of the present application.

[0051] wherein,

[0052] 100, a substrate layer;

[0053] 200, a stress regulation layer;

[0054] 300, a buffer layer;

[0055] 400, a dielectric layer; 401, a through hole;

[0056] 500, a gallium nitride column; 501, a nano-pore;

[0057] 600, a non-porous layer;

[0058] 700, a first doped semiconductor layer;

[0059] 800, a light emitting layer;

[0060] 900, a second doped semiconductor layer. DETAILED DESCRIPTION

[0061] The application will be described in further detail below with reference to the drawings and embodiments. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not intended to limit the scope of the application. In addition, it should be noted that, in the drawings, only parts related to the application are shown and not all structures. In the following description, the description of well-known structures and techniques is omitted to avoid unnecessary confusion of the concept of the application. In the drawings, various structural diagrams according to embodiments of the application are shown. These diagrams are not drawn to scale, in which certain details are exaggerated for the purpose of clarity and certain details can be omitted. The shapes of various regions, layers and their relative sizes and positional relationships shown in the drawings are only exemplary, and in actuality, they can be deviated due to manufacturing tolerances or technical limitations, and a person skilled in the art can additionally design regions / layers with different shapes, sizes and relative positions according to actual needs. In the context of the application, when a layer / element is referred to as being located on another layer / element, the layer / element can be directly located on the other layer / element, or there can be an intermediate layer / element between them. In addition, if a layer / element is located on another layer / element in one orientation, it can be located below the other layer / element when the orientation is reversed.

[0062] Gallium nitride material has the advantages of wide band gap, good stability, strong anti-radiation and high temperature resistance, and is widely used in the field of light emitting devices. For gallium nitride light emitting devices, the electron band gap of the semiconductor material can be changed by changing the indium content in the gallium nitride light emitting device, and the light emitting wavelength of the gallium nitride light emitting device can be changed. At present, the demand for red wavelength light emitting devices is huge, and in order to realize red wavelength light, it is necessary to further increase the indium content in the gallium nitride light emitting device.

[0063] The technical solution adopted in the related art is to etch the entire or multiple planar layer structures in the device into porous layers, and to realize stress relaxation by using the porous layers to realize the increase of the indium content. However, the large-area porous structure faces the situation of uneven porosity due to the difference in contact time with the electrolyte used in electrochemical etching, which also causes uneven relaxation.

[0064] Embodiments of the application provide a light emitting device preparation method, comprising the following steps:

[0065] S11: as shown in the figure, a substrate layer 100 is provided. Figure 3

[0066] The substrate layer 100 can be sapphire, or silicon carbide, or monocrystalline silicon, or glass.

[0067] S12: as shown in the figure, a buffer layer 200 is provided on the substrate layer 100. Figure 5 ​As shown in the figure, a buffer layer 300 is formed on one side surface of the substrate layer 100, and the buffer layer 300 has one or more target areas.

[0068] The buffer layer 300 is formed on the substrate by using a vapor phase epitaxy growth technology, a molecular beam epitaxy growth technology or other commonly used epitaxy growth technologies. The buffer layer 300 can be selected from one or more of gallium nitride, aluminum nitride and indium nitride. The buffer layer 300 is divided into one or more target areas on the side surface away from the substrate layer 100.

[0069] S13: As shown in the figure, Figure 8 A porous structure is formed in the target area on the buffer layer 300. The porous structure includes gallium nitride columns 500 embedded in the target area in an array form, and the gallium nitride columns 500 have nanopores 501.

[0070] Any one of the gallium nitride columns 500 is embedded in the buffer layer 300. The gallium nitride column 500 with the nanopore 501 can be directly formed in the buffer layer 300 by an ion implantation process combined with an electrochemical etching process, or can be formed in the buffer layer 300 by a photolithography exposure process, a vapor deposition process combined with an electrochemical etching process.

[0071] S14: As shown in the figure, Figure 12 A light-emitting structure layer is formed on the side surface of the gallium nitride column 500 away from the substrate layer 100. The light-emitting structure layer includes a first doped semiconductor layer 700, a light-emitting layer 800 and a second doped semiconductor layer 900. The first doped semiconductor layer 700 is located on the side surface of the gallium nitride column 500 away from the substrate layer 100. The light-emitting layer 800 is located on the side surface of the first doped semiconductor away from the gallium nitride column 500. The second doped semiconductor layer 900 is located on the side surface of the light-emitting layer 800 away from the first doped semiconductor layer 700. The conductive type of the first doped semiconductor layer 700 and the conductive type of the second doped semiconductor layer 900 are opposite.

[0072] When the first doped semiconductor layer 700 is N-type doped, the first doped semiconductor layer 700 can be N-type doped gallium nitride or N-type doped gallium indium nitride. The second doped semiconductor layer 900 is of opposite P-type conductivity, and the second doped semiconductor layer 900 can be P-type doped gallium or P-type doped gallium indium nitride. When the first doped semiconductor layer 700 is P-type doped, the second doped semiconductor layer 900 is of opposite N-type doped. The material of the light-emitting layer 800 includes a mixture formed by gallium nitride, aluminum elements and indium elements.

[0073] The light-emitting device prepared by the above method has nanopores 501 in the gallium nitride pillar 500, which can reduce the mismatch stress caused by the mismatch between the lattice constants of gallium nitride and indium nitride. Secondly, the nanopores 501 in the gallium nitride pillar 500 are conducive to stress relaxation, and due to the composition pulling effect, more indium is incorporated into the light-emitting structure layer. Thirdly, the porous structure is embedded only in the target area, which reduces the area of ​​the porous structure, thereby reducing the non-uniformity of pore size caused by large-area porousization, and further reducing the non-uniformity of stress relaxation.

[0074] The fabrication method of the light-emitting device in this embodiment will be described in detail below, such as... Figure 1 As shown, it includes the following steps:

[0075] S1: As Figure 3 As shown, sapphire was chosen as the substrate layer 100.

[0076] S2: As Figure 4 As shown, a low-temperature gallium nitride layer is formed on a sapphire substrate using vapor phase epitaxy, as... Figure 5 As shown, a U-shaped gallium nitride (GaN) layer with a thickness between 1 μm and 100 μm is grown on the surface of the low-temperature gallium nitride layer facing away from the sapphire substrate. There is a significant lattice mismatch and thermal mismatch between the U-shaped GaN and the sapphire substrate. Using low-temperature gallium nitride or aluminum nitride as a buffer layer can provide a better growth template for subsequent nitride epitaxy, thus improving the crystal quality of the GaN epitaxial layer to some extent.

[0077] S3: As Figure 6 As shown, a silicon dioxide dielectric layer 400 is grown on the surface of the U-shaped gallium nitride layer facing away from the low-temperature gallium nitride layer. The silicon dioxide dielectric layer 400 has a preset pattern, which includes an array of vias 401. Any via 401 can be a circular, hexagonal, square, elliptical, or other common via 401. The preset pattern allows the target area to be defined on the buffer layer 300. Figure 7 As shown, using a silicon dioxide dielectric layer 400 as a mask, a localized ion implantation process is employed to implant ions into a buffer layer 300 through vias 401 in a aperture array to form gallium nitride pillars 500. The implanted ions include one or more of silicon ions, germanium ions, boron ions, tellurium ions, iodine ions, carbon ions, phosphorus ions, arsenic ions, sulfur ions, antimony ions, and tin ions. The ion implantation depth is between 100 nm and 800 nm, and the implanted ion concentration in the localized ion implantation process is 10. 18 The gallium nitride pillar 500 is adapted to the shape of the corresponding through-hole 401. The gallium nitride pillar 500 can be a cylinder, hexagonal prism, cuboid, elliptical cylinder, or other prism. For example... Figure 8As shown, the gallium nitride column 500 is subjected to a porous treatment by using an electrochemical etching process to form a gallium nitride column 500 with nano-pores 501, and the nano-pores 501 are distributed in the gallium nitride column 500, and each of the nano-pores 501 is a dendritic pore. In an alternative embodiment, the nano-pores 501 can also be circular pores, elliptical pores or other common pores. The specific conditions of the electrochemical etching process are as follows: the electrolyte used includes oxalic acid, hydrofluoric acid or nitric acid, the concentration of the electrolyte is 0.1M-0.3M (M is mol / L), the etching voltage is 8V-15V (V is volt), and the negative electrode used includes a platinum electrode or a gold electrode.

[0078] S4: As shown in Figure 9 As shown, a non-porous layer 600 is grown on the side surface of the gallium nitride column 500 with nano-pores 501 away from the substrate, and the material of the non-porous layer 600 includes one or more of gallium nitride, indium nitride and gallium indium nitride, as shown in Figure 10 As shown, an N-type doped gallium nitride is grown on the side surface of the non-porous layer 600 away from the substrate layer 100, as shown in Figure 11 As shown, a light-emitting layer 800 is grown on the side surface of the N-type doped gallium nitride away from the non-porous layer 600, and the light-emitting layer 800 can be one or more quantum wells, such as gallium indium nitride / gallium nitride quantum wells, as shown in Figure 12 As shown, a P-type doped gallium nitride layer is grown on the side surface of the light-emitting layer 800 away from the first doped semiconductor layer 700.

[0079] S5: As shown in Figure 13 As shown, when the light-emitting structure layer is prepared, mesa etching is performed to remove the mask to the first doped semiconductor layer 700, and part of the P-type doped gallium nitride layer, the light-emitting layer 800 and the N-type doped gallium nitride layer are removed, and the silicon dioxide is etched to the N-type gallium nitride layer, and the electrode is prepared.

[0080] The embodiment also provides a light-emitting device, as shown in Figure 2 and Figure 13As shown, the light-emitting device comprises a substrate layer 100, a buffer layer 300, a porous structure and a light-emitting structure layer. The buffer layer 300 is located on one side surface of the substrate layer 100, and has one or more target regions. The porous structure is embedded in the target region, and comprises gallium nitride columns 500 arranged in an array, and the gallium nitride columns 500 have nanopores 501. The light-emitting structure layer is located on the side surface of the gallium nitride columns 500 away from the substrate layer 100, and comprises a first doped semiconductor layer 700, a light-emitting layer 800 and a second doped semiconductor layer 900. The first doped semiconductor layer 700 is located on the side surface of the gallium nitride columns 500 away from the substrate layer 100. The light-emitting layer 800 is located on the side surface of the first doped semiconductor layer 700 away from the gallium nitride columns 500. The second doped semiconductor layer 900 is located on the side surface of the light-emitting layer 800 away from the first doped semiconductor layer 700. The conductive type of the first doped semiconductor layer 700 is opposite to that of the second doped semiconductor layer 900.

[0081] Specifically, the substrate layer 100 is a sapphire substrate, the buffer layer 300 is a U-shaped gallium nitride, the first doped semiconductor layer 700 is N-type doped gallium nitride, and the second doped semiconductor layer 900 is P-type doped gallium nitride. The nanopores 501 in the gallium nitride columns 500 can reduce the mismatch stress caused by the mismatch of the lattice constant of gallium nitride and the lattice constant of indium nitride, and the scattering of light by the nanopores 501 can improve the light extraction efficiency of the light-emitting device. In addition, the nanopores 501 in the gallium nitride columns 500 can facilitate stress relaxation and more indium can be incorporated into the light-emitting structure layer due to the composition pulling effect. Furthermore, the porous structure is only embedded in the target region, which reduces the area of the porous structure and the non-uniformity of the pore size caused by large-area porosity, thereby reducing the non-uniformity of the stress relaxation degree. At the same time, the part of the buffer layer 300 outside the target region can provide support between the buffer layer 300 and the light-emitting structure layer, so that the target region can be more porous to form an air gap and achieve the effect of a mirror.

[0082] In one embodiment, the depth of the gallium nitride column 500 in the buffer layer 300 is 0.1-0.8 μm, such as 0.1 μm, 0.5 μm, 0.7 μm, 0.8 μm, the maximum width of the gallium nitride column 500 is 5-100 μm, such as 1 μm, 6 μm, 15 μm, 50 μm, 100 μm, and the distance between two adjacent gallium nitride columns 500 is 1-100 μm, such as 1 μm, 8 μm, 24 μm, 50 μm, 100 μm. The depth of the gallium nitride column 500 is selected to avoid the stress relaxation effect when the depth of the gallium nitride column in the buffer layer is less than 0.1 μm, and to avoid the crystal damage caused by the formation of gallium nitride when the depth of the gallium nitride column in the buffer layer is greater than 0.8 μm. The width of the gallium nitride column should meet the size of the light emitting device, and the distance between the gallium nitride columns should meet the arrangement distance of the light emitting device.

[0083] In one embodiment, the material of the light emitting layer 800 includes a mixture formed by gallium nitride, aluminum element and indium element. The indium element and aluminum element are doped in the light emitting layer 800 to form gallium nitride aluminum and gallium nitride indium alloys. By changing the aluminum and indium components in the alloy, the wavelength range of the light emission can be 200-1771 nm, so that the spectral variation range corresponding to the band gap variation of the gallium nitride based semiconductor material can be from the infrared light to the ultraviolet light wave region, so as to be applied to the lighting field with different wavelength requirements.

[0084] In one embodiment, the light emitting structure layer is less than or equal to the area of the target region. The light emitting structure layer is less than or equal to the area of the target region, that is, the light emitting structure layer is completely located on the gallium nitride indium column with the nano-pore 501, and the nano-pore 501 on the gallium nitride indium can improve the scattering of light, thereby improving the light extraction efficiency of the light emitting device.

[0085] In one embodiment, a non-porous layer 600 is further included, and the non-porous layer 600 is located between the gallium nitride column 500 and the first doped semiconductor layer 700. The material of the non-porous layer 600 includes gallium nitride. The non-porous layer 600 is used to provide a smooth surface for the growth of the light emitting layer 800.

[0086] In one embodiment, a stress regulating layer 200 is further included, and the stress regulating layer 200 is located between the substrate and the buffer layer 300. The material of the stress regulating layer 200 includes gallium nitride, and the thickness of the stress regulating layer 200 is less than the thickness of the buffer layer 300. The stress regulating layer 200 is used to regulate the lattice mismatch stress and thermal stress caused by the difference in the thermal expansion coefficient during the subsequent preparation and growth process of the light emitting device structure layer; and the stress regulating layer 200 is used to regulate the large thermal stress generated by the large difference in the thermal expansion coefficient between the silicon substrate and the gallium nitride material during the large-scale cooling process after the material preparation and growth are completed.

[0087] In the above description, the technical details such as the patterning, etching, etc. of each layer are not described in detail. However, those skilled in the art should understand that the layers, regions, etc. with desired shapes can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the above-described methods in order to form the same structure. In addition, although each embodiment is described above separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0088] In the description of the present specification, the description of the terms "the embodiment", "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in the present specification and the features of the different embodiments or examples, without contradiction.

[0089] In addition, the terms "first", "second", etc. are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is at least two, for example, two, three, etc., unless otherwise explicitly specified.

[0090] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like are based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0091] In this application, unless otherwise clearly indicated and limited, the terms "mounting", "connection", "connecting", "fixing" and the like should be interpreted broadly, for example, can be fixed connection, can also be detachable connection, or integrated; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be the internal communication of two elements or the interaction relationship of two elements, unless otherwise clearly limited. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0092] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement and simple improvement made on the essential content of the present application shall be included in the protection scope of the present application.

Claims

1. A light emitting device, characterized by, The application relates to a substrate layer (100); a buffer layer (300) on one side surface of the substrate layer (100), wherein the buffer layer (300) has one or more target areas; a porous structure embedded in the target area, wherein the porous structure comprises gallium nitride columns (500) arranged in an array, and the gallium nitride columns (500) have nanopores (501); and a light-emitting structure layer on the side surface of the gallium nitride columns (500) away from the substrate layer (100), wherein the light-emitting structure layer comprises a first doped semiconductor layer (700), a light-emitting layer (800) and a second doped semiconductor layer (900), the first doped semiconductor layer (700) is on the side surface of the gallium nitride columns (500) away from the substrate layer (100), the light-emitting layer (800) is on the side surface of the first doped semiconductor away from the gallium nitride columns (500), the second doped semiconductor layer (900) is on the side surface of the light-emitting layer (800) away from the first doped semiconductor layer (700), and the conductive type of the first doped semiconductor layer (700) is opposite to that of the second doped semiconductor layer (900). The depth of the gallium nitride columns (500) in the buffer layer (300) is 0.1-0.8 mu m, the maximum width of the gallium nitride columns (500) is 5-100 mu m, and the distance between two adjacent gallium nitride columns (500) is 1-100 mu m. The material of the light-emitting layer (800) comprises a mixture of gallium nitride, aluminum and indium. The area of the light-emitting structure layer is less than or equal to that of the target area. A non-porous layer (600) is further arranged between the gallium nitride columns (500) and the first doped semiconductor layer (700), and the material of the non-porous layer (600) comprises gallium nitride.

2. The light emitting device of claim 1, wherein, A stress regulation layer (200) is further arranged between the substrate and the buffer layer (300), the material of the stress regulation layer (200) comprises gallium nitride, and the thickness of the stress regulation layer (200) is less than that of the buffer layer (300).

3. The light emitting device according to claim 1 or 2, characterized in that, The application relates to a substrate layer (100); a buffer layer (300) on one side surface of the substrate layer (100), wherein the buffer layer (300) has one or more target areas; a porous structure embedded in the target area, wherein the porous structure comprises gallium nitride columns (500) arranged in an array, and the gallium nitride columns (500) have nanopores (501); and a light-emitting structure layer on the side surface of the gallium nitride columns (500) away from the substrate layer (100), wherein the light-emitting structure layer comprises a first doped semiconductor layer (700), a light-emitting layer (800) and a second doped semiconductor layer (900), the first doped semiconductor layer (700) is on the side surface of the gallium nitride columns (500) away from the substrate layer (100), the light-emitting layer (800) is on the side surface of the first doped semiconductor away from the gallium nitride columns (500), the second doped semiconductor layer (900) is on the side surface of the light-emitting layer (800) away from the first doped semiconductor layer (700), and the conductive type of the first doped semiconductor layer (700) is opposite to that of the second doped semiconductor layer (900).

4. The light emitting device according to claim 1 or 2, characterized in that, ​ 5. The light emitting device according to claim 1 or 2, wherein ​ 6. The light emitting device according to claim 1 or 2, wherein ​ 7. A method for fabricating a light-emitting device, characterized in that, ​ ​ ​ ​ A light emitting structure layer is formed on a side surface of the gallium nitride column (500) away from the substrate layer (100), the light emitting structure layer comprising a first doped semiconductor layer (700), a light emitting layer (800) and a second doped semiconductor layer (900), the first doped semiconductor layer (700) being located on a side surface of the gallium nitride column (500) away from the substrate layer (100), the light emitting layer (800) being located on a side surface of the first doped semiconductor away from the gallium nitride column (500), the second doped semiconductor layer (900) being located on a side surface of the light emitting layer (800) away from the first doped semiconductor layer (700), the first doped semiconductor layer (700) and the second doped semiconductor layer (900) having opposite conductive types.

8. The light emitting device manufacturing method according to claim 7, wherein A porous structure is formed in a target region on the buffer layer (300), comprising: A dielectric layer (400) is arranged on a side surface of the buffer layer (300) away from the substrate layer (100), the dielectric layer (400) having a preset pattern, the preset pattern comprising a hole array composed of a plurality of through holes (401); The dielectric layer (400) is used as a mask, and ions are injected into the buffer layer (300) through the through holes (401) in the hole array to form a gallium nitride column (500); The gallium nitride column (500) is subjected to a porous treatment to form nanopores (501); The material of the buffer layer (300) comprises one or more of gallium nitride, indium nitride and gallium indium nitride, and the ions comprise one or more of silicon ions, germanium ions, boron ions, tellurium ions, iodine ions, carbon ions, phosphorus ions, arsenic ions, sulfur ions, antimony ions and tin ions.

9. The light emitting device manufacturing method according to claim 8, wherein The gallium nitride column (500) is formed by a local ion implantation process, the depth of the ion implantation is 0.1-0.8 μm, the ion concentration of the local ion implantation process is 10 18 order of magnitude.

10. The light emitting device manufacturing method according to claim 9, wherein The gallium nitride column (500) is subjected to a porous treatment by using an electrochemical etching process; The parameters of the electrochemical etching process include: the electrolyte used comprises oxalic acid, hydrofluoric acid or nitric acid, the concentration of the electrolyte is 0.1M-0.3M, the etching voltage is 8V-15V, and the negative electrode used comprises a platinum electrode or a gold electrode.

11. The light emitting device manufacturing method according to any one of claims 8 to 10, wherein Further comprising: After the light emitting structure layer is formed, the mask is removed to the first doped semiconductor layer (700), and an electrode is formed on the light emitting structure layer after the mask is removed.

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