A SiP chip for radio frequency and digital-analog hybrid circuits

Abstract

The present invention discloses a SiP chip of a radio frequency and digital-analog hybrid circuit, the chip includes at least one hybrid channel, each hybrid channel includes a radio frequency circuit and a digital-analog circuit; the radio frequency circuit includes a down-conversion module, an amplifier, a filter and a balun; the digital-analog circuit includes a dual-channel ADC chip; the down-conversion module is used to down-convert the received signal, and transmit it to the first port of the balun through the amplifier and the filter in sequence, the second port and the third port of the balun are respectively connected to the ADC chip, and the ADC chip outputs the signal externally; the fourth port of the balun is open or grounded as a ground terminal. The present invention adopts circuit and package collaborative design, and by designing the line width and line spacing of the balun, the overall performance of the SiP can be greatly improved.

Description

Technical Field

[0001] The present invention relates to the field of chips, and in particular to a SiP chip of a radio frequency and digital-analog hybrid circuit. Background Art

[0002] RF and mixed analog circuits are the core components of radar and communication system links. With the increasing demand for miniaturization of the entire system, RF and mixed analog circuits are increasingly implemented using SiP (System in Package). At present, when designing SiP, the selected chips are installed in a ceramic tube or plastic package in a two-dimensional or three-dimensional form using wire bond, flip chip, SMT, etc. to achieve certain system functions. However, this method only considers the realization of miniaturization, and does not consider the impact of packaging on circuit performance. Summary of the invention

[0003] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a SiP chip for radio frequency and mixed analog and digital circuits, which adopts circuit and package collaborative design and can greatly improve the overall performance of SiP by designing the line width and line spacing of the balun.

[0004] The objective of the present invention is achieved through the following technical scheme: a SiP chip of radio frequency and digital-analog hybrid circuit, comprising at least one hybrid channel, each hybrid channel comprising a radio frequency circuit and a digital-analog circuit; the radio frequency circuit comprises a down-conversion module, an amplifier, a filter and a balun; the digital-analog circuit comprises a dual-channel ADC chip; the down-conversion module is used to down-convert a received signal, and transmit it to the first port of the balun in sequence through the amplifier and the filter, the second port and the third port of the balun are respectively connected to the ADC chip, and the ADC chip outputs the signal externally; the fourth port of the balun is open or grounded as a ground terminal;

[0005] The balun includes two sets of symmetrical two-wire mutually wound coupling lines;

[0006] Each set of two-line mutually wound coupling lines includes two microstrip lines with the same line width; each microstrip line is formed by connecting multiple sub-microstrip lines from the inside to the outside, forming a 90-degree angle between two adjacent sub-microstrip lines;

[0007] In the two microstrip lines included in each set of two-line mutually wound coupling lines, the first sub-microstrip line of the first microstrip line and the first sub-microstrip line of the second microstrip line are parallel to each other;

[0008] The first end of the first microstrip line in the first group of mutually coupled lines is connected to the first end of the first microstrip line in the second group of mutually coupled lines;

[0009] In the first group of mutually coupled lines, the second end of the first microstrip line serves as the first port of the balun;

[0010] In the first set of mutually wound coupled lines, the first end of the second microstrip line serves as the second port of the balun;

[0011] In the second set of mutually coupled lines, the first end of the second microstrip line serves as the third port of the balun;

[0012] In the second group of mutually coupled lines, the second end of the first microstrip line is grounded or open circuited as the fourth port of the balun;

[0013] The second end of the second microstrip line in the first group of mutually coupled lines is connected to the second end of the second microstrip line in the second group of mutually coupled lines through a grounding hole.

[0014] The first channel of the ADC chip is used to receive the signal from the third port of the balun, and output it after analog-to-digital conversion; the second channel of the ADC chip is used to receive the signal from the second port of the balun, and output it after analog-to-digital conversion.

[0015] The radio frequency circuit is packaged through the upper substrate, and the digital-analog circuit is packaged through the lower substrate; when the upper substrate and the lower substrate are packaged, external BGA pins are reserved, and the upper substrate and the lower substrate are connected through the BGA pins to achieve electrical connection between the radio frequency circuit and the digital-analog circuit.

[0016] When designing the SiP chip, the line width and spacing of the double-wire interwinding coupling line are adjusted to reduce the odd-mode impedance, thereby adjusting the amplitude-phase imbalance of the SiP chip, so that the SiP chip maintains amplitude-phase balance.

[0017] The beneficial effects of the present invention are as follows: the present invention adopts a circuit and package collaborative design method, and can greatly improve the overall performance of the SiP chip by designing (or adjusting) the line width and line spacing of the balun. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is the overall principle block diagram of the present invention;

[0019] Figure 2 This is a schematic diagram of the structure of the balun;

[0020] Figure 3 It is a schematic diagram of the packaging structure of the present invention;

[0021] Figure 4 This is a schematic diagram of the typical structure of the Marchand balun;

[0022] Figure 5 This is the schematic diagram of the balun four-port network;

[0023] Figure 6It is a schematic diagram of the even-mode model of four ports;

[0024] Figure 7 It is a schematic diagram of a four-port analog model;

[0025] Figure 8 This is a schematic diagram of a double-wire interwound structure. DETAILED DESCRIPTION

[0026] The technical solution of the present invention is further described in detail below in conjunction with the accompanying drawings, but the protection scope of the present invention is not limited to the following.

[0027] like Figure 1 As shown, a SiP chip of radio frequency and digital-analog hybrid circuit includes at least one hybrid channel, each hybrid channel includes a radio frequency circuit and a digital-analog circuit; the radio frequency circuit includes a down-conversion module, an amplifier, a filter and a balun; the digital-analog circuit includes a dual-channel ADC chip; the down-conversion module is used to down-convert the received signal, and transmit it to the first port of the balun through the amplifier and the filter in sequence, the second port and the third port of the balun are respectively connected to the ADC chip, and the ADC chip outputs the signal to the outside; the fourth port of the balun is open or grounded as a ground terminal.

[0028] like Figure 2 As shown, the balun includes two groups of symmetrical two-wire mutually wound coupling lines;

[0029] Each set of two-line mutually wound coupling lines includes two microstrip lines with the same line width; each microstrip line is formed by connecting multiple sub-microstrip lines from the inside to the outside, forming a 90-degree angle between two adjacent sub-microstrip lines;

[0030] In the two microstrip lines included in each set of two-line mutually wound coupling lines, the first sub-microstrip line of the first microstrip line and the first sub-microstrip line of the second microstrip line are parallel to each other;

[0031] The first end of the first microstrip line in the first group of mutually coupled lines is connected to the first end of the first microstrip line in the second group of mutually coupled lines;

[0032] In the first set of mutually coupled lines, the second end of the first microstrip line serves as the first port (P1) of the balun;

[0033] In the first set of mutually coupled lines, the first end of the second microstrip line serves as the second port (P2) of the balun;

[0034] In the second set of mutually coupled lines, the first end of the second microstrip line serves as the third port (P3) of the balun;

[0035] In the second group of mutually coupled lines, the second end of the first microstrip line is grounded or open circuited as the fourth port (P4) of the balun;

[0036] The second end of the second microstrip line in the first group of mutually coupled lines is connected to the second end of the second microstrip line in the second group of mutually coupled lines through a grounding hole.

[0037] The radio frequency circuit is packaged through the upper substrate, and the digital-analog circuit is packaged through the lower substrate; when the upper substrate and the lower substrate are packaged, external BGA pins are reserved, and the upper substrate and the lower substrate are connected through the BGA pins to achieve electrical connection between the radio frequency circuit and the digital-analog circuit.

[0038] When designing the SiP chip, the line width and spacing of the double-wire interwinding coupling line are adjusted to reduce the odd-mode impedance, thereby adjusting the amplitude-phase imbalance of the SiP chip, so that the SiP chip maintains amplitude-phase balance.

[0039] In an embodiment of the present application, the RF circuit (also called the RF chipset) and the digital-to-analog circuit (also called the digital-to-analog chipset) are packaged together in a PoP (Package on Package) manner, which can reduce interconnection losses and improve signal amplitude and phase imbalance. The RF chipset is located in the upper layer of the PoP, called the upper substrate package, and includes a down-conversion module (mixer), an amplifier, a filter (surface acoustic wave filter) and a balun; the digital-to-analog chipset is located in the lower layer of the PoP, called the lower substrate package, and includes an ADC chip (analog-to-digital converter). The upper and lower substrates are respectively packaged in a plastic package to protect the chips. BGA pins are reserved at the bottom of the upper substrate and the top of the lower substrate when packaged. The upper and lower substrates are connected through the BGA pins to achieve electrical connection between the RF circuit and the digital-to-analog circuit. External BGA pins are also reserved at the bottom of the lower substrate for RF or power input. The overall PoP packaging model is as follows: Figure 3 shown.

[0040] The interconnection between the RF chipset and the analog-to-digital chipset is a differential signal. When using a conventional PCB format, the phase and amplitude of the differential signal will be unbalanced due to differences in routing consistency, and it will not be able to provide a perfect differential signal to the ADC. Especially when the sampling rate of the ADC is very high, the poor quality differential signal will deteriorate the SFDR and SNR of the entire chip at the system level.

[0041] The input of the RF chipset is a sinusoidal signal, expressed as , after passing through the balun at the back end of the RF chipset, it is converted into a pair (two) of differential signals , , which can be expressed as follows:

[0042] (1)

[0043] in, and Respectively represent , The amplitude, is the angular frequency, , f is the frequency, For time, is the phase deviation between the two differential signals.

[0044] Modeling the analog-to-digital chipset as a symmetric third-order transfer function :

[0045] (2)

[0046] So, is the DC bias, , , are the first-order, second-order and third-order harmonic coefficients respectively, and the output It can be expressed as:

[0047]

[0048] (3)

[0049] Because the signal output by the RF chipset is unbalanced, when only the amplitude is unbalanced, that is, , , then we have:

[0050] (4)

[0051] Similarly, substituting formula (4) into formula (3), we can get:

[0052] (5)

[0053] From equation (5), we can see that when the signal has amplitude imbalance, the differential signal input to the digital-analog chipset will introduce even harmonics and odd harmonics after being sampled, where the second harmonic amplitude is proportional to , the third harmonic amplitude is proportional to , which is related to the magnitude of imbalance.

[0054] Assume again that the output amplitude of the RF chipset is balanced, but the phase is unbalanced, that is , , then we have:

[0055] (6)

[0056] Substituting formula (6) into formula (3) again, we can obtain:

[0057] (7)

[0058] From equation (7), we can see that when the signal has phase imbalance, the differential signal input to the digital-analog chipset will introduce even harmonics and odd harmonics after being sampled, where the amplitude of the second harmonic is proportional to , the third harmonic amplitude is proportional to .

[0059] Therefore, the differential signal with amplitude imbalance output by the RF chipset will cause even harmonics and odd harmonics after passing through the digital-analog chipset. The amplitude of the second harmonic is proportional to the square difference of the differential signal amplitude, and the amplitude of the third harmonic is proportional to the sum of the cubes of the differential signal amplitude. The differential signal with phase imbalance output by the RF chipset will cause even harmonics and odd harmonics after being sampled by the digital-analog chipset. The amplitude of the second harmonic is proportional to the square of the differential signal amplitude, and the amplitude of the third harmonic is proportional to the cube of the differential signal amplitude.

[0060] A typical balun structure is as follows: Figure 4 As shown in the figure, it consists of two coupled lines with a length of λ / 4 (λ is the wavelength), P1 is the unbalanced input end, and P2 and P3 are the balanced output ends. One end of the two coupled lines is grounded, and one end is open or grounded. The circuit is a three-port device, and the other port can be regarded as an open circuit or a short circuit. The amplitude and phase imbalance is analyzed through the four-port network parameters.

[0061] The schematic diagram of the four-port network is as follows Figure 5 As shown, the odd-even mode analysis method is used to Figure 5 Perform analysis such as Figure 6 and Figure 7 shown.

[0062] In the figure, T is the transmission coefficient and Γ is the reflection coefficient;

[0063] Ideally, the input port is matched and the output port power is half of the input port, which is expressed in S parameters as: , , is the standing wave at port 1, is the loss from port 2 to port 1, For the loss from port 3 to port 1, using the balun's S parameter matrix theory, it can be derived that, ideally:

[0064] (8)

[0065] (9)

[0066] In formula (8), is the even-mode reflection coefficient of port 1, is the odd-mode reflection coefficient of port 1, is the even-mode transmission coefficient, let the three ports be open or short-circuited, that is, the three-port reflection coefficient Γ = ±1, and equation (8) can be simplified to:

[0067] (10)

[0068] According to the definition of reflection coefficient:

[0069] (11)

[0070] In formula (11) is the input impedance, is the output impedance in ohms, is the odd-mode output impedance. Substituting equation (11) into equation (10), we can obtain:

[0071] (12)

[0072] It can be obtained that when the port is in an ideal matching condition, for a 50 ohm system, equation (12) can be expressed as:

[0073] (13)

[0074] At the same time, it can be seen from formula (9) that , that is, the even-mode transmission coefficient is 0, and the even-mode impedance is infinite. Therefore, when designing the balun, it is necessary to increase the even-mode impedance as much as possible to suppress the common-mode signal transmission. From formula (13), it can be obtained that if port 3 is short-circuited, when the odd-mode impedance is close to 25 ohms, a large even-mode impedance can be obtained, which can make the differential signal lossless. Transmission, that is, the amplitude and phase balance of the differential signal is optimal.

[0075] The present invention adopts a double-wire mutually wound coupling line. Figure 8 The figure is a schematic diagram of a two-wire interwinding structure. The line width and line spacing of the coupling line interact with each other to affect the coupling degree, thereby adjusting the odd-mode impedance. At a specific operating frequency, the odd-mode impedance can be reduced by adjusting the line width and spacing of the coupling line, thereby adjusting the amplitude-phase imbalance.

[0076] When the line spacing is certain, the increase of line width increases the coupling degree, which can reduce the odd-mode impedance and improve the amplitude-phase imbalance; when the line width is certain, the smaller the line spacing is, the larger the coupling factor can be, the smaller the odd-mode impedance of the coupled line is, and the amplitude-phase imbalance is improved. In addition, in order to ensure the processing reliability, the line width and line spacing should have a considerable ratio. Therefore, the specific adjustment method is: when the amplitude-phase imbalance is large, the line width can be increased or the line spacing can be reduced within a certain range. The adjustment situation is shown in Table 1.

[0077] The present invention can adjust the amplitude and phase imbalance of the balun by adjusting the line width w and the line spacing s.

[0078] In addition, based on the typical marchand balun structure, this design further improves the amplitude and phase imbalance of the balun by adding a matching unit from the capacitor to the ground at the open port. Here, the amplitude and phase imbalance refers to the imbalance in a certain frequency band (the design frequency band is 420MHz~460MHz). After adding a capacitor of a certain value in a certain frequency band, due to the influence of the capacitance value, it suppresses signals in different frequency bands to different degrees, which will also adjust the coupling degree in different frequency bands and adjust the amplitude and phase imbalance.

[0079] Table 1 Effects of coupling line width, line spacing and matching capacitance on balun imbalance

[0080]

[0081] Through the above design, we can see that the chip balun can achieve better amplitude and phase imbalance through fine design. Finally, 17um line width and 8um line spacing are selected, and a 9pF matching capacitor is added to the open port, and finally 0.26dB amplitude imbalance and 0.08° phase imbalance are obtained. Compared with the conventional flux-coupled balun, taking Mini-Circuits' TC1-1-13M+ as an example, its amplitude imbalance is 1.15dB and phase imbalance is 0.85°, which is a great improvement.

[0082] Therefore, the present invention reduces odd-mode impedance by adjusting the line width and spacing of the double-wire interwinding coupling line during design, thereby adjusting the amplitude-phase imbalance of the SiP chip, so that the designed SiP chip maintains amplitude-phase balance.

Claims

1. A SiP chip for radio frequency and mixed analog and digital circuits, characterized in that: It includes at least one mixing channel, each mixing channel includes a radio frequency circuit and a digital-analog circuit; the radio frequency circuit includes a down-conversion module, an amplifier, a filter and a balun; the digital-analog circuit includes a dual-channel ADC chip; the down-conversion module is used to down-convert the received signal, and transmit it to the first port of the balun through the amplifier and the filter in sequence, the second port and the third port of the balun are respectively connected to the ADC chip, and the ADC chip outputs the signal externally; the fourth port of the balun is open or grounded as a ground terminal; The balun includes two sets of symmetrical two-wire mutually wound coupling lines; Each set of two-line mutually wound coupling lines includes two microstrip lines with the same line width; each microstrip line is formed by connecting multiple sub-microstrip lines from the inside to the outside, forming a 90-degree angle between two adjacent sub-microstrip lines; In the two microstrip lines included in each set of two-line mutually wound coupling lines, the first sub-microstrip line of the first microstrip line and the first sub-microstrip line of the second microstrip line are parallel to each other; The first end of the first microstrip line in the first group of mutually coupled lines is connected to the first end of the first microstrip line in the second group of mutually coupled lines; In the first group of mutually coupled lines, the second end of the first microstrip line serves as the first port of the balun; In the first group of mutually wound coupled lines, the first end of the second microstrip line serves as the second port of the balun; In the second set of mutually coupled lines, the first end of the second microstrip line serves as the third port of the balun; In the second group of mutually coupled lines, the second end of the first microstrip line is grounded or open-circuited as the fourth port of the balun; The second end of the second microstrip line in the first group of mutually coupled lines and the second end of the second microstrip line in the second group of mutually coupled lines are connected to the grounding hole; The radio frequency circuit is packaged through the upper substrate, and the digital-analog circuit is packaged through the lower substrate; When the upper substrate and the lower substrate are packaged, BGA pins are reserved for external use. The upper substrate and the lower substrate are connected through the BGA pins to achieve electrical connection between the radio frequency circuit and the digital-analog circuit; When designing the SiP chip, the line width and spacing of the double-wire interwinding coupling line are adjusted to reduce the odd-mode impedance, thereby adjusting the amplitude-phase imbalance of the SiP chip, so that the SiP chip maintains amplitude-phase balance.

2. The SiP chip of a radio frequency and digital-analog hybrid circuit according to claim 1, characterized in that: The first channel of the ADC chip is used to receive the signal from the third port of the balun, and output it after analog-to-digital conversion; the second channel of the ADC chip is used to receive the signal from the second port of the balun, and output it after analog-to-digital conversion.

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