A hardware implementation circuit for the SM3 algorithm

Abstract

This invention belongs to the field of SM3 algorithm hardware circuits, and relates to a hardware implementation circuit for the SM3 algorithm, comprising: a message expansion circuit for receiving a preset bit input and iteratively expanding it to obtain an iteratively expanded output; and a compression circuit for receiving the iteratively expanded output of the message expansion circuit and compressing it; the compression circuit is connected to the message expansion circuit. The SM3 algorithm hardware implementation circuit provided by this application saves the use of adders and XOR gates, reduces the use of compressors, saves related wiring resources and footprint, and simplifies circuit design.

Description

Technical Field

[0001] This invention relates to the field of SM3 algorithm hardware circuit technology, and in particular to a hardware implementation circuit for the SM3 algorithm. Background Technology

[0002] The rapid development of technologies such as cloud computing, artificial intelligence, and the Internet of Things has placed higher demands on data processing speed and data security in high-throughput data transmission.

[0003] Currently, the most common method for achieving high-security data transmission in China is to use secure chips with built-in cryptographic algorithms. The SM3 cryptographic hash algorithm is a cryptographic hash algorithm independently developed in my country. Its core content is to generate a 256-bit hash value by padding, expanding, and iteratively compressing a message of length 1 bit. This algorithm can be widely used in data integrity detection, digital signature verification, random number generation, and other fields.

[0004] Current research results include a complete hardware implementation circuit for the SM3 algorithm, mainly consisting of a message expansion circuit and a compression circuit. Analysis shows that this circuit significantly improves the high throughput of the SM3 algorithm; however, its complex structure and numerous components result in high cost, slow processing speed, and relatively low operating efficiency, thus requiring improvement. Summary of the Invention

[0005] In view of this, the present invention provides a hardware implementation circuit for the SM3 algorithm.

[0006] Specifically, the present invention is achieved through the following technical solution:

[0007] According to a first aspect of the present invention, a hardware implementation circuit for the SM3 algorithm is provided, comprising:

[0008] The message expansion circuit is used to receive a preset bit input and iteratively expand it to obtain an iteratively expanded output;

[0009] A compression circuit is used to receive the iterative expansion output of the message expansion circuit and compress it; the compression circuit is connected to the message expansion circuit.

[0010] Optionally, the message extension circuit includes: a first input port, a second input port, a first data selector, a register, an XOR device, and an output port, wherein the first data selector is connected to the first input port, the second input port, the register, and the XOR device, and the XOR device is connected to the output port.

[0011] Optionally, the message extension circuit further includes: a third input port, a fourth input port, a second data selector, and a first extension chip, wherein the fourth input port is connected to the first extension chip, and the second data selector is connected to the third input port, the first extension chip, the register, and the XOR device, respectively.

[0012] Optionally, the message extension circuit further includes: a fifth input port, a sixth input port, a third data selector, and a second extension chip, wherein the fifth input port is connected to the second extension chip, and the third data selector is connected to the fifth input port, the second extension chip, the register, and the XOR device, respectively.

[0013] Optionally, the compression circuit includes a first compression circuit and a second compression circuit, wherein the first compression circuit is connected to the second compression circuit.

[0014] Optionally, the first compression circuit includes: a first compression input port, a second compression input port, a first compression data selector, a first additive compressor, a first compression register, a second compression register, and a first compression output port, wherein the first compression input port is connected to the first compression register and the first compression data selector, the first compression data selector is connected to the second compression input port and the first additive compressor, and the second compression register is connected to the first additive compressor, the first compression register, and the first compression output port.

[0015] Optionally, the first compression circuit further includes: a third compression input port, a fourth compression input port, and a second compression data selector, wherein the second compression data selector is connected to the third compression input port, the fourth compression input port, and the first additive compressor, respectively.

[0016] Optionally, the first compression circuit further includes a fifth compression input port, a sixth compression input port, and a third compression data selector, wherein the third compression data selector is connected to the fifth compression input port, the sixth compression input port, and the first additive compressor, respectively.

[0017] Optionally, the second compression circuit includes: a first sub-compression input port, a second sub-compression input port, a first sub-compression data selector, a second adder compressor, a first sub-compression register, and a first sub-compression output port, wherein the first sub-compression data selector is connected to the first sub-compression input port, the second sub-compression input port, and the second adder compressor, respectively, and the first sub-compression register is connected to the second adder compressor and the first sub-compression output port, respectively.

[0018] Optionally, the second compression circuit further includes: a third sub-compression input port, a fourth sub-compression input port, and a second sub-compression data selector, wherein the second sub-compression data selector is connected to the second additive compressor, the third sub-compression input port, and the fourth sub-compression input port, respectively.

[0019] The technical solution provided by this invention brings at least the following beneficial effects:

[0020] The hardware implementation circuit of the SM3 algorithm provided in this application saves the use of adders and XOR gates, and also reduces the use of compressors, saving related wiring resources and space, and simplifying circuit design. Attached Figure Description

[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0023] Figure 1 A schematic diagram of a message extension circuit in a hardware implementation circuit of the SM3 algorithm provided in an embodiment of the present invention;

[0024] Figure 2 A schematic diagram of the first compression circuit in a hardware implementation circuit of the SM3 algorithm provided in an embodiment of the present invention;

[0025] Figure 3 A schematic diagram of the second compression circuit in a hardware implementation circuit of the SM3 algorithm provided in an embodiment of the present invention;

[0026] Figure 4 This is a schematic diagram of a hardware implementation circuit for the SM3 algorithm provided in an embodiment of the present invention. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0028] Reference Figure 1-4 As shown, this application provides a hardware implementation circuit for the SM3 algorithm, including:

[0029] The message expansion circuit is used to receive a preset bit input and iteratively expand it to obtain an iteratively expanded output;

[0030] A compression circuit is used to receive the iterative expansion output of the message expansion circuit and compress it; the compression circuit is connected to the message expansion circuit.

[0031] In this embodiment, the compression circuit receives the iterative expansion output of the message expansion circuit and compresses it. In the message expansion circuit, the SM3 algorithm requires 132 32-bit inputs, expanding the original 512-bit message through 64 rounds of iterative expansion. Since the calculation method for each 32 inputs is the same, only the flowchart of the value obtained from the iterative expansion is shown here. This circuit uses three 2-to-1 data selectors and one adder to generate an additional 32-bit message from each of the original 16 32-bit messages. In actual operation, the circuit only needs to calculate the sum value by designing and controlling the value (which is controlled by an external timing circuit). Compared to the original round expansion circuit, this saves the use of an XOR gate circuit, as well as related logic gates and wiring resources. In the compression circuit, 64 rounds of iteration are performed with an initial value of 256 bits (the initial value is a fixed initial vector during the first compression). Each round of iteration receives the expanded message provided by the message expansion circuit, obtaining a 256-bit hash value. The compression circuit treats the 256-bit variable as eight 32-bit variables sequentially, and each iteration of compression generates eight new 32-bit variables. The circuit only needs to calculate the values ​​of E and A, while the other six variables are generated without any resources, either through simple assignment or circular shifting.

[0032] For example, the message extension circuit includes: a first input port Wi+7, a second input port Wi+10, a first data selector, a register C0, an XOR device, and an output port Pi, wherein the first data selector is connected to the first input port Wi+7, the second input port Wi+10, the register C0, and the XOR device, and the XOR device is connected to the output port Pi.

[0033] In this embodiment, the data from the first input port Wi+7 and the second input port Wi+10 are processed by the first data selector, register C0, and XOR, and then output through the output port Pi.

[0034] For example, the message extension circuit further includes: a third input port Wi, a fourth input port Wi+3, a second data selector, and a first extension chip, wherein the fourth input port Wi+3 is connected to the first extension chip, and the second data selector is connected to the third input port Wi, the first extension chip, the register C0, and the XOR device.

[0035] In this embodiment, the data from the fourth input port Wi+3 enters the first expansion chip, and then enters the second data selector together with the data from the third input port Wi.

[0036] For example, the message extension circuit further includes: a fifth input port Wi+13, a sixth input port WP, a third data selector, and a second extension chip, wherein the fifth input port Wi+13 is connected to the second extension chip, and the third data selector is connected to the fifth input port Wi+13, the second extension chip, the register C0, and the XOR device.

[0037] In this embodiment, the data from the fifth input port Wi+13 enters the second expansion chip, and then enters the third data selector together with the data from the sixth input port WP.

[0038] For example, the compression circuit includes: a first compression circuit and a second compression circuit, wherein the first compression circuit is connected to the second compression circuit.

[0039] In the embodiments of this application, the first compression circuit and the second compression circuit work together to iteratively expand and compress the received message expansion circuit output.

[0040] For example, the first compression circuit includes: a first compression input port A<<<12, a second compression input port H+Wj, a first compression data selector, a first adder compressor, a first compression register, a second compression register, and a first compression output port En, wherein the first compression input port is connected to the first compression register and the first compression data selector, the first compression data selector is connected to the second compression input port and the first adder compressor, and the second compression register is connected to the first adder compressor, the first compression register, and the first compression output port En.

[0041] In this embodiment of the application, the input data from the first compression input port A<<<12 and the second compression input port H+Wj are processed and output from the first compression output port En.

[0042] For example, the first compression circuit further includes: a third compression input port E, a fourth compression input port GGj (E, F, G) and a second compression data selector 3-2CSA, wherein the second compression data selector is connected to the third compression input port, the fourth compression input port and the first additive compressor respectively.

[0043] In this embodiment, the data input from the third compression input port E and the fourth compression input port GGj (E, F, G) enters the second compression data selector 3-2CSA.

[0044] For example, the first compression circuit further includes: a fifth compression input port Tj<<<j, a sixth compression input port SS1, and a third compression data selector, wherein the third compression data selector is connected to the fifth compression input port, the sixth compression input port, and the first additive compressor, respectively.

[0045] In this embodiment, the data input from the fifth compression input port Tj<<<j and the sixth compression input port SS1 enters the third compression data selector.

[0046] For example, the second compression circuit includes: a first sub-compression input port H, a second sub-compression input port Wj', a first sub-compression data selector, a second adder compressor 4-2CSA, a first sub-compression register, and a first sub-compression output port An, wherein the first sub-compression data selector is connected to the first sub-compression input port, the second sub-compression input port, and the second adder compressor, respectively, and the first sub-compression register is connected to the second adder compressor and the first sub-compression output port, respectively.

[0047] In this embodiment of the application, the input data from the first sub-compression input port H and the second sub-compression input port Wj' are processed and output from the first sub-compression output port An.

[0048] For example, the second compression circuit further includes: a third sub-compression input port Wj, a fourth sub-compression input port D, and a second sub-compression data selector, wherein the second sub-compression data selector is connected to the second additive compressor, the third sub-compression input port, and the fourth sub-compression input port, respectively.

[0049] In this embodiment, the data input from the third sub-compression input port Wj and the fourth sub-compression input port D enters the second sub-compression data selector.

[0050] The schematic diagram of the compression circuit proposed in this patent is as follows: Figure 2 and Figure 3As shown, the compression circuit is divided into two independent circuit modules, used to implement the calculation of and , and related intermediate values, respectively. The intermediate values ​​include the calculation of and . Its main advantages are: First, by using a 3-2 compressor, a 2-to-1 data selector, and a 4-2 adder compressor, more than two variables are compressed into two variables before addition, reducing the use of adders, thus reducing the critical path, simplifying the circuit structure, and improving the running speed. Second, the calculation of and is achieved by controlling three 2-to-1 data selectors, sharing the same 3-2 compressor, and then performing the addition operation. Simultaneously, the calculation of is achieved by adding two zeros to form four input terminals, allowing it to share a 4-2 adder compressor with the calculation of the A value, greatly saving resources. The final overall architecture of the compression circuit is shown below. Figure 4 As shown.

[0051] The hardware implementation circuit of the SM3 algorithm provided in this application saves the use of adders and XOR gates, and also reduces the use of compressors, saving related wiring resources and space, and simplifying circuit design.

[0052] It should be noted that in this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are mainly for the purpose of better describing this application and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0053] Furthermore, in addition to indicating location or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0054] Furthermore, the terms "installation," "setup," "equipped with," "connection," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0055] Furthermore, the terms "first," "second," etc., are primarily used to distinguish different devices, elements, or components (which may be the same or different in specific type and construction), and are not intended to indicate or imply the relative importance or quantity of the indicated devices, elements, or components. Unless otherwise stated, "a plurality of" means two or more.

[0056] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A hardware implementation circuit for the SM3 algorithm, characterized in that, include: The message expansion circuit is used to receive a preset bit input and iteratively expand it to obtain an iteratively expanded output; A compression circuit is used to receive the iterative expansion output of the message expansion circuit and compress it; The compression circuit is connected to the message expansion circuit; The message extension circuit includes: a first input port, a second input port, a first data selector, a register, an XOR device, and an output port, wherein the first data selector is connected to the first input port, the second input port, the register, and the XOR device, and the XOR device is connected to the output port. The message extension circuit further includes: a third input port, a fourth input port, a second data selector, and a first extension chip, wherein the fourth input port is connected to the first extension chip, and the second data selector is connected to the third input port, the first extension chip, the register, and the XOR device respectively; The message extension circuit further includes: a fifth input port, a sixth input port, a third data selector, and a second extension chip, wherein the fifth input port is connected to the second extension chip, and the third data selector is connected to the fifth input port, the second extension chip, the register, and the XOR device.

2. The hardware implementation circuit of the SM3 algorithm according to claim 1, characterized in that, The compression circuit includes a first compression circuit and a second compression circuit, wherein the first compression circuit is connected to the second compression circuit.

3. The hardware implementation circuit of the SM3 algorithm according to claim 2, characterized in that, The first compression circuit includes: a first compression input port, a second compression input port, a first compression data selector, a first additive compressor, a first compression register, a second compression register, and a first compression output port. The first compression input port is connected to the first compression register and the first compression data selector, the first compression data selector is connected to the second compression input port and the first additive compressor, and the second compression register is connected to the first additive compressor, the first compression register, and the first compression output port.

4. The hardware implementation circuit of the SM3 algorithm according to claim 3, characterized in that, The first compression circuit further includes a third compression input port, a fourth compression input port, and a second compression data selector, wherein the second compression data selector is connected to the third compression input port, the fourth compression input port, and the first additive compressor, respectively.

5. The hardware implementation circuit of the SM3 algorithm according to claim 3, characterized in that, The first compression circuit further includes a fifth compression input port, a sixth compression input port, and a third compression data selector, wherein the third compression data selector is connected to the fifth compression input port, the sixth compression input port, and the first additive compressor, respectively.

6. The hardware implementation circuit of the SM3 algorithm according to claim 2, characterized in that, The second compression circuit includes: a first sub-compression input port, a second sub-compression input port, a first sub-compression data selector, a second adder compressor, a first sub-compression register, and a first sub-compression output port, wherein the first sub-compression data selector is connected to the first sub-compression input port, the second sub-compression input port, and the second adder compressor, respectively, and the first sub-compression register is connected to the second adder compressor and the first sub-compression output port, respectively.

7. The hardware implementation circuit of the SM3 algorithm according to claim 6, characterized in that, The second compression circuit further includes: a third sub-compression input port, a fourth sub-compression input port, and a second sub-compression data selector, wherein the second sub-compression data selector is connected to the second additive compressor, the third sub-compression input port, and the fourth sub-compression input port, respectively.

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