An Internet of Things-based chip production process supervision system and method

Abstract

The present invention discloses a supervision system and method for the chip production process based on the Internet of Things, belonging to the technical field of data supervision. The present invention collects chip production process data, transmits it to a database for label assignment operation on the warehoused data, and constructs a corresponding data set; retrieves chip data with a completed basic production structure, conducts surface defect image data analysis and electrical property defect analysis for each chip, obtains the analysis results and extracts the corresponding characteristic data to generate corresponding characteristic defect vectors; combines the surface defect characteristic vectors and electrical defect characteristic vectors for associated defect analysis, judges the associated influence degree between the surface defect and the electrical defect of the current chip according to the analysis results, and conducts a double defect judgment on the current chip through the judgment results; combines the chip defect analysis results of the current production batch to conduct a fault analysis on the chip production process stage, and feeds back the process fault analysis results and the chip defect analysis results to the manual terminal for data.

Description

Technical Field

[0001] The present invention relates to the technical field of data supervision, and specifically provides a supervision system and method for the chip production process based on the Internet of Things. Background Art

[0002] The supervision of the chip production process is an essential link in semiconductor manufacturing. Its core purpose is to ensure product quality, performance, and reliability, while meeting market demands, regulatory requirements, and corporate strategic goals.

[0003] In the current environment, the supervision of chip production is relatively strict. Chip manufacturers determine the quality of chips through precise observation and testing before leaving the factory, and eliminate defective chips. However, this model is not perfect. In the existing environment, detecting and screening new products can ensure the usability of chips to a certain extent, but there is a lack of data mining for defective chips, and it is impossible to determine whether the abnormal operation of defective chips is entirely caused by the observed defects. Therefore, it is impossible to determine whether there are hidden defects, which is not conducive to fault discovery in the entire chip production line. Summary of the Invention

[0004] The purpose of the present invention is to provide a supervision system and method for the chip production process based on the Internet of Things to solve the problems raised in the above background art.

[0005] To solve the above technical problems, the present invention provides the following technical solutions:

[0006] A supervision method for the chip production process based on the Internet of Things, the method comprising the following steps:

[0007] S100. Collect data from each chip production process segment, comprehensively transmit it to the database, and assign attribute tags to each data for storage, thereby constructing a corresponding chip data set.

[0008] S200. Retrieve data of chips that have completed the basic production structure, analyze the surface defect image data and electrical property defects of each chip, obtain the defect analysis results of each chip, and extract the corresponding feature data to generate a corresponding feature defect vector for each chip.

[0009] S300. Combine the surface defect feature vectors and electrical defect feature vectors of each chip for associated defect analysis, judge the associated influence degree between the surface defect and the electrical defect of the current chip according to the analysis result, and perform a double-defect judgment on the current chip based on the judgment result; the double-defect judgment is to judge whether there are hidden defects in the current chip according to the associated analysis.

[0010] S400 performs fault analysis on the chip production process stage based on the chip defect analysis results of the current production batch, and feeds back the process fault analysis results and the chip defect analysis results to the manual end for data.

[0011] The specific steps for the S100 to collect data from each chip production process segment, comprehensively transmit it to the database, and assign attribute tags to each data for storage in the database to construct the corresponding chip data set are as follows:

[0012] S101: Install inductive sensing device at each process segment of the chip production line. When a chip wafer is detected, record the time point, the sequence number data of the current chip wafer, and the production operation type data. The sequence number data is the position data of the current chip wafer in the current production line. Combine and transmit the data recorded for each chip wafer at each process segment on the production line to the database.

[0013] S102: When the chip data is stored in the database, use the stored sequence number data as the retrieval header tag in the chip library, and generate sub-clue tags by extending the header tag. Each sub-clue tag consists of the production operation type data of the chip and the implementation time period corresponding to the generated operation type. Use the header tag of each chip data as the header node, and the corresponding sub-clue tags as associated sub-nodes to generate corresponding element nodes, and comprehensively generate a data set of chip data for the current batch of chips by combining the element nodes of each chip in the current batch.

[0014] The specific steps for the S200 to retrieve data of the chips that have completed the basic production framework, perform surface defect image data analysis and electrical property defect analysis on each chip, obtain the defect analysis results of each chip, and extract the corresponding characteristic data to generate the corresponding characteristic defect vector for each chip are as follows:

[0015] S201. Retrieve data of the chips that have completed the basic production infrastructure from the database; the chips that have completed the basic production infrastructure refer to the chips that have completed the basic production type operations of the product and are facing the packaging step; determine the production data of each chip in each production type operation on the production line according to the retrieved data, and detect the surface defect image data and electrical property defects of the chips by combining the generation data of each chip; extract the surface images of each chip, and input the extracted image data into the surface defect image analysis model; conduct power-on experiments on each chip, obtain the electrical operation data of the corresponding chips according to the experimental data, and input the operation data into the corresponding electrical property defect analysis model; the surface defect image analysis model is a defect analysis model constructed by the corresponding chip staff using a big data model in combination with the defect type data corresponding to a large number of chip defect surface data images and the corresponding defect image feature data; the electrical property defect analysis model is an electrical defect analysis model constructed by chip staff through a large number of electrical experiments on chips, obtaining the electrical property operation data of each chip, fitting the corresponding electrical property operation curve by combining time data, and analyzing according to the curve evolution.

[0016] S202. Perform defect analysis output on each chip according to the surface defect image analysis model and the electrical property defect analysis model, and obtain the surface defect type data and defect image coordinate data of the corresponding chips and the electrical defect type and defect time curve data of the corresponding chips; respectively perform feature data conversion on the surface defect data and electrical defect data of each chip to obtain the feature vector data of the corresponding defects; the conversion calculation formulas are respectively where and are the surface defect feature vector and electrical defect feature vector of the corresponding chips respectively; s n is the area of each surface defect of the chip; s all is the total area of the surface defects of the chip; is the defect type data of each surface defect of the chip; α is the surface defect type; n is the number of surface defects of the chip; is the vector constructed by the coordinates of the two endpoints with the largest distance in each surface defect image of the chip; y m is the curve amplitude of each electrical defect of the chip; y all is the total curve amplitude of the electrical defects of the chip; is the curve type data of each electrical defect of the chip; β is the electrical defect type; m is the number of electrical defects of the chip; is the vector constructed by the coordinates of two time points of each defect curve segment in the electrical defect curve of the chip; i and u are constants; since there may be multiple surface defects and electrical defects in the chip, area ratio and amplitude ratio are introduced as balance coefficients to perform vector conversion calculation on each defect respectively.

[0017] The S300 combines the surface defect feature vectors and electrical defect feature vectors of each chip to perform associated defect analysis, and determines the associated influence degree between the surface defects and electrical defects of the current chip according to the analysis results. The specific steps for performing double-defect judgment on the current chip based on the judgment results are as follows:

[0018] S301. Map the surface defect feature vectors of the corresponding chip and the electrical defect vectors to the same plane respectively to obtain the included angle data between each surface defect vector and each electrical defect vector; perform associated influence analysis on each surface defect with respect to each electrical defect in combination with the included angle data. The calculation formula is Where is the influence degree of each surface defect with respect to each electrical defect; is the mapping included angle between each surface defect vector and each electrical defect vector respectively; if then it is determined that the corresponding surface defect has a strong correlation influence on the corresponding electrical defect; if then it is determined that the corresponding surface defect has a weak correlation influence on the corresponding electrical defect; where G re is the system preset value;

[0019] S302. According to the influence analysis of different surface defects on each electrical defect, perform associated influence analysis on the comprehensive surface defect data of the chip and the comprehensive electrical defect data. The calculation formula is Where ComG is the associated influence degree of the comprehensive surface defect data of the chip on the comprehensive electrical defect data; is the included angle constructed after mapping the surface defect feature vector and the electrical defect feature vector of the chip to the same plane; is the number of influence degrees of each surface defect that has a strong correlation influence on the corresponding electrical defect with respect to each electrical defect; n*m is the total number of calculations of the influence degrees of each surface defect with respect to each electrical defect;

[0020] S303. Combine the associated influence analysis results of the comprehensive surface defect data of the chip on the comprehensive electrical defect data to perform double-defect judgment on the chip; if ComG < ComG re , then it is determined that the current chip has potential defect; if ComG ≥ ComG re , then it is determined that the current chip does not have potential defect; where ComG re is the system preset value; since the electrical operation defects of the chip are generally caused by defects in the manufacturing of the chip itself, if the influence of the current observable surface defects on the electrical defects is less than the calculation threshold, it means that the defects affecting the electrical defects of the current chip are not only the observable surface defect part, so the current chip has potential defect.

[0021] The S400 performs a fault analysis on the chip production process stage in combination with the chip defect analysis results of the current production batch. The specific steps for manually feeding back the chip defect analysis results and the process fault analysis results are as follows:

[0022] S401. Perform a fault analysis on the chip production process stage by analyzing the proportion of chips with potential defects in the current batch of chips. The calculation formula is where Q is the quantity proportion of potential-defect chips in the corresponding batch; M(ht) is the quantity of potential-defect chips in the current batch; M all is the quantity of chips in the current batch; if Q < Q re , then perform a fault analysis on the production operations that cause surface defects in the chips; if Q ≥ Q re , then it is recommended to stop the production line and conduct a comprehensive inspection;

[0023] S402. Feed back and display the chip defect analysis results and the process fault analysis results through the manual supervision port.

[0024] An Internet-of-Things-based chip production process supervision system, the system includes a chip data storage module, a defect feature vector generation module, a defect correlation analysis module, and a fault feedback analysis module;

[0025] The chip data storage module collects data through each chip production process segment, and comprehensively transmits it to the database and assigns attribute tags to each data for storage, constructing a corresponding chip data set; the defect feature vector generation module retrieves data for the chips that have completed the basic production framework, performs surface defect image data analysis and electrical property defect analysis on each chip, obtains the defect analysis results of each chip, and extracts the corresponding feature data to generate the corresponding feature defect vectors for each chip; the defect correlation analysis module performs associated defect analysis by combining the surface defect feature vectors and electrical defect feature vectors of each chip, judges the associated influence degree between the surface defects and electrical defects of the current chip according to the analysis results, and performs a double-defect judgment on the current chip through the judgment results; the double-defect judgment is to judge whether there are potential defects in the current chip according to the correlation analysis; the fault feedback analysis module performs a fault analysis on the chip production process stage in combination with the chip defect analysis results of the current production batch, and feeds back the process fault analysis results and the chip defect analysis results to the manual terminal.

[0026] The chip data storage module includes a chip data acquisition unit and a data storage unit; the chip data acquisition unit installs inductive sensing devices at each process section of the chip production line. When a chip wafer is detected, it records the time point, the sequence data of the current chip wafer, and the production operation type data; the sequence data is the position data of the current chip wafer in the current production line; the data recorded by each chip wafer at each process section on the production line is integrated and transmitted to the database; when the chip data is stored, the data storage unit uses the storage sequence data as the retrieval head tag in the chip library and generates sub-clue tags by extending the head tag; each sub-clue tag consists of the production operation type data of the chip and the implementation time period corresponding to the generated operation type; using the head tag of each chip data as the head node and the corresponding sub-clue tag as the associated sub-node to generate the corresponding element node, and integrating the element nodes of each chip in the current batch to generate a data set of the corresponding batch of chip data.

[0027] The defect feature vector generation module includes a defect detection unit and a defect feature vector construction unit; the defect detection unit retrieves data of the chips that have completed the basic production structure from the database; determines the production data of each chip in each production type operation on the production line according to the retrieved data, and combines the generated data of each chip to detect the surface defect image data and electrical property defects of the chip; extracts the surface images of each chip and inputs the extracted image data into the surface defect image analysis model; conducts a power-on experiment on each chip, obtains the electrical operation data of the corresponding chip according to the experimental data, and inputs the operation data into the corresponding electrical property defect analysis model; the defect feature vector construction unit outputs defect analysis for each chip according to the surface defect image analysis model and the electrical property defect analysis model, and obtains the surface defect type data, defect image coordinate data of the corresponding chip, and the electrical defect type and defect time curve data of the corresponding chip; respectively performs feature data conversion on the surface defect data and electrical defect data of each chip to obtain the feature vector data of the corresponding defect.

[0028] The defect correlation analysis module includes a defect correlation analysis unit, a comprehensive correlation degree analysis unit, and a dual judgment unit; the defect correlation analysis unit maps the surface defect feature vectors of the corresponding chips and the electrical defect vectors in the same plane respectively to obtain the included angle data between each surface defect vector and each electrical defect vector; analyzes the correlation influence of each surface defect on each electrical defect in combination with the included angle data; judges the correlation influence of the corresponding surface defect on the corresponding electrical defect according to the analysis result; the comprehensive correlation degree analysis unit analyzes the correlation influence of the comprehensive surface defect data of the chip on the comprehensive electrical defect data according to the influence of different surface defects on each electrical defect; the dual judgment unit combines the analysis result of the correlation influence of the comprehensive surface defect data of the chip on the comprehensive electrical defect data to perform a dual defect judgment on the chip.

[0029] The fault feedback analysis module includes a production process fault analysis unit and a data feedback unit; the production process fault analysis unit analyzes the proportion of chips with potential defects in the current batch of chips to perform fault analysis on the chip production process stage; the data feedback unit feeds back and displays the chip defect analysis result and the process fault analysis result through the manual supervision port.

[0030] Compared with the prior art, the beneficial effects achieved by the present invention are as follows: The present invention realizes data collection, marking, defect detection, defect correlation analysis, and fault feedback analysis in the chip production process through multiple module units; further conducts correlation analysis on defects on the basis of conventional chip defect detection, can determine the correlation influence of each surface defect on its electrical operation, deeply excavates the correlation between the surface defects and electrical defects of each chip, so as to obtain whether there are potential defects in the corresponding chip according to the causal relationship between the defects; locates and analyzes the faults of the chip production line by determining potential defects and combining the chip production batch data, and gives fault analysis suggestions in the corresponding situation. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The drawings are used to provide a further understanding of the present invention, and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention, and do not constitute a limitation to the present invention. In the drawings:

[0032] Figure 1 is a schematic structural diagram of a chip production process supervision system based on the Internet of Things according to the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0033] Next, in combination with the accompanying drawings in the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0034] Please refer to Figure 1 , the present invention provides a technical solution:

[0035] A method for supervising the chip production process based on the Internet of Things, the method comprising the following steps:

[0036] S100. Collect data from each chip production process segment, perform comprehensive transmission to the database, and assign attribute tags to each data for storage in the database, thereby constructing a corresponding chip data set;

[0037] S200. Retrieve data of the chips that have completed the basic production infrastructure, perform surface defect image data analysis and electrical property defect analysis on each chip, obtain the defect analysis results of each chip, and extract the corresponding feature data to generate the corresponding feature defect vectors for each chip;

[0038] S300. Perform associated defect analysis by combining the surface defect feature vectors and electrical defect feature vectors of each chip, judge the associated influence degree between the surface defects and electrical defects of the current chip according to the analysis results, and perform double-defect judgment on the current chip based on the judgment results; the double-defect judgment is to judge whether there are potential defect problems with the current chip according to the associated analysis;

[0039] S400. Combine the chip defect analysis results of the current production batch to perform fault analysis on the chip production process stage, and feed back the process fault analysis results and chip defect analysis results to the manual terminal for data.

[0040] The specific steps of S100 for collecting data from each chip production process segment, performing comprehensive transmission to the database, and assigning attribute tags to each data for storage in the database to construct a corresponding chip data set are as follows:

[0041] S101. Install inductive sensing devices at each process segment of the chip production line. When a chip wafer is detected, record the time point, the position data of the current chip wafer, and the production operation type data; the position data is the position data of the current chip wafer on the current production line; comprehensively combine the data recorded for each chip wafer at each process segment on the production line and transmit it to the database for aggregation;

[0042] S102. When storing chip data in the database, use the storage sequence data as the retrieval header tag in the chip library, and generate sub-thread tags by extending the header tag; each sub-thread tag consists of the production operation type data of the chip and the implementation time period corresponding to the generated operation type; use the header tag of each chip data as the header node, and use the corresponding sub-thread tag as the associated sub-node to generate the corresponding element node, and comprehensively generate the data set of the chip data of the current batch for each element node of the chips in the current batch.

[0043] The specific steps for S200 to retrieve data for the chips that have completed the basic production architecture, perform surface defect image data analysis and electrical property defect analysis for each chip, obtain the defect analysis results of each chip, and extract the corresponding feature data to generate the corresponding feature defect vector for each chip are as follows:

[0044] S201. Retrieve data for the chips that have completed the basic production architecture in the database; determine the production data of each chip for each production type operation on the production line according to the retrieved data, and perform surface defect image data detection and electrical property defect detection on the chips in combination with the generated data of each chip; extract the surface images of each chip, and input the extracted image data into the surface defect image analysis model; perform a power-on experiment on each chip, obtain the electrical operation data of the corresponding chip according to the experimental data, and input the operation data into the corresponding electrical property defect analysis model.

[0045] S202. Output defect analysis for each chip according to the surface defect image analysis model and the electrical property defect analysis model, obtain the surface defect type data and defect image coordinate data of the corresponding chip, and the electrical defect type and defect time curve data of the corresponding chip; perform feature data conversion on the surface defect data and electrical defect data of each chip respectively to obtain the feature vector data of the corresponding defect; the conversion calculation formulas are respectively Where and are the surface defect feature vector and electrical defect feature vector of the corresponding chip respectively; s n is the area of each surface defect of the chip; s all is the total area of the surface defects of the chip; is the defect type data of each surface defect of the chip; α is the surface defect type; n is the number of surface defects of the chip; is the vector constructed by the coordinates of the two endpoints with the largest distance in each surface defect image of the chip; y m is the curve amplitude of each electrical defect of the chip; y all is the total curve amplitude of the electrical defects of the chip; is the curve type data of each electrical defect of the chip; β is the electrical defect type; m is the number of electrical defects of the chip; A vector constructed from the coordinates of two time - segment points of each defect curve segment in the electrical defect curve of the chip; i and u are constants.

[0046] The S300 combines the surface defect feature vectors and electrical defect feature vectors of each chip for associated defect analysis, and determines the associated influence degree between the surface defects and electrical defects of the current chip according to the analysis results. The specific steps for performing double - defect judgment on the current chip through the judgment results are as follows:

[0047] S301. Map the surface defect feature vectors and electrical defect vectors of the corresponding chip to the same plane respectively to obtain the included - angle data between each surface defect vector and each electrical defect vector; perform an associated influence analysis of each surface defect on each electrical defect in combination with the included - angle data. Its calculation formula is Where is the influence degree of each surface defect on each electrical defect; is the mapping included - angle between each surface defect vector and each electrical defect vector; if then it is determined that the corresponding surface defect has a strong correlation influence on the corresponding electrical defect; if then it is determined that the corresponding surface defect has a weak correlation influence on the corresponding electrical defect; where G re is the system preset value;

[0048] S302. According to the influence analysis of different surface defects on each electrical defect, perform an associated influence analysis on the comprehensive surface defect data and comprehensive electrical defect data of the chip. Its calculation formula is Where ComG is the associated influence degree of the comprehensive surface defect data of the chip on the comprehensive electrical defect data; is the included - angle constructed after mapping the surface defect feature vector and electrical defect feature vector of the chip to the same plane; is the number of influence degrees of each surface defect that has a strong correlation influence on the corresponding electrical defect on each electrical defect; n*m is the total number of calculations of the influence degrees of each surface defect on each electrical defect;

[0049] S303. Combine the associated influence analysis results of the comprehensive surface defect data of the chip on the comprehensive electrical defect data to perform double - defect judgment on the chip; if ComG < ComG re , then it is determined that the current chip has potential defect; if ComG ≥ ComG re , then it is determined that the current chip has no potential defect; where ComG re is the system preset value.

[0050] The S400 performs a fault analysis on the chip production process stage in combination with the chip defect analysis results of the current production batch. The specific steps for manually feeding back the chip defect analysis results and the process fault analysis results are as follows:

[0051] S401. Perform a fault analysis on the chip production process stage by analyzing the proportion of chips with potential defects in the current batch of chips. The calculation formula is where Q is the quantity proportion of potential-defect chips in the corresponding batch; M(ht) is the quantity of potential-defect chips in the current batch; M all is the quantity of chips in the current batch; if Q < Q re , then perform a fault analysis on the production operations that cause surface defects in the chips; if Q ≥ Q re , then it is recommended to stop the production line and conduct a comprehensive inspection;

[0052] S402. Feed back and display the chip defect analysis results and the process fault analysis results through the manual supervision port.

[0053] An Internet-of-Things-based chip production process supervision system, the system includes a chip data warehousing module, a defect feature vector generation module, a defect correlation analysis module, and a fault feedback analysis module;

[0054] The chip data warehousing module collects data from each chip production process segment, comprehensively transmits it to the database, and assigns attribute tags to each data for warehousing to construct a corresponding chip data set; the defect feature vector generation module retrieves data for the chips that have completed the basic production architecture, conducts surface defect image data analysis and electrical property defect analysis for each chip, obtains the defect analysis results of each chip, and extracts the corresponding feature data to generate the corresponding feature defect vectors for each chip; the defect correlation analysis module conducts a correlation defect analysis by combining the surface defect feature vectors and electrical defect feature vectors of each chip, judges the correlation influence degree between the surface defect and the electrical defect of the current chip according to the analysis results, and conducts a double-defect judgment on the current chip through the judgment results; the double-defect judgment is to judge whether there are potential defects in the current chip according to the correlation analysis; the fault feedback analysis module performs a fault analysis on the chip production process stage in combination with the chip defect analysis results of the current production batch, and feeds back the process fault analysis results and the chip defect analysis results to the manual end.

[0055] The chip data storage module includes a chip data acquisition unit and a data storage unit; the chip data acquisition unit installs inductive sensing devices at each process section of the chip production line. When a chip wafer is detected, it records the time point, the sequence number data of the current chip wafer, and the production operation type data; the sequence number data is the position data of the current chip wafer in the current production line; the data recorded by each chip wafer at each process section on the production line is integrated and transmitted to the database; when the chip data is stored, the data storage unit uses the stored sequence number data as the retrieval head label in the chip library, and generates sub-thread labels by extending the head label; each sub-thread label consists of the production operation type data of the chip and the implementation time period corresponding to the generated operation type; using the head label of each chip data as the head node and the corresponding sub-thread label as the associated sub-node to generate the corresponding element node, and integrating the element nodes of each chip in the current batch to generate a data set of the chip data corresponding to the current batch.

[0056] The defect feature vector generation module includes a defect detection unit and a defect feature vector construction unit; the defect detection unit retrieves data of the chips that have completed the basic production structure in the database; determines the production data of each chip in each production type operation on the production line according to the retrieved data, and combines the generated data of each chip to detect the surface defect image data and electrical property defects of the chip; extracts the surface image of each chip and inputs the extracted image data into the surface defect image analysis model; conducts a power-on experiment on each chip, obtains the electrical operation data of the corresponding chip according to the experimental data, and inputs the operation data into the corresponding electrical property defect analysis model; the defect feature vector construction unit outputs defect analysis for each chip according to the surface defect image analysis model and the electrical property defect analysis model, and obtains the surface defect type data and defect image coordinate data of the corresponding chip, as well as the electrical defect type and defect time curve data of the corresponding chip; respectively performs feature data conversion on the surface defect data and electrical defect data of each chip to obtain the feature vector data of the corresponding defect.

[0057] The defect correlation analysis module includes a defect correlation analysis unit, a comprehensive correlation degree analysis unit, and a dual judgment unit; the defect correlation analysis unit maps the surface defect feature vectors of the corresponding chips and the electrical defect vectors to the same plane respectively to obtain the included angle data between each surface defect vector and each electrical defect vector; analyzes the correlation influence of each surface defect on each electrical defect in combination with the included angle data; judges the correlation influence of the corresponding surface defect on the corresponding electrical defect according to the analysis result; the comprehensive correlation degree analysis unit analyzes the correlation influence of the comprehensive surface defect data of the chip on the comprehensive electrical defect data according to the influence analysis of different surface defects on each electrical defect; the dual judgment unit conducts a dual defect judgment on the chip in combination with the analysis result of the correlation influence of the comprehensive surface defect data of the chip on the comprehensive electrical defect data.

[0058] The fault feedback analysis module includes a production process fault analysis unit and a data feedback unit; the production process fault analysis unit analyzes the fault of the chip production process stage by analyzing the proportion of chips with potential defects in the current batch of chips; the data feedback unit feeds back and displays the chip defect analysis result and the process fault analysis result through the manual supervision port.

[0059] In the embodiment:

[0060] Currently, a certain chip manufacturing factory is equipped with the chip production supervision system of the present invention. When it produces a batch of chips, inductive sensing device is installed at each process section of the chip production line. When a chip wafer is detected, the time point, the sequence number data of the current chip wafer, and the production operation type data are recorded; the sequence number data is the position data of the current chip wafer in the current production line; the data recorded by each chip wafer at each process section on the production line is integrated and transmitted to the database in a centralized manner; when the chip data is stored in the database, the stored sequence number data is used as the retrieval head label in the chip library, and sub-clue labels are generated by extending the head label; each sub-clue label is composed of the production operation type data of the chip and the implementation time period of the corresponding production operation type; taking the head label of each chip data as the head node and the corresponding sub-clue label as the associated sub-node to generate the corresponding element node, and comprehensively generating the data set of the corresponding batch of chip data for each element node of the current batch of chips.

[0061] Retrieve data of the chips that have completed the basic production architecture from the database; determine the production data of each chip for each production type operation on the production line according to the retrieved data, and detect the surface defect image data and electrical property defects of the chips by combining the generated data of each chip; extract the surface images of each chip and input the extracted image data into the surface defect image analysis model; conduct a power-on experiment on each chip, obtain the electrical operation data of the corresponding chip according to the experimental data, and input the operation data into the corresponding electrical property defect analysis model; perform defect analysis output on each chip according to the surface defect image analysis model and the electrical property defect analysis model to obtain the surface defect type data and defect image coordinate data of the corresponding chip and the electrical defect type and defect time curve data of the corresponding chip; respectively perform feature data conversion on the surface defect data and electrical defect data of each chip to obtain the feature vector data of the corresponding defects; the conversion calculation formulas are respectively Respectively perform coplanar mapping on the surface defect feature vectors and electrical defect vectors of the corresponding chips to obtain the included angle data between the surface defect vectors and the electrical defect vectors; conduct an analysis of the associated influence of each surface defect on each electrical defect in combination with the included angle data, and its calculation formula is Judge each chip in the current batch according to the calculation result. If Then it is judged that the corresponding surface defect has a strong correlation effect on the corresponding electrical defect; if Then it is judged that the corresponding surface defect has a weak correlation effect on the corresponding electrical defect; where G re Is the system preset value;

[0062] Conduct an analysis of the associated influence of the comprehensive surface defect data of the chips on the comprehensive electrical defect data according to the analysis of the influence of different surface defects on each electrical defect, and its calculation formula is Judge each chip in the current batch according to the calculation result. If ComG < ComG re , then it is judged that the current chip has potential defect; if ComG ≥ ComG re , then it is judged that the current chip has no potential defect; where ComG re Is the system preset value;

[0063] Conduct a fault analysis on the chip production process stage by analyzing the proportion of the chips with potential defects in the current batch of chips, and its calculation formula is Since the current calculation result is Q < Q re , then conduct a fault analysis on the production operations that cause surface defects of the chips; feedback and display the chip defect analysis results and process fault analysis results through the manual supervision port.

[0064] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device.

[0065] Finally, it should be noted that the above are only preferred embodiments of the present invention and are not used to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for supervising the chip production process based on the Internet of Things, characterized in that: The method includes the following steps: S100. Collect data from each chip production process segment, comprehensively transmit it to the database, and perform an operation of assigning attribute tags to each piece of data when it is stored in the database, so as to construct a corresponding chip data set; S200. Retrieve data of the chips that have completed the basic production framework, perform surface defect image data analysis and electrical property defect analysis on each chip, obtain the defect analysis results of each chip, and extract the corresponding feature data to generate a corresponding feature defect vector for each chip; S300. Conduct associated defect analysis by combining the surface defect feature vectors and electrical defect feature vectors of each chip, judge the associated influence degree between the surface defects and electrical defects of the current chip according to the analysis results, and perform a dual defect judgment on the current chip through the judgment results; the dual defect judgment is to judge whether there are potential defect problems in the current chip according to the associated analysis; The specific steps of S300 are as follows: S301. Map the surface defect feature vectors and electrical defect vectors of the corresponding chips to the same plane respectively to obtain the included angle data between each surface defect vector and each electrical defect vector; analyze the associated influence of each surface defect on each electrical defect in combination with the included angle data, and its calculation formula is ; where is the influence degree of each surface defect on each electrical defect; is the mapping included angle between each surface defect vector and each electrical defect vector; if , it is determined that the corresponding surface defect has a strong correlation effect on the corresponding electrical defect; if , it is determined that the corresponding surface defect has a weak correlation effect on the corresponding electrical defect; where is the system preset value; is the number of surface defects of the chip; is the vector constructed by the coordinates of the two endpoints with the largest distance in the images of each surface defect of the chip; is the number of electrical defects of the chip; is the vector constructed by the coordinates of two time points of each defect curve segment in the electrical defect curve of the chip; S302. According to the analysis of the influence of different surface defects on each electrical defect, perform a correlation influence analysis on the comprehensive electrical defect data based on the comprehensive surface defect data of the chip. The calculation formula is ; where is the correlation influence degree of the comprehensive surface defect data of the chip on the comprehensive electrical defect data; is the included angle formed after the co-planar mapping of the surface defect feature vector and the electrical defect feature vector of the chip; is the quantity of the influence degrees of each surface defect with a strong correlation influence on the corresponding electrical defect on the corresponding electrical defect; is the total calculation quantity of the influence degrees of each surface defect on each electrical defect; where and are the surface defect feature vector and the electrical defect feature vector of the corresponding chip respectively; S303. Perform a correlation impact analysis on the comprehensive electrical defect data based on the comprehensive surface defect data of the chip, and conduct a dual-defect judgment on the chip; if , it is determined that the current chip has potential defective defects; if , it is determined that the current chip does not have potential defective defects; where is a system preset value. S400. Combine the chip defect analysis results of the current production batch to conduct a fault analysis on the chip production process stage, and feed back the process fault analysis results and chip defect analysis results to the manual terminal for data.

2. The method for supervising the chip production process based on the Internet of Things according to claim 1, wherein: The specific steps of S100 for collecting data from each chip production process segment, comprehensively transmitting it to the database, and performing an operation of assigning attribute tags to each piece of data when it is stored in the database, so as to construct a corresponding chip data set are as follows: S101. Install inductive sensing equipment at each process segment of the chip production line. When a chip wafer is detected, record the time point, the sequence number data of the current chip wafer, and the production operation type data; the sequence number data is the position data of the current chip wafer on the current production line; comprehensively combine the data recorded by each chip wafer on the production line at each process segment and converge and transmit it to the database; S102. When the chip data is stored in the database, use the stored sequence number data as the retrieval header tag in the chip library, and generate sub-clue tags by extending the header tag; each sub-clue tag is composed of the production operation type data of the chip and the implementation time period corresponding to the generated operation type; use the header tag of each chip data as the header node, use the corresponding sub-clue tag as the associated sub-node to generate the corresponding element node, and comprehensively generate a data set of the corresponding batch of chip data for the element nodes of each chip in the current batch.

3. The method for supervising the chip production process based on the Internet of Things according to claim 2, wherein: The specific steps of S200 for retrieving data of the chips that have completed the basic production framework, performing surface defect image data analysis and electrical property defect analysis on each chip, obtaining the defect analysis results of each chip, and extracting the corresponding feature data to generate a corresponding feature defect vector for each chip are as follows: S201. Retrieve data of the chips that have completed the basic production infrastructure from the database; determine the production data of each chip for each production type operation on the production line according to the retrieved data, and detect the surface defect image data and electrical property defects of the chips by combining the generated data of each chip; extract the surface images of each chip and input the extracted image data into the surface defect image analysis model; conduct a power-on experiment on each chip, obtain the electrical operation data of the corresponding chip according to the experimental data, and input the operation data into the corresponding electrical property defect analysis model; S202. Perform defect analysis output on each chip according to the surface defect image analysis model and the electrical property defect analysis model, and obtain the surface defect type data, defect image coordinate data of the corresponding chip, and the electrical defect type and defect time curve data of the corresponding chip; respectively perform feature data conversion on the surface defect data and electrical defect data of each chip to obtain the feature vector data of the corresponding defects; The conversion calculation formulas are as follows ; ; where and are the surface defect feature vector and electrical defect feature vector of the corresponding chip respectively; is the area of each surface defect of the chip; is the total area of the surface defects of the chip; is the defect type data corresponding to each surface defect of the chip; is the surface defect type; is the number of surface defects of the chip; is the vector constructed by the coordinates of the two endpoints with the largest distance in the images of each surface defect of the chip; is the curve amplitude of each electrical defect of the chip; is the total curve amplitude of the electrical defects of the chip; is the curve type data corresponding to each electrical defect of the chip; is the electrical defect type; is the number of electrical defects of the chip; is the vector constructed by the coordinates of two time points of each defect curve segment in the electrical defect curve of the chip; and are constants.

4. The method for supervising the chip production process based on the Internet of Things according to claim 3, characterized in that: The specific steps of S400 for performing fault analysis on the chip production process stage in combination with the chip defect analysis results of the current production batch and feeding back the chip defect analysis results and process fault analysis results to the manual terminal are as follows: S401. Conduct a fault analysis on the chip production process stage by analyzing the proportion of chips with potential hidden defects in the current batch of chips. The calculation formula is ; where is the quantity proportion of hidden danger chips in the corresponding batch; is the quantity of hidden danger chips in the current batch; is the quantity of chips in the current batch; If , then conduct a fault analysis on the production operations that cause surface defects in the chips; If , then it is recommended to stop the production line and conduct a comprehensive inspection; S402. Feed back and display the chip defect analysis results and process fault analysis results through the manual supervision port.

5. A chip production process supervision system based on the Internet of Things, which applies a chip production process supervision method based on the Internet of Things as described in any one of claims 1-4, characterized in that: The system includes a chip data storage module, a defect feature vector generation module, a defect correlation analysis module, and a fault feedback analysis module; The chip data storage module collects data through each chip production process segment, performs comprehensive transmission to the database, and assigns attribute tags to each data for storage, constructing a corresponding chip data set; the defect feature vector generation module retrieves data of the chips that have completed the basic production infrastructure, conducts surface defect image data analysis and electrical property defect analysis on each chip, obtains the defect analysis results of each chip, and extracts the corresponding feature data to generate the corresponding feature defect vectors of each chip; The defect correlation analysis module conducts correlated defect analysis by combining the surface defect feature vectors and electrical defect feature vectors of each chip, judges the correlation influence degree between the surface defects and electrical defects of the current chip according to the analysis results, and conducts a double-defect judgment on the current chip through the judgment results; the double-defect judgment is to judge whether there are potential defects in the current chip according to the correlation analysis; The fault feedback analysis module conducts fault analysis on the chip production process stage in combination with the chip defect analysis results of the current production batch, and feeds back the process fault analysis results and the chip defect analysis results to the manual terminal.

6. The supervision system for the chip production process based on the Internet of Things according to claim 5, characterized in that: The chip data storage module includes a chip data collection unit and a data storage unit; the chip data collection unit installs inductive sensing devices at each process segment of the chip production line, and records the time point, the sequence data of the current chip wafer, and the production operation type data when the chip wafer is detected; the sequence data is the position data of the current chip wafer in the current production line; Integrate the data recorded by each chip wafer on the production line in each process section and converge and transmit it to the database; when the data warehousing unit warehouses chip data, use the warehousing sequence data as the retrieval header tag in the chip library, and generate sub-thread tags by extending the header tag; each sub-thread tag consists of the production operation type data of the chip and the implementation time period corresponding to the generated operation type; use the header tag of each chip data as the header node, and the corresponding sub-thread tag as the associated sub-node to generate the corresponding element node, and synthesize the element nodes of each chip in the current batch to generate a data set of the corresponding batch of chip data.

7. The supervision system for the chip production process based on the Internet of Things according to claim 6, characterized in that: The defect feature vector generation module includes a defect detection unit and a defect feature vector construction unit; The defect detection unit retrieves data of the chips that have completed the basic production architecture in the database; determines the production data of each chip in each production type operation on the production line according to the retrieved data, and combines the generated data of each chip to detect the surface defect image data and electrical property defects of the chips; extract the surface images of each chip and input the extracted image data into the surface defect image analysis model; conduct a power-on experiment on each chip, obtain the electrical operation data of the corresponding chip according to the experimental data, and input the operation data into the corresponding electrical property defect analysis model; the defect feature vector construction unit performs defect analysis output on each chip according to the surface defect image analysis model and the electrical property defect analysis model, and obtains the surface defect type data and defect image coordinate data of the corresponding chip and the electrical defect type and defect time curve data of the corresponding chip; respectively perform feature data conversion on the surface defect data and electrical defect data of each chip to obtain the feature vector data of the corresponding defects.

8. An Internet of Things-based chip production process supervision system according to claim 7, characterized in that: The defect correlation analysis module includes a defect correlation analysis unit, a comprehensive correlation degree analysis unit, and a double judgment unit; The defect correlation analysis unit respectively performs coplanar mapping on the surface defect feature vectors and electrical defect vectors of the corresponding chips to obtain the included angle data between the surface defect vectors and the electrical defect vectors; combines the included angle data to analyze the correlation influence of each surface defect on each electrical defect; judges the correlation influence of the corresponding surface defect on the corresponding electrical defect according to the analysis result; the comprehensive correlation degree analysis unit analyzes the correlation influence of the comprehensive surface defect data of the chip on the comprehensive electrical defect data according to the influence analysis of different surface defects on each electrical defect; the double judgment unit combines the analysis result of the correlation influence of the comprehensive surface defect data of the chip on the comprehensive electrical defect data to perform a double defect judgment on the chip.

9. The supervision system for the chip production process based on the Internet of Things according to claim 8, wherein: The fault feedback analysis module includes a production process fault analysis unit and a data feedback unit; the production process fault analysis unit analyzes the proportion of chips with potential defects in the current batch of chips to conduct a fault analysis on the chip production process stage; the data feedback unit feeds back and displays the chip defect analysis result and the process fault analysis result through the manual supervision port.

Images