Data processing method and device, storage device and storage medium

Abstract

Embodiments of the present application disclose a data processing method and device, a storage device and a storage medium, which are used for optimizing the write performance and efficiency of the storage device. The method comprises the following steps: receiving a data write request, wherein the data write request comprises a logical block address (LBA) of a first cache to be accessed and target data; judging whether there is a write conflict of the target data in the first cache according to the LBA; if there is a write conflict, writing the target data into a second cache; if the target data written into the second cache does not have a write conflict in the first cache, transmitting the target data written into the second cache to the first cache, so that a host chip transmits the target data written into the first cache to a flash memory chip. Through the data conflict processing between different caches, the memory read-write frequency of the storage device is reduced, and the write performance of the host is improved, thereby solving the problem that the write performance of the storage device and the host is limited in the prior art.

Description

Technical Field

[0001] This application relates to the field of data storage technology, and in particular to data processing methods, apparatus, storage devices, and storage media. Background Technology

[0002] Storage devices are commonly used for reading and writing stored data. The write data sent by the host needs to be transferred to the storage device's DDR memory through the storage device's main controller chip first, and then the write data in the storage device's DDR memory is written to the storage device's flash memory chip.

[0003] The existing method for writing the data requires allocating a dedicated memory space from the memory of the storage device to temporarily store the data to be written. The data to be written is transmitted to the memory of the storage device through the main control chip. The software program in the storage device manages, groups, and handles conflicts of the data temporarily stored in the memory. Finally, the data is written to the flash memory chip and the dedicated memory space for temporarily storing the data to be written is released.

[0004] However, in existing technologies, the write performance of storage devices and hosts is mainly limited by the read and write performance of the storage device's memory. Frequent writing and reading of data in the storage device's memory can cause the host's write performance to be only half of the memory performance, meaning that the read and write directions each account for half of the performance, thus leading to a decrease in host write performance efficiency. Summary of the Invention

[0005] Based on the above problems, embodiments of this application provide a data processing method, apparatus, storage device, and storage medium, with the aim of optimizing host write performance.

[0006] In a first aspect, embodiments of this application provide a data processing method applied to a storage device, the storage device including a main control chip, a first cache, a second cache, and a flash memory chip, the method comprising:

[0007] Receive a data write request, the data write request including the logical block address (LBA) of the first cache to be accessed and the target data;

[0008] Based on the LBA, determine whether there is a write conflict in the first cache for the target data;

[0009] If a write conflict exists, the target data is written to the second cache;

[0010] Based on the LBA, determine whether there is a write conflict in the first cache for the target data to be written to the second cache;

[0011] If no write conflict exists, the target data to be written to the second cache is transferred to the first cache, so that the main control chip of the storage device transfers the target data written to the first cache to the flash memory chip.

[0012] In one embodiment, after determining whether there is a write conflict in the first cache for the target data based on the LBA, the method further includes:

[0013] If no write conflict exists, the target data is written to the first cache so that the main control chip of the storage device can transfer the target data written in the first cache to the flash memory chip.

[0014] In one embodiment, after writing the target data to the second cache if a write conflict occurs, the method further includes:

[0015] If the target data is unaligned data and the starting address of the target data is continuous with the ending address of the data already written in the LBA, then the target data written to the second cache is transferred to the first cache, so that the main control chip of the storage device transfers the target data written to the first cache to the flash memory chip.

[0016] In one embodiment, determining whether there is a write conflict in the first cache for the target data based on the LBA includes:

[0017] In response to multiple received data write requests, determine whether the LBAs of the multiple data write requests overlap;

[0018] If the LBAs of the multiple data write requests overlap, the received data write requests are executed sequentially.

[0019] If the LBAs of the multiple data write requests do not overlap, the received data write requests are executed simultaneously.

[0020] In one embodiment, determining whether there is a write conflict in the first cache for the target data based on the LBA includes:

[0021] Obtain a pre-stored cache table; the cache table includes storage location information of the data already written in the first cache;

[0022] Based on the LBA of the first cache to be accessed and the storage location information of the written data in the first cache, it is determined whether there is a write conflict in the first cache for the target data.

[0023] In one embodiment, the first cache includes multiple logical blocks, and the step of transferring the target data written in the first cache to the flash memory chip includes:

[0024] When the amount of stored data in any of the logical blocks meets a preset data amount threshold, the written data in the logical block is transferred to the flash memory chip.

[0025] In one embodiment, the first cache includes multiple logical blocks, each logical block including multiple sectors, and the flash memory chip stores a preset alignment write rule. The step of transferring the target data written to the first cache to the flash memory chip includes:

[0026] When the cache duration of the logical block meets the preset time threshold, if the written data in the logical block does not meet the preset alignment write rule, the target sector that does not meet the preset alignment write rule is determined and the index of the target sector is obtained.

[0027] Based on the storage location information of the data already written in the target sector and the index of the target sector, first supplementary data is obtained from the flash memory chip;

[0028] The first supplementary data and the written data of the logical block are merged and transmitted to the flash memory chip.

[0029] Secondly, embodiments of this application also provide a data processing apparatus applied to a storage device, the storage device including a main control chip, a first cache, a second cache, and a flash memory chip, the data processing apparatus comprising:

[0030] A request receiving unit is used to receive a data write request, wherein the data write request includes the logical block address (LBA) of the first cache to be accessed and the target data;

[0031] The conflict detection unit is used to determine whether there is a write conflict in the first cache for the target data based on the LBA;

[0032] A data transmission unit is used to write the target data into the second cache if a write conflict occurs;

[0033] The conflict detection unit is further configured to determine, based on the LBA, whether there is a write conflict in the first cache for the target data to be written to the second cache;

[0034] The data transmission unit is further configured to transfer the target data written to the second cache to the first cache if there is no write conflict, so that the main control chip of the storage device transfers the target data written to the first cache to the flash memory chip.

[0035] Thirdly, embodiments of this application also provide a storage device, the storage device including a main control chip, a first cache, a second cache and a flash memory chip, wherein the main control chip, the first cache, the second cache and the flash memory chip are all interconnected, the main control chip includes a memory and a processor, and the main control chip implements the data processing method as described in the first aspect above by running a computer program.

[0036] Fourthly, embodiments of this application also provide a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the data processing method as described in the first aspect above.

[0037] As can be seen from the above technical solutions, the embodiments of this application have the following advantages: After receiving a data write request, the system determines whether a write conflict exists based on LBA. If a write conflict exists in the first cache, the target data is written to the second cache. After the conflict is resolved, the target data is transferred to the first cache and finally written to the flash memory chip. This multi-layered storage structure allows for flexible use of the second cache to mitigate write conflict issues, reducing the frequency of data read / write operations in memory and the latency caused by write conflicts in the first cache, thereby improving the overall read / write performance of the storage device and optimizing the host's write efficiency. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0039] Figure 1 A schematic diagram of a system architecture provided for an embodiment of this application;

[0040] Figure 2 This is a schematic flowchart of a data processing method provided in an embodiment of this application;

[0041] Figure 3 This is a schematic flowchart of a data processing method provided in an embodiment of this application;

[0042] Figure 4 This is a schematic diagram of a data processing device structure provided in an embodiment of this application;

[0043] Figure 5 This is a schematic diagram of a storage device structure provided in an embodiment of this application. Detailed Implementation

[0044] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0045] Furthermore, the terms "first," "second," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance. It should be noted that features in the embodiments of this application can be combined with each other unless there is conflict.

[0046] Storage devices are commonly used for reading and writing stored data. The write data sent by the host needs to be transferred to the memory of the storage device through the main control chip of the storage device first, and then the write data in the memory of the storage device is written into the flash memory chip of the storage device.

[0047] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the system architecture of a data processing system provided in an embodiment of this application. The data processing system 100 provided in this embodiment may include a host 101 and a storage device 102. The host can be a device that connects to the storage device to access data in the storage device. The host can be virtual, such as a virtual machine. The host can also be a physical device, such as a personal computer, server, laptop, smartphone, tablet, etc. The storage device 102 can communicate with the host 101, and data can be written to the storage device 102 through the host 101. The storage device 102 may include a main control chip 103, a first cache 104, a second cache 105, and a flash memory chip 106. The main control chip 103 is communicatively connected to the first cache 104, the second cache 105, and the flash memory chip 106. The storage device 102 communicates with the host 101 through the main control chip 103. The main control chip 103 executes any of the following data processing methods by running computer programs or instructions.

[0048] In this embodiment, the storage device 102 may include solid-state drives (SSDs) and mobile devices (such as mobile phones and tablets). The cache used for temporary storage or conflict management of written data may include a first cache 104 and a second cache 105. In this embodiment, the first cache 104 may use a storage medium with higher read / write speeds, such as static random access memory (SRAM). The first cache 104 can be understood as a hardware cache. Taking SRAM as an example, a hardware cache refers to a segment of SRAM space managed by the hardware module of the storage device 102. The allocation of this SRAM space is entirely completed automatically by the hardware module, and the software module is only responsible for space release. The second cache 105 may use dynamic random access memory (DRAM) or double data rate synchronous dynamic random access memory (DDR). The second cache 105 can be understood as a software cache. Taking DDR as an example, a software cache refers to a segment of DDR space managed by software logic. The entire lifecycle of the software cache, including space allocation, usage, management, and release, is controlled by the software module. Through this tiered caching strategy, the storage device can balance speed and capacity requirements, achieving high-performance and efficient data access. Flash memory chip 106 is a non-volatile storage chip in storage device 102 used for persistent data storage, typically employing NAND Flash. The controller chip 103 may include a central processing unit (CPU), a system-on-a-chip (SoC), etc.

[0049] Under the same conditions, when using only DDR or other dynamic random access memory as software cache, the host write performance is only around 10GB / s; when using only SRAM or other static random access memory as hardware cache, the host write performance can reach 11GB / s. However, in the data processing method provided in this application, by combining the first cache and the second cache (i.e., combining software cache and hardware cache) to manage conflicts in the written data, the host write performance can be improved to 12GB / s. Therefore, the embodiments of this application not only accelerate the data writing processing speed but also improve the write performance of the storage device and the host.

[0050] The various embodiments of this application will now be described in further detail with reference to the accompanying drawings and the system architecture of the data processing system described above.

[0051] Please refer to Figure 2 , Figure 2 This is a schematic flowchart illustrating a data processing method provided in an embodiment of this application. It should be noted that the data processing method provided in this embodiment is not based on... Figure 2 The specific order described below is a limitation. It should be understood that in other embodiments, the order of some steps in the data processing method of this application embodiment can be interchanged according to actual needs, or some steps can be omitted or deleted.

[0052] The following will be about Figure 2 The specific process shown in this application is described in detail. The data processing method provided in this embodiment includes steps S201-S205.

[0053] S201: Receive a data write request. The data write request includes the logical block address (LBA) of the first cache to be accessed and the target data.

[0054] In this embodiment, the data processing method can be applied to a storage device, and the data write request can be a data write request sent by the host. For example, the data write request may include an identifier of the logical partition of the first cache to be accessed, the logical block address (LBA) of the logical partition to be accessed, and the target data (including data size or offset and other related information). The logical partition of the first cache may contain multiple LBAs, each LBA pointing to a specific storage space or data block within the logical partition. The identifier of the logical partition may be a volume, logical unit number (LUN), partition, or other logical storage unit identifier. Furthermore, to improve the processing efficiency of critical data and critical tasks, the priority of the data write request may also be included.

[0055] Of course, existing NAND Flash storage media use FLBA (Flatten Logic Block Address) addressing. FLBA addressing can be considered a type of LBA addressing because these storage media do not have physical heads or cylinders; instead, they use NAND Flash to store data. Therefore, this type of storage media is more suitable for flattened addressing methods. Using FLBA addressing can also simplify the addressing structure and improve read / write performance and efficiency. Therefore, for this addressing method, a data write request can include the logical block address (FLBA) of the first cache to be accessed, the target data (including data size or offset information), etc. It is important to note that "the logical block address (LBA) of the logical partition to be accessed" or "the logical block address (FLBA) of the first cache to be accessed" will be referred to as "the LBA to be accessed" from now on.

[0056] Upon receiving a data write instruction, the storage location of the target data can be determined based on the information carried by the data write instruction, namely the start and end positions of storage in the first cache. The cache is pre-divided into multiple logical blocks for data storage, each logical block comprising multiple sectors, each with the same storage capacity. For example, the storage capacity of each logical block is 4096 bytes (4K), and the storage capacity of each sector is 512 bytes. For instance, the start position of logical block [0] is 0k, and the end position is 4k; the start position of logical block [1] is 4k, and the end position is 8k.

[0057] Typically, to avoid omissions and errors when processing data write requests, the host usually sends these data write requests sequentially through a queue management mechanism and transmits them in a specific order; on the storage device side, data write requests are received and processed one by one to ensure that each request is processed correctly and to avoid data conflicts and corruption.

[0058] It is understandable that, assuming the LBA is 100 (i.e., logical block

[100] ), the sector size is 512 bytes, and the target data size is 1024 bytes (i.e., 2 sectors), the start and end positions of the target data in the cache can be determined based on the target data and LBA in the data write request. For example, the start address is calculated as: LBA * sector size = 100 * 512 = 51200 bytes, and the end address is calculated as: start address + target data size - 1 = 51200 + 1024 - 1 = 52223 bytes.

[0059] S202: Determine whether there is a write conflict in the first cache for the target data based on LBA.

[0060] First-level caches (such as SRAM) typically have faster read and write speeds than second-level caches (such as DRAM), enabling faster response times without conflicts and reducing accesses to slower storage media, thereby improving the overall efficiency of the data write process. Therefore, host writes data preferentially to the first cache, requiring the LBA (Large Buffer Object) carried in the write request to determine if a write conflict exists in the first cache.

[0061] Specifically, it can be confirmed whether the LBA to be accessed in the first cache is already occupied or being accessed in the first cache. Specifically, referring to the previous example where the start and end positions in the cache can be determined based on the target data and LBA in the data write request, check if there is already data in the range of 51200 to 52223 bytes in the first cache. If data already exists in the range of 51200 to 51600 bytes, then a write conflict exists. Alternatively, if the LBA to be accessed in the data write request already contains data, a write conflict can also be confirmed; this situation is understood as a conflict involving the same LBA.

[0062] S203: If a write conflict exists, the target data is written to the second cache.

[0063] If a conflict exists in the first cache, the target data can be temporarily stored in the second cache to avoid data loss and errors. For example, based on the aforementioned example where the start and end positions in the cache can be determined according to the target data and LBA in the data write request, if the first cache does not have enough contiguous space to store the 1024 bytes of target data, the system may need to write part of the data to the second cache, or directly transfer the entire 1024 bytes of target data to the second cache. Further, after writing the target data to the second cache, the data write request is marked as complete.

[0064] S204: Determine whether there is a write conflict in the first cache for the target data to be written to the second cache based on LBA.

[0065] If a write conflict is confirmed during the initial check, the target data will be temporarily written to the second cache. Over time, the conflicting data in the first cache may have been flushed to the memory chip, meaning the original write conflict may no longer exist. Therefore, it is necessary to check again to see if the conflict has been resolved before writing the target data back to the first cache.

[0066] S205: If there is no write conflict, the target data to be written to the second cache is transferred to the first cache, so that the main controller chip of the storage device can transfer the target data to be written to the first cache to the flash memory chip.

[0067] Compared to existing technologies that require allocating a memory space (typically 4KB) from main memory before transferring data, this new technology manages, groups, and handles conflicts of the data cached in memory before sending it to the backend software for writing to flash memory chips (such as NAND Flash). Once the data is successfully written to the flash memory, the previously allocated memory space is released. However, if the data size doesn't match the allocated memory space, write amplification can occur, meaning the actual amount of data written to flash memory exceeds the original data size, reducing memory lifespan. Furthermore, each request requires a write operation followed by erasing or releasing the memory space before the next request can be written. This frequent writing and reading from memory also impacts memory lifespan and degrades host write performance.

[0068] This application embodiment introduces a first cache and a second cache. After receiving a data write request, it determines whether there is a write conflict in the first cache based on the LBA of the target data to be accessed. If a write conflict exists, the target data is written to the second cache. If there is no write conflict in the first cache, the target data written to the second cache is transferred to the first cache, so that the main control chip can transfer the target data written to the first cache to the flash memory chip. Through this multi-level storage structure, the first and second caches can be flexibly used to solve the problems of write conflicts and frequent erase / write operations, reducing the frequency of data read / write in memory and the latency caused by write conflicts in the first cache, improving the overall read / write performance of the storage device, and thus optimizing the host's write efficiency.

[0069] Furthermore, if the data write request includes a priority, and the LBA of the first data write request is accessed by the second data write request, the priority of the second data write request can be compared to see if it is higher than that of the first data write request. If so, the first data write request will not be executed until the second data write request is marked as complete, at which point the first data write request will be executed.

[0070] Please combine Figure 3 Understand the data processing method provided in the following embodiments of this application. Figure 3 This is a schematic flowchart illustrating a data processing method provided in an embodiment of this application. It should be noted that the data processing method provided in this embodiment is not based on... Figure 3 The specific order described below is a limitation. It should be understood that in other embodiments, the order of some steps in the data processing method of this application embodiment can be interchanged according to actual needs, or some steps can be omitted or deleted.

[0071] In one embodiment, after determining whether there is a write conflict in the first cache based on LBA, the method further includes: if there is no write conflict, writing the target data into the first cache so that the main control chip of the storage device can transfer the target data written into the first cache to the flash memory chip.

[0072] The first cache (such as SRAM) acts as a high-speed cache, significantly improving data write and read speeds. Since the read and write speeds of the first cache are much higher than those of flash memory, writing the target data to the first cache first improves overall performance. Multiple write requests and conflict management can be handled more efficiently in the first cache. Flash memory chips (such as NAND Flash) have a limited write lifespan; frequent writes shorten their lifespan. By writing data to the first cache first, the frequency of direct writes to flash memory is reduced, extending the lifespan of the flash memory chips. Furthermore, after the target data is written to the first cache, the data write request is marked as complete.

[0073] In a feasible embodiment, assuming the storage capacity of the currently set logical block is 4096 bytes (i.e., 4K), and the target data with a write conflict is a complete 4K of data, this complete 4K of data can be understood as aligned data. Then, it is possible to detect whether there is a write conflict for the target data in the first cache. If there is no conflict, the complete 4K target data is copied from the second cache to the first cache. If there is a conflict, after the conflicting data in the first cache is written to the flash memory chip, the target data is marked as ready for flushing, and the copying of the target data to the first cache is triggered. After the copy is complete, the target data can be flushed, i.e., written to the flash memory chip.

[0074] In one embodiment, after writing the target data to the second cache if a write conflict occurs, the method further includes: if the target data is unaligned data and the starting address of the target data is continuous with the ending address of the written data in the LBA, then the target data written to the second cache is transferred to the first cache, so that the main control chip of the storage device transfers the target data written in the first cache to the flash memory chip.

[0075] Unaligned data refers to data whose starting address is not perfectly aligned with the boundary of a storage unit (such as a sector or block) on the storage device. When the target data is unaligned, it typically will not completely fill a logical block in the first cache. When the target data is transferred to the second cache, because the LBA corresponding to the target data already contains written data, a write conflict (i.e., a same LBA conflict) occurs, preventing the data from being written to the storage space corresponding to the LBA. However, the already written data in the storage space corresponding to the LBA does not actually fill the space, resulting in wasted storage resources and data write latency.

[0076] Based on the above phenomenon, this application embodiment detects the starting address of the target data in the second cache and the ending address of the written data in the LBA to be accessed in the first cache. If the starting address of the target data is continuous with the ending address of the written data in the first cache, it means that this part of the unaligned data can be merged with the written data in the first cache, thereby making full use of the unfilled logical blocks in the first cache and reasonably scheduling the target data temporarily stored in the second cache.

[0077] For example, suppose a logical block LBA[0] of the first cache has the following cache information:

[0078] Total size: 4KB;

[0079] Data written: 3KB, occupying space from address 0 to address 3071 (in bytes);

[0080] Now, a data write request has been received. There is target data that needs to be written, and the information it carries is as follows:

[0081] LBA to be accessed: LBA[0];

[0082] Size: 2KB;

[0083] Starting address: Address 3072;

[0084] In this case, the starting address (3072) of the target data is contiguous with the ending address (3071) of the data already written in the first cache. However, due to a write conflict with the data already written in LBA[0], the target data may not be able to be directly written into the remaining 1KB space of LBA[0], resulting in 1KB of space being unusable.

[0085] Please refer to Figure 3In this embodiment, if the starting address of the target data to be written to the second cache is found to be continuous with the ending address (3071) of the data already written in the first cache, the target data in the second cache can be migrated back to the first cache. Specifically, the entire 2KB target data can be written to the next available address of LBA[0], i.e., address 3072. This situation can also be understood as merging the target data in the second cache with the data already written in the first cache if the starting address of the target data is found to be continuous with the ending address of the data already written in the first cache. In another feasible embodiment, if it is found that the starting address 0 of LBA[1] has been occupied by other data, making it impossible to write the remaining 1KB of the target data (from 4096 to 5199) together, then the first 1KB of the target data (from 3072 to 4095) can be written to LBA[0], while the remaining 1KB of the target data continues to be temporarily stored in the second cache. Subsequently, the system will continuously monitor the first cache. Once there is enough free space in LBA[0], the remaining 1KB of data temporarily stored will be migrated to the first cache to complete the process of writing the target data into the first cache. This will enable the main control chip of the storage device to transfer the target data written in the first cache to the flash memory chip.

[0086] The embodiments of this application can integrate and organize unaligned data and target data with write conflicts, effectively and rationally utilize storage space, reduce storage waste caused by data misalignment, and improve data management efficiency, so that data can fill each logical block and be successfully written to the flash memory chip, reducing write operation fragmentation and improving write efficiency.

[0087] Please refer to Figure 3 In some feasible embodiments, if the target data is unaligned data and cannot be merged with the written data in the first cache (i.e., the start address of the target data is not contiguous with the end address of the written data in the first cache), then after the written data that conflicts with the target data in the first cache is written to the flash memory chip, the target data is marked as ready to be flushed, triggering the copying of the target data to the first cache. After the copying is completed, the target data can be flushed, i.e., written to the flash memory chip.

[0088] In one embodiment, determining whether there is a write conflict in the first cache based on the LBA includes: in response to multiple received data write requests, determining whether the LBAs of the multiple data write requests overlap; if the LBAs of the multiple data write requests overlap, then executing the received data write requests sequentially; if the LBAs of the multiple data write requests do not overlap, then executing the received data write requests simultaneously.

[0089] As mentioned in the foregoing embodiments, typically, the host sends these data write requests sequentially through a queue management mechanism, transmitting them in a specific order. Meanwhile, the storage device receives and processes each data write request one by one. Therefore, the following situation may occur: if a first data write request is received and data is written, and then a second data request is received, the main control chip can analyze whether the LBA carried by the second data write request is the same as or overlaps with the LBA carried by the first data write request. If LBA overlap is detected, meaning multiple requests point to the same logical block or address range, the system will execute these write requests in the order they are received, processing data write requests according to the first-come, first-served principle to avoid overwriting previous data. If the LBAs of the two data write requests do not overlap, meaning each request points to a different logical block or address range, the system can execute these requests simultaneously.

[0090] This avoids write conflicts during data writing, ensuring data integrity and consistency. Even under high load or with a large number of requests, it effectively manages data writes, improving storage throughput through parallel processing when multiple requests have overlapping LBAs, and avoiding unnecessary data overwriting or rewriting through sequential processing when multiple requests have non-overlapping LBAs.

[0091] To ensure the accuracy and security of data write operations, in one embodiment, determining whether there is a write conflict in the first cache based on the LBA includes: obtaining a pre-stored cache table; the cache table includes storage location information of the written data in the first cache; and determining whether there is a write conflict in the first cache based on the LBA of the first cache to be accessed and the storage location information of the written data in the first cache.

[0092] The cache table may include the following:

[0093]

[0094] When a data write request is received, the Level Requirement Array (LBA) carried in the request is checked. The LBA to be accessed is compared with the storage location information in the cache table to determine whether the target data in the data write request will overlap or conflict with data already existing in the first cache. If the LBA to be accessed is not found in the cache table, meaning the LBA is not occupied, the write operation can be performed, and the target data can be written to the LBA to be accessed; otherwise, a write conflict is determined, and the target data is transferred to the second cache. By using a cache table to perform conflict detection, the system can effectively handle different data write requests, optimize the use of storage resources, prevent data loss or corruption, and improve the management efficiency and performance of storage devices.

[0095] In one embodiment, the first cache includes multiple logical blocks, and transferring the target data written in the first cache to the flash memory chip includes: when the amount of stored data in any logical block meets a preset data amount threshold, transferring the written data in the logical block to the flash memory chip.

[0096] In this embodiment of the application, in order to reduce frequent small-scale write operations and decrease the access frequency of the flash memory chip, after receiving the data write instruction, it can be determined whether to trigger the step of retrieving the written data from the logical block and writing it to the flash memory chip based on the amount of stored data in the logical block in the first cache. The preset data amount threshold defines the amount of stored data in the logical block that triggers the event of flushing the written data to the flash memory chip. If the amount of used data or the amount of stored data in a certain logical block is greater than or equal to the preset data amount threshold, the written data in the logical block is directly stored in the flash memory chip. For example, if the preset data amount threshold is 4K, and the written data in LBA[0] is 4K, then the written data in the logical block is transmitted to the flash memory chip. It should be noted that the embodiments of the present invention do not impose detailed limitations on the preset data amount threshold, which can be set according to the actual situation.

[0097] To optimize storage efficiency and device performance, in one embodiment, the first cache includes multiple logical blocks, each logical block including multiple sectors. The flash memory chip stores a preset alignment write rule. Transferring target data written to the first cache to the flash memory chip includes: when the cache duration of the logical block meets a preset time threshold, if the written data in the logical block does not meet the preset alignment write rule, determining the target sector that does not meet the preset alignment write rule and obtaining the index of the target sector; obtaining first supplementary data from the flash memory chip based on the storage location information of the written data in the target sector and the index of the target sector; merging the first supplementary data and the written data of the logical block and transferring them to the flash memory chip.

[0098] Here, the preset alignment write rule can be the alignment rule in a non-volatile storage medium protocol. In this embodiment, it can be the cache duration of each logical block. If the cache duration after writing data to a logical block reaches a preset time threshold (such as 30 seconds or 1 minute), the written data of that logical block is written to the flash memory chip. Before performing the write operation, it is necessary to determine whether the target data meets the preset alignment rule.

[0099] Specifically, for example, if the preset alignment rule is 4K (i.e., set to the size of a logical block), it is necessary to determine whether the starting address of the written data in each sector under this logical block is aligned with or consistent with the starting address of the sector. Similarly, it is also necessary to determine whether the ending address of the written data in each sector under this logical block is aligned with or consistent with the ending address of the sector. If all sectors are aligned or consistent, the data can be written to the flash memory chip. If the written data in a sector does not fill the sector, such as if the ending address of the written data is not aligned with or consistent with the ending address of the sector, or if no data is written to a sector, then the sector does not meet the preset alignment writing rule. It is necessary to determine the index of the sector that does not meet the preset alignment rule, the storage location information of the written data (the storage location information includes at least one of the starting address and ending address of the written data), and the ending address of the sector, so that supplementary data can be obtained from the flash memory chip to fill the gaps.

[0100] For example, if the written data is located at addresses 2560 to 3000 in sector [5], then according to the sector index (e.g., the index of sector [5] in logical block [0] is S4), the "end address 3000" of the written data in sector [5] and the "end address 3071" of the sector, the supplementary data corresponding to addresses 3001 to 3071 of the corresponding sector [5] needs to be obtained from the flash memory chip and merged with the written data in the first cache, thereby filling the missing parts of the sector. Alternatively, if no data has been written to sector [5], the supplementary data corresponding to the address can be obtained from the flash memory chip according to the index "sector [5] of logical block [0]" to fill the missing parts of the sector. Finally, the supplementary data written to the sector is merged with the data of other sectors to achieve data alignment of each sector, i.e., the entire logical block. This method not only ensures the alignment of the written data, but also improves the efficiency of data writing and the lifespan of the flash memory chip.

[0101] To implement the data processing method of this application embodiment, this application embodiment also provides a data processing apparatus applied to a storage device, the storage device including a main control chip, a first cache, a second cache, and a flash memory chip, such as... Figure 4 As shown, the data processing device includes:

[0102] The request receiving unit 401 is used to receive a data write request, the data write request including the logical block address (LBA) of the first cache to be accessed and the target data;

[0103] The conflict detection unit 402 is used to determine whether there is a write conflict in the first cache for the target data based on the LBA;

[0104] The data transmission unit 403 is used to write the target data into the second cache if a write conflict occurs;

[0105] The conflict detection unit 402 is further configured to determine, based on the LBA, whether there is a write conflict in the first cache for the target data to be written to the second cache;

[0106] The data transmission unit 403 is further configured to transfer the target data written to the second cache to the first cache if there is no write conflict, so that the main control chip of the storage device transfers the target data written to the first cache to the flash memory chip.

[0107] In one embodiment, the data transmission unit is further configured to write the target data into the first cache if there is no write conflict, so that the main control chip of the storage device transmits the target data written in the first cache to the flash memory chip.

[0108] In one embodiment, the data transmission unit is further configured to transfer the target data written to the second cache to the first cache if the target data is unaligned data and the start address of the target data is continuous with the end address of the data already written to the LBA, so that the main control chip of the storage device transfers the target data written to the first cache to the flash memory chip.

[0109] In one embodiment, the apparatus further includes a processing unit. The processing unit is configured to, in response to a plurality of received data write requests, determine whether the LBAs of the plurality of data write requests overlap; if the LBAs of the plurality of data write requests overlap, then execute the received data write requests sequentially; if the LBAs of the plurality of data write requests do not overlap, then execute the received data write requests simultaneously.

[0110] In one embodiment, the apparatus further includes an acquisition unit. The acquisition unit is configured to acquire a pre-stored cache table; the cache table includes storage location information of data already written to the first cache.

[0111] The processing unit is further configured to determine whether there is a write conflict in the first cache for the target data based on the LBA of the first cache to be accessed and the storage location information of the written data in the first cache.

[0112] In one embodiment, the data transmission unit is further configured to transmit the written data in the logical block to the flash memory chip when the amount of stored data in any of the logical blocks meets a preset data amount threshold.

[0113] In one embodiment, the processing unit is further configured to, when the cache duration of the logical block meets a preset time threshold, if the written data in the logical block does not meet the preset alignment write rule, determine the target sector that does not meet the preset alignment write rule and obtain the index of the target sector;

[0114] The acquisition unit is further configured to acquire first supplementary data from the flash memory chip based on the storage location information of the data already written in the target sector and the index of the target sector;

[0115] The data transmission unit is further configured to merge the first supplementary data and the written data of the logical block, and transmit them to the flash memory chip.

[0116] In practical applications, the processing unit can be implemented by combining the main control chip in the storage device with the communication interface, while the request receiving unit, conflict detection unit, data transmission unit, processing unit, and acquisition unit can be implemented by the communication interface in the data processing device.

[0117] It should be noted that the data processing apparatus provided in the above embodiments is only illustrated by the division of the above-described program modules. In practical applications, the above processing can be assigned to different program modules as needed, that is, the internal structure of the apparatus can be divided into different program modules to complete all or part of the processing described above. In addition, the data processing apparatus and data processing method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process can be found in the method embodiments, which will not be repeated here.

[0118] Based on the hardware implementation of the above program modules, and in order to implement the data processing method provided in this application embodiment, this application embodiment also provides a storage device, such as... Figure 5 As shown, the storage device 500 includes a main control chip 501, a first cache 502, a second cache 503, and a flash memory chip 504. The main control chip 501, the first cache 502, the second cache 503, and the flash memory chip 504 are all interconnected. The main control chip 501 runs a computer program to implement the data processing method described in any of the above descriptions.

[0119] Of course, in practical applications, the various components in the storage device 500 are coupled together through a bus system 505. It is understood that the bus system 505 is used to realize communication between these components. In addition to a data bus, the bus system 505 also includes a power bus, a control bus, and a status signal bus, etc. However, for clarity, in... Figure 5 The general designated all buses as Bus System 505.

[0120] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the data processing method described in any of the above embodiments.

[0121] This application also provides a computer program product that stores a computer program / instruction thereon, which, when executed by a processor, is used to implement the data processing method described in any of the above-mentioned embodiments.

[0122] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0123] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between apparatuses or units through some interfaces, and may be electrical, mechanical, or other forms.

[0124] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0125] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0126] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a storage device (which may be a personal computer, server, solid-state drive, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A data processing method, characterized in that, Applied to a storage device, the storage device including a main control chip, a first cache, a second cache, and a flash memory chip, the method includes: Receive a data write request, the data write request including the logical block address (LBA) of the first cache to be accessed and the target data; Based on the LBA, determine whether there is a write conflict in the first cache for the target data; If a write conflict exists, the target data is written to the second cache; The type of the target data to be written to the second cache is determined. If the target data is unaligned data and the starting address of the target data is continuous with the ending address of the data already written to the LBA, the target data to be written to the second cache is transferred to the first cache, so that the main control chip of the storage device transfers the target data written to the first cache to the flash memory chip. Based on the LBA, determine whether there is a write conflict in the first cache for the target data to be written to the second cache; If no write conflict exists, the target data to be written to the second cache is transferred to the first cache, so that the main control chip of the storage device transfers the target data written to the first cache to the flash memory chip.

2. The data processing method according to claim 1, characterized in that, After determining whether there is a write conflict in the first cache for the target data based on the LBA, the method further includes: If no write conflict exists, the target data is written to the first cache so that the main control chip of the storage device can transfer the target data written in the first cache to the flash memory chip.

3. The data processing method according to claim 1, characterized in that, The step of determining whether there is a write conflict in the first cache for the target data based on the LBA includes: In response to multiple received data write requests, determine whether the LBAs of the multiple data write requests overlap; If the LBAs of the multiple data write requests overlap, the received data write requests are executed sequentially. If the LBAs of the multiple data write requests do not overlap, the received data write requests are executed simultaneously.

4. The data processing method according to claim 1, characterized in that, The step of determining whether there is a write conflict in the first cache for the target data based on the LBA includes: Obtain a pre-stored cache table; the cache table includes storage location information of the data already written in the first cache; Based on the LBA of the first cache to be accessed and the storage location information of the written data in the first cache, it is determined whether there is a write conflict in the first cache for the target data.

5. The data processing method according to claim 1, characterized in that, The first cache includes multiple logical blocks, and the step of transferring the target data written in the first cache to the flash memory chip includes: When the amount of stored data in any of the logical blocks meets a preset data amount threshold, the written data in the logical block is transferred to the flash memory chip.

6. The data processing method according to claim 1, characterized in that, The first cache includes multiple logical blocks, each logical block includes multiple sectors, and the flash memory chip stores a preset alignment write rule. The step of transferring the target data written to the first cache to the flash memory chip includes: When the cache duration of the logical block meets the preset time threshold, if the written data in the logical block does not meet the preset alignment write rule, the target sector that does not meet the preset alignment write rule is determined and the index of the target sector is obtained. Based on the storage location information of the data already written in the target sector and the index of the target sector, first supplementary data is obtained from the flash memory chip; The first supplementary data and the written data of the logical block are merged and transmitted to the flash memory chip.

7. A data processing apparatus, characterized in that, Applied to a storage device, the storage device including a main control chip, a first cache, a second cache, and a flash memory chip, the data processing device includes: A request receiving unit is used to receive a data write request, wherein the data write request includes the logical block address (LBA) of the first cache to be accessed and the target data; The conflict detection unit is used to determine whether there is a write conflict in the first cache for the target data based on the LBA; A data transmission unit is used to write the target data into the second cache if a write conflict occurs; The data transmission unit is used to determine the type of target data to be written to the second cache. If the target data is unaligned data and the starting address of the target data is continuous with the ending address of the data already written in the LBA, the target data to be written to the second cache is transmitted to the first cache, so that the main control chip of the storage device transmits the target data written to the first cache to the flash memory chip. The conflict detection unit is further configured to determine, based on the LBA, whether there is a write conflict in the first cache for the target data to be written to the second cache; The data transmission unit is further configured to transfer the target data written to the second cache to the first cache if there is no write conflict, so that the main control chip of the storage device transfers the target data written to the first cache to the flash memory chip.

8. A storage device, characterized in that, The storage device includes a main control chip, a first cache, a second cache, and a flash memory chip. The main control chip, the first cache, the second cache, and the flash memory chip are all interconnected. The main control chip runs a computer program to implement the data processing method as described in any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the data processing method as described in any one of claims 1 to 6.

10. A computer program product having a computer program / instructions stored thereon, characterized in that, When executed by a processor, the computer program / instructions are used to implement the data processing method as described in any one of claims 1 to 6.

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