Device bandwidth allocation system, method, device, medium and product

Abstract

The embodiment of the present invention provides a device bandwidth allocation system, method, device, medium and product, including: a target device and a central processing unit, wherein a weak electric potential sensing amplification circuit and a channel induced electric field register are arranged on a slot of the target device, the slot supports a number of channels corresponding to the target device type, and the channel induced electric field register is connected to the central processing unit; the weak electric potential sensing amplification circuit is used to detect the induced electromotive force corresponding to each channel when an alternating voltage is detected in the channels at both ends of the target device, and determine the induced voltage state corresponding to each channel based on the induced electromotive force; the channel induced electric field register is used to store the value of the induced voltage state corresponding to each channel; the central processing unit reads the value of the induced voltage state corresponding to each channel in the channel induced electric field register, and determines the bandwidth allocation state of each channel based on the value of the induced voltage state in the channel induced electric field register within the target bandwidth.

Description

Technical Field

[0001] The present invention relates to the technical field of servers, and in particular to a device bandwidth allocation system, method, device, medium and product. Background Art

[0002] The PICe interface on the server motherboard generally uses PCIe x8 slots and PCIe x16 slots to facilitate the later insertion of different types of expansion cards. Even if the gold finger on the expansion card is x2 or x4, it can also be plugged into the PCIe x8 slot or PCIex16 slot. However, the bandwidth directly provided by the central processor to the PCIe x8 slot and PCIe x16 slot is the maximum bandwidth, and the central processor also allocates the maximum bandwidth, resulting in a waste of PCIe resources and a loss of central processor function. For example, two PCIE X8 devices are plugged into two PCIE X16 slots, but it is impossible to support two X8 devices in one X16 slot; PCIe cannot automatically identify and allocate bandwidth.

[0003] At present, the method used by PCIe to automatically identify and allocate bandwidth is to use expansion chips instead of GPIO to dynamically configure bandwidth. However, this method requires adding a bandwidth allocation table in the detection program, expansion chip detection or physical resistance detection. After obtaining the change data, it is necessary to match the numerical value with the corresponding number of Lanes in the pre-set bandwidth allocation table, and then the central processing unit analyzes the corresponding bandwidth for allocation. In the early stage, it is necessary to count the data of different expansion cards to simulate and build a table. The types and models of corresponding expansion cards are fixed. After the expansion card data that is not in the table is plugged in, there will be recognition errors. The table needs to be matched when used, resulting in low efficiency in overall recognition and allocation of bandwidth. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a device bandwidth allocation system, method, device, medium and product. The specific technical solutions are as follows:

[0005] In a first aspect of the present invention, a device bandwidth allocation method is first provided, wherein the device bandwidth allocation system comprises: a target device and a central processing unit, wherein a weak potential sensing amplifier circuit and a channel sensing electric field register are provided on a slot of the target device, wherein the slot supports a number of channels corresponding to the type of the target device, and the channel sensing electric field register is connected to the central processing unit;

[0006] The weak potential sensing amplifier circuit is used to detect the induced electromotive force corresponding to each channel when detecting the presence of alternating voltage in the channels at both ends of the target device, and determine the induced voltage state corresponding to each channel based on the induced electromotive force;

[0007] The channel induced electric field register is used to store the value of the induced voltage state corresponding to each of the channels;

[0008] The central processing unit reads the value of the induced voltage state corresponding to each of the channels in the channel induced electric field register, and determines the bandwidth allocation state of each channel based on the value of the induced voltage state in the channel induced electric field register within the target bandwidth.

[0009] Optionally, the weak electric potential sensing amplifier circuit is an analog voltage amplifier circuit based on a gate circuit.

[0010] Optionally, the weak potential sensing amplification circuit includes a plurality of NOT gates connected in series in sequence, and a plurality of the NOT gates are connected in parallel with a target resistor.

[0011] Optionally, each of the channels includes four signal lines, and the four signal lines include a transmitting positive signal line, a transmitting negative signal line, a receiving positive signal line, and a receiving negative signal line.

[0012] Optionally, the induced voltage state includes any one of a negative voltage state, a positive voltage state and a no induced voltage state.

[0013] Optionally, the channels at both ends of the target device include a first channel and a second channel, and the non-induced voltage state is determined by allocating the first channel and the second channel to different PCIe devices to generate a non-enclosed electric field.

[0014] In a second aspect of the present invention, a device bandwidth allocation method is provided, which is applied to any device bandwidth allocation system described in the first aspect, and the method includes:

[0015] In the case where it is detected that there is an alternating voltage in the channels at both ends of the target device, detecting the induced electromotive force corresponding to each of the channels, determining the induced voltage state corresponding to each of the channels based on the induced electromotive force, and storing the value of the induced voltage state corresponding to each of the channels;

[0016] Read the value of the induced voltage state corresponding to each of the channels in the channel induced electric field register, and determine the bandwidth allocation state of each channel based on the value of the induced voltage state in the channel induced electric field register within the target bandwidth

[0017] Optionally, determining the bandwidth allocation state of each channel based on the value of the induced voltage state in the channel induced electric field register within the target bandwidth includes:

[0018] According to the preset bandwidth allocation rule, it is determined in turn whether the values ​​of the induced voltage states in the channel induced electric field registers within different target bandwidths are consistent, and the bandwidth allocation state of each channel is output.

[0019] Optionally, the target bandwidth includes a first bandwidth, a second bandwidth, a third bandwidth, a fourth bandwidth and a fifth bandwidth.

[0020] Optionally, determining in sequence whether the values ​​of the induced voltage states in the channel induced electric field registers within different target bandwidths are consistent according to a preset bandwidth allocation rule, and outputting the bandwidth allocation state of each channel includes:

[0021] Determining whether the induced voltage states in the channel induced electric field registers within the first bandwidth are consistent;

[0022] If not, determining whether the induced voltage states in the channel induced electric field registers within the second bandwidth are consistent, wherein the second bandwidth is smaller than the first bandwidth;

[0023] If not, determining whether the induced voltage states in the channel induced electric field registers within the third bandwidth are consistent, wherein the third bandwidth is smaller than the second bandwidth;

[0024] If not, determining whether the induced voltage states in the channel induced electric field registers within the fourth bandwidth are consistent, wherein the fourth bandwidth is smaller than the third bandwidth;

[0025] If not, the two channels corresponding to the fourth bandwidth are allocated as the fifth bandwidth, and the bandwidth allocation state of each channel is the fifth bandwidth, wherein the fifth bandwidth is smaller than the fourth bandwidth.

[0026] Optionally, before the step of detecting the presence of alternating voltages in the channels at both ends of the target device, detecting the induced electromotive force corresponding to each of the channels, and determining the induced voltage state corresponding to each of the channels based on the induced electromotive force, the method includes:

[0027] Applying alternating voltages in opposite directions to the positive signal transmission line corresponding to any first channel and the negative signal transmission line corresponding to any second channel;

[0028] If the first channel and the second channel correspond to the same target device, the positive signal transmission line corresponding to the first channel and the negative signal transmission line corresponding to the second channel generate an effective closed electric field;

[0029] If the first channel and the second channel correspond to different target devices, the positive signal transmission line corresponding to the first channel and the negative signal transmission line corresponding to the second channel generate an invalid non-enclosed electric field.

[0030] Optionally, after the step of generating an effective closed electric field by the positive signal transmission line corresponding to the first channel and the negative signal transmission line corresponding to the second channel if the first channel and the second channel correspond to the same target device, the method includes:

[0031] generating a target induced magnetic field based on the effective closed electric field;

[0032] In the target induced magnetic field, the induced electromotive force corresponding to each channel is obtained through a weak potential induction amplification circuit.

[0033] In a third aspect of the present invention, a device bandwidth allocation apparatus is provided, the apparatus comprising:

[0034] The first module is used to detect the induced electromotive force corresponding to each channel when it is detected that there is an alternating voltage in the channels at both ends of the target device, determine the induced voltage state corresponding to each channel based on the induced electromotive force, and store the value of the induced voltage state corresponding to each channel;

[0035] The second module is used to read the value of the induced voltage state corresponding to each channel in the channel induced electric field register, and determine the bandwidth allocation state of each channel based on the value of the induced voltage state in the channel induced electric field register within the target bandwidth.

[0036] In a fourth aspect of the implementation of the present invention, there is also provided a communication device, comprising: a transceiver, a memory, a processor, and a program stored in the memory and executable on the processor;

[0037] The processor is used to read the program in the memory to implement the device bandwidth allocation method as described in any one of the first aspects.

[0038] In a fifth aspect of the implementation of the present invention, a computer-readable storage medium is further provided, wherein instructions are stored in the computer-readable storage medium, and when the computer-readable storage medium is executed on a computer, the computer implements the device bandwidth allocation method as described in any one of the first aspects.

[0039] In a sixth aspect of the implementation of the present invention, a computer program product is also provided, including a computer program / instruction, and when the computer program / instruction is executed by a processor, the device bandwidth allocation method as described in any one of the first aspects is implemented.

[0040] The device bandwidth allocation system provided by the embodiment of the present invention comprises: a target device and a central processing unit, wherein a weak potential induction amplification circuit and a channel induction electric field register are arranged on the slot of the target device, wherein the slot supports a number of channels corresponding to the target device type, and the channel induction electric field register is connected to the central processing unit; the weak potential induction amplification circuit is used to detect the induced electromotive force corresponding to each of the channels when an alternating voltage is detected in the channels at both ends of the target device, and determine the induced voltage state corresponding to each of the channels based on the induced electromotive force; the channel induction electric field register is used to store the value of the induced voltage state corresponding to each of the channels; the central processing unit reads the value of the induced voltage state corresponding to each of the channels in the channel induction electric field register, and determines the bandwidth allocation state of each channel based on the value of the induced voltage state in the channel induction electric field register within the target bandwidth. The detection mechanism of the embodiment of the present invention is stable and reliable; it does not need to occupy GPIO resources, and does not need to occupy additional communication interfaces such as IIC. It realizes the fully automated and intelligent identification and allocation of server PCIe device bandwidth allocation. Each device only needs to have a weak potential sensing amplification circuit on each PCIe lane. If there is an induced electromotive force on this lane, the corresponding induced voltage state value will be written into the induced electric field register. By applying alternating voltage to the lanes at both ends of each PCIe Port X16, it is detected whether the lane induced electric field register state within its bandwidth is consistent, and the bandwidth allocation of each lane is finally determined. The bandwidth allocation is more accurate and fast, avoiding the use of the intermediate bandwidth allocation table for coordination and verification, improving the bandwidth allocation efficiency, and achieving the effect of multiple devices being directly connected to one PCIe slot without being affected by the bandwidth, avoiding the small error in the voltage value of the PCIe slot being directly collected, and improving the accuracy of the central processor in identifying PCIe devices and the accuracy of bandwidth allocation. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below.

[0042] Figure 1 A schematic diagram of a device bandwidth allocation system provided by an embodiment of the present invention;

[0043] Figure 2 It is a flowchart of the steps of a method for allocating device bandwidth provided by an embodiment of the present invention;

[0044] Figure 3 It is a device block diagram of a device bandwidth allocation device provided by an embodiment of the present invention;

[0045] Figure 4is a schematic diagram of a communication device provided by an embodiment of the present invention;

[0046] Figure 5 It is a circuit connection diagram of a weak potential sensing amplifier circuit provided by an embodiment of the present invention;

[0047] Figure 6 It is a schematic diagram of a current and magnetic field direction diagram of an alternating voltage between each lane provided by an embodiment of the present invention;

[0048] Figure 7 It is a schematic diagram of a gate circuit transfer characteristic curve provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0049] To make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. However, it will be appreciated by those skilled in the art that in the embodiments of the present invention, many technical details are proposed in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can be implemented. The division of the following embodiments is for the convenience of description, and should not constitute any limitation on the specific implementation of the present invention. The various embodiments can be combined and referenced with each other without contradiction.

[0050] It should be noted that in the embodiments of the present application, before describing the overall technical solution, in order to facilitate those skilled in the art to better understand the present application, the relevant technology is described.

[0051] First, Faraday's law of electromagnetic induction: This law states that the induced electromotive force in a closed loop is proportional to the rate of change of the magnetic flux passing through the loop. Although it describes the phenomenon caused by the change of magnetic flux, it can be known from Maxwell's equations that the changing magnetic field will also generate an electric field, which indirectly leads to the generation of induced electromotive force.

[0052] Second, eddy current effect: In an alternating electric field, if a conductor (such as a metal block) is placed in the electric field, the change in the electric field will generate vortex-shaped induced currents in the conductor, namely eddy currents. These eddy currents will generate their own magnetic fields, which will interact with the magnetic field of the original electric field, resulting in energy loss and heat generation.

[0053] Third, electromagnetic heating: The eddy current effect generated by the alternating electric field can be used to heat the conductor non-contactly. This principle is widely used in electromagnetic induction heating equipment, such as induction cookers, induction quenching, etc.

[0054] Fourth, wireless energy transmission: Alternating electric fields and the resulting alternating magnetic fields can be used for wireless energy transmission, such as wireless charging technology, in which the transmitter generates an alternating electric field and the coil in the receiver induces current, thereby realizing wireless transfer of energy.

[0055] Fifth, communication technology: In wireless communications, antennas transmit information by emitting and receiving alternating electric fields (and accompanying magnetic fields). For example, Wi-Fi, Bluetooth, and cellular networks are all based on this principle.

[0056] PCIe has made fundamental changes in bus structure, which are mainly reflected in two aspects: one is the change from parallel bus to serial bus; the other is the use of point-to-point interconnection. The bus connecting the devices under the bridge in the original parallel bus structure is changed into a link. A link can contain one or more channels. Each channel consists of two pairs of differential signal lines to form a dual-simplex serial transmission channel. There are no dedicated data, address, control and clock lines. Various transactions on the bus are organized into information packets for transmission. PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion card standard, mainly used to connect the central processing unit and various expansion cards, such as graphics cards, sound cards and network adapters. The bandwidth of PCIe is closely related to its version and the number of Lanes. The following are detailed information on different versions of PCIe and their bandwidth:

[0057] PCIe 1.0: The online bit transfer rate is 2.5Gb / s, using 8 / 10 encoding, so the bandwidth of PCIe 1.0x1 is 250MB / s.

[0058] PCIe 2.0: The online bit transfer rate is doubled to 5Gb / s, using 8 / 10 encoding, so the bandwidth of PCIe 2.0x 1 is 500MB / s.

[0059] PCIe 3.0: The online bit transfer rate is 8Gb / s, using 128 / 130 encoding, so the bandwidth of PCIe 3.0x 1 is 1GB / s.

[0060] PCIe 4.0: The online bit transfer rate is increased to 16GT / s.

[0061] PCIe 5.0: The online bit transfer rate can reach up to 32GT / s.

[0062] In addition, the bandwidth of PCIe is also related to the number of its lanes. For example, the theoretical maximum bandwidth of the PCIe x1 slot is 1GB / s, which is suitable for devices with low data transmission requirements; the theoretical maximum bandwidth of the PCIe x4 slot is 4GB / s, which is suitable for devices with medium bandwidth requirements; the theoretical maximum bandwidth of the PCIe x8 slot is 8GB / s, which is suitable for devices with higher data transmission speed requirements; the PCIe x16 slot has the highest theoretical maximum bandwidth of 16GB / s, which is widely used to connect high-performance graphics cards.

[0063] Therefore, in the embodiment of the present application, in the alternating induced magnetic field generated by the alternating electric field, each PCIe lane of the central processor is equivalent to cutting the magnetic flux lines. Since the direction of the magnetic poles in the closed magnetic field is opposite to the direction of the magnetic poles outside the closed magnetic field at the same time, the direction of the induced electromotive force of the lanes (HSOn(1) and HSOp(N)) and Lane2-LaneN-1 in the closed magnetic field is opposite to the direction of the induced electromotive force of the lanes (LaneM and other Lanes) outside the closed magnetic field at the same time. A weak potential induction amplifier circuit is designed for each PCIe lane of the central processor. Whether there is an induced electromotive force on this lane will write the corresponding induced voltage state: 0x00 (negative voltage), 0x01 (positive voltage), 0xFF (no induced voltage) value into the induced electric field register. Therefore, an alternating voltage is applied to the lanes at both ends of each PCIe Port X16 to detect whether the states of the lane induced electric field registers within the X16 bandwidth are consistent. If they are consistent, the bandwidth allocated to the Port is X16. If they are inconsistent, an alternating voltage is applied to the lanes at both ends of each X8 of the Port for detection, and the states of the lane induced electric field registers within the x8 bandwidth are read to check whether they are consistent. If the states of the internal lane induced electric field registers are still inconsistent, the lane detection operation of X4 X2 is performed in this way. If the consistency of the induced electric field register states is still not obtained under the detection of the lane state of X2, the two lanes of X2 are allocated to X1, and finally the bandwidth allocation of each lane is determined.

[0064] Reference Figure 1 , the device bandwidth allocation system includes: a target device and a central processing unit, a slot of the target device is provided with a weak potential sensing amplification circuit and a channel sensing electric field register, the slot supports a number of channels corresponding to the type of the target device, and the channel sensing electric field register is connected to the central processing unit;

[0065] The weak potential sensing amplifier circuit is used to detect the induced electromotive force corresponding to each channel when detecting the presence of alternating voltage in the channels at both ends of the target device, and determine the induced voltage state corresponding to each channel based on the induced electromotive force;

[0066] The channel induced electric field register is used to store the value of the induced voltage state corresponding to each of the channels;

[0067] The central processing unit reads the value of the induced voltage state corresponding to each of the channels in the channel induced electric field register, and determines the bandwidth allocation state of each channel based on the value of the induced voltage state in the channel induced electric field register within the target bandwidth.

[0068] Furthermore, each of the channels includes four signal lines, and the four signal lines include a transmitting positive signal line, a transmitting negative signal line, a receiving positive signal line, and a receiving negative signal line.

[0069] It should be noted that in an embodiment of the present application, the target device includes a target PCIe device, and the bandwidth allocation status of each channel is ultimately determined by the central processing unit. During the boot process, the CPU can read the value of the induced voltage state corresponding to each of the channels in the channel induced electric field register by loading the BIOS code, and determine the bandwidth allocation status of each channel based on the value of the induced voltage state in the channel induced electric field register within the target bandwidth.

[0070] It should be noted that, refer to Figure 6 , Figure 6 It is a schematic diagram of the current and magnetic field direction diagram of the alternating voltage between each lane provided by an embodiment of the present invention. There are four lines (HSOp, HSOn, HSIp, HSIn) in each lane of the PCIe slot, where p is positive, and n is negative. Specifically, the transmission (Tx) pair: HSOp: High Speed ​​Output Positive, transmitting positive signal line, and HSOn: High Speed ​​Output Negative, transmitting negative signal line. The receiving (Rx) pair: HSIp: High Speed ​​Input Positive, receiving positive signal line, and HSIn: High Speed ​​Input Negative, receiving negative signal line, so each pair of differential signal lines constitutes a Lane.

[0071] Figure 6In the example, HSOp(1) and HSOn(N) are subjected to alternating voltages in opposite directions with a period of f. In the first half period 0-f / 2, the voltage of HSOp(1) changes from 0 to VCC, and that of HSOn(N) changes from VCC to 0. In the second half period f / 2-f, the voltage of HSOp(1) changes from VCC to 0, and that of HSOn(N) changes from 0 to VCC. Assuming that Lane1 and LaneN are assigned to the same PCIe device, HSOp(1) and HSOn(N) can form an effective closed electric field. According to the right-hand rule, in the first half period 0-f / 2, the direction of the magnetic field is from outside to inside as shown in the figure, and in the second half period f / 2-f, the direction of the magnetic field is from inside to outside as shown in the figure. If Lane1 and LaneN are not assigned to the same PCIe device, the closed electric field cannot be effectively generated, and the corresponding induced magnetic field cannot be generated.

[0072] Furthermore, the induced voltage state includes any one of a negative voltage state, a positive voltage state and a no induced voltage state.

[0073] Further, the channels at both ends of the target device include a first channel and a second channel, and the non-induced voltage state is determined by the first channel and the second channel being allocated to different PCIe devices to generate a non-enclosed electric field.

[0074] In the alternating induced magnetic field generated by the alternating electric field, each PCIe lane of the CPU is equivalent to cutting the magnetic flux lines. Since the direction of the magnetic poles in the closed magnetic field is opposite to that outside the closed magnetic field at the same time, the direction of the induced electromotive force of the lanes (HSOn(1) and HSOp(N)) and Lane2-LaneN-1 in the closed magnetic field and the direction of the induced electromotive force of the lanes (LaneM and other Lanes) outside the closed magnetic field are opposite at the same time.

[0075] Each PCIe lane in the CPU is designed with a weak electric potential sensing amplifier circuit. Whether there is an induced electromotive force on this lane, the corresponding induced voltage state: 0x00 (negative voltage), 0x01 (positive voltage), 0xFF (no induced voltage) value will be written into the lane induced electric field register.

[0076] Figure 1 In the invention, a weak potential sensing amplifier circuit and a lane induced electric field register are set on each PCIe Port X16 slot, the lane induced electric field register is connected to the central processing unit, and the central processing unit reads the amplified induced electromotive force state written in the lane induced electric field register.

[0077] Furthermore, the weak potential sensing amplifier circuit is an analog voltage amplifier circuit based on a gate circuit.

[0078] Furthermore, the weak potential sensing amplification circuit includes a plurality of NOT gates connected in series in sequence, and a plurality of the NOT gates are connected in parallel with the target resistor.

[0079] It should be noted that, in the embodiment of the present application, the weak potential sensing amplifier circuit is as follows: Figure 5 As shown, the weak potential induction amplifier circuit is an analog voltage amplifier circuit composed of gate circuits, which is composed of three NOT gates D1, D2, and D3 connected in series, and a large resistor R2 is connected in parallel to the three NOT gates D1, D2, and D3. Among them, Ui is the input alternating voltage, Uo is the output alternating voltage, R1 is the input resistor, and R2 is the feedback bias resistor, which biases the working points of the three NOT gates near 1 / 2VDD.

[0080] The circuit amplification factor A=R2 / R1. If the parameters are set to R1=10K and R2=1M, the amplification factor A=100 times.

[0081] Working principle of weak potential induction amplifier circuit: The output characteristic curve of the gate circuit is also called the transfer characteristic curve, as follows Figure 7 As shown in the graph, there is a relatively steep section in the middle of the curve. Figure 7 The part between the dotted lines AB in the curve is called the state transition area of ​​the NOT gate circuit. The voltage input corresponding to the midpoint Q of the curve is called the state transition voltage, which is represented by UT. Generally, UT is UDD / 2, which is half of the power supply voltage. In the transition area, since the curve is relatively steep, as long as the input voltage has a small change, it will cause a large change in the output voltage. Therefore, in the state transition area, the NOT gate has a voltage amplification effect. This area is also called the linear amplification area. Here, the characteristics of this area are used to form an amplifier for the gate circuit to amplify the signal.

[0082] from Figure 7 It can be seen that the state transition area of ​​the gate circuit is very small, that is, the AB segment in the figure. If the input signal cannot enter this area, the amplifier will not be able to amplify the signal or will cause serious distortion of the amplified signal.

[0083] In transistor amplifiers, in order to amplify the input signal without distortion, a suitable bias circuit needs to be set. Similarly, for amplifiers composed of gate circuits, appropriate static bias is also required. This biasing method usually biases the input end at the Q point of the curve, that is, 1 / 2 of the working power supply voltage UDD. At this time, the circuit has the largest dynamic range for the input signal.

[0084] Therefore, an alternating voltage is applied to the lanes at both ends of each PCIe Port X16 to detect whether the states of the lane induced electric field registers within the X16 bandwidth are consistent. If they are consistent, the bandwidth allocated to the Port is X16. If they are inconsistent, an alternating voltage is applied to the lanes at both ends of each X8 of the Port for detection, and the states of the lane induced electric field registers within the x8 bandwidth are read to check whether they are consistent. If the states of the internal lane induced electric field registers are still inconsistent, the lane detection operations of X4 and X2 are performed in turn. If the consistency of the lane induced electric field register states is still not obtained after detection under the lane state of X2, the two lanes of X2 are allocated to X1, and the bandwidth allocation of each lane is finally determined.

[0085] The device bandwidth allocation system provided by the embodiment of the present invention comprises: a target device and a central processing unit, wherein a weak potential induction amplification circuit and a channel induction electric field register are arranged on the slot of the target device, wherein the slot supports a number of channels corresponding to the target device type, and the channel induction electric field register is connected to the central processing unit; the weak potential induction amplification circuit is used to detect the induced electromotive force corresponding to each of the channels when an alternating voltage is detected in the channels at both ends of the target device, and determine the induced voltage state corresponding to each of the channels based on the induced electromotive force; the channel induction electric field register is used to store the value of the induced voltage state corresponding to each of the channels; the central processing unit reads the value of the induced voltage state corresponding to each of the channels in the channel induction electric field register, and determines the bandwidth allocation state of each channel based on the value of the induced voltage state in the channel induction electric field register within the target bandwidth. The detection mechanism of the embodiment of the present invention is stable and reliable; it does not need to occupy GPIO resources, and does not need to occupy additional communication interfaces such as IIC. It realizes the fully automated and intelligent identification and allocation of server PCIe device bandwidth allocation. Each device only needs to have a weak potential sensing amplification circuit on each PCIe lane. If there is an induced electromotive force on this lane, the corresponding induced voltage state value will be written into the induced electric field register. By applying alternating voltage to the lanes at both ends of each PCIe Port X16, it is detected whether the lane induced electric field register state within its bandwidth is consistent, and the bandwidth allocation of each lane is finally determined. The bandwidth allocation is more accurate and fast, avoiding the use of the intermediate bandwidth allocation table for coordination and verification, improving the bandwidth allocation efficiency, and achieving the effect of multiple devices being directly connected to one PCIe slot without being affected by the bandwidth, avoiding the small error in the voltage value of the PCIe slot being directly collected, and improving the accuracy of the central processor in identifying PCIe devices and the accuracy of bandwidth allocation.

[0086] Reference Figure 2, shows a flow chart of the steps of a device bandwidth allocation method provided by an embodiment of the present invention, the method may include:

[0087] Step 101, in the case where it is detected that there is an alternating voltage in the channels at both ends of the target device, detecting the induced electromotive force corresponding to each of the channels, determining the induced voltage state corresponding to each of the channels based on the induced electromotive force, and storing the value of the induced voltage state corresponding to each of the channels;

[0088] Step 102, reading the value of the induced voltage state corresponding to each of the channels in the channel induced electric field register, and determining the bandwidth allocation state of each channel based on the value of the induced voltage state in the channel induced electric field register within the target bandwidth.

[0089] Further, the determining of the bandwidth allocation state of each channel based on the value of the induced voltage state in the channel induced electric field register within the target bandwidth includes:

[0090] According to the preset bandwidth allocation rule, it is determined in turn whether the values ​​of the induced voltage states in the channel induced electric field registers within different target bandwidths are consistent, and the bandwidth allocation state of each channel is output.

[0091] Furthermore, the target bandwidth includes a first bandwidth, a second bandwidth, a third bandwidth, a fourth bandwidth and a fifth bandwidth.

[0092] Further, determining in sequence whether the values ​​of the induced voltage states in the channel induced electric field registers within different target bandwidths are consistent according to the preset bandwidth allocation rule, and outputting the bandwidth allocation state of each channel includes:

[0093] Determining whether the induced voltage states in the channel induced electric field registers within the first bandwidth are consistent;

[0094] If not, determining whether the induced voltage states in the channel induced electric field registers within the second bandwidth are consistent, wherein the second bandwidth is smaller than the first bandwidth;

[0095] If not, determining whether the induced voltage states in the channel induced electric field registers within the third bandwidth are consistent, wherein the third bandwidth is smaller than the second bandwidth;

[0096] If not, determining whether the induced voltage states in the channel induced electric field registers within the fourth bandwidth are consistent, wherein the fourth bandwidth is smaller than the third bandwidth;

[0097] If not, the two channels corresponding to the fourth bandwidth are allocated as the fifth bandwidth, and the bandwidth allocation state of each channel is the fifth bandwidth, wherein the fifth bandwidth is smaller than the fourth bandwidth.

[0098] It should be noted that, in the embodiment of the present application, the first bandwidth, the second bandwidth, the third bandwidth, the fourth bandwidth and the fifth bandwidth are X16, X8, X4, X2 and X1 respectively.

[0099] Apply alternating voltage to the lanes at both ends of each PCIe Port X16 to detect whether the states of the lane induced electric field registers within the X16 bandwidth are consistent. If they are consistent, the bandwidth allocated to the port is X16. If they are inconsistent, apply alternating voltage to the lanes at both ends of each X8 of the port for detection, and similarly read the states of the lane induced electric field registers within the x8 bandwidth to check whether they are consistent. If the states of the internal lane induced electric field registers are still inconsistent, perform lane detection operations on X4 and X2 in turn. If the consistency of the lane induced electric field register states is still not obtained after detection under the lane state of X2, the two lanes of X2 are allocated to X1, and finally the bandwidth allocation of each lane is determined.

[0100] Further, before the step of detecting the presence of alternating voltages in the channels at both ends of the target device, detecting the induced electromotive force corresponding to each of the channels, and determining the induced voltage state corresponding to each of the channels based on the induced electromotive force, the method includes:

[0101] Applying alternating voltages in opposite directions to the positive signal transmission line corresponding to any first channel and the negative signal transmission line corresponding to any second channel;

[0102] If the first channel and the second channel correspond to the same target device, the positive signal transmission line corresponding to the first channel and the negative signal transmission line corresponding to the second channel generate an effective closed electric field;

[0103] If the first channel and the second channel correspond to different target devices, the positive signal transmission line corresponding to the first channel and the negative signal transmission line corresponding to the second channel generate an invalid non-enclosed electric field.

[0104] It should be noted that in the embodiment of the present application, the weak electric potential sensing amplification circuit on each PCIe lan determines whether the state of the induced electric field register of each lane is consistent by identifying the state consistency of the lane induced electric field register, and then determines whether the same device is plugged into adjacent lanes.

[0105] Further, after the step of generating an effective closed electric field by the positive signal transmission line corresponding to the first channel and the negative signal transmission line corresponding to the second channel if the first channel and the second channel correspond to the same target device, the method includes:

[0106] generating a target induced magnetic field based on the effective closed electric field;

[0107] In the target induced magnetic field, the induced electromotive force corresponding to each channel is obtained through a weak potential induction amplification circuit.

[0108] The detection mechanism of the embodiment of the present invention is stable and reliable; it does not need to occupy GPIO resources, and does not need to occupy additional IIC and other communication interfaces. It realizes the fully automated intelligent identification and allocation of bandwidth allocation of server PCIe devices. It only needs each device to have a weak potential sensing amplification circuit on each PCIe lane. Whether there is an induced electromotive force on this lane, the corresponding induced voltage state value will be written into the induced electric field register. By applying an alternating voltage to the lanes at both ends of each PCIe Port X16, it is detected whether the states of the lane induced electric field registers within its bandwidth are consistent, and finally the bandwidth allocation of each lane is determined. The bandwidth allocation is more accurate and fast, avoiding the use of the intermediate bandwidth allocation table for coordination and verification, improving the bandwidth allocation efficiency, and realizing the effect of plugging multiple devices into one PCIe slot, which is directly unaffected by the bandwidth, avoiding the error of directly collecting the voltage value of the PCIe slot, and improving the accuracy of the central processor in identifying PCIe devices and the accuracy of bandwidth allocation.

[0109] Reference Figure 3 The embodiment of the present invention further provides a device bandwidth allocation apparatus, the apparatus comprising:

[0110] The first module 301 is used to detect the induced electromotive force corresponding to each channel when it is detected that there is an alternating voltage in the channels at both ends of the target device, determine the induced voltage state corresponding to each channel based on the induced electromotive force, and store the value of the induced voltage state corresponding to each channel;

[0111] The second module 302 reads the value of the induced voltage state corresponding to each of the channels in the channel induced electric field register, and determines the bandwidth allocation state of each channel based on the value of the induced voltage state in the channel induced electric field register within the target bandwidth.

[0112] The device bandwidth allocation device provided by the embodiment of the present invention has a stable and reliable detection mechanism; it does not need to occupy GPIO resources, and does not need to occupy additional communication interfaces such as IIC. It realizes the fully automated intelligent identification and allocation of server PCIe device bandwidth allocation. It only needs each device to have a weak potential sensing amplification circuit on each PCIe lane. Whether there is an induced electromotive force on this lane, the corresponding induced voltage state value will be written into the induced electric field register. By applying an alternating voltage to the lanes at both ends of each PCIe PortX16, it is detected whether the lane induced electric field register state within its bandwidth is consistent, and finally the bandwidth allocation of each lane is determined. The bandwidth allocation is more accurate and fast, avoiding the use of the intermediate bandwidth allocation table for coordination and verification, improving the bandwidth allocation efficiency, and realizing a PCIe slot plug-in multiple devices, which are directly unaffected by the bandwidth, avoiding the error of directly collecting the voltage value of the PCIe slot, and improving the accuracy of the central processor in identifying the PCIe device and the accuracy of bandwidth allocation.

[0113] The embodiment of the present invention also provides a communication device, such as Figure 4 As shown, it includes a processor 401, a communication interface 402, a memory 403 and a communication bus 404, wherein the processor 401, the communication interface 402, and the memory 403 communicate with each other through the communication bus 404.

[0114] Memory 403, used for storing computer programs;

[0115] The processor 401, when used to execute the program stored in the memory 403, can implement the following steps:

[0116] In the case where it is detected that there is an alternating voltage in the channels at both ends of the target device, detecting the induced electromotive force corresponding to each of the channels, determining the induced voltage state corresponding to each of the channels based on the induced electromotive force, and storing the value of the induced voltage state corresponding to each of the channels;

[0117] The value of the induced voltage state corresponding to each of the channels in the channel induced electric field register is read, and the bandwidth allocation state of each channel is determined based on the value of the induced voltage state in the channel induced electric field register within the target bandwidth.

[0118] Among them, the memory and the processor are connected in a bus manner, and the bus may include any number of interconnected buses and bridges, and the bus connects various circuits of one or more processors and memories together. The bus can also connect various other circuits such as peripheral devices, voltage regulators, and power management circuits together, which are all well known in the art, so this article will not further describe them. The bus interface provides an interface between the bus and the transceiver. The transceiver can be one element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices on a transmission medium. The data processed by the processor can be transmitted on a wired medium or on a wireless medium through an antenna. Further, the antenna also receives data and transmits the data to the processor. The processor is responsible for managing the bus and general processing, and can also provide various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. The memory can be used to store data used by the processor when performing operations.

[0119] The communication bus mentioned in the above terminal can be a peripheral component interconnect standard (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0120] The communication interface is used for communication between the above terminal and other devices.

[0121] The memory may include a random access memory (RAM) or a non-volatile memory, such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

[0122] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0123] In another embodiment of the present invention, a computer-readable storage medium is provided. The computer-readable storage medium stores instructions. When the instructions are executed on a computer, the computer executes the device bandwidth allocation method described in any of the above embodiments.

[0124] In another embodiment of the present invention, a computer program product including instructions is provided. When the computer program product is run on a computer, the computer executes the device bandwidth allocation method described in any one of the above embodiments.

[0125] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive Solid State Disk (SSD)), etc.

[0126] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0127] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0128] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A device bandwidth allocation system, characterized in that: The device bandwidth allocation system comprises: a target device and a central processor, a slot of the target device is provided with a weak potential sensing amplification circuit and a channel sensing electric field register, the slot supports a number of channels corresponding to the type of the target device, and the channel sensing electric field register is connected to the central processor; The weak potential sensing amplifier circuit is used to detect the induced electromotive force corresponding to each channel when detecting the presence of alternating voltage in the channels at both ends of the target device, and determine the induced voltage state corresponding to each channel based on the induced electromotive force; The channel induced electric field register is used to store the value of the induced voltage state corresponding to each of the channels; The central processing unit reads the value of the induced voltage state corresponding to each of the channels in the channel induced electric field register, and determines the bandwidth allocation state of each channel based on the value of the induced voltage state in the channel induced electric field register within the target bandwidth.

2. The system according to claim 1, characterized in that The weak potential induction amplifier circuit is an analog voltage amplifier circuit based on a gate circuit.

3. The system according to claim 2, characterized in that The weak potential sensing amplification circuit comprises a plurality of NOT gates connected in series in sequence, and a plurality of the NOT gates are connected in parallel with a target resistor.

4. The system according to claim 1, characterized in that Each of the channels includes four signal lines, and the four signal lines include a transmitting positive signal line, a transmitting negative signal line, a receiving positive signal line, and a receiving negative signal line.

5. The system according to claim 4, characterized in that The induced voltage state includes any one of a negative voltage state, a positive voltage state and a no induced voltage state.

6. The system according to claim 5, characterized in that The channels at both ends of the target device include a first channel and a second channel, and the non-induced voltage state is determined by the first channel and the second channel being allocated to different devices to generate a non-enclosed electric field.

7. A device bandwidth allocation method, characterized in that: Applied to the device bandwidth allocation system described in any one of claims 1 to 6, the method comprising: In the case where it is detected that there is an alternating voltage in the channels at both ends of the target device, detecting the induced electromotive force corresponding to each of the channels, determining the induced voltage state corresponding to each of the channels based on the induced electromotive force, and storing the value of the induced voltage state corresponding to each of the channels; The value of the induced voltage state corresponding to each of the channels in the channel induced electric field register is read, and the bandwidth allocation state of each channel is determined based on the value of the induced voltage state in the channel induced electric field register within the target bandwidth.

8. The method according to claim 7, characterized in that The determining of the bandwidth allocation state of each channel based on the value of the induced voltage state in the channel induced electric field register within the target bandwidth includes: According to the preset bandwidth allocation rule, it is determined in turn whether the values ​​of the induced voltage states in the channel induced electric field registers within different target bandwidths are consistent, and the bandwidth allocation state of each channel is output.

9. The method according to claim 8, characterized in that The target bandwidth includes a first bandwidth, a second bandwidth, a third bandwidth, a fourth bandwidth, and a fifth bandwidth.

10. The method according to claim 9, characterized in that The step of determining in sequence whether the values ​​of the induced voltage states in the channel induced electric field registers within different target bandwidths are consistent according to the preset bandwidth allocation rule, and outputting the bandwidth allocation state of each channel includes: Determining whether the induced voltage states in the channel induced electric field registers within the first bandwidth are consistent; If not, determining whether the induced voltage states in the channel induced electric field registers within the second bandwidth are consistent, wherein the second bandwidth is smaller than the first bandwidth; If not, determining whether the induced voltage states in the channel induced electric field registers within the third bandwidth are consistent, wherein the third bandwidth is smaller than the second bandwidth; If not, determining whether the induced voltage states in the channel induced electric field registers within the fourth bandwidth are consistent, wherein the fourth bandwidth is smaller than the third bandwidth; If not, the two channels corresponding to the fourth bandwidth are allocated as the fifth bandwidth, and the bandwidth allocation state of each channel is the fifth bandwidth, wherein the fifth bandwidth is smaller than the fourth bandwidth.

11. The method according to claim 7, characterized in that Before the step of detecting the presence of alternating voltages in the channels at both ends of the target device, detecting the induced electromotive force corresponding to each of the channels, and determining the induced voltage state corresponding to each of the channels based on the induced electromotive force, the method includes: Applying alternating voltages in opposite directions to the positive signal transmission line corresponding to any first channel and the negative signal transmission line corresponding to any second channel; If the first channel and the second channel correspond to the same target device, the positive signal transmission line corresponding to the first channel and the negative signal transmission line corresponding to the second channel generate an effective closed electric field; If the first channel and the second channel correspond to different target devices, the positive signal transmission line corresponding to the first channel and the negative signal transmission line corresponding to the second channel generate an invalid non-enclosed electric field.

12. The method according to claim 11, characterized in that After the step of generating an effective closed electric field by the positive signal transmission line corresponding to the first channel and the negative signal transmission line corresponding to the second channel if the first channel and the second channel correspond to the same target device, the method includes: generating a target induced magnetic field based on the effective closed electric field; In the target induced magnetic field, the induced electromotive force corresponding to each channel is obtained through a weak potential induction amplification circuit.

13. A communication device, characterized in that: include: A transceiver, a memory, a processor, and a program stored on the memory and executable on the processor; The processor is used to read the program in the memory to implement the device bandwidth allocation method as described in any one of claims 7 to 12.

14. A readable storage medium for storing a program, characterized in that: When the program is executed by a processor, the device bandwidth allocation method as described in any one of claims 7 to 12 is implemented.

15. A computer program product, comprising instructions stored on a non-transitory computer-readable storage medium, and when the instructions are executed by a computer, the device bandwidth allocation method according to any one of claims 7 to 12 is implemented.

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