Scanning circuit and display panel

Abstract

The present invention discloses a scanning circuit and a display panel. The scanning circuit includes: a driving control module, a first output module, and a second output module. The driving control module is used to control the potential of the first node and the second node according to a trigger input signal, a first clock signal, a second clock signal, and a first potential signal; the first output module is used to output a third clock signal in response to the potential of the first node, or to output a first potential signal in response to the potential of the second node; the second output module is used to output the first clock signal in response to the potential of the first node, or to output the first potential signal in response to the potential of the second node; wherein the waveforms of the first clock signal and the second clock signal are the same and the pulses do not overlap, the pulse width of the first clock signal is greater than the pulse width of the third clock signal; and the pulse time of the third clock signal is within the pulse time of the first clock signal. The present invention is conducive to the realization of a narrow bezel of a display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a scanning circuit and a display panel. Background Art

[0002] With the continuous development of display technology, the application range of display panels is becoming increasingly broad, and people's requirements for display panels are also becoming increasingly higher. Display panels include pixel circuits and scanning circuits that provide scanning signals to the pixel circuits. The scanning circuit provides scanning signals for each row of pixel circuits to scan row by row, driving the pixel circuits to complete processes such as reset and data writing.

[0003] In the prior art, in order to enhance the threshold compensation effect of the driving transistor in the pixel circuit and thus improve display uniformity, a scheme is designed to separately control the data writing transistor and the threshold compensation transistor. By setting the pulse width of the scanning signal connected to the threshold compensation transistor to be greater than the pulse width of the scanning signal connected to the data writing transistor, the threshold compensation time of the driving transistor is extended, thereby achieving sufficient threshold compensation. However, in the prior art, each row scanning circuit can only output one duty cycle waveform, and the same set of cascaded scanning circuits can only output one set of scanning signals with the same pulse width. In order to provide scanning signals with different pulse widths (or different duty cycles), two sets of scanning circuits are required, which makes the overall structure of the scanning driving circuit complex and is not conducive to the design of a narrow bezel of the display panel. Summary of the Invention

[0004] The present invention provides a scanning circuit and a display panel, so that the same scanning circuit outputs two scanning signals with different pulse widths, which is beneficial to the realization of a narrow frame of the display panel.

[0005] In a first aspect, an embodiment of the present invention provides a scanning circuit, comprising:

[0006] a drive control module, wherein the first output terminal and the second output terminal of the drive control module are connected to the first node and the second node respectively; the drive control module is used to control the potential of the first node and the second node according to the trigger input signal, the first clock signal, the second clock signal and the first potential signal;

[0007] a first output module, connected to the first node and the second node, respectively, configured to output the third clock signal as the first scanning signal in response to the potential of the first node, or output the first potential signal as the first scanning signal in response to the potential of the second node;

[0008] a second output module, connected to the first node and the second node, respectively, and configured to output the first clock signal as a second scanning signal in response to the potential of the first node, or output the first potential signal as the second scanning signal in response to the potential of the second node;

[0009] The first clock signal and the second clock signal have the same waveform and their pulses do not overlap; the pulse width of the first clock signal is greater than the pulse width of the third clock signal; and the pulse time of the third clock signal is within the pulse time of the first clock signal.

[0010] Optionally, the first output module includes: a first output unit connected to the first node, configured to output the third clock signal as the first scanning signal in response to the potential of the first node;

[0011] a second output unit, connected to the second node, and configured to respond to the potential of the second node and output the first potential signal as the first scanning signal;

[0012] Preferably, the first output unit comprises: a first transistor; a gate of the first transistor is connected to the first node, a first electrode of the first transistor is connected to the third clock signal, and a second electrode of the first transistor is connected to the output end of the first output module;

[0013] The second output unit includes: a second transistor and a first capacitor; the gate of the second transistor is connected to the second node and the first end of the first capacitor respectively, the first electrode of the second transistor and the second end of the first capacitor are both connected to the first potential signal, and the second electrode of the second transistor is connected to the output end of the first output module;

[0014] Preferably, the first output unit further includes: a second capacitor connected between the gate of the first transistor and the output end of the first output module.

[0015] Optionally, the second output module includes: a third output unit connected to the first node, configured to respond to the potential of the first node and output the first clock signal as the second scanning signal;

[0016] a fourth output unit, connected to the second node, and configured to respond to the potential of the second node and output the first potential signal as the second scanning signal;

[0017] Preferably, the third output unit includes: a third transistor and a third capacitor; the gate of the third transistor is connected to the first node, the first electrode of the third transistor is connected to the first clock signal, and the second electrode of the third transistor is connected to the output end of the second output module; the third capacitor is connected between the gate of the third transistor and the output end of the second output module;

[0018] The fourth output unit includes: a fourth transistor; the gate of the fourth transistor is connected to the second node, the first electrode of the fourth transistor is connected to the first potential signal, and the second electrode of the fourth transistor is connected to the output end of the second output module.

[0019] Optionally, the drive control module includes: a trigger input unit connected to the first node, and configured to control the potential of the first node according to the trigger input signal and the second clock signal;

[0020] a potential control unit, connected to the second node, and configured to control the potential of the second node according to the second clock signal;

[0021] A node inter-control unit is respectively connected to the first node and the second node, and is used to transmit the second clock signal to the second node in response to the potential of the first node, or to transmit the first potential signal to the first node in response to the first clock signal and the potential of the second node.

[0022] Optionally, the trigger input unit includes: a fifth transistor, a gate of the fifth transistor is connected to the second clock signal, a first electrode of the fifth transistor is connected to the trigger input signal, and a second electrode of the fifth transistor is connected to the first node.

[0023] Optionally, the potential control unit includes: a sixth transistor;

[0024] The gate of the sixth transistor is connected to the second clock signal, the first electrode of the sixth transistor is connected to the second potential signal, and the second electrode of the sixth transistor is connected to the second node;

[0025] Alternatively, the gate electrode and the first electrode of the sixth transistor are both connected to the second clock signal, and the second electrode of the sixth transistor is connected to the second node.

[0026] Optionally, the node mutual control unit includes: a first node control subunit, configured to transmit the second clock signal to the second node in response to the potential of the first node;

[0027] a second node control subunit, configured to transmit the first potential signal to the first node in response to the first clock signal and the potential of the second node;

[0028] Preferably, the first node control subunit includes: a seventh transistor; a gate of the seventh transistor is connected to the first node, a first electrode of the seventh transistor is connected to the second clock signal, and a second electrode of the seventh transistor is connected to the second node;

[0029] The second node control subunit includes: an eighth transistor and a ninth transistor; the gate of the eighth transistor is connected to the second node, the first electrode of the eighth transistor is connected to the first potential signal, the second electrode of the eighth transistor is connected to the first electrode of the ninth transistor, the gate of the ninth transistor is connected to the first clock signal, and the second electrode of the ninth transistor is connected to the first node;

[0030] Preferably, at least one of the seventh transistor, the eighth transistor and the ninth transistor is a dual-gate transistor.

[0031] Optionally, the scanning circuit further includes: a protection module; a control terminal of the protection module is connected to the second potential signal, a first terminal of the protection module is connected to the first node, and a second terminal of the protection module is connected to the first output module and the second output module;

[0032] Preferably, the protection module includes: a tenth transistor; the gate of the tenth transistor serves as the control end of the protection module, the first electrode of the tenth transistor serves as the first end of the protection module, and the second electrode of the tenth transistor serves as the second end of the protection module.

[0033] In a second aspect, an embodiment of the present invention further provides a display panel comprising: a plurality of cascade-connected scanning circuits such as those provided in any embodiment of the present invention; wherein the second scanning signal output by the scanning circuit at this level serves as a trigger input signal for the scanning circuit at the next level.

[0034] Optionally, the display panel further includes: an input signal line, a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line;

[0035] The input signal line is connected to the drive control module in the first-stage scanning circuit; the signal transmitted in the input signal line serves as a trigger input signal for the first-stage scanning circuit;

[0036] The first clock signal line is respectively connected to the drive control module and the second output module in the odd-numbered scanning circuit, and the drive control module in the even-numbered scanning circuit; the signal transmitted by the first clock signal line is respectively used as the first clock signal of the odd-numbered scanning circuit and the second clock signal of the even-numbered scanning circuit;

[0037] The second clock signal line is connected to the drive control module in the odd-numbered scanning circuit and the drive control module and the second output module in the even-numbered scanning circuit respectively; the signal transmitted by the second clock signal line serves as the second clock signal of the odd-numbered scanning circuit and the first clock signal of the even-numbered scanning circuit respectively.

[0038] The third clock signal line is connected to the first output module in the odd-numbered scanning circuit; the signal transmitted by the third clock signal line serves as the third clock signal of the odd-numbered scanning circuit;

[0039] The fourth clock signal line is connected to the first output module in the even-level scanning circuit; the signal transmitted by the fourth clock signal line serves as the third clock signal of the even-level scanning circuit; wherein the waveform of the signal transmitted by the third clock signal line is the same as that of the signal transmitted by the fourth clock signal line and the pulses do not overlap.

[0040] The scanning circuit provided by the embodiment of the present invention includes a driving control module, a first output module and a second output module, and is connected to three clock signals. Among them, the first clock signal and the second clock signal are clock signals with the same pulse width, and the two can cooperate with the trigger input signal and the first potential signal to control the output state of the driving control module, thereby controlling the potential of the first node and the second node. Based on the potential of the first node and the second node, the first output module can output at least one pulse of the third clock signal as a pulse of the first scanning signal, and the second output module can output at least one pulse of the first clock signal as a pulse of the second scanning signal. Since the pulse widths of the first clock signal and the third clock signal are different, the scanning circuit can simultaneously output two scanning signals with different pulse widths. In this way, compared with the solution of providing two groups of scanning circuits in the prior art, the embodiment of the present invention only requires one group of scanning circuits, which simplifies the structure of the scanning driving circuit as a whole, and is conducive to the realization of a narrow frame of the display panel.

[0041] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0043] Figure 1 This is a schematic structural diagram of a scanning circuit provided by an embodiment of the present invention;

[0044] Figure 2 is a structural diagram of another scanning circuit provided by an embodiment of the present invention;

[0045] Figure 3 This is a driving timing diagram of a scanning circuit provided by an embodiment of the present invention;

[0046] Figure 4 This is a driving timing diagram of another scanning circuit provided by an embodiment of the present invention;

[0047] Figure 5 This is a structural diagram of another scanning circuit provided by an embodiment of the present invention;

[0048] Figure 6 This is a structural diagram of another scanning circuit provided by an embodiment of the present invention;

[0049] Figure 7 is a structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0050] Figure 8 This is a driving timing diagram of a display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0051] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0052] It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and the accompanying drawings are used to distinguish similar items and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, such that the embodiments of the present invention described herein can be implemented in sequences other than those illustrated or described herein. Furthermore, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions.

[0053] An embodiment of the present invention provides a scanning circuit, which enables the same scanning circuit to output two scanning signals with different pulse widths. Figure 1 FIG is a schematic diagram of a scanning circuit provided by an embodiment of the present invention. Figure 1 The scanning circuit 100 includes: a driving control module 10 , a first output module 20 and a second output module 30 .

[0054] The first and second output terminals of the drive control module 10 are connected to the first and second nodes N1, N2, respectively. The drive control module 10 is configured to control the potentials of the first and second nodes N1, N2, based on a trigger input signal SIN, a first clock signal SCK1, a second clock signal SCK2, and a first potential signal VGH. The first output module 20 is connected to the first and second nodes N1, N2, and is configured to output the third clock signal SCK3 as a first scan signal GOUT1 in response to the potential of the first node N1, or to output the first potential signal VGH as a first scan signal GOUT1 in response to the potential of the second node N2. The second output module 30 is connected to the first and second nodes N1, N2, and is configured to output the first clock signal SCK1 as a second scan signal GOUT2 in response to the potential of the first node N1, or to output the first potential signal VGH as a second scan signal in response to the potential of the second node N2. Among them, the waveforms of the first clock signal SCK1 and the second clock signal SCK2 are the same and the pulses do not overlap; the pulse width of the first clock signal SCK1 is greater than the pulse width of the third clock signal SCK3, and the pulse time of the third clock signal SCK3 is within the pulse time of the first clock signal SCK1.

[0055] Among them, the pulses of each of the above-mentioned clock signals refer to the on-pulses of each clock signal. For example, if the on-potential of the functional unit connected to the clock signal is a low potential, then the pulse of the clock signal refers to a low potential pulse. In addition, the pulses of other signals involved in this article also refer to on-pulses, that is, the pulses of each signal refer to the pulses corresponding to the potential that controls the on-state of the functional unit connected to the signal. Pulse width refers to the duration of the on-potential of the signal within a pulse cycle. When the pulse cycle is the same, the larger the pulse width of the signal, the larger the duty cycle of the signal. The first clock signal SCK1 and the second clock signal SCK2 have the same waveform and non-overlapping pulses, which means that the high and low potential values of the first clock signal SCK1 and the second clock signal SCK2 are the same, the pulse width is the same, and the pulses of the first clock signal SCK1 and the second clock signal SCK2 appear alternately. The pulse time of the third clock signal SCK3 is within the pulse time of the first clock signal SCK1, which can be understood as: the pulse start time of the third clock signal SCK3 is not earlier than the pulse start time of the first clock signal SCK1, and the pulse end time of the third clock signal SCK3 is not later than the pulse end time of the first clock signal SCK1.

[0056] Exemplarily, the first clock signal SCK1, the second clock signal SCK2, and the third clock signal SCK3 are clock signals with the same pulse frequency. The pulse widths of the first clock signal SCK1 and the second clock signal SCK2 are the same, and the pulses of the first clock signal SCK1 and the second clock signal SCK2 appear alternately; the pulse width of the first clock signal SCK1 is greater than the pulse width of the third clock signal SCK3, and the pulses of the first clock signal SCK1 overlap the pulses of the third clock signal SCK3. The first potential signal VGH can be a DC voltage signal, which can be set to the cut-off potential of the scan signal, for example, a high potential. The trigger input signal SIN can be a pulse signal with a low on-state potential, and its pulse width at least overlaps the pulse width of the first clock signal SCK1.

[0057] Exemplarily, the output states of the scanning circuit include:

[0058] In the first output state, the drive control module 10 controls the first node N1 to be at an on-state potential, causing the first output module 20 to output the third clock signal SCK3 as the first scan signal GOUT1 in response to the on-state potential of the first node N1; and the second output module 30 to output the first clock signal SCK1 as the second scan signal GOUT2 in response to the on-state potential of the first node N1. This output state lasts for at least the duration of one pulse of the first clock signal SCK1, so that the first scan signal GOUT1 includes a complete pulse of the third clock signal SCK3, and the second scan signal GOUT2 includes a complete pulse of the first clock signal SCK1.

[0059] In the second output state, the drive control module 10 controls the second node N2 to be at an on-state potential, causing the first output module 20 to respond to the on-state potential of the second node N2 and output the first potential signal VGH as the first scanning signal GOUT1. The second output module 30 responds to the on-state potential of the second node N2 and outputs the first potential signal VGH as the second scanning signal GOUT2. In this output state, both the first scanning signal GOUT1 and the second scanning signal GOUT2 maintain an off-state potential.

[0060] In summary, based on the trigger input signal SIN, the first clock signal SCK1, the second clock signal SCK2, and the first potential signal VGH, the drive control module 10 controls the potentials of the first node N1 and the second node N2 to control the onset and duration of each output state in the scanning circuit 100, thereby achieving drive control of the scanning circuit 100. Specifically, the first output module 20 and the second output module 30 can have the same circuit structure; based on the potentials of the first node N1 and the second node N2, the first output module 20 and the second output module 30 can have the same conduction state; the only difference is that when the lower input and output terminals of the output modules are connected, the first output module 20 outputs the third clock signal SCK3, and the second output module 30 outputs the first clock signal SCK1. Therefore, the pulse widths of the first scanning signal GOUT1 and the second scanning signal GOUT2 can correspond to the pulse widths of the third clock signal SCK3 and the first clock signal SCK1, respectively. The two scanning signals output by the scanning circuit 100 can have the same pulse frequency and different pulse widths. By adjusting the pulse width of the first clock signal SCK1 and the third clock signal SCK3, the pulse width of each scanning signal can be conveniently adjusted. It should be noted that when the first clock signal SCK1 and the third clock signal SCK3 are both at the cut-off potential, the first output state and the second output state can appear simultaneously.

[0061] The scanning circuit 100 provided in an embodiment of the present invention includes a drive control module 10, a first output module 20, and a second output module 30, and is connected to three clock signals. The first clock signal SCK1 and the second clock signal SCK2 are clock signals with the same pulse width. They can cooperate with the trigger input signal SIN and the first potential signal VGH to control the output state of the drive control module 10, thereby controlling the potential of the first node N1 and the second node N2. Based on the potential of the first node N1 and the second node N2, the first output module 20 can output at least one pulse of the third clock signal SCK3 as a pulse of the first scanning signal GOUT1, and the second output module 30 can output at least one pulse of the first clock signal SCK1 as a pulse of the second scanning signal GOUT2. Because the pulse widths of the first clock signal SCK1 and the third clock signal SCK3 are different, the scanning circuit can simultaneously output two scanning signals of different pulse widths. Thus, compared to the solution of providing two sets of scanning circuits in the prior art, the embodiment of the present invention only requires one set of scanning circuits, which simplifies the structure of the scanning drive circuit as a whole and facilitates the realization of a narrow bezel on the display panel.

[0062] The driving process of the scanning circuit is described below in combination with a specific driving sequence and a specific functional unit structure that may be included in each module.

[0063] Figure 2 FIG is a schematic diagram of another scanning circuit provided by an embodiment of the present invention. Figure 2 Exemplarily, the scanning circuit includes: a trigger input terminal 71, a first potential signal terminal 61, a second potential signal terminal 62, a first clock terminal 51, a second clock terminal 52, and a third clock terminal 53, respectively used to receive the trigger input signal SIN, the first potential signal VGH, the second potential signal VGL, the first clock signal SCK1, the second clock signal SCK2, and the third clock signal SCK3 required by the scanning circuit. In addition, the scanning circuit includes: a first scanning output terminal 81 and a second scanning output terminal 82, respectively used to output the first scanning signal GOUT1 and the second scanning signal GOUT2. Exemplarily, the logic of the first potential signal VGL and the second potential signal VGH are opposite, for example, the first potential signal VGL is a low potential signal, and the second potential signal VGH is a high potential signal.

[0064] See also Figure 2 In one embodiment, the drive control module 10 optionally includes: a trigger input unit 110, a potential control unit 120, and a node mutual control unit 130. Based on the joint control of the trigger input unit 110, the potential control unit 120, and the node mutual control unit 130, the time during which the first node N1 is stabilized at the on-potential and the time during which the second node N2 is stabilized at the off-potential covers the pulse duration of the first clock signal SCK1 and the third clock signal SCK3, so that the first output module 20 can output the pulse of the third clock signal SCK3, and the second output module 30 can output the pulse of the first clock signal SCK1, so that the first scanning signal GOUT1 and the second scanning signal GOUT2 constitute two scanning signals with the same pulse frequency but different pulse widths.

[0065] The trigger input unit 110 is configured to control the potential of the first node N1 based on the trigger input signal SIN and the second clock signal SCK2. For example, the trigger input unit 110 is connected to the trigger input terminal 71, the second clock terminal 52, and the first node N1, respectively, and is configured to transmit the trigger input signal SIN to the first node N1 in response to the second clock signal SCK2.

[0066] The potential control unit 120 is configured to control the potential of the second node N2 according to the second clock signal SCK2. For example, the potential control unit 120 is connected to the second clock terminal 52, the second potential signal terminal 62, and the second node N2, respectively, and is configured to transmit the second potential signal VGL to the second node N2 in response to the second clock signal SCK2.

[0067] The node inter-control unit 130 is configured to transmit the second clock signal SCK2 to the second node N2 in response to the potential of the first node N1 , or transmit the first potential signal VGH to the first node N1 in response to the first clock signal SCK1 and the potential of the second node N2 .

[0068] Specifically, the node mutual control unit 130 includes a first node control subunit 131 and a second node control subunit 132. The first node control subunit 131 is connected to the first node N1, the second node N2, and the second clock terminal 52, respectively, and is configured to transmit the second clock signal SCK2 to the second node N2 in response to the potential of the first node N1. The second node control subunit 132 is connected to the first node N1, the second node N2, the first clock terminal 51, and the first potential signal terminal 61, respectively, and is configured to transmit the first potential signal VGH to the first node N1 in response to the first clock signal SCK1 and the potential of the second node N2. The two node mutual control subunits can achieve mutual control of the node potentials of the first node N1 and the second node N2. When the trigger input unit 110 and / or the potential control unit 120 are turned off, a stable potential is provided to the first node N1 and the second node N2 as much as possible, thereby ensuring the accuracy of the output states of the first output module 40 and the second output module 50, thereby improving the output stability of the scanning circuit.

[0069] Continue to see Figure 2 Based on the above embodiments, the first output module 20 optionally includes a first output unit 210 and a second output unit 220, each of which controls whether the third clock signal SCK3 and the first potential signal VGH are output from the first scan output terminal 81. The first output unit 210 is connected to the first node N1 and is configured to output the third clock signal SCK3 as the first scan signal GOUT1 in response to the potential of the first node N1. The second output unit 220 is connected to the second node N2 and is configured to output the first potential signal VGH as the first scan signal GOUT1 in response to the potential of the second node N2.

[0070] Continue to see Figure 2 Based on the above embodiments, the second output module 30 optionally includes: a third output unit 310 and a fourth output unit 320, which respectively control whether the first clock signal SCK1 and the first potential signal VGH are output from the second scan output terminal 82. The third output unit 310 is connected to the first node N1 and is configured to respond to the potential of the first node N1 and output the first clock signal SCK1 as the second scan signal GOUT2; the fourth output unit 320 is connected to the second node N2 and is configured to respond to the potential of the second node N2 and output the first potential signal VGH as the second scan signal GOUT2.

[0071] Figure 31 is a driving timing diagram of a scanning circuit provided by an embodiment of the present invention. Figure 2 and Figure 3 , taking the case where the on-state potentials of all signals are low as an example, illustratively, the driving process of the scanning circuit includes:

[0072] In the first phase T1, the trigger input signal SIN and the second clock signal SCK2 are both at a low level, while the first clock signal SCK1 and the third clock signal SCK3 are both at a high level. The trigger input unit 110 turns on, transmitting the low level of the trigger input signal SIN to the first node N1, causing the potential VN1 of the first node N1 to be low. In response to the low level of the first node N1, the first node control subunit 131 turns on, transmitting the low level of the second clock signal SCK2 to the second node N2, causing the potential VN2 of the second node N2 to be low. Simultaneously, the potential control unit 120 turns on, transmitting the low level of the second potential signal VGL to the second node N2. Therefore, under the dual action of the potential control unit 120 and the first node control subunit 131, the second node N2 is at a low level. The second node control subunit 132 turns off in response to the high level of the first clock signal SCK1. The first output unit 210 is turned on in response to the low potential of the first node N1 and outputs a high potential of the third clock signal SCK3. Furthermore, the second output unit 220 is turned on in response to the low potential of the second node N2 and outputs a high potential of the first potential signal VGH. Therefore, the first scan signal GOUT1 is at a high potential. The third output unit 310 is turned on in response to the low potential of the first node N1 and outputs a high potential of the first clock signal SCK1. Furthermore, the fourth output unit 320 is turned on in response to the low potential of the second node N2 and outputs a high potential of the first potential signal VGH. Therefore, the second scan signal GOUT2 is at a high potential.

[0073] In the second phase T2, the trigger input signal SIN, the first clock signal SCK1, the second clock signal SCK2, and the third clock signal SCK3 are all at high potentials. The trigger input unit 110 and the potential control unit 120 are both turned off. The potential VN1 of the first node N1 maintains the low potential of the previous phase. The first node control subunit 131 is turned on in response to the low potential of the first node N1, and transmits the high potential of the second clock signal SCK2 to the second node N2, causing the potential VN2 of the second node N2 to jump to a high potential. The second node control subunit 132 is turned off in response to the high potential of the first clock signal SCK1. The first output unit 210 is turned on in response to the low potential of the first node N1, outputting the high potential of the third clock signal SCK3. The second output unit 220 is turned off in response to the high potential of the second node N2, and thus the first scan signal GOUT1 maintains a high potential. The third output unit 310 is turned on in response to the low potential of the first node N1 and outputs the high potential of the first clock signal SCK1. The fourth output unit 320 is turned off in response to the high potential of the second node N2. Therefore, the second scan signal GOUT2 maintains a high potential.

[0074] In the third phase T3, the trigger input signal SIN and the second clock signal SCK2 are both high, and the third phase T3 includes low-level pulses of the first clock signal SCK1 and the third clock signal SCK3. The trigger input unit 110 and the potential control unit 120 are both off. The potential VN1 of the first node N1 remains low, as in the previous phase. The first node control subunit 131 turns on in response to the low potential of the first node N1, transmitting the high potential of the second clock signal SCK2 to the second node N2, maintaining the high potential of the second node N2. The second node control subunit 132 turns off in response to the high potential of the first clock signal SCK1 and the high potential of the second node N2. The first output unit 210 turns on in response to the low potential of the first node N1, outputting the same potential as the third clock signal SCK3. The second output unit 220 turns off in response to the high potential of the second node N2. Therefore, the first scan signal GOUT1 includes a low-level pulse with the same pulse width as the third clock signal SCK3. The third output unit 310 is turned on in response to the low potential of the first node N1 and outputs the same potential as the first clock signal SCK1. The fourth output unit 320 is turned off in response to the high potential of the second node N2. Therefore, the second scan signal GOUT2 includes a low potential pulse with the same pulse width as the first clock signal SCK1.

[0075] In the fourth stage T4, the trigger input signal SIN, the first clock signal SCK1, the second clock signal SCK2, and the third clock signal SCK3 are all at high levels. The operating states of the drive control module 10, the first output module 20, and the second output module 30 are the same as those in the second stage T2 and are not further described. Therefore, the first node N1 maintains a low potential, the second node N2 maintains a high potential, and the first scan signal GOUT1 and the second scan signal GOUT2 are both at high potentials.

[0076] In the fifth stage T5, the second clock signal SCK2 is at a low level, and the trigger input signal SIN, the first clock signal SCK1, and the third clock signal SCK3 are all at high levels. The trigger input unit 110 turns on, transmitting the high level of the trigger input signal SIN to the first node N1, causing the first node N1 to transition to a high level. The first node control subunit 131 turns off in response to the high level of the first node N1. The potential control unit 120 turns on, transmitting the low level of the second potential signal VGL to the second node N2, causing the second node N2 to transition to a low level. The second node control subunit 132 turns off in response to the high level of the first clock signal SCK1. The first output unit 210 turns off in response to the high level of the first node N1, and the second output unit 220 turns on in response to the low level of the second node N2, outputting a high level of the first potential signal VGH. Therefore, the first scan signal GOUT1 is at a high level. The third output unit 310 turns off in response to the high level of the first node N1, and the fourth output unit 320 turns on in response to the low level of the second node N2, outputting a high level of the first potential signal VGH. Therefore, the second scan signal GOUT2 is at a high level.

[0077] In the sixth phase T6, the trigger input signal SIN, the first clock signal SCK1, the second clock signal SCK2, and the third clock signal SCK3 are all high. The trigger input unit 110 and the potential control unit 120 are both off. The first node N1 maintains the high potential of the previous phase, and the second node N2 maintains the low potential of the previous phase. The first node control subunit 131 turns off in response to the high potential of the first node N1, and the second node control subunit 132 turns off in response to the high potential of the first clock signal SCK1. The first output unit 210 turns off in response to the high potential of the first node N1, and the second output unit 220 turns on in response to the low potential of the second node N2, outputting the high potential of the first potential signal VGH. Therefore, the first scan signal GOUT1 remains high. The third output unit 310 turns off in response to the high potential of the first node N1, and the fourth output unit 320 turns on in response to the low potential of the second node N2, outputting the high potential of the first potential signal VGH. Therefore, the second scan signal GOUT2 remains high.

[0078] In the seventh stage T7, the trigger input signal SIN and the second clock signal SCK2 are both at a high level, and the third stage T3 includes low-level pulses of the first clock signal SCK1 and the third clock signal SCK3. The trigger input unit 110 and the potential control unit 120 are both turned off. The second node N2 maintains the low level of the previous stage. The second node control subunit 132 is turned on in response to the low level of the first clock signal SCK1 and the low level of the second node N2, transmitting the high level of the first potential signal VGH to the first node N1, so that the first node N1 maintains a high level. The first node control subunit 131 is turned off in response to the high level of the first node N1. The first output unit 210 is turned off in response to the high level of the first node N1, and the second output unit 220 is turned on in response to the low level of the second node N2, outputting the high level of the first potential signal VGH. Therefore, the first scan signal GOUT1 maintains a high level. The third output unit 310 is turned off in response to the high potential of the first node N1, and the fourth output unit 320 is turned on in response to the low potential of the second node N2, outputting the high potential of the first potential signal VGH. Therefore, the second scan signal GOUT2 maintains a high potential.

[0079] In the eighth stage T8, the trigger input signal SIN, the first clock signal SCK1, the second clock signal SCK2, and the third clock signal SCK3 are all at high levels. The operating states of the drive control module 10, the first output module 20, and the second output module 30 are the same as those in the sixth stage T6 and are not further described. Therefore, the first node N1 maintains a high level, the second node N2 maintains a low level, and the first scan signal GOUT1 and the second scan signal GOUT2 are both at high levels.

[0080] The subsequent stages repeat the fifth stage T5 to the eighth stage T8 until the trigger input signal SIN changes to a low level again.

[0081] Figure 3 The example in FIG2 shows that the pulse of the trigger input signal SIN completely overlaps with the pulse of the second clock signal SCK2 in the first phase T1, but this is not intended to limit the present invention. In other embodiments, the pulse width of the trigger input signal SIN may be increased. Figure 4 As shown, the pulse of the trigger input signal SIN can start at the beginning of the first stage T1 and continue until the end of the fourth stage T4. Combined with the analysis of the above driving process, it can be seen that in the second stage T2 to the fourth stage T4, since the second clock signal SCK2 is at a high level, the trigger input unit 110 is controlled to be turned off and the trigger input signal SIN cannot be transmitted backward. Therefore, the level of the trigger input signal SIN in the second stage T2 to the fourth stage T4 can be set arbitrarily, and the input signal SIN can jump to a high level at any time in the second stage T2 to the fourth stage T4.

[0082] The above embodiments exemplarily illustrate the working process of each functional unit in the scanning circuit. The specific structure that each functional unit may have is described below, but it is not intended to limit the present invention.

[0083] Figure 5 FIG. 1 is a schematic diagram of another scanning circuit provided by an embodiment of the present invention. Figure 5 In one embodiment, the trigger input unit 110 optionally includes a fifth transistor M5, wherein a gate of the fifth transistor M5 is connected to the second clock signal SCK2, a first electrode of the fifth transistor M5 is connected to the trigger input signal SIN, and a second electrode of the fifth transistor M5 is connected to the first node N1. In this embodiment, the trigger input unit 110 includes a single transistor, simplifying the structure of the trigger input unit 110.

[0084] Continue to see Figure 5 In one embodiment, the potential control unit 120 optionally includes a sixth transistor M6. A gate of the sixth transistor M6 is connected to the second clock signal SCK2, a first electrode of the sixth transistor M6 is connected to the second potential signal VGL, and a second electrode of the sixth transistor M6 is connected to the second node N2. In this embodiment, the potential control unit 120 includes a single transistor, simplifying the structure of the potential control unit 120.

[0085] Continue to see Figure 5 In one embodiment, the first node control subunit 131 optionally includes a seventh transistor M7; a gate of the seventh transistor M7 is connected to the first node N1, a first electrode of the seventh transistor M7 is connected to the second clock signal SCK2, and a second electrode of the seventh transistor M7 is connected to the second node N2. In this embodiment, the first node control subunit 131 includes a single transistor, simplifying the structure of the first node control subunit 131.

[0086] Continue to see Figure 5 In one embodiment, optionally, the second node control subunit 132 includes: an eighth transistor M8 and a ninth transistor M9; the gate of the eighth transistor M8 is connected to the second node N2, the first electrode of the eighth transistor M8 is connected to the first potential signal VGH, the second electrode of the eighth transistor M8 is connected to the first electrode of the ninth transistor M9, the gate of the ninth transistor M9 is connected to the first clock signal SCK1, and the second electrode of the ninth transistor M9 is connected to the first node N1.

[0087] Furthermore, in order to reduce leakage through the node mutual control unit 130 and ensure the stability of the potentials of the first node N1 and the second node N2, at least one of the seventh transistor M7, the eighth transistor M8 and the ninth transistor M9 may be set as a dual-gate transistor.

[0088] Continue to see Figure 5 In one embodiment, the first output unit 210 optionally includes a first transistor M1; a gate of the first transistor M1 is connected to the first node N1, a first electrode of the first transistor M1 is connected to the third clock signal SCK3, and a second electrode of the first transistor M1 is connected to the output terminal of the first output module 20, i.e., the first scan output terminal 81. In this embodiment, the first output unit 210 includes a single transistor, which simplifies the structure of the first output unit 210.

[0089] The second output unit 220 includes a second transistor M2 and a first capacitor C1. The gate of the second transistor M2 is connected to the second node N2 and the first end of the first capacitor C1, respectively. The first electrode of the second transistor M2 and the second end of the first capacitor C1 are both connected to the first potential signal VGH. The second electrode of the second transistor M2 is connected to the output end of the first output module 20. The first capacitor C1 is used to maintain the potential of the second node N2.

[0090] The third output unit 310 includes a third transistor M3 and a third capacitor C3. The gate of the third transistor M3 is connected to the first node N1, the first electrode of the third transistor M3 is connected to the first clock signal SCK1, and the second electrode of the third transistor M3 is connected to the output terminal of the second output module 30, namely, the second scan output terminal 82. The third capacitor C3 is connected between the gate of the third transistor M3 and the output terminal of the second output module 30. The third capacitor C3, based on its coupling effect, can couple the potential jump at the falling edge of the second scan signal GOUT2 to the first terminal of the third capacitor, thereby further reducing the gate potential of the third transistor M3 and the gate potential of the first transistor M1, thereby making the first transistor M1 and the third transistor M3 more fully conductive, thereby fully outputting the conduction pulse of the corresponding clock signal.

[0091] The fourth output unit 320 includes: a fourth transistor M4; a gate of the fourth transistor M4 is connected to the second node N2, a first electrode of the fourth transistor M4 is connected to the first potential signal VGH, and a second electrode of the fourth transistor M4 is connected to the output end of the second output module 30.

[0092] It can be understood that the gate of the fourth transistor M4 and the gate of the second transistor M2 are actually connected to the same node (i.e., the second node N2). Therefore, the first end of the first capacitor C1 is actually also connected to the gate of the fourth transistor M4. The first capacitor C1 can actually simultaneously maintain the potential of the gates of the second transistor M2 and the fourth transistor M4 by storing and maintaining the potential of the second node N2. Therefore, there is no need to set capacitors separately for the second transistor M2 and the fourth transistor M4. Here, the first capacitor C1 is exemplarily included in the second output unit 220, but this is not intended to limit the present invention. In other embodiments, the first capacitor C1 can also be included in the fourth output unit 320.

[0093] Figure 6 FIG. 1 is a schematic diagram of another scanning circuit provided by an embodiment of the present invention. Figure 6 Based on the above embodiments, the first output unit 210 may optionally further include a second capacitor C2 connected between the gate of the first transistor M1 and the output terminal of the first output module 20. Similar to the function of the third capacitor C3, the second capacitor C2 can reduce the gate potentials of the first transistor M1 and the third transistor M3 through coupling at the falling edge of the first scanning signal GOUT1, thereby cooperating with the coupling function of the third capacitor C3 to ensure that the first transistor M1 and the third transistor M3 are fully turned on and fully output the conduction pulse of the corresponding clock signal.

[0094] The above embodiments exemplarily provide a specific structure of the potential control unit 120 and the connection method with each signal, but are not intended to limit the present invention. Figure 6 As shown, optionally, the gate and first electrode of the sixth transistor can both be connected to the second clock signal SCK2, so that the second transistor T2 forms a diode connection. This can also achieve the function of controlling the second node N2 to a low potential when the second clock signal SCK2 is at a low potential. This configuration can reduce the number of signals required by the scanning circuit 100, eliminate the need for a second potential signal terminal 62, and thus simplify the structure and wiring of the scanning circuit.

[0095] Continue to see Figure 6Based on the above embodiments, the scanning circuit 100 may optionally further include a protection module 40; a control terminal of the protection module 40 is connected to the second potential signal VGL, a first terminal of the protection module 40 is connected to the first node N1, and a second terminal of the protection module 40 is connected to the first output module 20 and the second output module 30, specifically, to the gate of the first transistor M1 and the gate of the third transistor M3. In this embodiment, the gate of the first transistor M1 and the gate of the third transistor M3 are indirectly connected to the first node N1 via the protection module 40. The presence of the protection module 40 prevents the extremely low potentials reached by the first transistor M1 and the third transistor M3 due to capacitive coupling from being transmitted to the first node N1, thereby reducing the risk of damage to the transistors connected to the first node N1 due to high voltage stress.

[0096] Specifically, the protection module 40 includes a tenth transistor M10; the gate of the tenth transistor M10 serves as a control terminal of the protection module 40, the first electrode of the tenth transistor M10 serves as a first terminal of the protection module 40, and the second electrode of the tenth transistor M10 serves as a second terminal of the protection module 40. The protection principle of the tenth transistor M10 is as follows: the turn-on condition of the tenth transistor M10 is that the gate-source voltage difference (the voltage difference between the gate and the first electrode) is less than its threshold voltage. When the gate of the first transistor M1 is coupled to an extremely low potential, if this potential is transmitted toward the first node N1 through the tenth transistor M10, the gate-source voltage difference of the tenth transistor M10 will be greater than its threshold voltage, and the turn-on condition of the tenth transistor M10 will not be met, causing the tenth transistor M10 to be turned off, thereby preventing the extremely low potential from being transmitted to the first node N1.

[0097] In summary, the scanning circuit provided in an embodiment of the present invention can simultaneously output two scanning signals with different pulse widths by adding a set of output modules and corresponding clock signals, thereby enabling the data write transistor and the threshold compensation transistor in the pixel circuit to be connected to different scanning signals. For example, the data write transistor in the same pixel circuit is connected to the first scanning signal GOUT1, and the threshold compensation transistor is connected to the second scanning signal GOUT2 output by the same scanning circuit 100, so that the conduction time of the threshold compensation transistor is longer than the conduction time of the data write transistor. On the basis of ensuring that data writing is completed, the threshold voltage compensation time of the driving transistor is increased, and the threshold voltage compensation effect of the driving transistor in each pixel circuit is improved, thereby improving the display uniformity of the display panel and enhancing the display effect.

[0098] It should be noted that, in each transistor involved in the above embodiments, the first electrode can be called the source or the drain, and correspondingly, the second electrode can be called the drain or the source. Since the structure of the transistor in the display panel is symmetrical, the source and drain of each transistor are not distinguished.

[0099] It should also be noted that in the above embodiments, all transistors in the scanning circuit are shown as P-type transistors by way of example, and this is not intended to limit the present invention. In other embodiments, some or all of the transistors may be replaced with N-type transistors as needed, and the high and low potentials of the control signals connected to the transistor gates may be adjusted accordingly.

[0100] An embodiment of the present invention further provides a display panel comprising a plurality of cascade-connected scanning circuits such as those provided by any embodiment of the present invention, which has corresponding beneficial effects. Figure 7 Schematic diagram of the structure of a display panel provided by an embodiment of the present invention. Figure 7 For example, the display panel may include a display driver circuit disposed in a non-display area and pixel circuits arranged in an array in the display area (not shown). The scan driver circuit includes a plurality of scan circuits connected in cascade, and each scan circuit may be connected to a corresponding pixel circuit via a first scan line LS1 and a second scan line LS2.

[0101] The cascade connection of the scanning circuits at each stage means that the second scan output terminal of the scanning circuit at one stage is electrically connected to the trigger input terminal of the scanning circuit at the next stage. For example, the second scan output terminal 82 of the first-stage scanning circuit 1001 is connected to the trigger input terminal 71 of the second-stage scanning circuit 1002, the second scan output terminal 82 of the second-stage scanning circuit 1002 is connected to the trigger input terminal 71 of the third-stage scanning circuit 1003, and so on.

[0102] In this scan drive circuit, the second scan signal GOUT2 output by the scan circuit is equivalent to a shifted output of the trigger input signal connected to the scan circuit at that level. The cascade connection in this embodiment is equivalent to using the second scan signal GOUT2 output by the scan circuit at one level as the trigger input signal for the scan circuit at the next level. Therefore, the second scan signal GOUT2 output by the scan circuit at the next level is equivalent to a shifted output of the second scan signal GOUT2 output by the scan circuit at the current level. This enables a step-by-step shifted output of the second scan signal GOUT2. Since the pulses of the first scan signal GOUT1 at each level actually correspond one-to-one with the pulses of the second scan signal GOUT2 at each level, this cascade connection structure also enables a step-by-step shifted output of the first scan signal GOUT1.

[0103] Continue to see Figure 7 Based on the above embodiments, optionally, the display panel further includes: an input signal line LIN, a first clock signal line LCK1, a second clock signal line LCK2, a third clock signal line LCK3 and a fourth clock signal line LCK4.

[0104] The input signal line LIN is connected to the driving control module in the first-level scanning circuit 1001, and specifically can be connected to the trigger input terminal 71 in the first-level scanning circuit 1001, so that the signal IN transmitted in the input signal line LIN serves as the trigger input signal of the first-level scanning circuit 1001.

[0105] The first clock signal line LCK1 is connected to the drive control module and the second output module in the odd-stage scanning circuit, as well as the drive control module in the even-stage scanning circuit. Specifically, the first clock signal line LCK1 can be connected to the first clock terminal 51 in the odd-stage scanning circuit and the second clock terminal 52 in the even-stage scanning circuit, so that the signal CK1 transmitted by the first clock signal line LCK1 serves as the first clock signal required by the odd-stage scanning circuit and the second clock signal required by the even-stage scanning circuit, respectively.

[0106] The second clock signal line LCK2 is connected to the drive control module in the odd-stage scanning circuit, and the drive control module and the second output module in the even-stage scanning circuit. Specifically, the second clock signal line LCK2 can be connected to the second clock terminal 52 in the odd-stage scanning circuit and the first clock terminal 51 in the even-stage scanning circuit, so that the signal CK2 transmitted by the second clock signal line LCK2 serves as the second clock signal required by the odd-stage scanning circuit and the first clock signal required by the even-stage scanning circuit, respectively.

[0107] The third clock signal line LCK3 is connected to the first output module in the odd-numbered scanning circuit, specifically to the third clock terminal 53 in the odd-numbered scanning circuit, so that the signal CK3 transmitted by the third clock signal line LCK3 serves as the third clock signal required by the odd-numbered scanning circuit.

[0108] The fourth clock signal line LCK4 is connected to the first output module in the even-numbered scanning circuit; specifically, it can be connected to the third clock terminal 53 in the even-numbered scanning circuit, so that the signal CK4 transmitted by the fourth clock signal line LCK4 serves as the third clock signal required by the even-numbered scanning circuit.

[0109] Among them, the waveform of the signal CK1 transmitted by the first clock signal line LCK1 and the waveform of the signal CK2 transmitted by the second clock signal line LCK2 are the same and the pulses do not overlap; and the waveform of the signal CK3 transmitted by the third clock signal line LCK3 and the waveform of the signal CK4 transmitted by the fourth clock signal line LCK4 are the same and the pulses do not overlap.

[0110] Furthermore, the display panel may also include: a first potential signal line, used to transmit a first potential signal, which can be connected to the first potential signal end of each level of scanning circuit; a second potential signal line, used to transmit a second potential signal, which can be connected to the second potential signal end of each level of scanning circuit.

[0111] like Figure 7 The output waveform of the cascade-connected multi-stage scanning circuit shown can be seen in Figure 8 , Figure 8 The waveforms of the first four-stage first scanning signals GOUT1_1 to GOUT1_4 and the waveforms of the first four-stage second scanning signals GOUT2_1 to GOUT2_4 are given as examples. Figure 8 It can be seen that under this cascade structure, the step-by-step shift output of the first scanning signal and the step-by-step shift output of the second scanning signal can be reliably achieved.

[0112] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0113] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A scanning circuit, characterized in that: include: a driving control module, wherein a first output terminal and a second output terminal of the driving control module are connected to a first node and a second node respectively; The driving control module is used to control the potential of the first node and the second node according to the trigger input signal, the first clock signal, the second clock signal and the first potential signal; a first output module, connected to the first node and the second node, respectively, configured to output the third clock signal as the first scanning signal in response to the potential of the first node, or output the first potential signal as the first scanning signal in response to the potential of the second node; a second output module, connected to the first node and the second node, respectively, and configured to output the first clock signal as a second scanning signal in response to the potential of the first node, or output the first potential signal as the second scanning signal in response to the potential of the second node; The first clock signal and the second clock signal have the same waveform and their pulses do not overlap; the pulse width of the first clock signal is greater than the pulse width of the third clock signal, and the pulse time of the third clock signal is within the pulse time of the first clock signal; The drive control module includes: a trigger input unit connected to the first node, and configured to control the potential of the first node according to the trigger input signal and the second clock signal; a potential control unit, connected to the second node, and configured to control the potential of the second node according to the second clock signal; A node inter-control unit is respectively connected to the first node and the second node, and is used to transmit the second clock signal to the second node in response to the potential of the first node, or to transmit the first potential signal to the first node in response to the first clock signal and the potential of the second node.

2. The scanning circuit according to claim 1, wherein: The first output module includes: a first output unit connected to the first node, configured to respond to the potential of the first node and output the third clock signal as the first scanning signal; The second output unit is connected to the second node and is configured to respond to the potential of the second node and output the first potential signal as the first scanning signal.

3. The scanning circuit according to claim 2, wherein: The first output unit includes: a first transistor; a gate of the first transistor is connected to the first node, a first electrode of the first transistor is connected to the third clock signal, and a second electrode of the first transistor is connected to the output end of the first output module; The second output unit includes: a second transistor and a first capacitor; the gate of the second transistor is respectively connected to the second node and the first end of the first capacitor, the first electrode of the second transistor and the second end of the first capacitor are both connected to the first potential signal, and the second electrode of the second transistor is connected to the output end of the first output module.

4. The scanning circuit according to claim 3, wherein: The first output unit further includes: a second capacitor connected between the gate of the first transistor and the output end of the first output module.

5. The scanning circuit according to claim 1, wherein: The second output module includes: a third output unit connected to the first node, configured to respond to the potential of the first node and output the first clock signal as the second scanning signal; The fourth output unit is connected to the second node, and is configured to respond to the potential of the second node and output the first potential signal as the second scanning signal.

6. The scanning circuit according to claim 5, wherein: The third output unit includes: a third transistor and a third capacitor; the gate of the third transistor is connected to the first node, the first electrode of the third transistor is connected to the first clock signal, and the second electrode of the third transistor is connected to the output end of the second output module; the third capacitor is connected between the gate of the third transistor and the output end of the second output module; The fourth output unit includes: a fourth transistor; the gate of the fourth transistor is connected to the second node, the first electrode of the fourth transistor is connected to the first potential signal, and the second electrode of the fourth transistor is connected to the output end of the second output module.

7. The scanning circuit according to claim 1, wherein: The trigger input unit includes: a fifth transistor, a gate of the fifth transistor is connected to the second clock signal, a first electrode of the fifth transistor is connected to the trigger input signal, and a second electrode of the fifth transistor is connected to the first node.

8. The scanning circuit according to claim 1, wherein: The potential control unit includes: a sixth transistor; The gate of the sixth transistor is connected to the second clock signal, the first electrode of the sixth transistor is connected to the second potential signal, and the second electrode of the sixth transistor is connected to the second node; Alternatively, the gate electrode and the first electrode of the sixth transistor are both connected to the second clock signal, and the second electrode of the sixth transistor is connected to the second node.

9. The scanning circuit according to claim 1, wherein: The node mutual control unit includes: a first node control subunit, configured to transmit the second clock signal to the second node in response to the potential of the first node; The second node control subunit is configured to transmit the first potential signal to the first node in response to the first clock signal and the potential of the second node.

10. The scanning circuit according to claim 9, wherein: The first node control subunit includes: a seventh transistor; a gate of the seventh transistor is connected to the first node, a first electrode of the seventh transistor is connected to the second clock signal, and a second electrode of the seventh transistor is connected to the second node; The second node control subunit includes: an eighth transistor and a ninth transistor; the gate of the eighth transistor is connected to the second node, the first electrode of the eighth transistor is connected to the first potential signal, the second electrode of the eighth transistor is connected to the first electrode of the ninth transistor, the gate of the ninth transistor is connected to the first clock signal, and the second electrode of the ninth transistor is connected to the first node.

11. The scanning circuit according to claim 10, wherein: At least one of the seventh transistor, the eighth transistor, and the ninth transistor is a dual-gate transistor.

12. The scanning circuit according to claim 1, wherein: Also includes: Protection module; The control end of the protection module is connected to the second potential signal, the first end of the protection module is connected to the first node, and the second end of the protection module is connected to the first output module and the second output module.

13. The scanning circuit according to claim 12, wherein: The protection module includes: a tenth transistor; the gate of the tenth transistor serves as the control terminal of the protection module, the first electrode of the tenth transistor serves as the first terminal of the protection module, and the second electrode of the tenth transistor serves as the second terminal of the protection module.

14. A display panel, characterized in that: include: A cascade-connected multi-stage scanning circuit as described in any one of claims 1 to 13; wherein the second scanning signal output by the scanning circuit of this stage serves as a trigger input signal for the scanning circuit of the next stage.

15. The display panel according to claim 14, wherein: Also included: an input signal line, a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line; The input signal line is connected to the drive control module in the first-stage scanning circuit; the signal transmitted in the input signal line serves as a trigger input signal for the first-stage scanning circuit; The first clock signal line is respectively connected to the drive control module and the second output module in the odd-numbered scanning circuit, and the drive control module in the even-numbered scanning circuit; the signal transmitted by the first clock signal line is respectively used as the first clock signal of the odd-numbered scanning circuit and the second clock signal of the even-numbered scanning circuit; The second clock signal line is connected to the drive control module in the odd-numbered scanning circuit and the drive control module and the second output module in the even-numbered scanning circuit respectively; the signal transmitted by the second clock signal line serves as the second clock signal of the odd-numbered scanning circuit and the first clock signal of the even-numbered scanning circuit respectively. The third clock signal line is connected to the first output module in the odd-numbered scanning circuit; the signal transmitted by the third clock signal line serves as the third clock signal of the odd-numbered scanning circuit; The fourth clock signal line is connected to the first output module in the even-level scanning circuit; the signal transmitted by the fourth clock signal line serves as the third clock signal of the even-level scanning circuit; wherein the waveform of the signal transmitted by the third clock signal line is the same as that of the signal transmitted by the fourth clock signal line and the pulses do not overlap.

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