Key scanning circuit and device and keyboard
By combining a key module, a signal selection output module, and a signal acquisition and processing module, the high cost of existing key scanning circuits is solved, the key detection frequency can be flexibly adjusted, and the detection efficiency of some keys is improved. This technology is applied in the field of electronic circuit design, specifically in the field of electronic circuit technology, especially in keyboard key scanning circuits.
Patent Information
- Application Number
- CN202520149970.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-22
- Publication Date
- 2026-01-06
- Estimated Expiration
- 2035-01-22
AI Technical Summary
Existing key scanning circuits are too expensive to meet the high response requirements of some keys, and the scanning rate cannot be flexibly adjusted.
The design employs a combination of a button module, a signal selection output module, and a signal acquisition and processing module. By outputting multiple scanning signals within one cycle, it achieves a response to all button press operations and re-detects some button signals, increasing the detection frequency without changing the overall scanning frequency.
Without increasing the overall scanning frequency, the detection frequency of some buttons was increased, thus reducing the implementation cost.
Smart Images
Figure CN223772039U_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of electronic circuit technology, and in particular relates to a key scanning circuit, device and keyboard. Background Technology
[0002] Currently, most keyboard key scanning circuits use matrix scanning. The basic principle is to connect rows and columns to a microcontroller via resistors or transistors. Key collision resolution can be achieved through the unidirectional conduction characteristic of diodes, or by using a multi-channel analog multiplexer / demultiplexer (hereinafter referred to as multiplexer) in conjunction with an AD (analog-to-digital converter) function. Ultimately, the MCU is programmed to scan the state of each key to determine whether it has been pressed. However, current key scanning circuit designs are "one-to-one." Whether it's a conventional key matrix scan or a circuit using multiplexers, one channel corresponds to one key, resulting in all keys having the same scanning rate. When a high response time for a specific key is required, the only solution is to increase the scanning rate of all keys, leading to excessively high costs. Utility Model Content
[0003] The purpose of this application is to provide a key scanning circuit that addresses the problem of excessive cost in current key scanning circuits when implementing high-response requirements for some keys.
[0004] A first aspect of this application provides a key scanning circuit, including:
[0005] The button module is used to output N button signals corresponding to N different pressing operations.
[0006] A signal selection output module, electrically connected to the key module, is used to detect the Lth key signal based on the Lth scan signal and the Kth key signal based on the Mth scan signal, and output the Lth detection signal based on the detected Lth key signal or the Kth detection signal based on the detected Kth key signal; and
[0007] The signal acquisition and processing module is electrically connected to the signal selection and output module, and is used to sequentially and cyclically output the Lth scan signal and the Mth scan signal, and to respond to the Lth detection signal and the Kth detection signal;
[0008] Where N is greater than or equal to 2, L is less than or equal to N, M is greater than N, M is less than 2N, K is less than N, and N and K are both positive integers.
[0009] In one embodiment, the signal selection output module includes a first signal selection component and a second signal selection component;
[0010] The first signal selection component is used to detect the first key signal based on the first scan signal and output the first detection signal;
[0011] The second signal selection component is used to detect the Kth key signal based on the Pth scan signal and output the Kth detection signal;
[0012] Where I is less than N, P is greater than the maximum value of I, P is less than or equal to the maximum value of M, and I and P are both positive integers.
[0013] In one embodiment, N equals 12, I is less than or equal to 8, P is greater than 8 and less than or equal to 16, M is less than or equal to 16, and K is greater than or equal to 9 and less than or equal to 12.
[0014] In one embodiment, the first signal selection component includes a first multiplexer chip;
[0015] The first multiplexer chip includes a scan signal input pin, a detection signal output pin, a first detection pin, a second detection pin, a third detection pin, a fourth detection pin, a fifth detection pin, a sixth detection pin, a seventh detection pin, and an eighth detection pin;
[0016] The first multiplexer chip has a scan signal input pin for inputting the first scan signal, a detection signal output pin for outputting the first detection signal, a first detection pin for inputting the first key signal, a second detection pin for inputting the second key signal, a third detection pin for inputting the third key signal, a fourth detection pin for inputting the fourth key signal, a fifth detection pin for inputting the fifth key signal, a sixth detection pin for inputting the sixth key signal, a seventh detection pin for inputting the seventh key signal, and an eighth detection pin for inputting the eighth key signal.
[0017] In one embodiment, the first signal selection component includes a second multiplexer chip;
[0018] The second multiplexer chip includes a scan signal input pin, a detection signal output pin, a ninth detection pin, a tenth detection pin, an eleventh detection pin, a twelfth detection pin, a thirteenth detection pin, a fourteenth detection pin, a fifteenth detection pin, and a sixteenth detection pin;
[0019] The scan signal input pin of the second multiplexer chip is used to input the Pth scan signal; the detection signal output pin of the second multiplexer chip is used to output the Kth detection signal; the ninth detection pin of the second multiplexer chip is used to input the ninth key signal; the tenth detection pin of the second multiplexer chip is used to input the tenth key signal; the eleventh detection pin of the second multiplexer chip is used to input the eleventh key signal; the twelfth detection pin of the second multiplexer chip is used to input the twelfth key signal; the thirteenth detection pin of the second multiplexer chip is used to input the ninth key signal; the fourteenth detection pin of the second multiplexer chip is used to input the tenth key signal; the fifteenth detection pin of the second multiplexer chip is used to input the eleventh key signal; and the sixteenth detection pin of the second multiplexer chip is used to input the twelfth key signal.
[0020] In one embodiment, the signal acquisition and processing module includes a signal acquisition and processing chip;
[0021] The signal acquisition and processing chip includes a first scan signal output pin, a second scan signal output pin, a first detection signal input pin, and a second detection signal input pin;
[0022] The first scan signal output pin of the signal acquisition and processing chip is used to output the I-th scan signal, the second scan signal output pin of the signal acquisition and processing chip is used to output the P-th scan signal, the first detection signal input pin of the signal acquisition and processing chip is used to input the I-th detection signal, and the second detection signal input pin of the signal acquisition and processing chip is used to input the K-th detection signal.
[0023] In one embodiment, the button module includes 12 Hall effect button components;
[0024] The Nth Hall effect button component outputs the Nth button signal after the Nth press operation.
[0025] A second aspect of this application also provides a key scanning device, including the key scanning circuit described in any one of the above claims.
[0026] A third aspect of this application also provides a keyboard, including a key scanning circuit as described in any of the above-mentioned items.
[0027] In one embodiment, the Kth key signal corresponds to the W key, A key, S key, and D key on the keyboard.
[0028] The beneficial effects of this utility model embodiment compared with the prior art are as follows: In this solution, the Lth scan signal output by the signal acquisition and processing module within one cycle can already realize the response to all pressing operations of the button module, and the Mth scan signal is also output to re-detect the Kth button signal in the button module, thereby improving the detection scanning frequency of some buttons in the button module. Furthermore, because the detection scanning frequency of the Kth button signal is increased without changing the overall button detection scanning frequency, the implementation cost is reduced. Attached Figure Description
[0029] Figure 1 A first example schematic diagram of a key scanning circuit provided in an embodiment of this application;
[0030] Figure 2 A second example schematic diagram of the key scanning circuit provided in the embodiments of this application;
[0031] Figure 3 A circuit schematic diagram of the signal selection output module provided in the embodiments of this application;
[0032] Figure 4 The circuit schematic diagram of the signal acquisition and processing module provided in the embodiments of this application;
[0033] Figure 5 The circuit diagram of the Hall button assembly provided in the embodiments of this application is shown. Detailed Implementation
[0034] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.
[0035] Figure 1 A first example schematic diagram of a key scanning circuit provided in an embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below:
[0036] A key scanning circuit includes a key module 110, a signal selection and output module 120, and a signal acquisition and processing module 130. Specifically:
[0037] The button module 110 is used to output N button signals corresponding to N different pressing operations. When the button module 110 is pressed, it outputs the corresponding button signal according to the pressing operation. In one embodiment, the button module 110 includes multiple buttons, and pressing each button can be understood as performing one type of pressing operation on the button module 110.
[0038] The signal selection output module 120 is electrically connected to the key module 110 and is used to detect the Lth key signal according to the Lth scan signal and the Kth key signal according to the Mth scan signal, and output the Lth detection signal according to the detected Lth key signal or the Kth detection signal according to the detected Kth key signal.
[0039] The signal acquisition and processing module 130 is electrically connected to the signal selection and output module 120, and is used to sequentially and cyclically output the Lth scan signal and the Mth scan signal, and to respond to the Lth detection signal and the Kth detection signal.
[0040] The signal acquisition and processing module 130 outputs the Lth scan signal and the Mth scan signal in a sequential loop. This can be understood as outputting the Lth scan signal in sequence, and then outputting the Mth scan signal in sequence after the Lth scan signal is output, and then repeating the above operation. For example, the signal acquisition and processing module 130 starts outputting the first scan signal, then outputs the second scan signal until it outputs the scan signal when the M value reaches its maximum value, and then repeats the above operation.
[0041] Where N is greater than or equal to 2, L is less than or equal to N, M is greater than N, M is less than 2N, K is less than N, and N and K are both positive integers.
[0042] In this embodiment, the signal acquisition and processing module 130 sequentially outputs the Lth scan signal and the Mth scan signal to the signal selection and output module 120, thereby controlling the signal selection and output module 120 to detect whether the button module 110 is outputting the Lth button signal based on the input Lth scan signal, or controlling the signal selection and output module 120 to detect whether the button module 110 is outputting the Kth button signal based on the Mth scan signal. This enables the signal selection and output module 120 to detect all N types of button signals output by the button module 110, and to respond to the Lth and Kth detection signals output by the signal selection and output module 120, thereby determining which buttons of the button module 110 have been pressed at this time. In addition, within one cycle, the Lth scan signal output by the signal acquisition and processing module 130 can already respond to all pressing operations of the button module 110, and also outputs the Mth scan signal to re-detect the Kth button signal in the button module 110, thereby increasing the detection scanning frequency of some buttons in the button module 110. Furthermore, because the detection scanning frequency of the Kth button signal is increased without changing the overall button detection scanning frequency, the implementation cost is reduced.
[0043] like Figure 2 As shown, in one embodiment, the signal selection output module 120 includes a first signal selection component 121 and a second signal selection component 122;
[0044] The first signal selection component 121 is used to detect the first key signal according to the first scan signal and output the first detection signal;
[0045] The second signal selection component 122 is used to detect the Kth key signal according to the Pth scan signal and output the Kth detection signal;
[0046] Where I is less than N, P is greater than the maximum value of I, P is less than or equal to the maximum value of M, and I and P are both positive integers.
[0047] In one embodiment, N equals 12, I is less than or equal to 8, P is greater than 8 and less than or equal to 16, M is less than or equal to 16, and K is greater than or equal to 9 and less than or equal to 12.
[0048] In this embodiment, the I-th scan signal and the I-th key signal have a one-to-one correspondence, meaning that the first signal selection component 121 will only scan the corresponding I-th key signal based on the I-th scan signal. The P-th scan signal and the K-th key signal have a two-to-one relationship, meaning that the second signal selection component 122 will scan the same K-th key signal based on two different P-th scan signals. For example, the second signal selection component 122 may scan and detect the ninth key signal based on the ninth scan signal, and also detect the ninth key signal based on the thirteenth scan signal.
[0049] Please see Figure 3 In one embodiment, the first signal selection component 121 includes a first multiplexer chip MUX1;
[0050] The first multiplexer chip MUX1 includes scan signal input pins A0 / A1 / A2, detection signal output pin Z, first detection pin Y3, second detection pin Y0, third detection pin Y1, fourth detection pin Y2, fifth detection pin Y4, sixth detection pin Y6, seventh detection pin Y7 and eighth detection pin Y8;
[0051] The scan signal input pins A0 / A1 / A2 of the first multiplexer chip MUX1 are used to input the first scan signal; the detection signal output pin Z of the first multiplexer chip MUX1 is used to output the first detection signal; the first detection pin Y3 of the first multiplexer chip MUX1 is used to input the first key signal; the second detection pin Y0 of the first multiplexer chip MUX1 is used to input the second key signal; the third detection pin Y1 of the first multiplexer chip MUX1 is used to input the third key signal; the fourth detection pin Y2 of the first multiplexer chip MUX1 is used to input the fourth key signal; the fifth detection pin Y4 of the first multiplexer chip MUX1 is used to input the fifth key signal; the sixth detection pin Y6 of the first multiplexer chip MUX1 is used to input the sixth key signal; the seventh detection pin Y7 of the first multiplexer chip MUX1 is used to input the seventh key signal; and the eighth detection pin Y5 of the first multiplexer chip MUX1 is used to input the eighth key signal.
[0052] In one embodiment, the first signal selection component 121 includes a second multiplexer chip MUX2;
[0053] The second multiplexer chip MUX2 includes scan signal input pins A0 / A1 / A2, detection signal output pin Z, ninth detection pin Y3, tenth detection pin Y0, eleventh detection pin Y1, twelfth detection pin Y2, thirteenth detection pin Y4, fourteenth detection pin Y6, fifteenth detection pin Y7 and sixteenth detection pin Y8;
[0054] The scan signal input pins A0 / A1 / A2 of the second multiplexer chip MUX2 are used to input the Pth scan signal; the detection signal output pin Z of the second multiplexer chip MUX2 is used to output the Kth detection signal; the ninth detection pin Y3 of the second multiplexer chip MUX2 is used to input the ninth key signal; the tenth detection pin Y0 of the second multiplexer chip MUX2 is used to input the tenth key signal; the eleventh detection pin Y1 of the second multiplexer chip MUX2 is used to input the eleventh key signal; the twelfth detection pin Y2 of the second multiplexer chip MUX2 is used to input the twelfth key signal; the thirteenth detection pin Y4 of the second multiplexer chip MUX2 is used to input the ninth key signal; the fourteenth detection pin Y6 of the second multiplexer chip MUX2 is used to input the tenth key signal; the fifteenth detection pin Y7 of the second multiplexer chip MUX2 is used to input the eleventh key signal; and the sixteenth detection pin Y5 of the second multiplexer chip MUX2 is used to input the twelfth key signal.
[0055] Please see Figure 4 In one embodiment, the signal acquisition and processing module 130 includes a signal acquisition and processing chip U3;
[0056] The signal acquisition and processing chip U3 includes a first scan signal output pin PC0 / PC1 / PC2, a second scan signal output pin PC0 / PC1 / PC2, a first detection signal input pin PC3, and a second detection signal input pin PA0. The first scan signal and the second scan signal share pins PC0 / PC1 / PC2 of the signal acquisition and processing chip U3.
[0057] The first scan signal output pins PC0 / PC1 / PC2 of the signal acquisition and processing chip U3 are used to output the I-th scan signal, the second scan signal output pins PC0 / PC1 / PC2 of the signal acquisition and processing chip U3 are used to output the P-th scan signal, the first detection signal input pin PC3 of the signal acquisition and processing chip U3 is used to input the I-th detection signal, and the second detection signal input pin of the signal acquisition and processing chip U3 is used to input the K-th detection signal.
[0058] The first multiplexer chip MUX1 and the second multiplexer chip MUX2 can be selected as an 8-to-1 multiplexer. This multiplexer has three built-in address selection terminals (A0~A2), an enable input terminal (E#), eight independent input / output terminals (Y0~Y7), and a common input / output terminal (Z). In the circuit, grounding E# makes the input terminal of the multiplexer valid. The signal acquisition and processing chip U3 controls the address selection terminal of the multiplexer during the scan cycle. If the first scan signal output by the signal acquisition and processing chip U3 contains the information A0=L, A1=L, A2=0, then the Y0 of the multiplexer is mapped to Z for output. By connecting the ADC pin of the signal acquisition and processing chip U3 to the Z pin of the multiplexer, the scanning of 8 channels can be realized by controlling the address selection terminal.
[0059] Please see Figure 5 , Figure 5 A schematic diagram of one Hall effect button assembly is shown. In one embodiment, the button module 110 includes 12 Hall effect button assemblies, and the Nth Hall effect button assembly outputs the Nth button signal after the Nth press operation. The Hall element in the Hall effect button assembly is connected to VCC and GND to provide the necessary operating conditions, and the OUT pin of the Hall element is connected to a pin (Y0~Y7) of an 8-to-1 multiplexer. When working (pressed), the permanent magnet (moving up and down, i.e., the shaft is pressed and lifted) will cause the Hall element to output a voltage within a certain range, which corresponds to the button signal.
[0060] In other embodiments, the button module 110 may also be composed of a mechanical button assembly or a photoelectric button assembly.
[0061] This application embodiment also provides a key scanning device, including the key scanning circuit as described in any of the above items. Because the key scanning device of this embodiment includes the key scanning circuit as described in any of the above items, the key scanning device of this embodiment includes the beneficial effects corresponding to the key scanning circuit as described in any of the above items.
[0062] This application embodiment also provides a keyboard, including a key scanning circuit as described in any of the above claims. The key scanning circuit is used to detect keyboard keys. Because the keyboard in this embodiment includes the key scanning circuit as described in any of the above claims, the keyboard in this embodiment has the same beneficial effects as the key scanning circuit described in any of the above claims.
[0063] In one embodiment, the Kth key signal corresponds to the W, A, S, and D keys on the keyboard. The above embodiments are merely illustrative of the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. A key scan circuit, characterized by, The application comprises: a key module for outputting N kinds of key signals respectively corresponding to N kinds of pressing operations; a signal selection output module electrically connected with the key module, for detecting an Lth key signal according to an Lth scanning signal and detecting an Kth key signal according to an Mth scanning signal, and outputting an Lth detection signal according to the detected Lth key signal or outputting an Kth detection signal according to the detected Kth key signal; a signal acquisition processing module electrically connected with the signal selection output module, for outputting the Lth scanning signal and the Mth scanning signal in sequence and responding to the Lth detection signal and the Kth detection signal; wherein N is greater than or equal to 2, L is less than or equal to N, M is greater than N, M is less than 2N, K is less than N, and N and K are positive integers. The signal selection output module comprises a first signal selection component and a second signal selection component; 2. The key scan circuit of claim 1, wherein, the first signal selection component is used for detecting an Ith key signal according to an Ith scanning signal and outputting an Ith detection signal; the second signal selection component is used for detecting an Kth key signal according to a Pth scanning signal and outputting an Kth detection signal; wherein I is less than N, P is greater than the maximum value of I, P is less than or equal to the maximum value of M, and I and P are positive integers. N is equal to 12, I is less than or equal to 8, P is greater than 8 and less than or equal to 16, M is less than or equal to 16, and K is greater than or equal to 9 and less than or equal to 12.
3. The key scan circuit of claim 2, wherein, The first signal selection component comprises a first multiplexer chip; 4. The key scan circuit of claim 3, wherein, the first multiplexer chip comprises a scanning signal input pin, a detection signal output pin, a first detection pin, a second detection pin, a third detection pin, a fourth detection pin, a fifth detection pin, a sixth detection pin, a seventh detection pin and an eighth detection pin; the scanning signal input pin of the first multiplexer chip is used for inputting the Ith scanning signal, the detection signal output pin of the first multiplexer chip is used for outputting the Ith detection signal, the first detection pin of the first multiplexer chip is used for inputting a first key signal, the second detection pin of the first multiplexer chip is used for inputting a second key signal, the third detection pin of the first multiplexer chip is used for inputting a third key signal, the fourth detection pin of the first multiplexer chip is used for inputting a fourth key signal, the fifth detection pin of the first multiplexer chip is used for inputting a fifth key signal, the sixth detection pin of the first multiplexer chip is used for inputting a sixth key signal, the seventh detection pin of the first multiplexer chip is used for inputting a seventh key signal, and the eighth detection pin of the first multiplexer chip is used for inputting an eighth key signal. The first signal selection component comprises a second multiplexer chip; 5. The key scan circuit of claim 4, wherein, the second multiplexer chip comprises a scanning signal input pin, a detection signal output pin, a ninth detection pin, a tenth detection pin, an eleventh detection pin, a twelfth detection pin, a thirteenth detection pin, a fourteenth detection pin, a fifteenth detection pin and a sixteenth detection pin; The scan signal input pin of the second multiplexer chip is used for inputting the first P scan signal, the detection signal output pin of the second multiplexer chip is used for outputting the first K detection signal, the ninth detection pin of the second multiplexer chip is used for inputting a ninth key signal, the tenth detection pin of the second multiplexer chip is used for inputting a tenth key signal, the eleventh detection pin of the second multiplexer chip is used for inputting an eleventh key signal, the twelfth detection pin of the second multiplexer chip is used for inputting a twelfth key signal, the thirteenth detection pin of the second multiplexer chip is used for inputting the ninth key signal, the fourteenth detection pin of the second multiplexer chip is used for inputting the tenth key signal, the fifteenth detection pin of the second multiplexer chip is used for inputting the eleventh key signal, and the sixteenth detection pin of the second multiplexer chip is used for inputting the twelfth key signal.
6. The key scan circuit of claim 5, wherein, The signal acquisition and processing module comprises a signal acquisition and processing chip; The signal acquisition and processing chip comprises a first scan signal output pin, a second scan signal output pin, a first detection signal input pin and a second detection signal input pin; The first scan signal output pin of the signal acquisition and processing chip is used for outputting the first I scan signal, the second scan signal output pin of the signal acquisition and processing chip is used for outputting the first P scan signal, the first detection signal input pin of the signal acquisition and processing chip is used for inputting the first I detection signal, and the second detection signal input pin of the signal acquisition and processing chip is used for inputting the first K detection signal.
7. The key scan circuit of claim 5, wherein, The key module comprises 12 Hall key assemblies. The Nth Hall key assembly outputs an Nth key signal after an Nth pressing operation.
8. A key scan device, characterized by The key scanning circuit comprises the key scanning circuit according to any one of claims 1-7.
9. A keyboard, characterized by The key scanning circuit comprises the key scanning circuit according to any one of claims 1-7.
10. The keyboard of claim 9, wherein, The first K key signal corresponds to W, A, S and D keys of the keyboard.