Antifuse array structure and antifuse memory device

Abstract

The present application relates to an antifuse array structure and an antifuse memory device. The antifuse array structure comprises an array region and an edge region, with the edge region surrounding the array region. The antifuse array structure includes: antifuse units located in the array region and arranged in an array; dummy fuse units located in the edge region; both the antifuse units and the dummy fuse units include select transistors and antifuse devices, with one of the source and drain regions of the select transistors connected to a bit line and the other connected to the antifuse device; in a first direction, antifuse devices in the same row are connected to the same programming conductor, and select transistors in the same row are connected to the same word line; in a second direction, select transistors in the same column are connected to the same bit line. Embodiments of the present application can effectively improve the reliability of the antifuse array structure and the antifuse memory device.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to an antifuse array structure and an antifuse memory device. Background Art

[0002] Advances in semiconductor technology have led to the emergence of antifuse memory technology. Antifuse memory devices can be programmed by breaking down a dielectric layer (e.g., gate oxide). The resulting connections are highly reliable and free of reverse growth issues, resulting in unlimited read cycles.

[0003] However, the reliability of existing anti-fuse memory devices needs to be improved. Summary of the Invention

[0004] Based on this, embodiments of the present application provide an antifuse array structure and an antifuse memory device to improve the reliability of the antifuse memory device.

[0005] An antifuse array structure comprises an array region and an edge region, wherein the edge region surrounds the array region, and the antifuse array structure comprises:

[0006] Antifuse units are located in the array area and arranged in an array in the array area;

[0007] a dummy fuse unit, located in the edge area;

[0008] The anti-fuse unit and the dummy fuse unit each include a selection transistor and an anti-fuse device, wherein one of a source region and a drain region of the selection transistor is connected to a bit line, and the other is connected to the anti-fuse device;

[0009] In a first direction, the anti-fuse devices in the same row are connected to the same programming conductor, and the selection transistors in the same row are connected to the same word line;

[0010] In the second direction, the selection transistors in the same column are connected to the same bit line.

[0011] In one embodiment, at least one programming wire located in the edge region and connected to the dummy fuse unit is grounded.

[0012] In one embodiment, at least one word line located in the edge region and connected to the dummy fuse unit is grounded.

[0013] In one embodiment, at least one bit line located in the edge region and connected to the dummy fuse unit is grounded.

[0014] In one embodiment, the antifuse array structure further includes:

[0015] At least one dummy conductive line is located in the edge region and is arranged in the same layer and in parallel with the programming conductive line and the word line.

[0016] In one embodiment, the dummy fuse unit is located between the dummy conductive line and the anti-fuse unit.

[0017] In one embodiment, at least one of the pseudo conductive lines is grounded.

[0018] In one embodiment, the material of the dummy conductive line includes polysilicon.

[0019] In one embodiment, the antifuse array structure further includes a first conductivity type well region, and the array region and the edge region are both located in the first conductivity type well region.

[0020] In one embodiment, the dummy fuse unit is disposed around the array region.

[0021] An antifuse memory device comprises a peripheral circuit and any one of the antifuse array structures described above, wherein the peripheral circuit is used to control the antifuse array structure.

[0022] The aforementioned antifuse array structure and antifuse memory device are provided with an edge region surrounding the array region, and an antifuse unit is disposed in the edge region. The antifuse unit and the dummy fuse unit both include a select transistor and an antifuse device, and both have the same structure, thereby ensuring manufacturability. Furthermore, the provision of the dummy fuse unit allows reflection and diffraction during the photolithography process to act on the dummy fuse unit, thereby preventing reflection and diffraction from affecting the pattern accuracy of the antifuse units in the array region during the photolithography process. Therefore, embodiments of the present application can ensure excellent performance of the antifuse units in the array region, thereby improving the reliability of the antifuse array structure and, consequently, the reliability of the antifuse memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 A schematic top view of an antifuse array structure is provided in one embodiment;

[0025] Figure 2 A schematic diagram of a partial cross-sectional structure of an antifuse array structure is provided in one embodiment;

[0026] Figure 3A schematic top view of an antifuse array structure is provided in another embodiment.

[0027] Description of reference numerals:

[0028] 100 - anti-fuse unit, 200 - pseudo-fuse unit, 10 - selection transistor, 20 - anti-fuse device, 300 - semiconductor substrate, 311 - active area, 11 - bit line, 12 - word line, 13 - programming wire, 400 - pseudo-wire, 500 - guard ring structure, 510 - guard ring, 520 - conductive contact structure, 530 - metal conductive ring. DETAILED DESCRIPTION

[0029] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0031] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there can be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0032] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0033] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0034] In one embodiment, an antifuse memory device is provided, comprising a peripheral circuit and an antifuse array structure, wherein the peripheral circuit is used to control the antifuse array structure.

[0035] In one embodiment, see Figure 1 , an antifuse array structure is provided, which has an array region 1a and an edge region 2a. The edge region 2a surrounds the array region 1a.

[0036] Meanwhile, the antifuse array structure includes an antifuse unit 100 and a dummy fuse unit 200. The antifuse unit 100 is located in the array region 1a, and the dummy fuse unit 200 is located in the edge region 2a.

[0037] The anti-fuse unit 100 and the dummy fuse unit 200 may each include a selection transistor 10 and an anti-fuse device 20 .

[0038] See also Figure 2The selection transistor 10 can be formed based on a semiconductor substrate 300. The semiconductor substrate 300 can be a single-layer structure or a multi-layer structure. For example, the semiconductor substrate 300 can include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the semiconductor substrate 300 can also include a substrate such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

[0039] A shallow trench isolation (STI) structure may be formed in the semiconductor substrate 300 , and the STI structure may isolate a plurality of active regions 311 spaced apart in the semiconductor substrate 300 . The selection transistor 10 may be formed based on the active regions 311 .

[0040] The active region may be a P-type active region or an N-type active region. The selection transistor 10 formed based on the P-type active region may be an NMOS. The selection transistor 10 formed based on the N-type active region may be a PMOS.

[0041] The source region S and drain region D of the select transistor 10 can be formed by doping the active region. For example, a P-type active region can be formed by implanting N-type ions to form the source region S and drain region D. An N-type active region can be implanted by implanting P-type ions to form the source region S and drain region D. One of the source region S and drain region D of the select transistor 10 is connected to the bit line 11, and the other is connected to the anti-fuse device 20. The gate of the select transistor 10 is connected to the word line 12.

[0042] The anti-fuse device 20 may be an anti-fuse transistor or an anti-fuse capacitor structure.

[0043] When the anti-fuse device 20 is an anti-fuse transistor, see Figure 1 as well as Figure 2 The anti-fuse transistor and the select transistor 10 can be formed based on the same active region 311. In this case, the anti-fuse transistor and the select transistor 10 can share the source region S or the drain region D, so that the two are connected to each other. At the same time, the gate of the anti-fuse transistor is connected to the programming wire 13. The programming wire 13 can be arranged parallel to the word line 12 and perpendicular to or intersecting the bit line 11. The programming wire 13 can serve as the gate of the anti-fuse transistor, and the word line 12 can serve as the gate of the select transistor 10.

[0044] Meanwhile, when the anti-fuse device 20 is an anti-fuse transistor, a plurality of anti-fuse units 100 may be formed on the same active region 311 and arranged along the extending direction of the active region 311. In this case, the select transistors 10 of adjacent anti-fuse units 100 may be adjacent to each other and share a source region S or a drain region D. And / or, the anti-fuse transistors of adjacent anti-fuse units 100 may be adjacent to each other and share a source region S or a drain region D.

[0045] When the anti-fuse device 20 is an anti-fuse capacitor structure, the first plate of the anti-fuse capacitor structure can be connected to the programming wire 13, and the second plate of the anti-fuse capacitor structure can be connected to the source region S or the drain region D of the select transistor 10. The programming wire 13 can be arranged parallel to the word line 12 and perpendicular to or intersecting the bit line 11.

[0046] At the same time, the anti-fuse units 100 are arranged in an array in the array region 1a. The dummy fuse units 200 in the edge region 2a can be arranged in an array together with the anti-fuse units 100 in the array region 1a. Of course, the dummy fuse units 200 in the edge region 2a can also be arranged in a different array arrangement than the anti-fuse units 100 in the array region 1a, and this is not limited here.

[0047] In the first direction, the same row of anti-fuse devices 20 is connected to the same programming conductor 13, and the same row select transistor 10 is connected to the same word line 12. In the second direction, the same column select transistor 10 is connected to the same bit line 11. In this case, the programming conductor 13 and the word line 12 can extend along the first direction, and the bit line 11 can extend along the second direction. The first direction intersects the second direction.

[0048] In this embodiment, both the antifuse unit 100 and the dummy fuse unit 200 include a select transistor 10 and an antifuse device 20, and both have identical structures, thereby ensuring manufacturability. Furthermore, the provision of the dummy fuse unit 200 allows reflection and diffraction during the photolithography process to act on the dummy fuse unit 200, thereby preventing reflection and diffraction from affecting the pattern accuracy of the antifuse unit 100 in the array region 1a. Therefore, this embodiment ensures excellent performance of the antifuse unit 100 in the array region 1a, thereby improving the reliability of the antifuse array structure.

[0049] In one embodiment, see Figure 1 The dummy fuse unit 200 can be arranged around the array region 1a, thereby surrounding the antifuse unit 100 in the array region 1a. In this case, the antifuse unit 100 in the array region 1a can be well protected, so that the antifuse units 100 located at various positions in the array region 1a can be prevented from affecting the pattern accuracy due to reflection and diffraction during the photolithography process.

[0050] Of course, in other embodiments, the dummy fuse unit 200 may also be disposed on one side or several sides of the array region 1 a rather than completely surrounding the array region 1 a , and may be specifically disposed according to actual needs.

[0051] In one embodiment, at least one programming conductive line 13 located in the edge region 2 a and connected to the dummy fuse unit 200 is grounded.

[0052] The programming conductive line 13 located in the edge region 2 a may be connected to the ground terminal through related conductive plugs and wiring layers.

[0053] The programming wire 13 may be made of a metal material or a conductive material such as polysilicon. The metal material may include copper (Cu), aluminum (Al), cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), etc.

[0054] At this time, in the second direction, the programming wires 13 in the edge area 2a can shield the antifuse units 100 arrayed in the array area 1a, thereby preventing the key signal lines input to the antifuse units 100 from being affected by noise.

[0055] As an example, see Figure 1 In the edge regions 2a located above and below the array region 1a in the second direction, a row of active regions 310 arranged along the first direction may be provided. Each active region 310 extends along the second direction, and two dummy fuse units 200 arranged along the second direction are formed based on the same active region 310. In the two dummy fuse units 200 formed based on the same active region 310, the select transistors 10 are adjacent and share a source region S or a drain region D. The shared source region S or drain region D is connected to the bit line 11. Furthermore, in the two dummy fuse units 200 formed based on the same active region 310, the anti-fuse device 20 in each dummy fuse unit 200 is located on a side of the select transistor 10 therein that is away from the other dummy fuse unit 200.

[0056] At this time, two rows of dummy fuse cells 200 may be formed in the edge region 2 a on the upper side of the array region 1 a , and two rows of dummy fuse cells 200 may be formed in the edge region 2 a on the lower side of the array region 1 a .

[0057] At the same time, in the first direction, the anti-fuse devices 20 of the dummy fuse units 200 located in the same row are connected to the same programming wire 13. Therefore, two programming wires 13 can be provided in the edge regions 2a above and below the array region 1a. In this case, four programming wires 13 can be provided in the edge region 2a. Any one, some, or all of the four programming wires 13 can be grounded.

[0058] For example, at least one programming wire 13 can be grounded in the upper edge region 2a of the array region 1a, and at least one programming wire 13 can be grounded in the lower edge region 2a of the array region 1a. In this case, both the upper and lower edge regions 2a of the array region 1a have grounded programming wires 13, thereby shielding the array region A1 from both the upper and lower sides in the second direction, thereby achieving a better shielding effect for the array region A1.

[0059] Of course, the number of rows of dummy fuse units 200 in the edge region 2 a above and below the array region 1 a in the second direction may also be different, and this is not limited here.

[0060] Furthermore, it can be understood that the grounded programming wire 13 located in the edge region 2a is a programming wire 13 that is connected only to the dummy fuse unit 200 in the edge region 2a and is not connected to the anti-fuse unit 100 in the array region 1a. In other words, the grounded programming wire 13 is not a programming wire 13 shared by the dummy fuse unit 200 and the anti-fuse unit 100. In this case, the anti-fuse unit 100 in the array region 1a can be guaranteed to operate normally.

[0061] For example, see Figure 1 The programming wires 13 connected to the pseudo-fuse units 200 located in the edge areas 2a on the upper and lower sides of the array area 1a can be grounded, while the programming wires 13 connected to the pseudo-fuse units 200 located in the edge areas 2a on the left and right sides of the array area 1a are shared by the pseudo-fuse units 200 and the anti-fuse units 100 and cannot be grounded.

[0062] In one embodiment, at least one word line 12 located in the edge region 2 a and connected to the dummy fuse unit 200 is grounded.

[0063] The word lines 12 located in the edge region 2 a may be connected to the ground terminal through associated conductive plugs and wiring layers.

[0064] The word line 12 may be made of a metal material or a conductive material such as polysilicon. The metal material may include copper (Cu), aluminum (Al), cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), etc.

[0065] At this time, in the second direction, the word lines 12 in the edge region 2 a can shield the antifuse units 100 arrayed in the array region 1 a, thereby preventing the key signal lines input to the antifuse units 100 from being affected by noise.

[0066] See also Figure 1When a row of active areas 310 is formed in both the upper and lower edge regions 2a of the array region 1a, thereby forming two rows of dummy fuse cells 200, the anti-fuse devices 20 of the dummy fuse cells 200 in the same row are connected to the same word line 12 in the first direction. Therefore, two word lines 12 can be provided in both the upper and lower edge regions 2a of the array region 1a. Furthermore, in both the upper and lower edge regions 2a of the array region 1a, the two word lines 12 can be located between the two programming conductors 13. In this case, a total of four word lines 12 can be provided in the edge region 2a. Any one, some, or all of the four word lines 12 can be grounded.

[0067] As an example, at least one word line 12 can be grounded in the upper edge region 2a of the array region 1a, and at least one word line 12 can be grounded in the lower edge region 2a of the array region 1a. In this case, both the upper and lower edge regions 2a of the array region 1a have grounded word lines 12, thereby shielding the array region A1 from both the upper and lower sides, thereby providing better shielding for the array region A1 in the second direction.

[0068] It is understood that the grounded word line 12 located in the edge region 2a is a word line 12 that is connected only to the dummy fuse unit 200 in the edge region 2a and is not connected to the anti-fuse unit 100 in the array region 1a. In other words, the grounded word line 12 is not a word line 12 shared by the dummy fuse unit 200 and the anti-fuse unit 100. In this case, the anti-fuse unit 100 in the array region 1a can be guaranteed to operate normally.

[0069] For example, see Figure 1 The word lines 12 connected to the dummy fuse units 200 located in the edge regions 2a on the upper and lower sides of the array region 1a can be grounded, while the word lines 12 connected to the dummy fuse units 200 located in the edge regions 2a on the left and right sides of the array region 1a are shared by the dummy fuse units 200 and the anti-fuse units 100 and cannot be grounded.

[0070] Alternatively, in some examples, at least one word line 12 and / or at least one programming wire 13 may be selected from the edge area 2a on the upper side of the array area 1a for grounding, and at the same time, at least one word line 12 and / or at least one programming wire 13 may be selected from the edge area 2a on the lower side of the array area 1a for grounding.

[0071] For example, a word line is selected and grounded in the upper edge region 2a of the array region 1a, while a programming wire 13 is selected and grounded in the lower edge region 2a of the array region 1a. Another example is also possible, where a programming wire 13 is selected and grounded in the upper edge region 2a of the array region 1a, while a word line 12 is selected and grounded in the lower edge region 2a of the array region 1a. Another example is also possible, where a word line 12 is selected and grounded in the upper edge region 2a of the array region 1a, while a programming wire 13 is selected and grounded in the upper edge region 2a of the array region 1a; and a word line 12 is selected and grounded in the lower edge region 2a of the array region 1a, while a programming wire 13 is selected and grounded in the lower edge region 2a of the array region 1a. In this case, the array region A1 can be shielded from both the upper and lower sides, thereby providing better shielding for the array region A1 in the second direction.

[0072] In one embodiment, at least one bit line 11 located in the edge region 2 a and connected to the dummy fuse unit 200 is grounded.

[0073] As an example, the bit line 11 located in the edge region 2 a may be connected to the ground terminal through an associated conductive plug and wiring layer.

[0074] Alternatively, as an example, the bit line 11 located in the edge region 2a may be located above the word line 12 and the programming conductive line 13 in the edge region 2a. The bit line 11 may be connected to the word line 12 and / or the programming conductive line 13 in the edge region 2a via a conductive plug, thereby being grounded simultaneously with the word line 12 and / or the programming conductive line 13.

[0075] The material of the bit line 11 may be, for example, a metal material, and the metal material may include copper (Cu), aluminum (Al), cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), and the like.

[0076] At this time, in the first direction, the bit lines 11 in the edge region 2 a can shield the antifuse units 100 arrayed in the array region 1 a, thereby preventing the key signal lines input to the antifuse units 100 from being affected by noise.

[0077] As an example, see Figure 1 In the edge regions 2a located on the left and right sides of the array region 1a in the first direction, a row of active regions 310 arranged along the second direction can be provided. Each active region 310 extends along the second direction. Two dummy fuse units 200 arranged along the second direction are formed based on the same active region 310.

[0078] At this time, a column of dummy fuse cells 200 may be formed in the edge region 2 a on the left side of the array region 1 a , and a column of dummy fuse cells 200 may be formed in the edge region 2 a on the right side of the array region 1 a .

[0079] At the same time, in the second direction, the antifuse devices 20 of the dummy fuse cells 200 located in the same column are connected to the same bit line 11. Therefore, a bit line 11 can be provided in both the edge regions 2a on the left and right sides of the array region 1a. In this case, two bit lines 11 can be provided in the edge region 2a. Either one of the two bit lines 11 can be grounded, or both bit lines 11 can be grounded.

[0080] When both bit lines 11 are grounded, the array area A1 is shielded from both the left and right sides in the first direction, thereby achieving a better shielding effect on the array area A1.

[0081] Of course, the number of columns of the dummy fuse units 200 in the edge regions 2 a on the left and right sides of the array region 1 a in the second direction may also be different, and this is not limited here.

[0082] It is understood that the grounded bit line 11 located in the edge region 2a is a bit line 11 that is connected only to the dummy fuse unit 200 in the edge region 2a and is not connected to the anti-fuse unit 100 in the array region 1a. In other words, the grounded bit line 11 is not a bit line 11 shared by the dummy fuse unit 200 and the anti-fuse unit 100. In this case, the anti-fuse unit 100 in the array region 1a can be guaranteed to operate normally.

[0083] For example, see Figure 1 The bit line 11 connected to the dummy fuse unit 200 located in the edge area 2a on the left and right sides of the array area 1a can be grounded, while the bit line 11 connected to the dummy fuse unit 200 located in the edge area 2a on the upper and lower sides of the array area 1a is shared by the dummy fuse unit 200 and the anti-fuse unit 100 and cannot be grounded.

[0084] In some examples, at least one word line 12 and / or at least one programming wire 13 in the edge region 2a above the array region 1a may be grounded; at least one word line 12 and / or at least one programming wire 13 in the edge region 2a below the array region 1a may be grounded; at least one bit line 11 in the edge region 2a to the left of the array region 1a may be grounded; and at least one bit line 11 in the edge region 2a to the right of the array region 1a may be grounded. For example, all bit lines 11, all word lines 12, and all programming wires 13 within the edge region 2a may be grounded.

[0085] At this time, it is equivalent to performing closed shielding around the entire array area, thereby further ensuring that the key signal input to the anti-fuse unit 100 is not affected by noise, thereby playing a good shielding role.

[0086] In one embodiment, see Figure 1The antifuse array structure further includes at least one dummy conductive line 400. The dummy conductive line 400 is located in the edge region 2a. The material of the dummy conductive line 400 may include, but is not limited to, polycrystalline silicon.

[0087] The dummy conductive line 400, the programming conductive line 13 and the word line 12 are arranged in parallel. As an example, the dummy conductive line 400, the programming conductive line 13 and the word line 12 can be arranged in a pattern array with equal intervals in the second direction.

[0088] Therefore, the dummy conductive line 400 may extend along the first direction, and at least one dummy conductive line 400 may be provided in each of the edge regions 2a located above and below the array region 1a in the second direction.

[0089] The dummy conductive line 400, the programming conductive line 13 and the word line 12 are arranged in the same layer. At this time, the dummy conductive line 400 can be prepared in the edge area 2a while the programming conductive line 13 and the word line 12 are prepared in the array area A1.

[0090] At this time, by setting up the dummy wire 400, the reflection and diffraction during the photolithography process can act on the dummy wire 400, thereby avoiding affecting the pattern accuracy of the programming wire 13 and / or word line 12 in the array area 1a due to reflection and diffraction during the photolithography process, thereby improving the manufacturing reliability of the programming wire 13 and / or word line 12, and further ensuring the excellent performance of the anti-fuse unit 100 in the array area 1a.

[0091] In one embodiment, see Figure 1 , the dummy fuse unit 200 is located between the dummy conductive line 400 and the anti-fuse unit 100 .

[0092] At this time, the dummy fuse units 200 can be arranged in an array together with the antifuse units 100 , so that the environments of the antifuse units 100 in the array area 1 a during processing are more consistent, thereby improving the performance uniformity of the antifuse units 100 .

[0093] Of course, in other embodiments, the dummy conductive line 400 may also be disposed between the dummy fuse unit 200 and the anti-fuse unit 100 .

[0094] In one embodiment, at least one dummy conductive line 400 located in the edge region 2 a is grounded.

[0095] The dummy conductive line 400 may be connected to a ground terminal through a conductive plug and a wiring layer associated therewith.

[0096] At this time, in the second direction, the dummy conductive lines 400 in the edge region 2 a can shield the antifuse units 100 arrayed in the array region 1 a, thereby preventing the key signal lines input to the antifuse units 100 from being affected by noise.

[0097] As an example, when dummy wires 400 are provided in the edge areas 2a located above and below the array area 1a in the second direction, the dummy wires 400 located in the edge areas 2a located above and below the array area 1a can be grounded, and then the array area A1 can be shielded from both the upper and lower sides in the second direction, thereby achieving a better shielding effect on the array area A1.

[0098] And, as an example, see Figure 3 , the bit line 11 located in the edge region 2a can extend to above the dummy conductive line 400. At this time, the dummy conductive line 400 and the bit line 11 can be grounded simultaneously through a conductive plug.

[0099] In this case, for example, a dummy conductive line 400 may be provided in each of the edge regions 2a located above and below the array region 1a in the second direction, and a bit line 11 may be provided in each of the edge regions 2a located to the left and right of the array region 1a in the first direction. The ends of each bit line 11 may extend above the two dummy conductive lines 400, respectively. In this case, each dummy conductive line 400 may be connected to the dummy conductive lines 400 located on the left and right sides of the array region 1a via a conductive plug, thereby forming a closed shield around the array region 1a. This further ensures that the critical signals input to the antifuse unit 100 are not affected by noise, thereby providing an effective shielding effect.

[0100] In one embodiment, see Figure 2 The antifuse array structure further includes a first conductive type well region 310 , and both the array region 1 a and the edge region 2 a are located in the first conductive type well region 310 .

[0101] The first conductive type well region 310 can be a P-type well region or an N-type well region. A shallow trench isolation structure is formed in the first conductive type well region 310. The shallow trench isolation structure can isolate a plurality of spaced active regions 311 in the first conductive type well region 310.

[0102] At this time, the semiconductor substrate 300 used to form the antifuse array structure can have a second conductivity type. The semiconductor substrate 300 is doped to form a first conductivity type well region 310. A second conductivity type transistor is formed on the first conductivity type well region 310, thereby forming the antifuse unit 100. One of the first conductivity type and the second conductivity type is N-type, and the other is P-type.

[0103] As an example, semiconductor substrate 300 can be a P-type semiconductor substrate. During the formation of the antifuse array structure, portions of the P-type semiconductor substrate can be doped using ion implantation or other methods to form an N-type well region for forming the antifuse array structure. This N-type well region serves as the first conductivity type well region 310. Both array region 1a and edge region 2a are located in this N-type well region.

[0104] Alternatively, as an example, semiconductor substrate 300 may be an N-type semiconductor substrate. During the formation of the antifuse array structure, portions of the N-type semiconductor substrate may be doped using ion implantation or other methods to form a P-type well region for forming the antifuse array structure. This P-type well region serves as the first conductivity type well region 310. Both array region 1a and edge region 2a are located in this P-type well region.

[0105] In this embodiment, not only can the dummy fuse unit 200 be arranged around the array area 1a via the edge region 2a to improve the pattern accuracy and performance of the anti-fuse unit 100, but the edge region 2a and the array area 1a are also located in the same first conductivity type well region 310, thereby preventing the anti-fuse unit 100 (including the select transistor 10 and the anti-fuse device 20) located at the edge of the array area 1a from being affected by the well proximity effect. In this way, the device performance consistency of the anti-fuse unit 100 at various locations in the array area 1a can be improved.

[0106] Of course, in other embodiments, the edge region 2 a may not be located in the first conductivity type well region 310 , and this is not limited here.

[0107] Furthermore, in some embodiments, a first conductivity type well region 310 is formed on a second conductivity type semiconductor substrate 300 to form an antifuse unit 100 including a second conductivity type transistor. Furthermore, other semiconductor devices including first conductivity type transistors may also be formed on the semiconductor substrate 300 .

[0108] At this time, see Figure 1 The antifuse array structure may further include a guard ring structure 500. The guard ring structure 500 may surround the first conductive type well region 310, thereby preventing the occurrence of a latch-up effect.

[0109] The guard ring structure 500 may include a guard ring 510, a conductive contact structure 520, and a metal conductive ring 530. The guard ring 510 may be a ring-shaped region formed by heavily doping a semiconductor substrate or a first conductivity type well region. The metal conductive ring 530 may be located above and opposite the guard ring 510. The conductive contact structure 520 may be located between the guard ring 510 and the metal conductive ring 530, thereby connecting the two.

[0110] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0111] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. An antifuse array structure, characterized in that: The antifuse array structure comprises an array region and an edge region, wherein the edge region surrounds the array region. The antifuse array structure comprises: Antifuse units are located in the array area and arranged in an array in the array area; a dummy fuse unit located in the edge region and arranged at a position where reflection and diffraction effects during the photolithography process can act; The anti-fuse unit and the dummy fuse unit each include a selection transistor and an anti-fuse device, wherein one of a source region and a drain region of the selection transistor is connected to a bit line, and the other is connected to the anti-fuse device; In a first direction, the anti-fuse devices in the same row are connected to the same programming conductor, and the selection transistors in the same row are connected to the same word line; In the second direction, the selection transistors in the same column are connected to the same bit line.

2. The antifuse array structure according to claim 1, wherein: At least one programming wire located in the edge region and connected to the dummy fuse unit is grounded.

3. The antifuse array structure according to claim 1, wherein: At least one word line located in the edge region and connected to the dummy fuse unit is grounded.

4. The antifuse array structure according to claim 1, wherein: At least one bit line located in the edge region and connected to the dummy fuse unit is grounded.

5. The antifuse array structure according to claim 1, wherein: The antifuse array structure further includes: At least one dummy conductive line is located in the edge region and is arranged in the same layer and in parallel with the programming conductive line and the word line.

6. The antifuse array structure according to claim 5, wherein: The dummy fuse unit is located between the dummy conductive line and the anti-fuse unit.

7. The antifuse array structure according to claim 5, wherein: At least one of the dummy conductive lines is grounded.

8. The antifuse array structure according to claim 5, wherein: The material of the dummy conductive line includes polysilicon.

9. The antifuse array structure according to claim 1, wherein: The antifuse array structure further includes a first conductive type well region, and the array region and the edge region are both located in the first conductive type well region.

10. The antifuse array structure according to claim 1, wherein: The dummy fuse unit is arranged around the array region.

11. An anti-fuse memory device, characterized in that: The invention comprises a peripheral circuit and the antifuse array structure according to any one of claims 1 to 10, wherein the peripheral circuit is used to control the antifuse array structure.

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