A multi-chip parallel silicon carbide power module based on copper clip

By using copper clips to connect the upper and lower bridge arms of the DBC substrate in the silicon carbide power module, the problem of mismatch between parasitic inductance and thermal expansion coefficient of the silicon carbide power module is solved, achieving higher reliability and better current distribution balance.

CN119008602BActive Publication Date: 2026-06-02XI AN JIAOTONG UNIV
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
XI AN JIAOTONG UNIV
Filing Date
2024-08-13
Publication Date
2026-06-02

AI Technical Summary

Technical Problem

Existing interconnect technologies for silicon carbide power modules cannot fully leverage their advantages, resulting in issues such as high parasitic inductance, reliability problems caused by mismatched coefficients of thermal expansion, and uneven dynamic current distribution.

Method used

Copper clips are used instead of traditional aluminum bonding wires to connect the upper and lower bridge arms of the DBC substrate, optimizing the circuit topology, increasing heat dissipation paths, and adjusting the structural parameters of the copper clips to balance the parasitic inductance of the power source of the parallel chips.

Benefits of technology

The parasitic parameters of the interconnection section are reduced, reliability and heat dissipation are improved, the problem of uneven current distribution is optimized, and the stability and performance of multi-chip parallel silicon carbide power modules are enhanced.

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Abstract

The application relates to the technical field of semiconductor packaging, and discloses a multi-chip parallel silicon carbide power module based on a copper clamp, in which a copper clamp connecting assembly is used to connect an upper bridge arm DBC substrate and a lower bridge arm DBC substrate in a multi-chip parallel silicon carbide power module body, and replaces traditional aluminum bonding wires, so that the electrical interconnection between the power source poles of silicon carbide power semiconductor chips and the upper surface metal regions of the DBC substrates is completed, the parasitic parameters of the interconnection parts are reduced, the reliability of the interconnection structure is improved, and an additional top heat dissipation path is added for the silicon carbide power semiconductor chips, so that the heat dissipation capacity of the silicon carbide power module is enhanced, the parasitic inductance of the power source poles of the parallel chips is balanced by adjusting the structural parameters of the copper clamp, and the uneven dynamic current distribution problem existing in the use of the multi-chip parallel silicon carbide power module is optimized in combination with the symmetry of the layout.
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