A high-precision serial PRBS generation and bit error detection system

Abstract

The present invention discloses a high-precision serial PRBS generation and error code detection system, comprising: a first pseudo-random code generation circuit configured to generate a first pseudo-random code sequence and obtain a second pseudo-random code sequence after passing through a clock data recovery circuit; a second pseudo-random code generation circuit configured to generate a third pseudo-random code sequence, detect the phase difference with the second pseudo-random code sequence through a phase detection circuit, and then perform delay adjustment on the third pseudo-random code sequence according to the phase difference through a delay generation circuit to obtain a third pseudo-random code sequence with aligned phases; a pseudo-random code detection circuit configured to detect error codes in the second pseudo-random code sequence based on the third pseudo-random code sequence with aligned phases; and an error code statistics circuit configured to statistically calculate the error rate in real time based on the error detection result of the pseudo-random code detection circuit. The present invention can achieve precise error code detection and make up for the defects of traditional error code detection and generation circuits.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed interface circuits, and particularly to a high-precision serial PRBS generation and error code detection system. Background Art

[0002] In a high-speed serial data transmission system SerDes (Serializer-Deserializer), the transmitter encodes the lower-speed parallel data and completes the serialization of the data, and then converts the transmitted data into differential signals through a driving circuit and outputs them to the interconnection line. At the receiver, the receiver extracts the clock information from the data stream and samples the data with the recovered clock to recover the transmitted data signal. This process is called Clock Data Recovery (CDR), and the recovered data is further processed by serial-to-parallel conversion and decoding. The clock data recovery circuit is a key module for realizing high-speed serial communication. It recovers the clock signal from the serial data, then retimes the data to recover the data, and eliminates the jitter introduced during the data transmission process.

[0003] As the data rate continues to increase, the influence of non-ideal factors such as noise on the signal becomes greater and greater, resulting in a decline in signal quality and waveform degradation, thereby causing misidentification of data, that is, error codes. In a high-speed serial transmission system, due to the influence of non-ideal factors during the transmission process, the data received at the receiver is not ideal, but the superposition of the ideal signal and the influence during the transmission process. Jitter is an important factor causing error codes. Whether the CDR circuit at the receiver can recover the correct clock signal from the data stream with jitter signals superimposed and sample the correct data is an important performance index of the high-speed serial interface circuit.

[0004] The Pseudo Random Binary Sequence (PRBS) is widely used in the bit error rate test of communication systems because it is relatively easy to generate appropriate sequences at both the transmitter and the receiver through a Linear Feedback Shift Register (LFSR). To calculate the bit errors at the receiver, the sequence code stream at the receiver needs to be bit-synchronized with the code stream at the transmitter. After synchronization, the digital sequence at the receiver is compared with the digital sequence of the code stream at the transmitter to detect and count the bit errors. Taking a SerDes chip as an example, after entering the pseudo-random code test mode, the pseudo-random code generation circuit inside the chip generates a high-speed pseudo-random code. After inputting it into the signal channel link, the signal channel link recovers the high-speed clock and high-speed data. The bit errors generated by the data recovered after passing through the signal channel link system path are detected by the bit error detection loop, and the bit error rate is statistically calculated. Since there will be a relative phase delay of the clock and data after passing through the trace, directly sampling the data using the clock may result in errors. In addition, the existing solution consists of a pseudo-random code generation circuit and a bit error detection loop. Due to the existence of the loop, when there is one bit error at the input end, 1 - 3 bit errors will be randomly reported to the output end. Therefore, the existing bit error generation and detection solutions are not suitable for high-precision bit error detection scenarios.

[0005] In addition, the prior art generally uses a multi-bit (Bit) synchronization circuit to implement multiple-bit registers. In the parallel pseudo-random code bit error detection and statistics circuit, the number of registers for bit error statistics is very large and the number of bits is high. If both the speed and accuracy of the multi-bit synchronization circuit are to be considered, and real-time reading and sampling are to be achieved, a very large number of carry-lookahead synchronous adders need to be added to synchronize the data. However, synchronous adders have a large area and high power consumption, and are not suitable for the parallel pseudo-random code bit error detection and statistics circuit. Summary of the Invention

[0006] To solve the above problems, the present invention proposes a high-precision serial PRBS generation and bit error detection system, which introduces a delay generation circuit to calibrate the clock, thereby aligning the phase relationship between the clock and the data. The present invention can also enable the pseudo-random code detection circuit and the bit error statistics circuit to work in a low-overhead (i.e., small occupied area and low power consumption) state while obtaining data in real time.

[0007] The technical solution adopted by the present invention is as follows:

[0008] The present invention proposes a high-precision serial PRBS generation and bit error detection system, comprising:

[0009] The first pseudo-random code generation circuit is configured to generate a first pseudo-random code sequence PRBS data, and obtain a second pseudo-random code sequence CDR data_delay after passing through a clock data recovery circuit;

[0010] The second pseudo-random code generation circuit is configured to generate a third pseudo-random code sequence PRBS data', detect the phase difference with the second pseudo-random code sequence CDR data_delay through a phase detection circuit, and then perform a time delay adjustment on the third pseudo-random code sequence PRBS data' according to the phase difference through a time delay generation circuit to obtain a phase-aligned third pseudo-random code sequence PRBS data'_delay; the third pseudo-random code sequence PRBS data' has the same data as the first pseudo-random code sequence PRBS data, and the phases are the same or different;

[0011] The pseudo-random code detection circuit is configured to detect the error code in the second pseudo-random code sequence CDR data_delay based on the phase-aligned third pseudo-random code sequence PRBS data'_delay;

[0012] The error code statistics circuit is configured to statistically calculate the error rate in real time based on the error code detection result of the pseudo-random code detection circuit.

[0013] Further, after the phase detection circuit detects the phase difference between the third pseudo-random code sequence PRBS data' generated by the second pseudo-random code generation circuit and the second pseudo-random code sequence CDR data_delay recovered by the clock data recovery circuit, the time delay generation circuit is controlled based on a digital feedback loop to perform a time delay adjustment on the third pseudo-random code sequence PRBS data' generated by the second pseudo-random code generation circuit according to the phase difference, so as to obtain a phase-aligned third pseudo-random code sequence PRBS data'_delay.

[0014] Further, the phase detection circuit includes a first D flip-flop, a second D flip-flop, and a third D flip-flop. The clock terminal of the first D flip-flop inputs a sampling clock, the data terminal inputs the third pseudo-random code sequence PRBS data', and the output terminal generates a first data; the clock terminal of the second D flip-flop inputs the sampling clock, the data terminal inputs the first data, and the output terminal generates a second data; the clock terminal of the third D flip-flop inputs an edge sampling clock, the data terminal inputs the third pseudo-random code sequence PRBS data', and the output terminal generates a third data, and the edge sampling clock has a 180° phase difference from the sampling clock.

[0015] Further, the sampling clock is introduced by the clock recovered by the clock data recovery circuit, that is, the same as the clock used for the second pseudo-random code sequence CDR data_delay.

[0016] Further, when the first data is equal to the third data, it indicates that the sampling is advanced; when the second data is equal to the third data, it indicates that the sampling is delayed; the first data, the second data, and the third data are statistically analyzed to obtain phase information, and the phase information is output to the time delay generation circuit through a digital feedback loop to finally align the data.

[0017] Further, when an external input or a masking signal generated by timing is input, the error code detection and error code statistics are paused; after waiting for the digital sampling data, the masking signal is reset to zero again, and the error code statistics are continued.

[0018] Further, the error code statistics circuit includes a logic circuit and an asynchronous counter. The first input terminal of the logic circuit is connected to an error code signal, the second input terminal is connected to a masking signal, and the output terminal is electrically connected to the asynchronous counter to count the error code signal; the masking signal can block the error code signal from being transmitted to the asynchronous counter.

[0019] Further, the logic circuit includes a NOT gate unit and a NOR gate unit. The input terminal of the NOT gate unit is connected to an error code signal, the output terminal of the NOT gate unit is electrically connected to the first input terminal of the NOR gate unit, the second input terminal of the NOR gate unit is connected to a masking signal, and the output terminal of the NOR gate unit is electrically connected to the asynchronous counter.

[0020] Further, the asynchronous counter includes N D flip-flops connected in series successively, where N is a positive integer.

[0021] Further, the high-precision serial PRBS generation and error code detection system further includes a digital register. The signal input terminal of the digital register is electrically connected to the signal output terminal of the error code statistics circuit and receives the error rate information transmitted in real time by the error code statistics circuit based on the corresponding timing.

[0022] The beneficial effects of the present invention are as follows:

[0023] (1) Compared with the traditional pseudo-random code generation and detection circuit, the present invention performs phase alignment through two pseudo-random code generation circuits and a time delay generation circuit, that is, two pseudo-random code generation circuits output PRBS sequences with the same data (but the phases may not be the same). One path recovers data through a clock data recovery circuit, and the other path adjusts the phase through a time delay generation circuit to reach the same phase as the data recovered by the clock data recovery circuit, and then enters the pseudo-random code detection circuit through sampling, thereby realizing error code detection. The present invention can achieve precise error code detection and makes up for the defects of the traditional error code detection and generation circuits.

[0024] (2) Although synchronous counters can well achieve real-time synchronization and transfer data out, the problem of synchronous counters as error counting circuits lies in that in a parallel pseudo-random code error detection and counting circuit, the number of synchronous counters for error counting and the number of bits are both very large. Since the scale and power consumption of synchronous counters increase exponentially with the increase in the number of bits, it is difficult to obtain advantages in scale and power consumption. The present invention utilizes an asynchronous error counting circuit and a shielding signal (pause signal), and can transmit real-time bit error rate information through corresponding timing sequences, enabling the error detection circuit and the error counting circuit to work in a low-overhead state while obtaining data in real time, that is, occupying a small area and having low power consumption. Therefore, the present invention controls the scale at the same time as the power consumption with a large advantage at a small cost through timing. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a schematic diagram of a high-precision serial PRBS generation and error detection system of the present invention.

[0026] Figure 2 is a flowchart of a high-precision serial PRBS generation and error detection system of the present invention.

[0027] Figure 3 is a schematic diagram of a phase detection circuit of the present invention.

[0028] Figure 4 is a timing diagram of a phase detection circuit of the present invention.

[0029] Figure 5 is a block diagram of an existing parallel pseudo-random code error detection and counting circuit based on an asynchronous adder.

[0030] Figure 6 is a block diagram of an existing parallel pseudo-random code error detection and counting circuit based on a carry-lookahead adder.

[0031] Figure 7 is a schematic diagram of a logic circuit of an error counting circuit of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0032] In order to have a clearer understanding of the technical features, objectives, and effects of the present invention, the specific embodiments of the present invention will now be described. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention, that is, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0033] As Figure 1The schematic diagram of a high-precision serial PRBS generation and error code detection system according to this embodiment is shown. The system includes a first pseudo-random code generation circuit PRBS Gen1, a second pseudo-random code generation circuit PRBS Gen2, a pseudo-random code detection circuit PRBS Checker, and an error code statistics circuit BER Statistics. The first pseudo-random code generation circuit PRBS Gen1 is configured to generate a first pseudo-random code sequence PRBS data, and obtain a second pseudo-random code sequence CDR data_delay after passing through a clock data recovery circuit CDR; the second pseudo-random code generation circuit PRBS Gen2 is configured to generate a third pseudo-random code sequence PRBS data' (having the same data as the first pseudo-random code sequence PRBS data, but not necessarily the same phase). First, the phase difference with the second pseudo-random code sequence CDR data_delay is detected by a phase detection circuit PD, and then the third pseudo-random code sequence PRBS data' is adjusted in time delay according to the phase difference by a time delay generation circuit PI to obtain a third pseudo-random code sequence PRBS data'_delay with aligned phases; the pseudo-random code detection circuit PRBS Checker is configured to detect the error code in the second pseudo-random code sequence CDR data_delay based on the third pseudo-random code sequence PRBS data'_delay with aligned phases; the error code statistics circuit BER Statistics is configured to statistically calculate the error rate in real time based on the error code detection result of the pseudo-random code detection circuit PRBS Checker. Figure 1 In it, Analog represents the analog circuit part, and Digital represents the digital circuit part.

[0034] As Figure 2 The flowchart of a high-precision serial PRBS generation and error code detection system according to this embodiment is shown. First, PRBS sequences with the same data (but not necessarily the same phase) are output by two pseudo-random code generation circuits (i.e., the first generation circuit PRBS Gen1 and the second pseudo-random code generation circuit PRBS Gen2). One of them recovers data through a clock data recovery circuit CDR, and the other adjusts the phase through a time delay generation circuit PI to reach the same phase as the data recovered by the clock data recovery circuit CDR; then, it enters the pseudo-random code detection circuit PRBS Checker after sampling, thereby realizing error code detection.

[0035] Preferably, after the phase detection circuit PD detects the phase difference between the third pseudo-random code sequence PRBS data' generated by the pseudo-random code second generation circuit PRBS Gen2 and the second pseudo-random code sequence CDR data_delay recovered by the clock data recovery circuit CDR, the digital feedback loop PDC controls the delay generation circuit PI to adjust the delay of the third pseudo-random code sequence PRBS data' generated by the pseudo-random code second generation circuit PRBS Gen2 according to the phase difference, so as to obtain the phase-aligned third pseudo-random code sequence PRBS data'_delay.

[0036] Preferably, as Figure 3 shown is a schematic diagram of a phase detection circuit according to this embodiment. The phase detection circuit PD includes a first D flip-flop, a second D flip-flop, and a third D flip-flop. The clock terminal of the first D flip-flop inputs a sampling clock, the data terminal inputs the third pseudo-random code sequence PRBS data', and the output terminal generates a first data; the clock terminal of the second D flip-flop inputs a sampling clock, the data terminal inputs the first data, and the output terminal generates a second data; the clock terminal of the third D flip-flop inputs an edge sampling clock, the data terminal inputs the third pseudo-random code sequence PRBS data', and the output terminal generates a third data. Among them, the sampling clock input by the first D flip-flop and the second D flip-flop is introduced by the clock recovered by the clock data recovery circuit CDR, that is, the same as the clock used by the second pseudo-random code sequence CDR data_delay; the edge sampling clock input by the third D flip-flop has a 180° phase difference from the sampling clock.

[0037] As Figure 4 shown is a timing diagram of a phase detection circuit according to this embodiment. When the first data is equal to the third data, it indicates that the sampling is advanced; when the second data is equal to the third data, it indicates that the sampling is delayed; the first data, the second data, and the third data are statistically analyzed to obtain phase information, and the phase information is output to the delay generation circuit PI through the digital feedback loop to finally align the data.

[0038] Preferably, the pseudo-random code detection circuit PRBS Checker can be implemented by a high-speed exclusive OR gate.

[0039] As Figure 5 shown is an existing parallel pseudo-random code error detection and statistical circuit based on an asynchronous adder, where Hold represents a shielding signal, CKB represents an error signal, and DFF 0 ~DFF M both represent D flip-flops. Figure 5Among them, the multi-bit counter (i.e., adder) is an asynchronous circuit. During the process of high-speed error counting, real-time data acquisition cannot be achieved. Therefore, it is necessary to cooperate with the digital timing to complete real-time data acquisition, that is, first wait for the backend data to be stable through the shielding signal Hold, and then obtain the data of the asynchronous circuit through sampling. In contrast, as Figure 6 shown is the existing parallel pseudo-random code error detection and statistics circuit based on a carry-lookahead adder. Among them, the 4-bit carry-lookahead adder has exceeded the scale of the 32-bit asynchronous adder. More bits will result in a larger scale and very low cost performance.

[0040] In this embodiment, when the shielding signal Hold input from the external input or generated by timing is input, the error detection and error statistics are paused; after waiting for the digital sampling data, the shielding signal Hold is reset to zero again, and the error statistics continue. This embodiment uses an asynchronous error statistics circuit and the shielding signal Hold, and can transmit real-time error rate information through the corresponding timing, so that the error detection circuit and the error statistics circuit can work in a low-overhead state while obtaining data in real time, that is, small occupied area and low power consumption.

[0041] Preferably, the error statistics circuit includes a logic circuit and an asynchronous counter. The first input end of the logic circuit is connected to the error signal CKB, the second input end is connected to the shielding signal Hold, and the output end is electrically connected to the asynchronous counter, so as to count the error signal CKB. The shielding signal Hold can shield (pause) the error signal CKB from being transmitted to the asynchronous counter. More preferably, as Figure 7 shown is the logic circuit schematic diagram of an error statistics circuit of this embodiment. The logic circuit includes a NOT gate unit and a NOR gate unit. The input end of the NOT gate unit is connected to the error signal CKB, the output end of the NOT gate unit is electrically connected to the first input end of the NOR gate unit, the second input end of the NOR gate unit is connected to the shielding signal Hold, and the output end of the NOR gate unit is electrically connected to the asynchronous counter; the asynchronous counter includes N serially connected D flip-flops in sequence, where N is a positive integer.

[0042] Preferably, the high-precision serial PRBS generation and error detection system of this embodiment further includes a digital register. The signal input end of the digital register is electrically connected to the signal output end of the error statistics circuit, and receives the error rate information transmitted in real time by the error statistics circuit based on the corresponding timing.

[0043] The prerequisite for the error statistics circuit of this embodiment to work properly is that since the shielding signal Hold is needed to suspend the error statistics work, the error information lost during this period cannot affect the final result of the error rate. And the error statistics circuit of this embodiment is a probability statistics circuit, and a small amount of uncounted information does not affect the final result.

[0044] The above are only the preferred embodiments of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be changed within the scope of the concept described herein through the above teachings or the technology or knowledge in the relevant field. Any changes and variations made by those skilled in the art without departing from the spirit and scope of the present invention shall fall within the protection scope of the appended claims of the present invention.

Claims

1. A high-precision serial PRBS generation and error detection system, characterized in that: It includes a first pseudo-random code generating circuit, a second pseudo-random code generating circuit, a clock data recovery circuit, a phase detection circuit, a digital feedback loop, a time delay generating circuit, a pseudo-random code detecting circuit and a bit error statistics circuit, wherein: A first pseudo-random code generating circuit is configured to generate a first pseudo-random code sequence PRBS data, and obtain a second pseudo-random code sequence CDR data_delay after passing through a clock data recovery circuit; The second pseudo-random code generating circuit is configured to generate a third pseudo-random code sequence PRBS data', and detect the phase difference with the second pseudo-random code sequence CDR data_delay through the phase detection circuit, and control the delay generating circuit based on the digital feedback loop to perform delay adjustment on the third pseudo-random code sequence PRBS data' according to the phase difference to obtain a third pseudo-random code sequence PRBS data'_delay after phase alignment; the third pseudo-random code sequence PRBS data' has the same data as the first pseudo-random code sequence PRBS data, and the phase is the same or different; The pseudo-random code detection circuit is configured to detect a bit error in the second pseudo-random code sequence CDR data_delay based on the third pseudo-random code sequence PRBS data'_delay after phase alignment, and record it as a bit error signal; The bit error statistics circuit is configured to calculate the bit error rate in real time based on the bit error detection result of the pseudo-random code detection circuit.

2. A high-precision serial PRBS generation and error detection system according to claim 1, characterized in that: The phase detection circuit comprises a first D flip-flop, a second D flip-flop and a third D flip-flop, wherein a sampling clock is input to a clock terminal of the first D flip-flop, a third pseudo-random code sequence PRBS data' is input to a data terminal, and a first data is generated at an output terminal; The clock terminal of the second D flip-flop inputs a sampling clock, the data terminal inputs first data, and the output terminal generates second data; The clock terminal of the third D flip-flop inputs an edge sampling clock, the data terminal inputs a third pseudo-random code sequence PRBS data', and the output terminal generates third data. The edge sampling clock is 180° apart from the sampling clock in phase.

3. A high-precision serial PRBS generation and error detection system according to claim 2, characterized in that: The sampling clock is introduced by a clock recovered by a clock data recovery circuit, that is, the sampling clock is the same as the clock used by the second pseudo-random code sequence CDR data_delay.

4. A high-precision serial PRBS generation and error detection system according to claim 3, characterized in that: When the first data is equal to the third data, it indicates that the sampling is advanced; when the second data is equal to the third data, it indicates that the sampling is delayed; the first data, the second data and the third data are counted to obtain phase information, and the phase information is output to the delay generation circuit through a digital feedback loop to finally align the data.

5. A high-precision serial PRBS generation and error detection system according to claim 1, characterized in that: When an external input or a timed shielding signal is input, the error detection and error statistics are suspended; after waiting for the digital sampling data, the shielding signal is reset to zero and the error statistics are continued.

6. A high-precision serial PRBS generation and error detection system according to claim 5, characterized in that: The bit error statistics circuit includes a logic circuit and an asynchronous counter. The first input end of the logic circuit is connected to the bit error signal, the second input end is connected to the shielding signal, and the output end is electrically connected to the asynchronous counter, so as to count the bit error signal; the shielding signal can shield the bit error signal from being transmitted to the asynchronous counter.

7. A high-precision serial PRBS generation and error detection system according to claim 6, characterized in that: The logic circuit includes a NOT gate unit and a NOR gate unit, the input end of the NOT gate unit is connected to a bit error signal, the output end of the NOT gate unit is electrically connected to a first input end of the NOR gate unit, the second input end of the NOR gate unit is connected to a shielding signal, and the output end of the NOR gate unit is electrically connected to the asynchronous counter.

8. A high-precision serial PRBS generation and error detection system according to claim 6, characterized in that: The asynchronous counter includes N D flip-flops connected in series one after another, where N is a positive integer.

9. A high-precision serial PRBS generation and error detection system according to claim 1, characterized in that: It also includes a digital register, a signal input end of the digital register is electrically connected to a signal output end of the bit error statistics circuit, and receives bit error rate information transmitted in real time by the bit error statistics circuit based on a corresponding timing.

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