UWB-based extended clock synchronization method, system, device and medium

Abstract

The present invention discloses an extended clock synchronization method, system, device and medium based on UWB, and relates to the field of wireless clock synchronization technology. The method comprises: constructing a crystal oscillator control network based on a UWB module, and based on the principle of signal transmission, obtaining GPS_1PPS received by the main base station, IRQn generated by the slave base station, and Local_1PPS output by the voltage-controlled crystal oscillator; adding the time difference between GPS_1PPS and IRQn, which is the time difference of the synchronization signal, and the time difference between IRQn and Local_1PPS, which is the time difference of the crystal oscillator output, to obtain the control time difference; pre-processing the control time difference to obtain pre-processed time difference data, and calculating it using a conversion formula to obtain a frequency difference; using a voltage step control algorithm and a frequency difference to control the voltage adjustment amount of the voltage-controlled crystal oscillator to complete clock synchronization. The present invention can use wireless transmission technology instead of optical fiber transmission technology to achieve clock synchronization distribution.

Description

Technical Field

[0001] The present invention relates to the technical field of wireless clock synchronization, and in particular to an extended clock synchronization method, system, equipment and medium based on UWB. Background Art

[0002] Wireless clock synchronization is an important part of distributed network research. As early as the 1970s, with the emergence and development of distributed networks, how to maintain the consistency of local clocks between distributed network nodes has become a key area of ​​concern and research in academia and industry.

[0003] The traditional clock synchronization system uses optical fiber transmission to establish a clock synchronization distribution system. In this system, there are often multiple indoor baseband processing units (Building Base band Unite, BBU) in a machine room. When the number of BBU is too large, multiple GPS antennas need to be installed. In this case, the wired clock synchronization system based on optical fiber transmission has two problems: First, the shortage of antenna resources of the base station leads to the restriction of the installation of antennas by the external environment. Many base stations cannot set up and install GPS antennas outdoors, which brings great inconvenience and difficulty to the construction. Second, the numerous GPS line feeders in the base station involve a large scope of engineering, long delivery time, increased costs, and the numerous cables in the machine room lead to difficulties in comprehensive maintenance in the later stage. Summary of the invention

[0004] The purpose of the present invention is to provide a UWB-based extended clock synchronization method, system, device and medium, which can use wireless transmission technology instead of optical fiber transmission technology to achieve clock synchronization distribution.

[0005] To achieve the above object, the present invention provides the following solutions:

[0006] An extended clock synchronization method based on UWB, comprising:

[0007] Constructing a crystal oscillator control network based on a UWB module; the crystal oscillator control network includes: using the UWB module to transmit the second pulse time reference received by the master base station to the signal network of the slave base station in the form of ultra-wideband wireless transmission, and a TDC chip, a single-chip microcomputer, a DAC module, a voltage-controlled crystal oscillator and an FPGA module connected to the signal network in sequence; wherein the FPGA module is also connected to the TDC chip;

[0008] Based on the signal transmission principle of the crystal oscillator control network, GPS_1PPS received by the master base station, IRQn generated by the slave base station, and Local_1PPS output by the voltage-controlled crystal oscillator are obtained;

[0009] The time difference of the timing signal and the time difference of the crystal oscillator output are added to obtain the control time difference; the time difference of the timing signal is the reception delay time difference between the GPS_1PPS and the IRQn; the time difference of the crystal oscillator output is the time difference between the IRQn and the Local_1PPS;

[0010] Preprocessing the control time difference to obtain preprocessed time difference data; the preprocessing is used to filter out signal data with large errors and denoise the filtered signal data;

[0011] Calculate according to the pre-processed time difference data and the conversion formula to obtain the frequency difference;

[0012] The voltage adjustment amount of the voltage-controlled crystal oscillator is controlled by utilizing the voltage step control algorithm and the frequency difference to complete clock synchronization.

[0013] Optionally, the preprocessing adopts Raida's rule and sliding mean filtering.

[0014] Optionally, the conversion formula is expressed as:

[0015]

[0016] Among them, ΔT is the preprocessing time difference data, the unit is ps; Δf is the frequency difference, the unit is Hz.

[0017] Optionally, the voltage step control algorithm uses 10 MHz as the nominal frequency and the calculated frequency difference as the deviation, and controls the change of the voltage of the voltage-controlled crystal oscillator by setting the control value.

[0018] Optionally, the voltage step control algorithm is specifically expressed as:

[0019]

[0020] Among them, ΔU is the control voltage adjustment amount, δ is the step value, and N is the number of steps.

[0021] The present invention also provides an extended clock synchronization system based on UWB, comprising:

[0022] A network construction module is used to construct a crystal oscillator control network based on a UWB module; the crystal oscillator control network includes: a signal network that uses the UWB module to transmit the pulse-per-second time reference received by the master base station to the slave base station in the form of ultra-wideband wireless transmission, and a TDC chip, a single-chip microcomputer, a DAC module, a voltage-controlled crystal oscillator and an FPGA module that are sequentially connected to the signal network; wherein the FPGA module is also connected to the TDC chip;

[0023] A data acquisition module, used to obtain GPS_1PPS received by the master base station, IRQn generated by the slave base station, and Local_1PPS output by the voltage-controlled crystal oscillator based on the signal transmission principle of the crystal oscillator control network;

[0024] A time difference calculation module, used for adding the time difference of the timing signal and the time difference of the crystal oscillator output to obtain the control time difference; the time difference of the timing signal is the reception delay time difference between the GPS_1PPS and the IRQn; the crystal oscillator output time difference is the time difference between the IRQn and the Local_1PPS;

[0025] A preprocessing module, used for preprocessing the control time difference to obtain preprocessed time difference data; the preprocessing is used to filter out signal data with large errors and denoise the filtered signal data;

[0026] A frequency difference calculation module, used to calculate according to the pre-processed time difference data and the conversion formula to obtain the frequency difference;

[0027] The crystal oscillator adjustment amount control module is used to control the voltage adjustment amount of the voltage-controlled crystal oscillator by using the voltage step control algorithm and the frequency difference to complete clock synchronization.

[0028] The present invention also provides an electronic device, including a memory and a processor, wherein the memory is used to store a computer program, and the processor runs the computer program to enable the electronic device to execute the above-mentioned UWB-based extended clock synchronization method.

[0029] The present invention also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the UWB-based extended clock synchronization method as described above.

[0030] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0031] The present invention discloses an extended clock synchronization method, system, device and medium based on UWB, the method includes constructing a crystal oscillator control network based on a UWB module, and based on the principle of signal transmission, obtaining GPS_1PPS received by a main base station, IRQn generated by a slave base station and Local_1PPS output by a voltage-controlled crystal oscillator; adding the time difference between GPS_1PPS and IRQn, which is the time difference of the synchronization signal, and the time difference between IRQn and Local_1PPS, which is the time difference of the crystal oscillator output, to obtain a control time difference; pre-processing the control time difference to obtain pre-processed time difference data, and calculating using a conversion formula to obtain a frequency difference; using a voltage step control algorithm and a frequency difference to control the voltage adjustment amount of the voltage-controlled crystal oscillator to complete clock synchronization. The present invention can use wireless transmission technology instead of optical fiber transmission technology to achieve clock synchronization distribution. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0033] Figure 1 This is a schematic diagram of the crystal oscillator control network structure based on the UWB module of the present invention;

[0034] Figure 2 Schematic diagram of the time difference measured by the TDC measurement module in this embodiment. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] The purpose of the present invention is to provide a UWB-based extended clock synchronization method, system, device and medium, which can use wireless transmission technology instead of optical fiber transmission technology to achieve clock synchronization distribution.

[0037] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] like Figure 1 As shown, the present invention provides an extended clock synchronization method based on UWB, comprising:

[0039] Step 100: constructing a crystal oscillator control network based on a UWB module; the crystal oscillator control network includes: using the UWB module to transmit the pulse-per-second time reference received by the master base station to the signal network of the slave base station in the form of ultra-wideband wireless transmission, and a TDC chip, a single-chip microcomputer, a DAC module, a voltage-controlled crystal oscillator and an FPGA module connected to the signal network in sequence; wherein the FPGA module is also connected to the TDC chip;

[0040] Step 200: Based on the signal transmission principle of the crystal oscillator control network, obtain GPS_1PPS received by the master base station, IRQn generated by the slave base station, and Local_1PPS output by the voltage-controlled crystal oscillator;

[0041] Step 300: Add the timing signal time difference and the crystal oscillator output time difference to obtain the control time difference; the timing signal time difference is the reception delay time difference between the GPS_1PPS and the IRQn; the crystal oscillator output time difference is the time difference between the IRQn and the Local_1PPS;

[0042] Step 400: preprocessing the control time difference to obtain preprocessed time difference data; the preprocessing is used to filter out signal data with gross errors and denoise the filtered signal data;

[0043] Step 500: Calculate according to the pre-processed time difference data and the conversion formula to obtain the frequency difference;

[0044] Step 600: Using the voltage step control algorithm and the frequency difference to control the voltage adjustment amount of the voltage controlled crystal oscillator to complete clock synchronization.

[0045] Based on the above technical solution, the specific implementation methods of each step are provided as shown below.

[0046] Based on theoretical analysis and previous work experience, the algorithm design and structural design of the extended clock synchronization technology based on UWB were carried out, and the design scheme was optimized. The hardware of the present invention is divided into two parts, namely the master base station and the slave base station. The hardware structures of the two parts are basically the same. By writing different programs, the functions of the corresponding master and slave base stations are realized. The hardware composition of the base station includes:

[0047] 1) UWB chip, realizing ultra-wideband communication;

[0048] 2)ARM core main control chip;

[0049] 3) Field Programmable Gate Array (FPGA);

[0050] 4) 38.4MHz crystal oscillator and 10MHz voltage-controlled constant temperature crystal oscillator;

[0051] 5) Time-to-digital converter (TDC);

[0052] 6) Digital-to-analog converter (DAC);

[0053] 7) Clock buffer.

[0054] The UWB chip uses the DW1000 RF chip launched by Decawave. The chip uses a 38.4MHz crystal oscillator, which is multiplied by 13 times through the internal phase-locked loop circuit to get 499.2MHz, and then divided by four to get a 124.8MHz signal as the internal system clock. Therefore, the DW1000 internal timestamp accuracy can reach up to 15.6ps, providing the necessary prerequisite for accurate clock measurement.

[0055] The main control chip is the STM32H750 launched by STMicroelectronics. This chip uses the ARMCortex-M7 core, with a main frequency of up to 480MHz, and has strong computing power and processing speed. This feature makes this chip well suited for high-precision wireless clock synchronization. The H750 chip communicates with the DW1000 through the SPI protocol, thereby realizing its wireless transceiver control and status processing.

[0056] The FPGA module uses the XC7A100T-FGG484 chip launched by Xilinx. This chip is used to generate a high-precision second pulse signal. Since the hardware logic inside the FPGA can be processed in parallel, it can achieve low-latency pulse signal generation and extremely fast response speed. In addition, since the FPGA has a flexible clock management function inside, it can use PLL (phase-locked loop) and other technologies to generate a stable clock signal to ensure the accuracy and stability of the pulse signal.

[0057] The main control chip and FPGA module are driven by a constant temperature crystal oscillator with voltage control function. The short-term frequency accuracy of the crystal oscillator is ≤0.01ppm, the long-term stability voltage control voltage range is 2V±2V, the frequency traction range is greater than or equal to ±0.5ppm, and the voltage control linearity is less than 10%. The high-stability crystal oscillator plays an important role in the main control chip controlling the transmission and reception of the UWB chip and the FPGA generating a highly stable second pulse. The TDC module generates a suitable control quantity by measuring the time interval between the received signal and the local second pulse generated by the FPGA, and adjusts the stability of the voltage-controlled crystal oscillator through the DAC module.

[0058] Based on the above background, the specific technical solution and working principle are as follows:

[0059] After receiving the rising edge of the GPS second pulse signal, namely GPS_1PPS, the main base station immediately starts the UWB sending function and sends a synchronization signal. After receiving the synchronization signal, the slave base station will also send a synchronization signal return frame to the main base station. In this process, an interrupt event will be generated when the slave base station completes the sending of the synchronization signal return frame. Because the time interval between the rising edges of GPS_1PPS is an extremely precise 1s, although there will be a certain delay in the UWB module of the main base station sending the synchronization signal, the sending cycle is also 1s, and the period from the slave base station receiving the signal to completing the sending and generating the interrupt signal is also 1s. In the above process, the process of transmitting GPS_1PPS to the slave base station is realized. In this embodiment, the interrupt signal generated by the slave base station is recorded as IRQn.

[0060] The core of this embodiment is to tame the local 10MHz constant temperature crystal oscillator, and then use the tamed crystal oscillator to generate a highly stable local second pulse signal, recorded as Local_1PPS. The local second pulse signal uses the 10MHz constant temperature crystal oscillator as the clock signal of the FPGA and is generated by the internal timer of the FPGA. When the counter counts to the set rising edge position, the pulse signal is pulled high; when the counter counts to the set falling edge position, the pulse signal is pulled low. Because the pulse signal is a periodic signal, the essence of phase modulation is to adjust the initial phase of the local second pulse signal generated by the divider module.

[0061] Among them, discipline refers to using GPS_1PPS as the benchmark. After the master base station receives the second pulse signal, it immediately starts the DW1000 wireless transmission function to send the synchronization signal; after the slave base station receives the synchronization signal, an interrupt signal IRQn is generated. Through the above process, the wireless transmission of the reference second pulse signal between the master and slave base stations is realized. The frequency of IRQn on the slave base station and GPS_1PPS is 1Hz, but due to the delay in reception, there is a fixed time difference T between the two. D , which is the phase difference. The time difference ΔT between the IRQn signal and the local second pulse signal Local_1PPS is measured by the TDC7201 chip, and then the flight time T D The frequency output and initial phase of the local crystal oscillator are adjusted by the adjustment algorithm to achieve the same frequency and phase between GPS_1PPS and IRQn. The time differences t1 and t2 measured by the TDC measurement module are as follows: Figure 2 shown.

[0062]

[0063] ΔT=t2-t1

[0064] Where ΔT is the time difference, in ps, Δf is the frequency difference, in Hz; T is the time interval, which is 1s in this embodiment, and f is the TDC reference clock frequency, which is 10MHz in this embodiment. After unit conversion, we can get:

[0065]

[0066] Therefore, the time difference data in this system can be converted into frequency difference data through the above formula, and then sent to the DAC module to convert the frequency difference data into voltage adjustment amount, thereby adjusting the output frequency of the local constant temperature crystal oscillator.

[0067] In the above process, the time difference data ΔT and frequency difference Δf (HZ) The accuracy directly affects the accuracy of taming and maintenance, so the preprocessing of time difference data is very important. Therefore, this embodiment adopts the Laida rule and the sliding mean filtering method. The Laida rule is also called the 3δ rule. It takes the 3 times mean of a set of data as the standard. When the next value comes, it will be compared with this 3 times mean. If the value is greater than 3 times the mean, it will be discarded. Otherwise, it will be retained and the data mean will be recalculated. It can be described by the formula: Then X i This is a gross error and should be discarded; if Then X i It is a value within the normal fluctuation range and should be retained. is the arithmetic mean of the data, X i is the new data and is the standard deviation.

[0068] After using the Raida rule to eliminate the gross errors, the sliding mean filter is used to filter out the noise signal. The mean of the first N sampling points is used as the filtering result of the current sampling point, and the calculation formula is:

[0069]

[0070] The sliding mean filter is used to remove the noise in the time difference information. The relationship between the low-pass cutoff frequency and the number of smoothing points is:

[0071]

[0072] In the above formula, y(n) is the output signal sequence, x(n) is the input signal sequence, N is the number of smoothing points, and f c is the number of smoothing points, f s is the signal sampling rate. The filtering effect of the sliding mean filter is greatly affected by the size of the filter window (the number of smoothing points N). If N is too small, the filtering effect will not meet the requirements, and if N is too large, overfitting will occur. After comparing the filtering effects under different N values, the best filtering effect is when N is 64, and the filter window size is also set to 64 in the present invention.

[0073] After the ΔT time difference and Δf frequency difference are processed in the above process, the corresponding voltage adjustment amount can be calculated according to the voltage control sensitivity:

[0074]

[0075] Where K is the voltage control sensitivity, Δf is the frequency difference, and ΔU is the voltage adjustment amount.

[0076] If the DAC is used to directly output the voltage to perform feedback control on the OCXO (oven-controlled crystal oscillator), the instantaneous frequency mutation will lead to poor short-term frequency stability. In order to ensure the stability of the output frequency, the present invention uses a voltage step control algorithm to calibrate the OCXO (oven-controlled crystal oscillator).

[0077] PID control algorithm is the most classic feedback control algorithm, which takes the error signal as the controlled quantity and sets the appropriate K p 、T i and T d Three parameters, the proportion P, differential I, and integral D are summed to get the final control quantity. This feedback control algorithm allows the system output to always follow the input expected value and maintain a high degree of stability.

[0078] The mathematical model of the PID controller is:

[0079]

[0080] In the formula, e(k) is the deviation between the feedback value and the expected value, u(k) is the calculated control quantity, and K p 、T i and T d are proportional coefficient, integral time constant and differential time constant respectively, T c To control the cycle.

[0081] The proportional link can increase the response speed of the control system and act quickly on the output, but it will produce static errors, and a too large proportional coefficient will cause overshoot; the introduction of the integral link can integrate the deviation so that the control amount changes slowly to the expected value and eliminate the static error, but if the integral effect is too strong, it will produce oscillations and reduce the stability of the system. At this time, it is necessary to introduce a differential link, which reflects the changing trend of the deviation and makes advance adjustments based on the trend. In order to ensure a good short-term frequency stability index of the system output signal, the voltage adjustment amount should not be too large. According to the principle of the PID control algorithm, the present invention adopts a voltage step frequency adjustment algorithm, with 10MHz as the nominal frequency and the measured frequency difference as the deviation. By setting an appropriate control value, the control voltage is slowly changed, and the constant temperature crystal oscillator is tamed, which eliminates steady-state errors and reduces overshoot. The calculation formula is:

[0082]

[0083] In the formula, ΔU is the control voltage adjustment, δ is the step value, and N is the number of steps. The calculated N is not necessarily an integer. The actual number of steps is obtained by rounding the calculated N. Since the training is continuous, each rounding error will be adjusted in the next control cycle, so there is no cumulative error.

[0084] Therefore, it can be seen from the above content that the invention of this high-precision UWB wireless time and frequency transmission system realizes high-precision clock synchronization in a non-global navigation satellite system (GNSS) environment, and effectively solves the clock synchronization problem in indoor, underground and signal-restricted environments. By adopting ultra-wideband (UWB) technology, distributed clock synchronization control algorithm and adaptive filtering algorithm, the synchronization accuracy of nanoseconds is ensured, and the master-slave base station clock synchronization within 50ns and the local second pulse accuracy of 10ns are achieved. At the same time, the system supports long-distance transmission, up to 1 km, which enhances its application capability in a wide range. Compared with traditional limited clock synchronization technology, the wireless clock expansion technology based on UWB no longer uses data lines or optical fibers as carriers for data interaction, greatly expands the application scenarios of clock synchronization, and also saves the cumbersome process of layout and wiring, reducing the difficulty of hardware deployment. At the same time, it also greatly improves the scalability and spatial flexibility of the equipment, and reduces the hardware cost and use cost of adding synchronization nodes. For some application scenarios that require a small range of mobile clock nodes or a large number of slave nodes, the present invention has a good application prospect. The application of distributed algorithms improves the robustness and scalability of the system, making it adaptable to wireless network environments with high flexibility and network uncertainty. The system has a wide range of applications in industrial automation, intelligent transportation, the Internet of Things, and smart grids, improving the efficiency and reliability of various industries. In summary, the invention has achieved significant results in multiple levels of technology, application, and education, and has important social value and educational significance.

[0085] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0086] This article uses specific examples to illustrate the principles and implementation methods of the present invention. The above examples are only used to help understand the core idea of ​​the present invention. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A UWB-based extended clock synchronization method, characterized in that: include: Build a crystal oscillator control network based on UWB module; The crystal oscillator control network includes: using a UWB module to transmit the pulse-per-second time reference received by the master base station to a signal network of the slave base station in the form of ultra-wideband wireless transmission, and a TDC chip, a single-chip microcomputer, a DAC module, a voltage-controlled crystal oscillator and an FPGA module connected to the signal network in sequence; wherein the FPGA module is also connected to the TDC chip; Based on the signal transmission principle of the crystal oscillator control network, GPS_1PPS received by the master base station, IRQn generated by the slave base station, and Local_1PPS output by the voltage-controlled crystal oscillator are obtained; The time difference of the timing signal and the time difference of the crystal oscillator output are added to obtain the control time difference; the time difference of the timing signal is the reception delay time difference between the GPS_1PPS and the IRQn; the time difference of the crystal oscillator output is the time difference between the IRQn and the Local_1PPS; Preprocessing the control time difference to obtain preprocessed time difference data; the preprocessing is used to filter out signal data with large errors and denoise the filtered signal data; Calculate according to the pre-processed time difference data and the conversion formula to obtain the frequency difference; The voltage adjustment amount of the voltage-controlled crystal oscillator is controlled by utilizing the voltage step control algorithm and the frequency difference to complete clock synchronization.

2. The UWB-based extended clock synchronization method according to claim 1, characterized in that: The preprocessing adopts Raida's rule and sliding mean filtering.

3. The UWB-based extended clock synchronization method according to claim 1, characterized in that: The conversion formula is expressed as: Among them, ΔT is the preprocessing time difference data, the unit is ps; Δf is the frequency difference, the unit is Hz.

4. The UWB-based extended clock synchronization method according to claim 1, characterized in that: The voltage step control algorithm uses 10 MHz as the nominal frequency and the calculated frequency difference as the deviation, and controls the change of the voltage of the voltage-controlled crystal oscillator by setting the control value.

5. The UWB-based extended clock synchronization method according to claim 1, characterized in that: The control algorithm of the voltage step is specifically expressed as follows: Among them, ΔU is the control voltage adjustment amount, δ is the step value, and N is the number of steps.

6. An extended clock synchronization system based on UWB, characterized in that: include: Network building module, used to build a crystal oscillator control network based on UWB module; The crystal oscillator control network includes: using a UWB module to transmit the pulse-per-second time reference received by the master base station to a signal network of the slave base station in the form of ultra-wideband wireless transmission, and a TDC chip, a single-chip microcomputer, a DAC module, a voltage-controlled crystal oscillator and an FPGA module connected to the signal network in sequence; wherein the FPGA module is also connected to the TDC chip; A data acquisition module is used to obtain GPS_1PPS received by the main base station, IRQn generated by the slave base station, and Local_1PPS output by the voltage-controlled crystal oscillator based on the signal transmission principle of the crystal oscillator control network; A time difference calculation module, used for adding the time difference of the timing signal and the time difference of the crystal oscillator output to obtain the control time difference; the time difference of the timing signal is the reception delay time difference between the GPS_1PPS and the IRQn; the crystal oscillator output time difference is the time difference between the IRQn and the Local_1PPS; A preprocessing module, used for preprocessing the control time difference to obtain preprocessed time difference data; the preprocessing is used to filter out signal data with large errors and denoise the filtered signal data; A frequency difference calculation module, used to calculate according to the pre-processed time difference data and the conversion formula to obtain the frequency difference; The crystal oscillator adjustment amount control module is used to control the voltage adjustment amount of the voltage-controlled crystal oscillator by using the voltage step control algorithm and the frequency difference to complete clock synchronization.

7. An electronic device, characterized in that: The electronic device comprises a memory and a processor, wherein the memory is used to store a computer program, and the processor runs the computer program to enable the electronic device to perform the UWB-based extended clock synchronization method according to any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that: The computer program is stored therein, and when the computer program is executed by a processor, the UWB-based extended clock synchronization method as described in any one of claims 1 to 5 is implemented.

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