Chip System-Level Verification System Based on Python Language

Abstract

The present invention relates to the technical field of chip verification, and in particular to a chip system-level verification system based on the Python language, including: a preset Python script set in a first verification module, and a design under test set in a second verification module; the preset Python script sets the first verification module as the master device party and the second verification module as the slave device party; the first verification module generates a main thread of the Python script, sends a command to start the verification platform simulation thread to the second verification module, starts the verification platform simulation thread, and establishes a connection between the main thread of the Python script and the verification platform simulation thread; the main thread of the Python script controls the first verification module to send a verification request command to the second verification module, and the verification platform simulation thread controls the second verification module to process the verification request command. The present invention simplifies the chip system-level verification process, improves the verification efficiency, and reduces the verification cost.

Description

Technical Field

[0001] The present invention relates to the technical field of chip verification, and particularly to a chip system-level verification system based on the Python language. Background Art

[0002] Chip system-level verification refers to verifying the coordination and cooperation between the Design Under Test (DUT) and software. When performing chip system-level verification using traditional techniques, it is necessary to connect the IP (Intellectual Property) or model of a specific CPU, write relevant software, and compile it using a compiler that supports a specific instruction set. In this traditional process, it is necessary for hardware design engineers, model development engineers, and driver software engineers to cooperate and complete. For some special protocols, it is also necessary to write specific stimulus modules or models. It can be seen that the traditional method of chip system-level verification is difficult, the verification process is complex, the verification efficiency is low, and the personnel input cost is high. Therefore, how to simplify the chip system-level verification process, improve the chip system-level verification efficiency, and reduce the verification cost has become an urgent technical problem to be solved. Summary of the Invention

[0003] The purpose of the present invention is to provide a chip system-level verification system based on the Python language, which simplifies the chip system-level verification process, improves the chip system-level verification efficiency, and reduces the chip system-level verification cost.

[0004] According to one aspect of the present invention, there is provided a chip system-level verification system based on the Python language, including: a first verification module and a second verification module, wherein the first verification module includes a preset Python script, and the second verification module includes the Design Under Test.

[0005] The preset Python script includes a verification process, in which the first verification module is set as the master device party and the second verification module is set as the slave device party.

[0006] The first verification module is used to generate a Python script main thread in the first verification module based on the preset Python script. The Python script main thread sends a start verification platform simulation thread instruction to the second verification module, starts a verification platform simulation thread in the second verification module, and establishes a connection between the Python script main thread and the verification platform simulation thread, thereby establishing a connection between the first verification module and the second verification module.

[0007] The main thread of the Python script controls the first verification module to send a verification request instruction to the second verification module based on a preset Python script, and the verification platform simulation thread controls the second verification module to process the verification request instruction.

[0008] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solution, a chip system-level verification system based on the Python language provided by the present invention can achieve considerable technical progressiveness and practicality, and has wide utilization value in the industry. It has at least the following beneficial effects:

[0009] The system of the present invention constructs a verification process based on a Python script, sets the preset Python script side as the master device party, sets the device under test side as the slave device party, simulates the host behavior based on the preset Python script, realizes the chip system-level verification process based on the verification process in the preset Python script, simplifies the chip system-level verification process, improves the chip system-level verification efficiency, and reduces the chip system-level verification cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0011] Figure 1 Schematic diagram of a chip system-level verification system based on the Python language provided by an embodiment of the present invention;

[0012] Figure 2 Schematic diagram of the communication process between the main thread of the Python script and the verification platform simulation thread provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0013] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0014] An embodiment of the present invention provides a chip system-level verification system based on the Python language, as Figure 1As shown in the figure, it includes: a first verification module and a second verification module. Among them, the first verification module includes a preset Python script, and the second verification module includes the design under test. The preset Python script includes a verification process. In the verification process, the first verification module is set as the master device party, and the second verification module is set as the slave device party.

[0015] The first verification module is used to generate a Python script main thread in the first verification module based on the preset Python script. The Python script main thread sends a start verification platform simulation thread instruction to the second verification module, starts a verification platform simulation thread in the second verification module, and establishes a connection between the Python script main thread and the verification platform simulation thread, thereby establishing a connection between the first verification module and the second verification module. The Python script main thread controls the first verification module to send a verification request instruction to the second verification module based on the preset Python script, and the verification platform simulation thread controls the second verification module to process the verification request instruction. The communication process between the Python script main thread and the verification platform simulation thread is as Figure 2 shown, and the verification request instruction includes an interrupt request instruction and / or a read / write register request instruction.

[0016] It should be noted that in the prior art, it is usually necessary to obtain a log file to determine whether the simulation platform has successfully completed the simulation. In this application, the simulation platform can automatically determine the success and failure of the simulation. As an embodiment, if all the verification processes in the preset Python script are completed, the Python script main thread calls a preset simulation end function to send a verification success instruction to the second verification module. The second verification module ends the simulation based on the verification success instruction and sets the verification flag to the verification success flag. If a verification failure occurs during the execution of the verification process of the preset Python script, the Python script main thread calls a preset simulation end function to send a verification failure instruction to the second verification module. The second verification module ends the simulation based on the verification failure instruction and sets the verification flag to the verification failure flag.

[0017] As an embodiment, the first verification module further includes a first verification control unit and a second verification control unit. Among them, the first verification control unit is implemented based on Python, and the second verification control unit is implemented based on C++. It can be understood that both Python and C++ are existing programming languages and will not be elaborated here. The main thread of the Python script controls the first verification control unit to obtain instruction parameters from the preset Python script, and generates a verification request instruction through the interaction between the first verification control unit and the second verification control unit, and sends the verification request instruction to the second verification module through the second verification control unit.

[0018] As an embodiment, the second verification control unit includes a C++ function, and the C++ function includes an Application Programming Interface (API) function generated based on C++. The first verification control unit encapsulates the C++ function into a Python function through mixed programming of C++ and Python to realize the interaction between the first verification control unit and the second verification control unit. Among them, the first verification module includes a mixed programming library, and the first verification control unit realizes the mixed programming of C++ and Python based on the mixed programming library. The mixed programming library is developed and generated based on ctypes or the native C++ library of Python. Among them, ctypes is an external function library of Python, which provides data types compatible with the C language and allows calling functions in Dynamic Link Library (DLL) files or shared libraries. These libraries can be encapsulated in pure Python form using ctypes. The native C++ library of Python is also an existing library and will not be elaborated here.

[0019] As an embodiment, the main thread of the Python script generates M main device channels in the first verification module based on the preset Python script. The M main device channels include one main device interrupt service channel and (M - 1) main device read / write service channels. It should be noted that the first verification module generates an interrupt to the device in the DUT based on one main device interrupt service channel. The preset Python script can simulate multiple main devices, and each main device corresponds to a main device channel, which is used to simulate multiple main devices to send stimuli to the DUT.

[0020] The slave device side will also set a corresponding number of slave device channels, and the number of master device channels is determined based on the number of slave device channels corresponding to the device under test. As an embodiment, the verification platform simulation thread is used to correspondingly generate M slave device channels in the second verification module. The M slave device channels include one slave device interrupt service channel and (M - 1) slave device read / write service channels. The master device interrupt service channel corresponds to the slave device interrupt service channel, and each master device read / write service channel corresponds to one slave device read / write service channel.

[0021] At the end of the simulation, all channels on the master device side and the slave device side need to be closed. As an embodiment, when the main thread of the python script calls a preset simulation end function to send a verification success instruction or a verification failure instruction to the second verification module, it also sends a channel close instruction to the M master device channels to close the M master device channels. After the second verification module receives the verification success instruction or the verification failure instruction, it closes the M slave device channels. After the master device channels and the slave device channels are closed, the connection between the first verification module and the second verification module is disconnected, and the chip system verification ends.

[0022] As Figure 1 shown in the example, the second verification module further includes a verification model. The system establishes a connection between the second verification control unit and the verification model to establish a connection between the main thread of the python script and the verification platform simulation thread. The second verification control unit communicates with the verification model through a communication interface such as TCP / IP. Among them, TCP / IP is an existing communication method and will not be elaborated here. The verification platform simulation thread controls the verification model to receive the verification request instruction sent by the second verification control unit and forwards it to the design under test. It should be noted that the verification model is usually written and generated based on SystemC and / or C++ languages. The second verification control unit includes C++ functions and can directly communicate with the verification model. The second verification control unit and the first verification control unit communicate based on a hybrid programming library, so that the verification model indirectly communicates with the first verification control unit.

[0023] In the embodiment of the present invention, the preset python script can be used to initiate excitation transmission to the design under test and initiate simulation tests of interrupts. The excitation transmission can specifically include data transmission, register read / write operations, etc.

[0024] As an embodiment, the verification request instruction includes an interrupt request instruction and / or a read / write register request instruction. The interrupt request instruction includes an interrupt number and a slave device interrupt service channel. The read request instruction includes a slave device read / write service channel identifier and a target read address. The write request instruction includes a slave device read / write service channel identifier, a target write address, and target write data. The verification model forwards the interrupt request instruction to the design under test through the slave device interrupt service channel. The verification model forwards the verification request instruction to the design under test through the corresponding slave device channel based on the slave device read / write service channel identifier.

[0025] As an embodiment, the design under test includes a preset interrupt service function and a read / write service function. The design under test invokes the corresponding interrupt service function or read / write service function based on the verification request instruction to process the verification request instruction.

[0026] Specifically, for an interrupt request, the design under test obtains the corresponding interrupt number based on the received interrupt request, and then invokes the corresponding interrupt service function based on the interrupt number to perform an interrupt operation.

[0027] For a read register request instruction, the design under test parses the slave device read / write service channel identifier and the target read address based on the received read register request instruction, and then reads data from the corresponding target read address through the corresponding slave device channel and returns it to the first verification module.

[0028] For a write register request instruction, the design under test parses the slave device read / write service channel identifier, the target write address, and the target write data based on the received write register request instruction, and then writes the target write data to the target write address through the corresponding slave device channel. After the write is successful, it returns a confirmation of successful write message to the first verification module.

[0029] The design under test can be a design generated based on RTL or a design model generated based on SystemC. If the design under test is a design model generated based on SystemC, the verification model communicates with the design under test through a SystemC interface or a Transaction Level Modeling (TLM) interface. If the design under test is a design model generated based on RTL, the verification model communicates with the design under test through a Direct Programming Interface (DPI) or a Device-Kernel Interface (DKI). It should be noted that the SystemC interface, the TLM interface, the DPI interface, and the DKI interface are all existing communication interfaces and will not be described in detail here.

[0030] The system described in the present invention can quickly construct system-level test stimuli with a complexity equivalent to that of a driver based on Python scripts, and can use the Python language to extend the complexity of the stimuli, such as constructing data packets for various high-speed bus interface protocols to communicate with the DUT.

[0031] The above are only the preferred embodiments of the present invention, and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to the above-disclosed technical content to obtain equivalent embodiments with equivalent changes within the scope of the technical solution of the present invention. However, as long as the content does not depart from the technical solution of the present invention, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A chip system-level verification system based on the Python language It is characterized in that it includes: a first verification module and a second verification module, wherein the first verification module includes a preset Python script, and the second verification module includes a design under test; the preset Python script includes a verification process, in which the first verification module is set as the master device party and the second verification module is set as the slave device party in the verification process; the first verification module is used to generate a Python script main thread in the first verification module based on the preset Python script. The Python script main thread sends a start verification platform simulation thread instruction to the second verification module, starts a verification platform simulation thread in the second verification module, and establishes a connection between the Python script main thread and the verification platform simulation thread, thereby establishing a connection between the first verification module and the second verification module; the Python script main thread controls the first verification module to send a verification request instruction to the second verification module based on the preset Python script, and the verification platform simulation thread controls the second verification module to process the verification request instruction; if all the verification processes in the preset Python script are completed, the Python script main thread calls a preset simulation end function to send a verification success instruction to the second verification module. The second verification module ends the simulation based on the verification success instruction and sets the verification flag to a verification success flag; if a verification failure occurs during the execution of the verification process of the preset Python script, the Python script main thread calls a preset simulation end function to send a verification failure instruction to the second verification module. The second verification module ends the simulation based on the verification failure instruction and sets the verification flag to a verification failure flag.

2. The system according to claim 1, characterized in that the first verification module further includes a first verification control unit and a second verification control unit, wherein the first verification control unit is implemented based on Python, and the second verification control unit is implemented based on C++; the Python script main thread controls the first verification control unit to obtain instruction parameters from the preset Python script, and interacts with the second verification control unit through the first verification control unit to generate a verification request instruction, and sends the verification request instruction to the second verification module through the second verification control unit.

3. The system according to claim 2, characterized in that the second verification control unit includes a C++ function, and the first verification control unit encapsulates the C++ function into a Python function through mixed programming of C++ and Python to realize the interaction between the first verification control unit and the second verification control unit.

4. The system according to claim 3, characterized in that The first verification module includes a hybrid programming library. The first verification control unit implements hybrid programming of C++ and Python based on the hybrid programming library, and the hybrid programming library is developed and generated based on ctypes or the Python native C++ library.

5. The system according to claim 2, wherein The second verification module further includes a verification model. The system establishes a connection between the second verification control unit and the verification model, thereby establishing a connection between the main thread of the Python script and the verification platform simulation thread. The verification platform simulation thread controls the verification model to receive the verification request instruction sent by the second verification control unit and forwards it to the design under test.

6. The system according to claim 5, wherein The second verification control unit communicates with the verification model through a TCP / IP communication interface.

7. The system according to claim 5, wherein If the design under test is a design generated based on RTL, the verification model communicates with the design under test through a DPI interface or a DKI interface; If the design under test is a design model generated based on SystemC, the verification model communicates with the design under test through a SystemC interface or a TLM interface.

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