A pixel driving circuit, display device and driving method

Abstract

The present disclosure relates to the technical field of display, and discloses a pixel driving circuit, a display device and a driving method. The pixel driving circuit comprises: a first node coupled with a first electrode of a first driving transistor, a first electrode of a second driving transistor coupled with the first node, a data writing sub-circuit coupled with the first node, a first data voltage or a second data voltage of a data signal end input into the first node, a gate of the first driving transistor and a gate of the second driving transistor coupled with a gate control sub-circuit, the first data voltage input into the gate of the first driving transistor, or the second data voltage input into the gate of the second driving transistor, and a light emitting control sub-circuit providing a first driving current generated by the first driving transistor to a light emitting device, or providing a second driving current generated by the second driving transistor to the light emitting device, so as to meet the display requirement of the light emitting device while effectively reducing the backplane power consumption in the display process.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology and provides a pixel driving circuit, a display device, and a driving method. Background Art

[0002] Micro LEDs offer high resolution, low power consumption, high brightness, high contrast, high color saturation, fast response, thinness, and long life, making them a clear advantage in outdoor ultra-large screen displays. They offer advantages over existing OLED technology, including higher brightness, better luminous efficiency, and lower power consumption. However, during display, Micro LEDs require a high drive current, typically more than 100 times greater than OLEDs. This results in higher cross-voltage and higher backplane power consumption. Summary of the Invention

[0003] Embodiments of the present disclosure provide a pixel driving circuit, a display device, and a driving method for reducing backplane power consumption during a display process.

[0004] The specific technical solutions provided by this disclosure are as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a pixel driving circuit, comprising: a first driving transistor, a second driving transistor, a light-emitting device, a data writing subcircuit, a gating control subcircuit, and a light-emitting control subcircuit;

[0006] The first electrode of the first driving transistor is coupled to the first node and is configured to generate a first driving current according to the first data voltage;

[0007] A first electrode of the second driving transistor is coupled to the first node and configured to generate a second driving current according to a second data voltage;

[0008] The data writing sub-circuit is coupled to the first node and configured to input the first data voltage or the second data voltage of the data signal terminal into the first node in response to the signal of the scan signal terminal;

[0009] The gating control subcircuit is coupled to the gate of the first driving transistor and the gate of the second driving transistor, and is configured to input the first data voltage input to the first node into the gate of the first driving transistor, or input the second data voltage input to the first node into the gate of the second driving transistor in response to a signal from the gating control terminal;

[0010] The second electrode of the first driving transistor and the second electrode of the second driving transistor are coupled to the light-emitting device through a light-emitting control subcircuit, and the light-emitting control subcircuit is configured to provide the first driving current generated by the first driving transistor to the light-emitting device, or to provide the second driving current generated by the second driving transistor to the light-emitting device.

[0011] Optionally, the grayscale corresponding to the first data voltage is greater than the grayscale corresponding to the second data voltage.

[0012] Optionally, a width-to-length ratio of a channel of the first driving transistor is greater than a width-to-length ratio of a channel of the second driving transistor.

[0013] Optionally, the gating control subcircuit includes a first switching transistor, a second switching transistor and a third switching transistor;

[0014] The control terminal of the first switch transistor is coupled to the control terminal of the second switch transistor, the first terminal of the first switch transistor is coupled to the control terminal of the second driving transistor, and the second terminal of the first switch transistor is coupled to the second terminal of the second switch transistor;

[0015] A first terminal of the second switch transistor is coupled to the control terminal of the first driving transistor;

[0016] The control terminal of the third switch transistor is coupled to the scan signal terminal, the first terminal of the third switch transistor is coupled to the control terminal of the first switch transistor, and the second terminal of the third switch transistor is coupled to the gate control terminal;

[0017] The first switch transistor is of P type and the second switch transistor is of N type; or the first switch transistor is of N type and the second switch transistor is of P type.

[0018] Optionally, the data writing sub-circuit includes a fourth switching transistor;

[0019] The control terminal of the fourth switch transistor is coupled to the scan signal terminal, the first terminal of the fourth switch transistor is coupled to the data signal terminal, and the second terminal of the fourth switch transistor is coupled to the first terminal of the first driving transistor.

[0020] Optionally, the light emitting control subcircuit includes a fifth switching transistor;

[0021] The control terminal of the fifth switch transistor is coupled to the gate control terminal, the first terminal of the fifth switch transistor is coupled to the second terminal of the second driving transistor, and the second terminal of the fifth switch transistor is coupled to the light emitting device.

[0022] Optionally, a reset control subcircuit is further included;

[0023] The reset control subcircuit is coupled to the gate control subcircuit and is configured to reset the gates of the first driving transistor and the second driving transistor.

[0024] Optionally, the reset control subcircuit includes a sixth switching transistor, a seventh switching transistor and an eighth switching transistor;

[0025] The control terminal of the sixth switch transistor is coupled to the control terminal of the seventh switch transistor, the first terminal of the sixth switch transistor is coupled to the control terminal of the second driving transistor, and the second terminal of the sixth switch transistor is coupled to the initialization signal terminal;

[0026] A first terminal of the seventh switch transistor is coupled to the control terminal of the first driving transistor, and a second terminal of the seventh switch transistor is coupled to the initialization signal terminal;

[0027] The control terminal of the eighth switch transistor is coupled to the reset signal terminal, the first terminal of the eighth switch transistor is coupled to the gate control terminal, and the second terminal of the eighth switch transistor is coupled to the control terminal of the sixth switch transistor;

[0028] Among them, the type of the sixth switch transistor is P-type and the type of the seventh switch transistor is N-type; or, the type of the sixth switch transistor is N-type and the type of the seventh switch transistor is P-type, and the polarity of the first switch transistor and the sixth switch transistor is the same, and the polarity of the second switch transistor and the seventh switch transistor is the same.

[0029] Optionally, it further comprises: a ninth switch transistor, a first capacitor and a second capacitor;

[0030] The control terminal of the ninth switch transistor is coupled to the gate control terminal, the first terminal of the ninth switch transistor is coupled to the first power supply terminal, and the second terminal of the ninth switch transistor is coupled to the first terminal of the first driving transistor;

[0031] A first terminal of the first capacitor is coupled to the first power supply terminal, and a second terminal of the first capacitor is coupled to the control terminal of the first driving transistor;

[0032] A first terminal of the second capacitor is coupled to the first power terminal, and a second terminal of the second capacitor is coupled to the control terminal of the second driving transistor.

[0033] In a second aspect, an embodiment of the present disclosure further provides a display device comprising any one of the above-mentioned pixel driving circuits.

[0034] In a third aspect, an embodiment of the present disclosure further provides a driving method of any of the above pixel driving circuits, including:

[0035] The data writing sub-circuit inputs the first data voltage or the second data voltage of the data signal terminal into the first node in response to the signal of the scan signal terminal;

[0036] The strobe control subcircuit inputs the first data voltage input to the first node into the gate of the first driving transistor, or inputs the second data voltage input to the first node into the gate of the second driving transistor in response to the signal of the strobe control terminal;

[0037] The first driving transistor generates a first driving current according to the first data voltage, and the light-emitting control subcircuit provides the first driving current generated by the first driving transistor to the light-emitting device; or, the second driving transistor generates a second driving current according to the second data voltage, and the light-emitting control subcircuit provides the second driving current generated by the second driving transistor to the light-emitting device.

[0038] The beneficial effects of the present disclosure are as follows:

[0039] In summary, the present disclosure provides a pixel driving circuit, a display device, and a driving method. The pixel driving circuit includes: a first driving transistor, a second driving transistor, a light-emitting device, a data writing sub-circuit, a gating control sub-circuit, and a light-emitting control sub-circuit. During implementation, the first electrode of the first driving transistor is coupled to the first node and is configured to generate a first driving current according to a first data voltage. The first electrode of the second driving transistor is coupled to the first node and is configured to generate a second driving current according to a second data voltage. The data writing sub-circuit is coupled to the first node and is configured to input the first data voltage or the second data voltage of the data signal terminal into the first node in response to a signal of the scan signal terminal. The gating control sub-circuit is coupled to the gate of the first driving transistor and the gate of the second driving transistor and is configured to generate a second driving current in response to a signal of the gating control sub-circuit. The signal of the control terminal is inputted into the first data voltage of the first node and inputted into the gate of the first driving transistor, or the second data voltage of the first node is inputted into the gate of the second driving transistor, the second electrode of the first driving transistor and the second electrode of the second driving transistor are coupled to the light-emitting device through the light-emitting control sub-circuit, and the light-emitting control sub-circuit is configured to provide the first driving current generated by the first driving transistor to the light-emitting device, or provide the second driving current generated by the second driving transistor to the light-emitting device. The above arrangement realizes the time-sharing conduction of the first driving transistor and the second driving transistor, that is, the first driving transistor is enabled when the light-emitting device requires a small current display, and the second driving transistor is enabled when the light-emitting device requires a large current display. In this way, while meeting the display requirements of the light-emitting device, the backplane power consumption during the display process is effectively reduced.

[0040] Other features and advantages of the present disclosure will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present disclosure. The purposes and other advantages of the present disclosure can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0042] Figure 1 A connection diagram of a pixel driving circuit in the related art;

[0043] Figure 2 A timing diagram of a pixel driving circuit in the related art;

[0044] Figure 3 This is a connection diagram of a pixel driving circuit according to an embodiment of the present disclosure;

[0045] Figure 4 is a circuit connection diagram of a pixel driving circuit in an embodiment of the present disclosure;

[0046] Figure 5 is a connection diagram of another pixel driving circuit in an embodiment of the present disclosure;

[0047] Figure 6 is a circuit connection diagram of another pixel driving circuit in an embodiment of the present disclosure;

[0048] Figure 7 1 is a timing diagram of a pixel driving circuit in an embodiment of the present disclosure;

[0049] Figure 8 The figure is a flowchart of a driving method of a pixel driving circuit in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the technical solutions of the present disclosure, but not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments described in this disclosure without making any creative efforts shall fall within the scope of protection of the technical solutions of the present disclosure.

[0051] The terms "first," "second," and the like in the description and claims of the present invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, such that the embodiments of the present invention described herein can be practiced using orders other than those illustrated or described herein.

[0052] Micro LED displays offer higher brightness, better luminous efficiency, and lower power consumption. However, the high drive current required during display leads to higher voltage across the Micro LED and higher power consumption on the backplane.

[0053] See Figure 1 As shown, Figure 1The pixel circuit shown in FIG. Figure 1 The transistor M03 is a driving transistor. In order to make the light-emitting device L1 emit light during the display process, a large current must pass through the driving transistor M03, the transistor M04 and the transistor M06. In particular, the breakdown voltage Vds of the driving transistor M03 at different brightness levels is between 0V and 5V. The voltage fluctuation range is large, resulting in a corresponding large power consumption of the backplane.

[0054] above Figure 1 The working timing of the pixel circuit shown mainly includes three stages: t1, t2 and t3. Figure 2 The timing shown is described in detail below Figure 1 The working process of the pixel circuit shown.

[0055] Phase t1: The low level of the reset signal terminal Rset turns on the transistors M01 and M07, the high levels of the scan signal terminal Gate and the control signal terminal EM turn off the transistors M02, M04, M5 and M06, and the transistor M01 turns on, thereby resetting the gate of the driving transistor M03. The transistor M07 turns on, thereby resetting the anode of the light-emitting device L1.

[0056] Phase t2: The high level of the reset signal terminal Rset and the enable control terminal EM turns off the transistors M01, M07, M04 and M06, and the low level of the scan signal terminal Gate turns on the transistors M5, M03 and M02. The data of the data signal terminal Data is written to the gate of the driving transistor M03.

[0057] Phase t3: The low level of the control signal terminal EM turns on the transistors M04 and M06, and the high levels of the reset signal terminal Rset and the scan signal terminal Gate turn off the transistors M01, M02, M5 and M07, and the light-emitting device L1 emits light.

[0058] As can be seen from the above process, regardless of whether the current required by the light-emitting device L1 is large or small, the driving transistor M03 must be turned on and provide the data at the data signal terminal Data to the light-emitting device L1. During implementation, in order to meet all current requirements of the light-emitting device L1 (especially the high current requirement), the width-to-length ratio of the driving transistor M03 must be set to a large value. Obviously, when the current required by the light-emitting device L1 is small, the power consumption of the driving transistor M03 will be large, which means that to a certain extent, the power consumption of the backplane will be wasted.

[0059] The preferred embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0060] See Figure 3As shown, a pixel driving circuit proposed in an embodiment of the present application includes: a first driving transistor DT1, a second driving transistor DT2, a light-emitting device L1, a data writing sub-circuit 10, a gating control sub-circuit 20 and a light-emitting control sub-circuit 30.

[0061] A first electrode of the first driving transistor DT1 is coupled to the first node N1 and is configured to generate a first driving current according to a first data voltage.

[0062] A first electrode of the second driving transistor DT2 is coupled to the first node N1 and is configured to generate a second driving current according to the second data voltage.

[0063] It should be noted that, in the embodiment of the present application, the grayscale corresponding to the first data voltage is greater than the grayscale corresponding to the second data voltage.

[0064] During implementation, when the first driving transistor DT1 generates a first driving current according to the first data voltage, the first driving current acts on the light-emitting device L1, which makes the brightness of the light-emitting device L1 higher; when the second driving transistor DT2 generates a second driving current according to the second data voltage, the second driving current acts on the light-emitting device L1, which makes the brightness of the light-emitting device L1 lower.

[0065] In order to meet the requirement that the first data voltage and the second data voltage correspond to different grayscales, the width-to-length ratio of the channel of the first driving transistor DT1 is greater than the width-to-length ratio of the channel of the second driving transistor DT2 .

[0066] In the embodiment of the present application, when displaying at a high grayscale, the width-to-length ratio of the channel of the first driving transistor DT1 is set to be larger, for example, W / L=100um / 10um, to meet the needs of high current driving. When displaying at a low grayscale, the width-to-length ratio of the channel of the first driving transistor DT1 is set to be larger, for example, W / L=10um / 10um, to meet the needs of low current driving.

[0067] The data writing sub-circuit 10 is coupled to the first node N1 and is configured to input the first data voltage or the second data voltage of the data signal terminal into the first node N1 in response to the signal of the scan signal terminal.

[0068] During implementation, the data writing sub-circuit 10 is used to input the first data voltage or the second data voltage of the data signal end into the first node N1, and the first data voltage or the second data voltage reaches the first driving transistor DT1 or the second driving transistor DT2 through the above-mentioned first node N1 to generate a first driving current or a second driving current provided to the light-emitting device L1.

[0069] For example, see Figure 4As shown, the data writing sub-circuit 10 includes a fourth switch transistor M4.

[0070] The connection relationship between the fourth switch transistor M4 and other components is: the control end of the fourth switch transistor M4 is coupled to the scan signal end, the first end of the fourth switch transistor M4 is coupled to the data signal end, and the second end of the fourth switch transistor M4 is coupled to the first end of the first driving transistor DT1.

[0071] During implementation, when the scan signal terminal Gate is at a low level, the fourth switch transistor M4 is turned on, and the signal at the data signal terminal reaches the first node N1 through the fourth switch transistor M4.

[0072] The above-mentioned selection control sub-circuit 20 is coupled to the gate of the first driving transistor DT1 and the gate of the second driving transistor DT2, and is configured to input the first data voltage input to the first node N1 into the gate of the first driving transistor DT1, or input the second data voltage input to the first node N1 into the gate of the second driving transistor DT2 in response to the signal of the selection control terminal.

[0073] During implementation, the strobe control subcircuit 20 is used to control the input of a corresponding data voltage into the first drive transistor DT1 or the second drive transistor DT2. Typically, the signal at the strobe control terminal is input from an external circuit. For example, an external control chip IC pre-determines the voltage value of the data signal terminal Data and generates corresponding high and low level signals, and sends the high level signal corresponding to the larger voltage value or the low level signal corresponding to the smaller voltage value to the strobe control terminal.

[0074] Furthermore, the gate control subcircuit 20 inputs the first data voltage input to the first node N1 to the gate of the first driving transistor DT1 when the signal at the gate control terminal is at a high level. The gate control subcircuit 20 inputs the second data voltage input to the first node N1 to the gate of the second driving transistor DT2 when the signal at the gate control terminal is at a low level.

[0075] For example, see Figure 4 As shown, the gating control sub-circuit 20 includes a first switching transistor M1, a second switching transistor M2 and a third switching transistor M3.

[0076] The connection relationship between the first switch transistor M1 and other components is as follows: the control end of the first switch transistor M1 is coupled to the control end of the second switch transistor M2, the first end of the first switch transistor M1 is coupled to the control end of the second driving transistor DT2, and the second end of the first switch transistor M1 is coupled to the second end of the second switch transistor M2.

[0077] During implementation, when the signal of the selection control terminal is at a low level, the first switch transistor M1 is turned on, and the second data voltage input to the first node N1 is input to the gate of the second driving transistor DT2 via the turned-on second driving transistor DT2 and the first switch transistor M1.

[0078] Since the control terminal of the first switch transistor M1 is coupled to the control terminal of the second switch transistor M2 , when the first switch transistor M1 is turned on, the second switch transistor M2 is turned off.

[0079] The connection relationship between the second switch transistor M2 and other components is as follows: the first end of the second switch transistor M2 is coupled to the control end of the first driving transistor DT1 .

[0080] During implementation, when the signal of the selection control terminal is at a high level, the second switch transistor M2 is turned on, and the first data voltage input to the first node N1 is input to the gate of the first driving transistor DT1 through the turned-on first driving transistor DT1 and the first switch transistor M1.

[0081] The connection relationship between the third switch transistor M3 and other components is as follows: the control end of the third switch transistor M3 is coupled to the scan signal end, the first end of the third switch transistor M3 is coupled to the control end of the first switch transistor M1, and the second end of the third switch transistor M3 is coupled to the selection control end.

[0082] During implementation, when the signal at the scan signal end is at a high level, the third switch transistor M3 is turned on, and the signal at the selection control end is transmitted to the first switch transistor M1 and the second switch transistor M2 through the turned-on third switch transistor M3 to control the first switch transistor M1 or the second switch transistor M2 to be turned on.

[0083] It should be noted that, in order to achieve time-sharing conduction of the first drive transistor DT1 and the second drive transistor DT2, in the embodiment of the present application, the first switch transistor M1 is of P-type and the second switch transistor M2 is of N-type. Alternatively, the first switch transistor M1 is of N-type and the second switch transistor M2 is of P-type, that is, the same signal at the gate control terminal can only turn on one of the first switch transistor M1 and the second switch transistor M2, and thus turn on one of the first drive transistor DT1 and the second drive transistor DT2.

[0084] The second electrode of the first driving transistor DT1 and the second electrode of the second driving transistor DT2 are coupled to the light-emitting device L1 through the light-emitting control subcircuit 30. The light-emitting control subcircuit 30 is configured to provide the first driving current generated by the first driving transistor DT1 to the light-emitting device L1, or to provide the second driving current generated by the second driving transistor DT2 to the light-emitting device L1.

[0085] During the implementation process, after the first driving transistor DT1 and the second driving transistor DT2 generate corresponding driving currents, the above driving currents will continue to be transmitted to the light-emitting control sub-circuit 30, and the above driving currents will be transmitted to the light-emitting device L1 via the light-emitting control sub-circuit 30, that is, the light-emitting control sub-circuit 30 provides the first driving current generated by the first driving transistor DT1 to the light-emitting device L1, or provides the second driving current generated by the second driving transistor DT2 to the light-emitting device L1.

[0086] For example, see Figure 4 As shown, the light emitting control sub-circuit 30 includes a fifth switching transistor M5.

[0087] The connection relationship between the fifth switch transistor M5 and other components is: the control end of the fifth switch transistor M5 is coupled to the selection control end, the first end of the fifth switch transistor M5 is coupled to the second end of the second driving transistor DT2, and the second end of the fifth switch transistor M5 is coupled to the light-emitting device L1.

[0088] During implementation, when the strobe control terminal is at a low level, the fifth switch transistor M5 is turned on, and the fifth switch transistor M5 provides the first drive current or the second drive current to the light emitting device L1.

[0089] In addition, see Figure 5 As shown, the pixel driving circuit in the embodiment of the present application further includes a reset control subcircuit 40 .

[0090] The reset control sub-circuit 40 is coupled to the gate control sub-circuit 20 and is configured to reset the gates of the first driving transistor DT1 and the second driving transistor DT2 .

[0091] In order to realize the on-off control of the light emitting device L1 , the gates of the first driving transistor DT1 and the second driving transistor DT2 are reset by the reset control circuit.

[0092] For example, see Figure 6 As shown, the reset control sub-circuit 40 includes a sixth switch transistor M6, a seventh switch transistor M7 and an eighth switch transistor M8.

[0093] The connection relationship between the sixth switch transistor M6 and other components is as follows: the control end of the sixth switch transistor M6 is coupled to the control end of the seventh switch transistor M7, the first end of the sixth switch transistor M6 is coupled to the control end of the second driving transistor DT2, and the second end of the sixth switch transistor M6 is coupled to the initialization signal end.

[0094] The connection relationship between the seventh switch transistor M7 and other components is as follows: a first terminal of the seventh switch transistor M7 is coupled to the control terminal of the first driving transistor DT1 , and a second terminal of the seventh switch transistor M7 is coupled to the initialization signal terminal.

[0095] The connection relationship between the eighth switch transistor M8 and other components is: the control end of the eighth switch transistor M8 is coupled to the reset signal end, the first end of the eighth switch transistor M8 is coupled to the selection control end, and the second end of the eighth switch transistor M8 is coupled to the control end of the sixth switch transistor M6.

[0096] The sixth switch transistor M6 is of P-type, and the seventh switch transistor M7 is of N-type. Alternatively, the sixth switch transistor M6 is of N-type, and the seventh switch transistor M7 is of P-type, and the first switch transistor M1 and the sixth switch transistor M6 have the same polarity, and the second switch transistor M2 and the seventh switch transistor M7 have the same polarity.

[0097] During implementation, when the reset signal terminal is at a low level, the eighth switch transistor M8 is turned on, and the signal at the selection control terminal reaches the control terminal of the sixth switch transistor M6 and the control terminal of the seventh switch transistor M7 through the turned-on eighth switch transistor M8.

[0098] Since the sixth switch transistor M6 and the seventh switch transistor M7 are of different types, as shown in the figure, when the signal of the selection control terminal is a low-level signal, the sixth switch transistor M6 is turned on; when the signal of the selection control terminal is a high-level signal, the seventh switch transistor M7 is turned on, and the signal of the initialization signal terminal reaches the gate of the second drive transistor DT2 through the turned-on sixth switch transistor M6, thereby resetting the gate of the second drive transistor DT2, or the signal of the initialization signal terminal reaches the gate of the first drive transistor DT1 through the turned-on seventh switch transistor M7, thereby resetting the gate of the first drive transistor DT1.

[0099] In addition, in order to drive the light-emitting device L1 to emit light normally, the pixel driving circuit in the embodiment of the present application further includes: a ninth switch transistor M9, a first capacitor C1 and a second capacitor C2.

[0100] The connection relationship between the ninth switch transistor M9 and other components is: the control end of the ninth switch transistor M9 is coupled to the selection control end, the first end of the ninth switch transistor M9 is coupled to the first power supply end, and the second end of the ninth switch transistor M9 is coupled to the first end of the first driving transistor DT1.

[0101] During implementation, when the signal at the strobe control terminal is at a low level, i.e., during high grayscale display, the ninth switching transistor M9 is turned on, and the first power supply terminal is supplied to the anode of the light-emitting device L1 via the first driver transistor DT1 and the fifth switch transistor M5. The cathode of the light-emitting device L1 is coupled to the second power supply terminal. In this way, the light-emitting device L1 can display with a large current. When the signal at the strobe control terminal is at a high level, i.e., during low grayscale display, the ninth switching transistor M9 is turned on, and the first power supply terminal is supplied to the anode of the light-emitting device L1 via the second driver transistor DT2 and the fifth switch transistor M5. The cathode of the light-emitting device L1 is coupled to the second power supply terminal. In this way, the light-emitting device L1 can display with a small current. It should be noted that the voltage of the second power supply terminal is lower than the voltage of the first power supply terminal. The configuration of the first and second power supply terminals ensures the normal operation of the light-emitting device L1 and the peripheral circuits.

[0102] In addition, in order to be able to preserve the first data voltage and the second data voltage, a first capacitor C1 and a second capacitor C2 are further provided in the embodiment of the present application. The connection relationship between the first capacitor C1 and other components is: the first end of the first capacitor C1 is coupled to the first power supply end, and the second end of the first capacitor C1 is coupled to the control end of the first driving transistor DT1.

[0103] During the implementation process, when the data writing sub-circuit 10 inputs the first data voltage of the data signal end into the first node N1, and the selection control sub-circuit 20 inputs the first data voltage input into the first node N1 into the gate of the first driving transistor DT1, in order to ensure that the first data voltage continues to be provided to the light-emitting control circuit in the next timing, the first data voltage is stored through the first capacitor C1.

[0104] The connection relationship between the second capacitor C2 and other components is as follows: a first end of the second capacitor C2 is coupled to the first power supply end, and a second end of the second capacitor C2 is coupled to the control end of the second driving transistor DT2.

[0105] During the implementation process, when the data writing sub-circuit 10 inputs the second data voltage of the data signal end into the first node N1, and the selection control sub-circuit 20 inputs the second data voltage input into the first node N1 into the gate of the second driving transistor DT2, in order to ensure that the second data voltage continues to be provided to the light-emitting control circuit in the next timing, the second data voltage is stored through the second capacitor C2.

[0106] The following combines the timing Figure 7 The working process of the pixel driving circuit in the embodiment of the present application is described in detail.

[0107] Timing t11 stage: Rset = 0, Gate = 1, EM = 1, SW = 1

[0108] When the reset signal terminal Rset is at a low level, the eighth switching transistor is turned on, the selection control terminal SW is at a high level, the seventh switching transistor is turned on, and the signal of the initialization signal terminal resets the gate of the first driving transistor. At the same time, the first driving transistor is in the on state, the scan signal terminal Gate is at a high level, the third switching transistor and the fourth switching transistor are in the off state, and when the control signal terminal EM is at a high level, the fifth switching transistor is turned off.

[0109] Timing t12 stage: Rset = 1, Gate = 0, EM = 1, SW = 1

[0110] When the reset signal terminal Rset is at a high level, the eighth switching transistor is turned off, the reset process ends, the scanning signal terminal Gate is at a low level, the third switching transistor and the fourth switching transistor are in the on state, the control signal terminal EM is at a high level, the fifth switching transistor is turned off, the selection signal terminal SW is at a high level, the second switching transistor is turned on, the first switching transistor is turned off, the signal at the data signal terminal is written to the first node, and is written to the gate of the first driving transistor through the second switching transistor. At this time, since the first switching transistor is turned off, the gate of the second driving transistor is not reset. Therefore, the signal at the data signal terminal will not be written to the gate of the second driving transistor.

[0111] Timing t13 stage: Rset = 1, Gate = 1, EM = 0, SW = 1

[0112] When the reset signal terminal Rset is at a high level, the eighth switching transistor is turned off, the reset process ends, the scanning signal terminal Gate is at a high level, the third switching transistor and the fourth switching transistor are in the cut-off state, the selection signal terminal SW is at a high level, the second switching transistor is turned on, the first switching transistor is cut off, the signal at the data signal terminal is written to the first node, and is written to the gate of the first driving transistor through the second switching transistor. At this time, since the first switching transistor is cut off, the gate of the second driving transistor is not reset. Therefore, the signal at the data signal terminal will not be written to the gate of the second driving transistor. The control signal terminal EM is at a low level, the fifth switching transistor is turned on, and the loop composed of the first power supply terminal, the first driving transistor, the five switching transistors, the light-emitting device and the second power supply terminal is turned on, and the light-emitting device emits light according to the brightness corresponding to the signal at the data signal terminal written to the gate of the first driving transistor.

[0113] Timing t21 stage: Rset = 0, Gate = 1, EM = 1, SW = 0

[0114] When the reset signal terminal Rset is at a low level, the eighth switching transistor is turned on, the selection control terminal SW is at a low level, the sixth switching transistor is turned on, and the signal of the initialization signal terminal resets the gate of the second driving transistor. At the same time, the second driving transistor is in the on state, the scan signal terminal Gate is at a high level, the third switching transistor and the fourth switching transistor are in the off state, and when the control signal terminal EM is at a high level, the fifth switching transistor is turned off.

[0115] Timing t22 stage: Rset = 1, Gate = 0, EM = 1, SW = 0

[0116] When the reset signal terminal Rset is at a high level, the eighth switching transistor is turned off, the reset process ends, the scanning signal terminal Gate is at a low level, the third switching transistor and the fourth switching transistor are in the on state, the control signal terminal EM is at a high level, the fifth switching transistor is turned off, the selection signal terminal SW is at a low level, the second switching transistor is turned off, the first switching transistor is turned on, and the signal of the data signal terminal is written to the first node and written to the gate of the second driving transistor through the first switching transistor. At this time, since the second switching transistor is turned off, the gate of the first driving transistor is not reset. Therefore, the signal of the data signal terminal will not be written to the gate of the first driving transistor.

[0117] Timing t23 stage: Rset = 1, Gate = 1, EM = 0, SW = 0

[0118] When the reset signal terminal Rset is at a high level, the eighth switching transistor is turned off, the reset process ends, the scanning signal terminal Gate is at a high level, the third switching transistor and the fourth switching transistor are in the cut-off state, the selection signal terminal SW is at a low level, the second switching transistor is cut off, the first switching transistor is turned on, the signal at the data signal terminal is written to the first node, and is written to the gate of the second driving transistor through the first switching transistor. At this time, since the second switching transistor is cut off, the gate of the first driving transistor is not reset. Therefore, the signal at the data signal terminal will not be written to the gate of the first driving transistor. The control signal terminal EM is at a low level, the fifth switching transistor is turned on, and the loop composed of the first power supply terminal, the second driving transistor, the five switching transistors, the light-emitting device and the second power supply terminal is turned on, and the light-emitting device emits light according to the brightness corresponding to the signal at the data signal terminal written to the gate of the second driving transistor.

[0119] Based on the same inventive concept, an embodiment of the present disclosure provides a display device comprising any of the above-mentioned pixel driving circuits.

[0120] In the embodiments of the present invention, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. Other essential components of the display device are well understood by those skilled in the art and are not described in detail herein, nor should they be construed as limiting the present invention.

[0121] Based on the same inventive concept, a driving method for a pixel driving circuit is provided in an embodiment of the present disclosure. Figure 8 Shown, including:

[0122] Step 201: the data writing sub-circuit inputs the first data voltage or the second data voltage of the data signal terminal into the first node in response to the signal of the scan signal terminal.

[0123] During implementation, when the signal at the scan signal end is at a low level, the data writing sub-circuit inputs the first data voltage or the second data voltage at the data signal end into the first node.

[0124] Step 202: The strobe control subcircuit inputs the first data voltage input to the first node into the gate of the first driving transistor, or inputs the second data voltage input to the first node into the gate of the second driving transistor in response to the signal of the strobe control terminal.

[0125] When the signal at the strobe control terminal is at a high level, the strobe control subcircuit inputs the first data voltage input to the first node into the gate of the first drive transistor. Alternatively, when the signal at the strobe control terminal is at a low level, the strobe control subcircuit inputs the second data voltage input to the first node into the gate of the second drive transistor, thereby achieving time-sharing writing of the data voltages of the first drive transistor and the second drive transistor.

[0126] Step 203: The first driving transistor generates a first driving current according to the first data voltage, and the light emitting control subcircuit provides the first driving current generated by the first driving transistor to the light emitting device. Alternatively, the second driving transistor generates a second driving current according to the second data voltage, and the light emitting control subcircuit provides the second driving current generated by the second driving transistor to the light emitting device.

[0127] During implementation, when the strobe control terminal is at a high level, the first drive transistor generates a first drive current based on a first data voltage, and the light-emission control subcircuit provides the first drive current generated by the first drive transistor to the light-emitting device. Alternatively, when the strobe control terminal is at a low level, the second drive transistor generates a second drive current based on a second data voltage, and the light-emission control subcircuit provides the second drive current generated by the second drive transistor to the light-emitting device, thereby achieving time-sharing conduction of the first and second drive transistors.

[0128] In summary, in an embodiment of the present disclosure, a pixel driving circuit, a display device, and a driving method are provided. The pixel driving circuit includes: a first driving transistor, a second driving transistor, a light-emitting device, a data writing sub-circuit, a gating control sub-circuit, and a light-emitting control sub-circuit. During implementation, the first electrode of the first driving transistor is coupled to the first node and is configured to generate a first driving current according to a first data voltage. The first electrode of the second driving transistor is coupled to the first node and is configured to generate a second driving current according to a second data voltage. The data writing sub-circuit is coupled to the first node and is configured to input the first data voltage or the second data voltage of the data signal terminal into the first node in response to a signal of the scan signal terminal. The gating control sub-circuit is coupled to the gate of the first driving transistor and the gate of the second driving transistor and is configured to respond to the gating control. The signal of the control terminal is inputted into the first data voltage of the first node and inputted into the gate of the first driving transistor, or the second data voltage of the first node is inputted into the gate of the second driving transistor, the second electrode of the first driving transistor and the second electrode of the second driving transistor are coupled to the light-emitting device through the light-emitting control sub-circuit, and the light-emitting control sub-circuit is configured to provide the first driving current generated by the first driving transistor to the light-emitting device, or provide the second driving current generated by the second driving transistor to the light-emitting device. The above arrangement realizes the time-sharing conduction of the first driving transistor and the second driving transistor, that is, the first driving transistor is enabled when the light-emitting device requires a small current display, and the second driving transistor is enabled when the light-emitting device requires a large current display. In this way, while meeting the display requirements of the light-emitting device, the backplane power consumption during the display process is effectively reduced.

[0129] Those skilled in the art will appreciate that the embodiments of the present disclosure may be provided as methods, systems, or computer program product systems. Therefore, the present disclosure may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present disclosure may take the form of a computer program product system implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0130] The present disclosure is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program product systems according to the present disclosure. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0131] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0132] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 The steps for the function specified in one or more boxes.

[0133] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A pixel driving circuit, characterized in that: include: a first driving transistor, a second driving transistor, a light emitting device, a data writing sub-circuit, a gating control sub-circuit, and a light emitting control sub-circuit; The first electrode of the first driving transistor is coupled to the first node and is configured to generate a first driving current according to a first data voltage; A first electrode of the second driving transistor is coupled to the first node and configured to generate a second driving current according to a second data voltage; The data writing sub-circuit is coupled to the first node and configured to input the first data voltage or the second data voltage of the data signal terminal into the first node in response to a signal of the scan signal terminal; The gating control subcircuit is coupled to the gate of the first driving transistor and the gate of the second driving transistor, and is configured to input the first data voltage input to the first node into the gate of the first driving transistor, or input the second data voltage input to the first node into the gate of the second driving transistor in response to a signal from a gating control terminal. The gating control subcircuit includes a first switching transistor, a second switching transistor, and a third switching transistor. The control terminal of the first switching transistor is coupled to the control terminal of the second switching transistor, the first terminal of the first switching transistor is coupled to the control terminal of the second driving transistor, the second terminal of the first switching transistor is coupled to the second terminal of the second switching transistor, the first terminal of the second switching transistor is coupled to the control terminal of the first driving transistor, the control terminal of the third switching transistor is coupled to the scan signal terminal, the first terminal of the third switching transistor is coupled to the control terminal of the first switching transistor, and the second terminal of the third switching transistor is coupled to the gating control terminal. The first switching transistor is of P-type and the second switching transistor is of N-type, or the first switching transistor is of N-type and the second switching transistor is of P-type. The second electrode of the first driving transistor and the second electrode of the second driving transistor are coupled to the light-emitting device through the light-emitting control subcircuit, and the light-emitting control subcircuit is configured to provide the first driving current generated by the first driving transistor to the light-emitting device, or to provide the second driving current generated by the second driving transistor to the light-emitting device.

2. The circuit according to claim 1, wherein The grayscale corresponding to the first data voltage is greater than the grayscale corresponding to the second data voltage.

3. The circuit according to claim 1, wherein A width-to-length ratio of a channel of the first driving transistor is greater than a width-to-length ratio of a channel of the second driving transistor.

4. The circuit according to any one of claims 1 to 3, characterized in that The data writing sub-circuit includes a fourth switching transistor; The control terminal of the fourth switch transistor is coupled to the scan signal terminal, the first terminal of the fourth switch transistor is coupled to the data signal terminal, and the second terminal of the fourth switch transistor is coupled to the first terminal of the first driving transistor.

5. The circuit according to any one of claims 1 to 3, characterized in that The light emitting control subcircuit includes a fifth switching transistor; The control terminal of the fifth switch transistor is coupled to the gate control terminal, the first terminal of the fifth switch transistor is coupled to the second terminal of the second driving transistor, and the second terminal of the fifth switch transistor is coupled to the light emitting device.

6. The circuit according to any one of claims 1 to 3, characterized in that Also included is a reset control subcircuit; The reset control subcircuit is coupled to the gate control subcircuit and is configured to reset the gates of the first driving transistor and the second driving transistor.

7. The circuit according to claim 6, wherein: The reset control subcircuit includes a sixth switch transistor, a seventh switch transistor and an eighth switch transistor; The control terminal of the sixth switch transistor is coupled to the control terminal of the seventh switch transistor, the first terminal of the sixth switch transistor is coupled to the control terminal of the second driving transistor, and the second terminal of the sixth switch transistor is coupled to the initialization signal terminal; A first terminal of the seventh switch transistor is coupled to the control terminal of the first driving transistor, and a second terminal of the seventh switch transistor is coupled to the initialization signal terminal; The control terminal of the eighth switch transistor is coupled to the reset signal terminal, the first terminal of the eighth switch transistor is coupled to the gate control terminal, and the second terminal of the eighth switch transistor is coupled to the control terminal of the sixth switch transistor; The sixth switch transistor is of P type and the seventh switch transistor is of N type; or the sixth switch transistor is of N type and the seventh switch transistor is of P type, and the first switch transistor and the sixth switch transistor have the same polarity, and the second switch transistor and the seventh switch transistor have the same polarity.

8. The circuit according to claim 3, wherein: Also includes: a ninth switching transistor, a first capacitor and a second capacitor; The control terminal of the ninth switch transistor is coupled to the gate control terminal, the first terminal of the ninth switch transistor is coupled to the first power supply terminal, and the second terminal of the ninth switch transistor is coupled to the first terminal of the first driving transistor; A first terminal of the first capacitor is coupled to the first power supply terminal, and a second terminal of the first capacitor is coupled to the control terminal of the first driving transistor; A first terminal of the second capacitor is coupled to the first power terminal, and a second terminal of the second capacitor is coupled to the control terminal of the second driving transistor.

9. A display device, characterized in that: The method comprises the pixel driving circuit according to any one of claims 1 to 8.

10. A driving method for a pixel driving circuit according to any one of claims 1 to 8, characterized in that: include: The data writing sub-circuit inputs the first data voltage or the second data voltage of the data signal terminal into the first node in response to the signal of the scan signal terminal; The strobe control subcircuit inputs the first data voltage input to the first node into the gate of the first driving transistor, or inputs the second data voltage input to the first node into the gate of the second driving transistor in response to a signal from the strobe control terminal; A first driving transistor generates a first driving current according to a first data voltage, and a light emitting control subcircuit provides the first driving current generated by the first driving transistor to the light emitting device; Alternatively, the second driving transistor generates a second driving current according to a second data voltage, and the light emitting control subcircuit provides the second driving current generated by the second driving transistor to the light emitting device.

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