Pixel driving circuit and display substrate

Abstract

The utility model discloses a pixel driving circuit and a display substrate, and the pixel driving circuit comprises a first control sub-circuit which is configured to be communicated with a first node and a fifth node under the control of a signal of a first scanning signal end, storing a voltage difference between the signals of the first node and the first power supply end and a voltage difference between the signals of the fifth node and the first power supply end; the second control sub-circuit is configured to provide a signal of a first initial signal end or a third node to a fifth node under the control of signals of a first reset signal end and a second scanning signal end; and the third control sub-circuit is configured to provide a signal of a data signal end or a third initial signal end for the second node and provide a signal of a second initial signal end for the fourth node under the control of signals of a first scanning signal end and a second reset signal end.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the display field, specifically to a pixel driving circuit and a display substrate. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Utility Model Content

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a pixel driving circuit and a display substrate.

[0005] In a first aspect, this disclosure provides a pixel driving circuit, including: a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, a fourth control sub-circuit, and a driving sub-circuit;

[0006] The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving signal to the third node under the control of the signals of the first node and the second node.

[0007] The first control sub-circuit is electrically connected to the first scan signal terminal, the first power supply terminal, the first node and the fifth node respectively, and is configured to connect the first node and the fifth node under the control of the signal of the first scan signal terminal, and store the voltage difference between the signals of the first node and the first power supply terminal and the voltage difference between the signals of the fifth node and the first power supply terminal.

[0008] The second control sub-circuit is electrically connected to the first reset signal terminal, the second scan signal terminal, the first initial signal terminal, the third node, and the fifth node, respectively, and is configured to provide the first initial signal terminal or the third node signal to the fifth node under the control of the signals of the first reset signal terminal and the second scan signal terminal;

[0009] The third control sub-circuit is electrically connected to the first scan signal terminal, the second reset signal terminal, the data signal terminal, the second initial signal terminal, the third initial signal terminal, the second node, and the fourth node, respectively. It is configured to provide the data signal terminal or the third initial signal terminal to the second node and the second initial signal terminal to the fourth node under the control of the signals of the first scan signal terminal and the second reset signal terminal.

[0010] The fourth control sub-circuit is electrically connected to the light-emitting signal terminal, the first power supply terminal, the second node, the third node, and the fourth node, respectively, and is configured to provide the first power supply terminal signal to the second node and the third node signal to the fourth node under the control of the light-emitting signal terminal signal.

[0011] In an exemplary embodiment, the first control sub-circuit includes: a first storage sub-circuit, a second storage sub-circuit, and a connection sub-circuit;

[0012] The connecting sub-circuit is electrically connected to the first scanning signal terminal, the first node, and the fifth node, respectively, and is configured to connect the first node and the fifth node under the control of the signal from the first scanning signal terminal.

[0013] The first storage sub-circuit is electrically connected to the first node and the first power supply terminal respectively, and is configured to store the voltage difference between the signals of the first node and the first power supply terminal.

[0014] The second storage sub-circuit is electrically connected to the fifth node and the first power supply terminal respectively, and is configured to store the voltage difference between the signals of the fifth node and the first power supply terminal.

[0015] In an exemplary embodiment, the connecting sub-circuit includes a ninth transistor, the first storage sub-circuit includes a first capacitor, the second storage sub-circuit includes a second capacitor, and both the first capacitor and the second capacitor include a first electrode and a second electrode.

[0016] The control electrode of the ninth transistor is electrically connected to the first scan signal terminal, the first electrode of the ninth transistor is electrically connected to the first node, and the second electrode of the ninth transistor is electrically connected to the fifth node.

[0017] The first plate of the first capacitor is electrically connected to the first node, and the second plate of the first capacitor is electrically connected to the first power supply terminal.

[0018] The first plate of the second capacitor is electrically connected to the fifth node, and the second plate of the second capacitor is electrically connected to the first power supply terminal.

[0019] In an exemplary embodiment, the second control sub-circuit includes: a first transistor and a second transistor;

[0020] The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the first initial signal terminal, and the second electrode of the first transistor is electrically connected to the fifth node.

[0021] The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the fifth node, and the second electrode of the second transistor is electrically connected to the third node.

[0022] The type of at least one of the first transistor and the second transistor is opposite to the type of at least one transistor in the first control sub-circuit.

[0023] In an exemplary embodiment, the third control sub-circuit includes: a fourth transistor, a seventh transistor, and an eighth transistor;

[0024] The control electrode of the fourth transistor is electrically connected to the first scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the second node.

[0025] The control terminal of the seventh transistor is electrically connected to the second reset signal terminal, the first terminal of the seventh transistor is electrically connected to the second initial signal terminal, and the second terminal of the seventh transistor is electrically connected to the fourth node.

[0026] The control terminal of the eighth transistor is electrically connected to the second reset signal terminal, the first terminal of the eighth transistor is electrically connected to the third initial signal terminal, and the second terminal of the eighth transistor is electrically connected to the second node.

[0027] The voltage value of the signal at the third initial signal terminal is greater than the voltage value of the signal at the first power supply terminal.

[0028] In an exemplary embodiment, the driving sub-circuit includes a third transistor; the first control sub-circuit includes a ninth transistor, a first capacitor, and a second capacitor; the second control sub-circuit includes a first transistor and a second transistor; the third control sub-circuit includes a fourth transistor, a seventh transistor, and an eighth transistor; the fourth control sub-circuit includes a fifth transistor and a sixth transistor; and both the first capacitor and the second capacitor include a first electrode and a second electrode.

[0029] The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the first initial signal terminal, and the second electrode of the first transistor is electrically connected to the fifth node.

[0030] The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the fifth node, and the second electrode of the second transistor is electrically connected to the third node.

[0031] The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node.

[0032] The control electrode of the fourth transistor is electrically connected to the first scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the second node.

[0033] The control electrode of the fifth transistor is electrically connected to the light-emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node.

[0034] The control electrode of the sixth transistor is electrically connected to the light-emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node.

[0035] The control terminal of the seventh transistor is electrically connected to the second reset signal terminal, the first terminal of the seventh transistor is electrically connected to the second initial signal terminal, and the second terminal of the seventh transistor is electrically connected to the fourth node.

[0036] The control terminal of the eighth transistor is electrically connected to the second reset signal terminal, the first terminal of the eighth transistor is electrically connected to the third initial signal terminal, and the second terminal of the eighth transistor is electrically connected to the second node.

[0037] The control electrode of the ninth transistor is electrically connected to the first scan signal terminal, the first electrode of the ninth transistor is electrically connected to the first node, and the second electrode of the ninth transistor is electrically connected to the fifth node.

[0038] The first plate of the first capacitor is electrically connected to the first node, and the second plate of the first capacitor is electrically connected to the first power supply terminal.

[0039] The first plate of the second capacitor is electrically connected to the fifth node, and the second plate of the second capacitor is electrically connected to the first power supply terminal.

[0040] In an exemplary embodiment, at least one of the first and second transistors is of a type opposite to that of at least one of the third to ninth transistors;

[0041] At least one of the first transistor and the second transistor is an N-type transistor, and at least one of the third to the ninth transistors is a P-type transistor.

[0042] In an exemplary embodiment, at least one of the first to ninth transistors includes an active pattern, the active pattern including a channel region, a first region and a second region, the first region and the second region being located on opposite sides of the channel region;

[0043] The doping concentration of the channel region in the active pattern of the ninth transistor is greater than the doping concentration of the channel region in the active pattern of at least one of the first to eighth transistors.

[0044] In an exemplary embodiment, the doping concentration of at least one of the first and second regions in the active pattern of the ninth transistor is greater than or equal to the doping concentration of the channel region in the active pattern of the ninth transistor.

[0045] In an exemplary embodiment, during at least one display frame, the time period during which the signal at the second reset signal terminal is an effective level signal includes: a first time period and a second time period set at intervals, wherein the first time period occurs before the second time period;

[0046] The time period during which the signal at at least one of the first scan signal terminal, the second scan signal terminal, and the first reset signal terminal is an effective level signal is located between the first time period and the second time period.

[0047] In an exemplary embodiment, the time period during which the signal at the first scanning signal terminal is an effective level signal includes: a third time period and a fourth time period set at intervals, wherein the third time period occurs before the fourth time period, and the third time period includes: multiple sub-time periods set at intervals.

[0048] The time period during which the signal at the first reset signal terminal is at an effective level overlaps at least partially with the time period during which the signal at the second scan signal terminal is at an effective level; the time period during which the signal at the first reset signal terminal is at an effective level overlaps at least partially with the third time period; and the time period during which the signal at the second scan signal terminal is at an effective level overlaps at least partially with the fourth time period.

[0049] In an exemplary embodiment, the start time of the period when the signal at the first reset signal terminal is an effective level signal is earlier than the start time of the period when the signal at the second scan signal terminal is an effective level signal, and the end time of the period when the signal at the first reset signal terminal is an effective level signal is later than the start time of the period when the signal at the second scan signal terminal is an effective level signal, but earlier than the end time of the period when the signal at the second scan signal terminal is an effective level signal.

[0050] The start time of the third time period is later than the start time of the time period when the signal at the first reset signal terminal is at an effective level, and the end time of the third time period is earlier than the start time of the time period when the signal at the second scan signal terminal is at an effective level.

[0051] The start time of the fourth time period is later than the end time of the time period when the signal at the first reset signal terminal is at an effective level, and the end time of the fourth time period is later than the end time of the time period when the signal at the second scan signal terminal is at an effective level.

[0052] In a second aspect, this disclosure also provides a display substrate, comprising: a substrate and a plurality of the aforementioned pixel driving circuits and a plurality of first scan signal lines disposed on the substrate, wherein the pixel driving circuit comprises: at least one P-type transistor, and the at least one P-type transistor comprises: a fourth transistor and a ninth transistor;

[0053] At least one of the plurality of first scan signal lines is electrically connected to the control electrode of the fourth transistor and the control electrode of the ninth transistor in at least one pixel driving circuit, and at least one of the plurality of first scan signal lines extends at least partially along the first direction;

[0054] The control electrode of the fourth transistor in at least one pixel driving circuit is located on the side of the plurality of first scan signal lines and the control electrode of the ninth transistor in at least one pixel driving circuit close to the substrate.

[0055] In an exemplary embodiment, the orthographic projection of at least one of the plurality of first scan signal lines on the substrate at least partially overlaps with the orthographic projection of the control electrode of the fourth transistor in at least one pixel driving circuit on the substrate.

[0056] In an exemplary embodiment, the system further includes: multiple light-emitting signal lines and multiple second reset signal lines disposed on the substrate; the at least one P-type transistor further includes: a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor.

[0057] At least one of the plurality of light-emitting signal lines is electrically connected to the control electrode of the fifth transistor and the control electrode of the sixth transistor in at least one pixel driving circuit, and at least one of the plurality of second reset signal lines is electrically connected to the control electrode of the seventh transistor and the control electrode of the eighth transistor in at least one pixel driving circuit. At least a portion of the plurality of light-emitting signal lines and the plurality of second reset signal lines extend along a first direction.

[0058] The control electrode of at least one of the fifth, sixth, seventh, and eighth transistors in the multiple light-emitting signal lines, multiple second reset signal lines, and at least one pixel driving circuit is disposed on the same layer as the control electrode of the fourth transistor.

[0059] In an exemplary embodiment, the system further includes: a plurality of first reset signal lines and a plurality of second scan signal lines disposed on the substrate; the pixel driving circuit includes: at least one N-type transistor, and the at least one N-type transistor further includes: a first transistor and a second transistor;

[0060] At least one of the plurality of first reset signal lines is electrically connected to the control electrode of a first transistor in at least one pixel driving circuit, and at least one of the plurality of second scan signal lines is electrically connected to the control electrode of a second transistor in at least one pixel driving circuit. At least a portion of the plurality of first reset signal lines and the plurality of second scan signal lines extend along a first direction.

[0061] At least one of the plurality of first reset signal lines and the plurality of second scan signal lines is located on the side of the plurality of light emission signal lines and the plurality of second reset signal lines that is away from the substrate;

[0062] The orthographic projections of the active patterns of the fourth transistor and the ninth transistor of at least one pixel driving circuit onto the substrate at least partially overlap with the orthographic projections of at least one of the first and second scan signal lines onto the substrate.

[0063] In an exemplary embodiment, the first reset signal line, the first scan signal line, the second scan signal line, the light emission signal line, and the second reset signal line connected to at least one pixel driving circuit are arranged sequentially along a second direction on the substrate, and the first direction and the second direction intersect.

[0064] In an exemplary embodiment, it further includes: a plurality of first initial signal lines, a plurality of second initial signal lines, and a plurality of third initial signal lines disposed on the substrate;

[0065] At least one of the plurality of first initial signal lines, plurality of second initial signal lines, and plurality of third initial signal lines extends at least partially along a first direction;

[0066] The orthographic projection of the first initial signal line connected to at least one pixel driving circuit on the substrate is located on the side of the orthographic projection of the first reset signal line on the substrate that is far from the orthographic projection of the first scan signal line on the substrate.

[0067] The orthographic projection of the second initial signal line connected to at least one pixel driving circuit on the substrate is located on the side of the orthographic projection of the second reset signal line on the substrate that is away from the orthographic projection of the light emission signal line on the substrate.

[0068] At least a portion of the orthographic projection of the third initial signal line connected to at least one pixel driving circuit on the substrate overlaps at least a portion of the orthographic projection of the second reset signal line on the substrate, and is located between the orthographic projection of the light emission signal line on the substrate and the orthographic projection of the second initial signal line on the substrate.

[0069] In an exemplary embodiment, the system further includes: a circuit structure layer disposed on the substrate, the circuit structure layer comprising: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, and a fourth conductive layer; at least one first reset signal line comprising: a first reset connection line and a second reset connection line disposed on different layers and interconnected therewith; at least one second scan signal line comprising: a first scan connection line and a second scan connection line disposed on different layers and interconnected therewith; and at least one control electrode of an N-type transistor comprising: a first control electrode and a second control electrode.

[0070] The first conductive layer includes at least: multiple first initial signal lines, multiple light-emitting signal lines, multiple second reset signal lines, and the control electrode of at least one of the third to eighth transistors located in at least one pixel driving circuit;

[0071] The second conductive layer includes at least: a plurality of first scan signal lines, a first reset connection line of a plurality of first reset signal lines, a first scan connection line of a plurality of second scan signal lines, and a control electrode of a ninth transistor and a first control electrode of at least one N-type transistor located in at least one pixel driving circuit;

[0072] The third conductive layer includes at least: multiple second initial signal lines, multiple third initial signal lines, a second reset connection line of multiple first reset signal lines, a second scan connection line of multiple second scan signal lines, and a second control electrode of at least one N-type transistor located in at least one pixel driving circuit;

[0073] The fourth conductive layer includes at least: a first electrode and a second electrode of at least one transistor located in at least one pixel driving circuit.

[0074] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0075] The accompanying drawings are provided to further illustrate the technical solution of this utility model and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solution of this utility model and do not constitute a limitation on the technical solution of this utility model.

[0076] Figure 1 This is a schematic diagram of the pixel driving circuit provided in an embodiment of the present disclosure;

[0077] Figure 2A schematic diagram of the structure of a first control sub-circuit provided in an exemplary embodiment;

[0078] Figure 3 An equivalent circuit diagram of a first control sub-circuit provided as an exemplary embodiment;

[0079] Figure 4 An equivalent circuit diagram of a second control sub-circuit provided as an exemplary embodiment;

[0080] Figure 5 An equivalent circuit diagram of a second control sub-circuit provided as an exemplary embodiment;

[0081] Figure 6 Equivalent circuit diagrams of the driving sub-circuit and the fourth control sub-circuit provided as an exemplary embodiment;

[0082] Figure 7 An equivalent circuit diagram of a pixel driving circuit provided in an exemplary embodiment;

[0083] Figure 8 This is a cross-sectional schematic diagram of the ninth transistor;

[0084] Figure 9 for Figure 7 The provided timing diagram of the pixel driving circuit;

[0085] Figure 10 This is a schematic diagram of the structure of a display substrate provided in an embodiment of this disclosure;

[0086] Figure 11 for Figure 10 A partial schematic diagram of the membrane layers;

[0087] Figure 12 This is a schematic diagram of the pattern of the first semiconductor layer;

[0088] Figure 13 This is a schematic diagram of the pattern of the first conductive layer;

[0089] Figure 14 This is a schematic diagram after the first conductive layer pattern has been formed;

[0090] Figure 15 This is a schematic diagram of the pattern of the second conductive layer;

[0091] Figure 16 This is a schematic diagram after the second conductive layer pattern has been formed;

[0092] Figure 17 This is a schematic diagram of the pattern of the second semiconductor layer;

[0093] Figure 18 This is a schematic diagram after the second semiconductor layer pattern has been formed;

[0094] Figure 19 This is a schematic diagram of the pattern of the third conductive layer;

[0095] Figure 20 This is a schematic diagram after the third conductive layer pattern has been formed;

[0096] Figure 21 This is a schematic diagram showing the pattern after the fifth insulating layer has been formed.

[0097] Figure 22 This is a schematic diagram of the pattern of the fourth conductive layer;

[0098] Figure 23 This is a schematic diagram after the fourth conductive layer pattern has been formed. Detailed Implementation

[0099] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0100] In the accompanying drawings, the size of the constituent elements, the thickness of the layers, or the area are sometimes exaggerated for clarity. Therefore, one aspect of this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0101] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0102] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0103] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0104] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0105] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0106] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0107] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0108] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0109] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0110] Display products include pixel driving circuits and light-emitting devices. The display product achieves its display by driving the light-emitting devices to emit light through the pixel driving circuit. During reliability testing, some transistors in the pixel driving circuit are subjected to prolonged bias voltage and high temperature, causing a shift in transistor characteristics (e.g., threshold voltage). This threshold voltage shift leads to potential fluctuations in some nodes within the pixel driving circuit, thereby reducing the reliability of the pixel driving circuit and affecting the display effect of the display product.

[0111] Therefore, this disclosure provides a pixel driving circuit.

[0112] Figure 1 This is a schematic diagram of the pixel driving circuit provided in an embodiment of this disclosure. Figure 1 As shown in the embodiments of this disclosure, the pixel driving circuit can be configured to drive the light-emitting device L to emit light. The pixel driving circuit may include: a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, a fourth control sub-circuit, and a driving sub-circuit.

[0113] like Figure 1 As shown, the driving sub-circuit is electrically connected to the first node N1, the second node N2 and the third node N3 respectively, and is configured to provide a driving signal to the third node N3 under the control of the signals of the first node N1 and the second node N2.

[0114] like Figure 1As shown, the first control sub-circuit is electrically connected to the first scan signal terminal Gate1, the first power supply terminal VDD, the first node N1, and the fifth node N5, respectively. It is configured to connect the first node N1 and the fifth node N5 under the control of the signal of the first scan signal terminal Gate1, and to store the voltage difference between the signals of the first node N1 and the first power supply terminal VDD and the voltage difference between the signals of the fifth node N5 and the first power supply terminal VDD.

[0115] like Figure 1 As shown, the second control sub-circuit is electrically connected to the first reset signal terminal Reset1, the second scan signal terminal Gate2, the first initial signal terminal INIT1, the third node N3, and the fifth node N5, respectively. It is configured to provide the first initial signal terminal INIT1 or the third node N3 signal to the fifth node N5 under the control of the signals of the first reset signal terminal Reset1 and the second scan signal terminal Gate2.

[0116] like Figure 1 As shown, the third control sub-circuit is electrically connected to the first scan signal terminal Gate1, the second reset signal terminal Reset2, the data signal terminal Data, the second initial signal terminal INIT2, the third initial signal terminal INIT3, the second node N2, and the fourth node N4, respectively. It is configured to provide the data signal terminal Data or the third initial signal terminal INIT3 to the second node N2 and the second initial signal terminal INIT2 to the fourth node N4 under the control of the signals of the first scan signal terminal Gate1 and the second reset signal terminal Reset2.

[0117] like Figure 1 As shown, the fourth control sub-circuit is electrically connected to the light-emitting signal terminal EM, the first power supply terminal VDD, the second node N2, the third node N3, and the fourth node N4, respectively. It is configured to provide the first power supply terminal VDD signal to the second node N2 and the third node N3 signal to the fourth node N4 under the control of the light-emitting signal terminal EM.

[0118] like Figure 1 As shown, the light-emitting device L is electrically connected to the fourth node N4 and the second power supply terminal VSS.

[0119] In an exemplary embodiment, the first power supply terminal VDD continuously provides a high-level signal, and the second power supply terminal VSS continuously provides a low-level signal.

[0120] In an exemplary embodiment, the voltage value of the signal at at least one of the first initial signal terminal INIT1, the second initial signal terminal INIT2, and the third initial signal terminal INIT3 is constant, and it is a DC signal. In an exemplary embodiment, the DC signal may be one in which neither the magnitude nor the direction of the signal changes with time.

[0121] In an exemplary embodiment, the light-emitting device L may include a current-driven device, such as a current-driven light-emitting diode, like a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (OLED), or a quantum light-emitting diode (QLED). The typical size (e.g., length) of a Micro LED can be less than 100 μm, for example, 10 μm to 50 μm. The typical size (e.g., length) of a Mini LED can be approximately 100 μm to 300 μm, for example, 120 μm to 260 μm.

[0122] In an exemplary embodiment, the organic light-emitting layer may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In this exemplary embodiment, the hole injection layer of all sub-pixels may be a common layer connected together, the electron injection layer of all sub-pixels may be a common layer connected together, the hole transport layer of all sub-pixels may be a common layer connected together, the electron transport layer of all sub-pixels may be a common layer connected together, and the hole block layer of all sub-pixels may be a common layer connected together. The emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0123] In an exemplary embodiment, the light-emitting device L may include a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode). Exemplarily, the first electrode of the light-emitting device is electrically connected to the fourth node N4 in the pixel driving circuit, and the second electrode of the light-emitting device is electrically connected to the second power supply terminal VSS.

[0124] This disclosure, by setting a first control sub-circuit, can eliminate the influence of transistor characteristic offset on the potential of the first node during reliability testing of the pixel driving circuit, thereby improving the reliability of the pixel driving circuit and the display effect of the display product.

[0125] Figure 2 This is a schematic diagram of the structure of a first control sub-circuit provided as an exemplary embodiment. (See diagram below.) Figure 2 As shown, in an exemplary embodiment, the first control sub-circuit includes: a first storage sub-circuit, a second storage sub-circuit, and a connection sub-circuit.

[0126] like Figure 2 As shown, the connected sub-circuit is electrically connected to the first scan signal terminal Gate1, the first node N1 and the fifth node N5 respectively, and is configured to connect the first node N1 and the fifth node N5 under the control of the signal of the first scan signal terminal Gate1.

[0127] like Figure 2 As shown, the first storage sub-circuit is electrically connected to the first node N1 and the first power supply terminal VDD, respectively, and is configured to store the voltage difference between the signals of the first node N1 and the first power supply terminal VDD.

[0128] like Figure 2 As shown, the second storage sub-circuit is electrically connected to the fifth node N5 and the first power supply terminal VDD, respectively, and is configured to store the voltage difference between the signals of the fifth node N5 and the first power supply terminal VDD.

[0129] Figure 3 An equivalent circuit diagram of a first control sub-circuit provided as an exemplary embodiment. (e.g.) Figure 3 As shown, in the first control sub-circuit, the connected sub-circuit includes: a ninth transistor T9. The control electrode of the ninth transistor T9 is electrically connected to the first scan signal terminal Gate1, the first electrode of the ninth transistor T9 is electrically connected to the first node N1, and the second electrode of the ninth transistor T9 is electrically connected to the fifth node N5.

[0130] like Figure 3 As shown, in the first control sub-circuit, the first storage sub-circuit may include a first capacitor C1. The first capacitor C1 includes a first plate C11 and a second plate C12. The first plate C11 of the first capacitor C1 is electrically connected to the first node N1, and the second plate C12 of the first capacitor C1 is electrically connected to the first power supply terminal VDD.

[0131] like Figure 3As shown, in the first control sub-circuit, the second storage sub-circuit may include a second capacitor C2. The second capacitor C2 includes a first plate C21 and a second plate C22. The first plate C21 of the second capacitor C2 is electrically connected to the fifth node N5, and the second plate C22 of the second capacitor C2 is electrically connected to the first power supply terminal VDD.

[0132] Figure 3 Only one exemplary structure of the first control sub-circuit is shown. It will be readily understood by those skilled in the art that the implementation of the first control sub-circuit is not limited to this, and any implementation that achieves its function is acceptable.

[0133] In an exemplary embodiment Figure 4 An equivalent circuit diagram of a second control sub-circuit provided as an exemplary embodiment. (e.g.) Figure 4 As shown, the second control sub-circuit includes a first transistor T1 and a second transistor T2. The control electrode of the first transistor T1 is electrically connected to the first reset signal terminal Reset1, the first electrode of the first transistor T1 is electrically connected to the first initial signal terminal INIT1, and the second electrode of the first transistor T1 is electrically connected to the fifth node N5. The control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the fifth node N5, and the second electrode of the second transistor T2 is electrically connected to the third node N3.

[0134] In an exemplary embodiment, at least one of the first transistors T1 and the second transistor T2 is of the opposite type to the transistor type of at least one transistor in the first control sub-circuit.

[0135] Figure 4 Only one exemplary structure of the second control sub-circuit is shown. It will be readily understood by those skilled in the art that the implementation of the second control sub-circuit is not limited to this, and any implementation that achieves its function is acceptable.

[0136] In an exemplary embodiment Figure 5 An equivalent circuit diagram of a second control sub-circuit provided as an exemplary embodiment. (e.g.) Figure 5As shown, the third control sub-circuit includes: a fourth transistor T4, a seventh transistor T7, and an eighth transistor T8. Specifically, the control electrode of the fourth transistor T4 is electrically connected to the first scan signal terminal Gate1, the first electrode of the fourth transistor T4 is electrically connected to the data signal terminal, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the seventh transistor T7 is electrically connected to the second reset signal terminal Reset2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal terminal INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4; the control electrode of the eighth transistor T8 is electrically connected to the second reset signal terminal Reset2, the first electrode of the eighth transistor T8 is electrically connected to the third initial signal terminal INIT3, and the second electrode of the eighth transistor T8 is electrically connected to the second node N2.

[0137] In an exemplary embodiment, the voltage value of the signal at the third initial signal terminal INIT3 is greater than the voltage value of the signal at the first power supply terminal VDD.

[0138] Figure 5 Only one exemplary structure of the third control sub-circuit is shown. It will be readily understood by those skilled in the art that the implementation of the third control sub-circuit is not limited to this, and any implementation that achieves its function is acceptable.

[0139] In an exemplary embodiment Figure 6 Equivalent circuit diagrams of the driving sub-circuit and the fourth control sub-circuit provided as an exemplary embodiment. (See diagram below.) Figure 6 As shown, the driving sub-circuit includes a third transistor T3. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The third transistor T3 can be referred to as the driving transistor.

[0140] like Figure 6 As shown, the fourth control sub-circuit includes a fifth transistor T5 and a sixth transistor T6. The control electrode of the fifth transistor T5 is electrically connected to the light-emitting signal terminal EM, its first electrode is electrically connected to the first power supply terminal VDD, and its second electrode is electrically connected to the second node N2. Similarly, the control electrode of the sixth transistor T6 is electrically connected to the light-emitting signal terminal EM, its first electrode is electrically connected to the third node N3, and its second electrode is electrically connected to the fourth node N4. Both the fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors (LEDs).

[0141] Figure 6 Only one exemplary structure of the driver sub-circuit and the fourth control sub-circuit is shown. It will be readily understood by those skilled in the art that the implementation of the driver sub-circuit and the fourth control sub-circuit is not limited to this, and any implementation that achieves its function is acceptable.

[0142] Figure 7 This is an equivalent circuit diagram of a pixel driving circuit provided as an exemplary embodiment. For example... Figure 7 As shown, in an exemplary embodiment, the driving sub-circuit includes: a third transistor T3; the first control sub-circuit includes: a ninth transistor T9, a first capacitor C1, and a second capacitor C2; the second control sub-circuit includes: a first transistor T1 and a second transistor T2; the third control sub-circuit includes: a fourth transistor T4, a seventh transistor T7, and an eighth transistor T8; the fourth control sub-circuit includes: a fifth transistor T5 and a sixth transistor T6; and both the first capacitor C1 and the second capacitor C2 include: a first electrode plate and a second electrode plate.

[0143] like Figure 7As shown, the control electrode of the first transistor T1 is electrically connected to the first reset signal terminal Reset1, the first electrode of the first transistor T1 is electrically connected to the first initial signal terminal INIT1, and the second electrode of the first transistor T1 is electrically connected to the fifth node N5; the control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the fifth node N5, and the second electrode of the second transistor T2 is electrically connected to the third node N3; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first scan signal terminal Gate1, the first electrode of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the light emission signal terminal EM, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the light emission signal terminal E... M is electrically connected; the first terminal of the sixth transistor T6 is electrically connected to the third node N3, and the second terminal of the sixth transistor T6 is electrically connected to the fourth node N4; the control terminal of the seventh transistor T7 is electrically connected to the second reset signal terminal Reset2, and the first terminal of the seventh transistor T7 is electrically connected to the second initial signal terminal INIT2; the second terminal of the seventh transistor T7 is electrically connected to the fourth node N4; the control terminal of the eighth transistor T8 is electrically connected to the second reset signal terminal Reset2, and the first terminal of the eighth transistor T8 is electrically connected to the third initial signal terminal INIT3; the eighth transistor T... The second electrode of transistor 8 is electrically connected to the second node N2; the control electrode of the ninth transistor T9 is electrically connected to the first scan signal terminal Gate1, the first electrode of the ninth transistor T9 is electrically connected to the first node N1, and the second electrode of the ninth transistor T9 is electrically connected to the fifth node N5; the first plate C11 of the first capacitor C1 is electrically connected to the first node N1, and the second plate C12 of the first capacitor C1 is electrically connected to the first power supply terminal VDD; the first plate C21 of the second capacitor C2 is electrically connected to the fifth node N5, and the second plate C22 of the second capacitor C2 is electrically connected to the first power supply terminal VDD.

[0144] Based on their characteristics, transistors can be classified into N-type transistors and P-type transistors. When a transistor is P-type, its turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and its turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is N-type, its turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and its turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0145] In an exemplary embodiment, the N-type transistor can be an oxide thin-film transistor, the active layer of which is made of oxide semiconductor. Oxide thin-film transistors have advantages such as low leakage current.

[0146] In an exemplary embodiment, the P-type transistor can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor. The active layer of the LTPS thin-film transistor is made of low-temperature polycrystalline silicon, which has advantages such as high mobility and fast charging.

[0147] In an exemplary embodiment, at least one of the first transistor T1 and the second transistor T2 is of the opposite type to at least one of the third transistor T3 to the ninth transistor T9.

[0148] In an exemplary embodiment, at least one of the first transistor T1 and the second transistor T2 is an N-type transistor, and at least one of the third transistor T3 to the ninth transistor T9 is a P-type transistor.

[0149] In this disclosure, at least one of the first transistor T1 and the second transistor T2 is an N-type transistor, which can reduce the leakage current of the fifth node N5. The ninth transistor T9 is a P-type transistor, which can reduce the influence of the fifth node N5 on the first node N1 and improve the reliability of the pixel driving circuit.

[0150] In an exemplary embodiment, when all transistors in the pixel driving circuit are P-type transistors and N-type transistors, the display substrate uses Low Temperature Poly-Silicon (LTPS) technology. Compared with LTPS technology, LTPO technology has lower leakage current and faster pixel response. The display substrate has an additional oxide layer, which reduces the energy consumption required to excite the pixels, thereby reducing the power consumption when the screen is displayed.

[0151] In an exemplary embodiment, at least one of the first transistors T1 to the ninth transistor T9 includes an active pattern comprising a channel region, a first region, and a second region, the first region and the second region being located on opposite sides of the channel region. The doping concentration of the channel region 91-3 in the active pattern of the ninth transistor T9 is greater than the doping concentration of the channel region in the active pattern of at least one of the first transistors T1 to the eighth transistor T8.

[0152] This disclosure enables the ninth transistor T9 to have a higher mobility by using a channel region with a higher doping concentration in the active pattern than the channel region with a higher doping concentration in the active pattern of at least one of the first transistors T1 to the eighth transistor T8. This allows the ninth transistor T9 to achieve a balance in a short time regardless of the potential difference between the signals of the first node N1 and the fifth node N5, thus avoiding the flickering problem of display products caused by leakage.

[0153] In an exemplary embodiment Figure 8 This is a cross-sectional schematic diagram of the ninth transistor. (As shown) Figure 8 As shown, the doping concentration of at least one of the first region 91-1 and the second region 91-2 in the active pattern 91 of the ninth transistor T9 is greater than or equal to the doping concentration of the channel region 91-3 in the active pattern 91 of the ninth transistor T9.

[0154] In an exemplary embodiment Figure 8 The active pattern 41, control electrode 42, first electrode 43, and second electrode 44 of the fourth transistor are also shown. Figure 8 The fourth transistor can also be at least one of the following transistors: the third transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor. Figure 8 This is to illustrate the positional relationship between the control electrodes of the ninth transistor and the other P-type transistors besides the ninth transistor.

[0155] In an exemplary embodiment, the control electrode 92 of the ninth transistor T9 can be disposed on the same layer as the control electrode 42 of the fourth transistor. In this case, the thickness of the control electrode 92 of the ninth transistor T9 is less than the thickness of the control electrode 42 of the fourth transistor, or the control electrode 92 of the ninth transistor T9 can be located on the side of the control electrode 42 of the fourth transistor away from the substrate. Figure 8 This is illustrated by taking the example that the control electrode 92 of the ninth transistor T9 can be located on the side of the control electrode 42 of the fourth transistor that is far from the substrate.

[0156] In an exemplary embodiment, the ninth transistor T9 in this disclosure can be formed through the following process: forming an active pattern of the ninth transistor T9 on a substrate, lightly doping the active pattern of the ninth transistor, forming a first gate structure on the active pattern of the ninth transistor T9, heavily doping the active pattern of the ninth transistor T9, forming the gate electrode of the ninth transistor T9, and forming the first and second electrodes of the ninth transistor. The first gate structure includes the gate electrodes of the remaining P-type transistors other than the ninth transistor, and the orthographic projection of the first gate structure onto the substrate does not overlap with the orthographic projection of the active pattern of the ninth transistor T9 onto the substrate. Because the active pattern of the ninth transistor T9 is not blocked during heavy doping, ions can enter the channel region of the ninth transistor T9, thereby improving the mobility of the ninth transistor.

[0157] In an exemplary embodiment, the ninth transistor in this disclosure can be formed through the following process: forming an active pattern of the ninth transistor T9 on a substrate, lightly doping the active pattern of the ninth transistor, forming the gate electrodes of all P-type transistors on the active pattern of the ninth transistor T9, wherein the thickness of the gate electrode of the ninth transistor is less than the thickness of at least one gate electrode in the first gate structure, heavily doping the active pattern of the ninth transistor T9, forming the gate electrode of the ninth transistor T9, and forming the first and second electrodes of the ninth transistor. Since the thickness of the gate electrode of the ninth transistor is less than the thickness of at least one gate electrode in the first gate structure, when the active pattern of the ninth transistor T9 is heavily doped, some ions can enter the channel region of the ninth transistor T9, thereby improving the mobility of the ninth transistor.

[0158] In an exemplary embodiment, the ninth transistor in this disclosure can be formed through the following process: forming an active pattern of the ninth transistor T9 on a substrate, lightly doping the active pattern of the ninth transistor, forming a first gate structure on the active pattern of the ninth transistor T9, and heavily doping the active pattern of the ninth transistor T9 using a halftone mask, wherein the orthographic projection of the first gate structure on the substrate and the orthographic projection of the active pattern of the ninth transistor T9 on the substrate do not overlap. Because a halftone mask is used when heavily doping the active pattern of the ninth transistor T9, some ions can enter the channel region of the ninth transistor T9, thereby improving the mobility of the ninth transistor.

[0159] In an exemplary embodiment, after heavily doping the active pattern of the ninth transistor T9, it may include forming a control electrode 92, a first electrode 93, and a second electrode 94 of the ninth transistor. The first electrode 93 of the ninth transistor is electrically connected to a first region 91-1 of the active pattern of the ninth transistor, and the second electrode 94 of the ninth transistor is electrically connected to a second region 91-2 of the active pattern of the ninth transistor.

[0160] In an exemplary embodiment Figure 9 for Figure 7 The provided timing diagram for the pixel driving circuit is shown. Figure 9 As shown, in at least one display frame, the time period during which the signal of the second reset signal terminal Reset2 is an effective level signal includes: a first time period t1 and a second time period t2 with interval settings, wherein the first time period t1 occurs before the second time period t2.

[0161] In an exemplary implementation, such as Figure 9 As shown, the time period during which the signal of at least one of the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first reset signal terminal Reset1 is an effective level signal is located between the first time period t1 and the second time period t2.

[0162] In an exemplary implementation, such as Figure 9 As shown, the time periods during which the signal at the first scanning signal terminal Gate1 is an effective level signal include: a third time period t3 and a fourth time period t4 with intervals set. The third time period t3 occurs before the fourth time period t4, and the third time period t3 includes: multiple sub-time periods t30 with intervals set.

[0163] In an exemplary embodiment, the time period during which the signal at the first reset signal terminal Reset1 is at an active level overlaps at least partially with the time period during which the signal at the second scan signal terminal Gate2 is at an active level. For example, the start time of the time period during which the signal at the first reset signal terminal Reset1 is at an active level is earlier than the start time of the time period during which the signal at the second scan signal terminal Gate2 is at an active level, and the end time of the time period during which the signal at the first reset signal terminal Reset1 is at an active level is later than the start time of the time period during which the signal at the second scan signal terminal Gate2 is at an active level, but earlier than the end time of the time period during which the signal at the second scan signal terminal Gate2 is at an active level.

[0164] In an exemplary embodiment, the time period during which the signal at the first reset signal terminal Reset1 is at an active level overlaps at least partially with the third time period t3. For example, the start time of the third time period t3 is later than the start time of the time period during which the signal at the first reset signal terminal Reset1 is at an active level, and the end time of the third time period t3 is earlier than the start time of the time period during which the signal at the second scan signal terminal Gate2 is at an active level.

[0165] In an exemplary embodiment, the time period during which the signal at the second scan signal terminal Gate2 is at an active level overlaps at least partially with the fourth time period t4. For example, the start time of the fourth time period t4 is later than the end time of the time period during which the signal at the first reset signal terminal Reset1 is at an active level, and the end time of the fourth time period t4 is later than the end time of the time period during which the signal at the second scan signal terminal Gate2 is at an active level.

[0166] The pixel driving circuit in this disclosure is disposed in a display substrate. The display substrate may include a display area and a non-display area. The pixel driving circuit is located in the display area. The non-display area is provided with at least one driving circuit, which is configured to provide signals to a first reset signal terminal Reset1, a second reset signal terminal Reset2, a first scan signal terminal Gate1, a second scan signal terminal Gate2, and a light emission signal terminal EM connected to the pixel driving circuit.

[0167] The display substrate may include a first driving circuit, a second driving circuit, a third driving circuit, a fourth driving circuit, a fifth driving circuit, and a sixth driving circuit. The first driving circuit is configured to provide a signal to the light-emitting signal terminal of at least one pixel driving circuit; the second driving circuit is configured to provide a signal to the first scan signal terminal of at least one pixel driving circuit; the third driving circuit is configured to provide a signal to the second scan signal terminal of at least one pixel driving circuit; the fourth driving circuit is configured to provide a signal to the first reset signal terminal of at least one pixel driving circuit; and the fifth driving circuit is configured to provide a signal to the second reset signal terminal of at least one pixel driving circuit.

[0168] The following is through Figure 7 The operation of the example pixel driving circuit illustrates an exemplary embodiment of this disclosure. Figure 7 The pixel driving circuit includes nine transistors (first transistor T1 to ninth transistor T9) and two capacitors (first capacitor C1 and second capacitor C2). First transistor T1 and second transistor T2 are N-type transistors, and third transistor T3 to ninth transistor T9 are P-type transistors.

[0169] In an exemplary embodiment, combined with Figure 9 , Figure 7The operation of the provided pixel driving circuit may include:

[0170] In the first stage S1, also known as the initialization stage, the signals at the first reset signal terminal Reset1 and the second scan signal terminal Gate2 are low-level signals, while the signals at the first scan signal terminal Gate1 and the light emission signal terminal EM are high-level signals. The second reset signal terminal Reset2 is low-level for a portion of the time. The seventh transistor T7 and the eighth transistor T8 are turned on for a portion of the time, while the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the ninth transistor T9 are turned off.

[0171] When the seventh transistor T7 is turned on, the signal at the second initial signal terminal INIT2 is written to the fourth node N4 (which is also the anode of the light-emitting device L), initializing (resetting) the fourth node N4 (which is also the anode of the light-emitting device L), clearing its internal pre-stored voltage, and completing the initialization. When the eighth transistor T8 is turned on, the signal at the third initial signal terminal INIT3 is written to the second node N2, initializing (resetting) the second node N2, clearing its internal pre-stored voltage, and completing the initialization. When the third transistor T3 is turned on, the signal at the third initial signal terminal INIT3 is written to the third node N3 through the second node N2, initializing (resetting) the third node N3, clearing its internal pre-stored voltage, and completing the initialization.

[0172] In this stage, the voltage value V of the signal at the second node N2 N2 =Vinit3, the voltage value V of the signal at the third node N3. N3 =Vinit3, the voltage value V of the signal at the fourth node N4. N4 =Vinit2, where Vinit2 is the voltage value of the signal at the second initial signal terminal INIT2, and Vinit3 is the voltage value of the signal at the third initial signal terminal INIT3.

[0173] The second stage, S2, is called the reset stage. During this stage, the signal at the second scan signal terminal Gate2 is low, while the signals at the first reset signal terminal Reset1, the second reset signal terminal Reset2, and the light emission signal terminal EM are high. The first scan signal terminal Gate1 is low for multiple sub-time periods. The first transistor T1 is turned on, the fourth transistor T4 and the ninth transistor T9 are low for two sub-time periods, and the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off. Figure 9 This explanation uses two sub-time periods as an example.

[0174] When the first transistor T1 is turned on, the signal at the first initial signal terminal INIT1 is written to the fifth node N5, initializing (resetting) the fifth node N5 and clearing its internal pre-stored voltage, thus completing the initialization. When the ninth transistor T9 is turned on in the first sub-time period, the signal at the first initial signal terminal INIT1 is written to the first node N1 for the first time through the fifth node N5, initializing (resetting) the first node N1 and clearing its internal pre-stored voltage, thus completing the initialization. When the ninth transistor T9 is turned on in the second sub-time period, the signal at the first initial signal terminal INIT1 is written to the first node N1 for the second time through the fifth node N5, initializing (resetting) the first node N1 again and clearing its internal pre-stored voltage, thus completing the initialization. Since the second transistor T2 is turned off, in this stage, the second node N2 and the third node N3 still maintain the signals from the previous stage. At this time, the gate-source voltage difference of the third transistor T3 (i.e., the voltage difference between the signals of the first node N1 and the second node N2) is Vinit1-Vini3, where Vinit1 is the voltage value of the signal at the first initial signal terminal INIT1.

[0175] In this phase, the voltage value V of the signal at the first node N1 N1 =Vinit1, the voltage value V of the signal at the second node N2. N2 =Vinit3, the voltage value V of the signal at the third node N3. N3 =Vinit3, the voltage value V of the signal at the fourth node N4. N4 =Vinit2, the voltage value V of the signal at the fifth node N5. N5 =Vinit1.

[0176] The ninth transistor T9 in this disclosure is a low-temperature polycrystalline silicon thin-film transistor. Before the first sub-time period, the ninth transistor is affected by the voltage of the first node and the control electrode bias voltage. The potential of the first node is related to the data signal written in the previous display frame. That is, before the first sub-time period, the characteristics of the ninth transistor T9 are affected by the previous display frame. After the first sub-time period, the influence of the data signal written in the previous display frame on the characteristics of the ninth transistor T9 can be clearly seen. This disclosure initializes the first node N1 twice, in the first and second sub-time periods, which can better eliminate the influence of the data signal written in the previous display frame on the characteristics of the ninth transistor T9, improve image retention and low grayscale image quality of the display product, and effectively enhance the display effect of the display substrate.

[0177] The gate-source voltage difference of the third transistor T3 in this disclosure can improve the characteristics of the third transistor T3, thereby further improving the image retention of the display product.

[0178] The third stage, S3, is called the second initialization stage. The signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the first reset signal terminal Reset1, the second reset signal terminal Reset2, and the light emission signal terminal EM are all high-level signals. The first transistor T1 and the second transistor T2 are turned on, while the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned off.

[0179] When the first transistor T1 and the second transistor T2 are turned on, the signal at the first initial signal terminal INIT1 is written to the third node N3 through the fifth node N5, initializing (resetting) the third node N3 and the fifth node N5, clearing their internal pre-stored voltages, and completing the initialization. Since the ninth transistor T9 is turned off, the first node N1 retains the signal from the previous stage, and the ninth transistor T6 is turned off, so the fourth node N4 retains the signal from the previous stage.

[0180] In this phase, the voltage value V of the signal at the first node N1 N1 =Vinit1, the voltage value V of the signal at the second node N2. N2 =Vinit3, the voltage value V of the signal at the third node N3. N3 =Vinit1, the voltage value V of the signal at the fourth node N4. N4 =Vinit2, the voltage value V of the signal at the fifth node N5. N5 =Vinit1.

[0181] The fourth stage, S4, is called the threshold compensation and data writing stage. The signal at the first reset signal terminal (Reset1) is high, as are the signals at the second scan signal terminal (Gate2), the second reset signal terminal (Reset2), and the light emission signal terminal (EM). The first scan signal terminal (Gate1) is low for a portion of the time. The second transistor (T2) is turned on, and the fourth transistor (T4) and the ninth transistor (T9) are turned on for a portion of the time. The first transistor (T1), the fifth transistor (T5), the sixth transistor (T6), the seventh transistor (T7), and the eighth transistor (T8) are turned off.

[0182] When the second transistor T2 and the ninth transistor T9 are turned on, the first node N1, the third node N3, and the fifth node N5 are connected. When the fourth transistor T4 is turned on, the data signal on the data signal line Data continuously charges the first node N1 until the voltage value of the signal at the first node N1 is Vdata - |Vth|, where Vdata is the voltage value of the data signal and Vth is the threshold voltage of the third transistor T3. At this time, the voltage difference between the signals stored in the first capacitor C1 and the second capacitor C2 is Vdd - Vdata + |Vth|, where Vdd is the voltage value of the signal at the first power supply terminal VDD.

[0183] In this phase, the voltage value V of the signal at the first node N1 N1 =Vdata - |Vth|, the voltage value V of the signal at the second node N2. N2 =Vdata, the voltage value V of the signal at the third node N3. N3 =Vdata - |Vth|, the voltage value V of the signal at the fourth node N4. N4 =Vinit2, the voltage value V of the signal at the fifth node N5. N5 =Vdata-|Vth|.

[0184] The fifth stage, S5, is called the third initialization stage. The signals at the first reset signal terminal Reset1 and the second scan signal terminal Gate2 are low-level signals. The signals at the first scan signal terminal Gate1 and the light emission signal terminal EM are also low-level signals. The signal at the second reset signal terminal Reset2 is low-level for a portion of the time. The seventh transistor T7 and the eighth transistor T8 are turned on for a portion of the time, while the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the ninth transistor T9 are turned off.

[0185] When the seventh transistor T7 is turned on, the signal from the second initial signal terminal INIT2 is written to the fourth node N4 (which is also the anode of the light-emitting device L), initializing (resetting) the fourth node N4 (which is also the anode of the light-emitting device L), clearing its internal pre-stored voltage, and completing the initialization. When the eighth transistor T8 is turned on, the signal from the third initial signal terminal INIT3 is written to the second node N2, initializing (resetting) the second node N2, clearing its internal pre-stored voltage, and completing the initialization. When the third transistor T3 is turned on, the signal from the third initial signal terminal INIT3 is written to the third node N3 through the second node N2, initializing (resetting) the third node N3, clearing its internal pre-stored voltage, and completing the initialization. Since the second transistor T2 is turned off, the first node N1 and the fifth node N5 are the signals from the previous stage.

[0186] In this phase, the voltage value V of the signal at the first node N1 N1 =Vdata - |Vth|, the voltage value V of the signal at the second node N2. N2 =Vinit3, the voltage value V of the signal at the third node N3. N3 =Vinit3, the voltage value V of the signal at the fourth node N4. N4 =Vinit2, the voltage value V of the signal at the fifth node N5. N5 =Vdata-|Vth|.

[0187] In the sixth stage, S6, also known as the light-emitting stage, the signals at the first reset signal terminal Reset1, the second scan signal terminal Gate2, and the light-emitting signal terminal EM are low-level signals, while the signals at the first scan signal terminal Gate1 and the second reset signal terminal Reset2 are high-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned off.

[0188] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power signal output from the first power supply terminal VDD provides a driving voltage to the fourth node N4 (which is also the first terminal of the light-emitting device L) through the turned-on fifth transistor T5, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0189] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and its first electrode. The voltage value V of the signal at the first node N1 is... N1 =Vdata - |Vth|, the voltage value V of the signal at the second node N2. N2 =Vdd. Therefore, the drive current of the third transistor T3 is:

[0190] I = K * (Vsg - Vth) 2

[0191] =K*(V N2 -V N1- |Vth|) 2

[0192] =K*[Vdd-Vdata+|Vth|-Vth] 2

[0193] =K*(Vdd-Vdata) 2

[0194] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the light-emitting device L, and K is a constant.

[0195] As can be seen from the derivation of the above current formula, during the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current. This ensures uniform display brightness of the display product and improves the overall display effect of the display product.

[0196] This disclosure also provides a method for driving a pixel driving circuit, configured to drive the pixel driving circuit provided in any of the foregoing embodiments. The method for driving the pixel driving circuit may include the following steps:

[0197] Step S101: The driving sub-circuit provides a driving signal to the third node under the control of the signals from the first and second nodes.

[0198] Step S102: Under the control of the signal at the first scanning signal terminal, the first control sub-circuit connects the first node and the fifth node, and stores the voltage difference between the signals at the first node and the first power supply terminal, as well as the voltage difference between the signals at the fifth node and the first power supply terminal.

[0199] Step S103: Under the control of the signals from the first reset signal terminal and the second scan signal terminal, the second control sub-circuit provides the signal from the first initial signal terminal or the signal from the third node to the fifth node.

[0200] Step S104: Under the control of the signals from the first scan signal terminal and the second reset signal terminal, the third control sub-circuit provides the data signal terminal or the third initial signal terminal to the second node, and provides the second initial signal terminal to the fourth node.

[0201] Step S105: Under the control of the signal at the light-emitting signal terminal, the fourth control sub-circuit provides the signal from the first power supply terminal to the second node and the signal from the third node to the fourth node.

[0202] Figure 10 This is a schematic diagram of the structure of a display substrate provided in an embodiment of this disclosure. Figure 11 for Figure 10 A partial schematic diagram of the membrane layers. (See attached diagram.) Figure 10 and Figure 11 As shown, this disclosure also provides a display substrate including: a substrate (not shown in the figure) and a plurality of pixel driving circuits and a plurality of first scan signal lines GL1 provided in any of the foregoing embodiments disposed on the substrate. The pixel driving circuit includes: at least one P-type transistor, and the at least one P-type transistor includes: a fourth transistor T4 and a ninth transistor T9.

[0203] like Figure 10 and Figure 11 As shown, at least one of the multiple first scan signal lines GL1 is electrically connected to the control electrode 42 of the fourth transistor and the control electrode 92 of the ninth transistor in at least one pixel driving circuit, and at least one of the multiple first scan signal lines GL1 extends at least partially along the first direction D1.

[0204] like Figure 10 and Figure 11As shown, the control electrode 42 of the fourth transistor in at least one pixel driving circuit is located on the side near the substrate of the multiple first scan signal lines GL1 and the control electrode 92 of the ninth transistor in at least one pixel driving circuit.

[0205] In an exemplary embodiment, a portion of at least one of the plurality of first scan signal lines GL1 can serve as the control electrode 92 of the ninth transistor in at least one pixel driving circuit.

[0206] In an exemplary implementation, such as Figure 10 and Figure 11 As shown, adjacent pixel driving circuits located in the same row are symmetrically arranged with respect to virtual pixels extending along the second direction D2. The adjacent driving circuits in at least one pixel driving circuit located in the same row include: a first adjacent pixel driving circuit and a second adjacent pixel driving circuit.

[0207] In an exemplary implementation, such as Figure 11 As shown, the orthographic projection of at least one of the multiple first scan signal lines GL1 onto the substrate at least partially overlaps with the orthographic projection of the control electrode 42 of the fourth transistor in at least one pixel driving circuit onto the substrate.

[0208] In an exemplary implementation, such as Figure 10 and Figure 11 As shown, the display substrate may further include: multiple light-emitting signal lines EL and multiple second reset signal lines RL2 disposed on the substrate; at least one P-type transistor further includes: a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8.

[0209] In an exemplary embodiment, at least one of the plurality of light-emitting signal lines EL is electrically connected to the control electrode of the fifth transistor and the control electrode of the sixth transistor in at least one pixel driving circuit, and at least one of the plurality of second reset signal lines RL2 is electrically connected to the control electrode of the seventh transistor and the control electrode of the eighth transistor in at least one pixel driving circuit.

[0210] In an exemplary embodiment, at least one of the plurality of light-emitting signal lines EL and the plurality of second reset signal lines RL2 extends at least partially along the first direction D1.

[0211] In an exemplary embodiment, the control electrode of at least one of the following transistors in a pixel driving circuit—the plurality of light-emitting signal lines EL, the plurality of second reset signal lines RL2, and the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8—is disposed on the same layer as the control electrode 42 of the fourth transistor.

[0212] In an exemplary implementation, such as Figure 10 and Figure 11 As shown, the display substrate may further include: multiple first reset signal lines RL1 and multiple second scan signal lines GL2 disposed on the substrate. The pixel driving circuit includes: at least one N-type transistor, and the at least one N-type transistor further includes: a first transistor T1 and a second transistor T2.

[0213] In an exemplary embodiment, at least one of the plurality of first reset signal lines RL1 is electrically connected to the control electrode of a first transistor in at least one pixel driving circuit, and at least one of the plurality of second scan signal lines GL2 is electrically connected to the control electrode of a second transistor in at least one pixel driving circuit.

[0214] In an exemplary embodiment, at least one of the plurality of first reset signal lines RL1 and the plurality of second scan signal lines GL2 extends at least partially along a first direction D1.

[0215] In an exemplary implementation, such as Figure 10 and Figure 11 As shown, at least one of the multiple first reset signal lines RL1 and multiple second scan signal lines GL2 is located on the side of the multiple light emission signal lines EL and multiple second reset signal lines RL2 that is away from the substrate.

[0216] In an exemplary implementation, such as Figure 11 As shown, the orthographic projections of the active pattern 41 of the fourth transistor and the active pattern 91 of the ninth transistor of at least one pixel driving circuit onto the substrate at least partially overlap with the orthographic projections of at least one of the first scan signal line GL1 and the second scan signal line GL2 onto the substrate.

[0217] In an exemplary implementation, such as Figure 10 and Figure 11 As shown, the first reset signal line RL1, the first scan signal line GL1, the second scan signal line GL2, the light emission signal line EL, and the second reset signal line RL2, connected to at least one pixel driving circuit, are sequentially arranged along the second direction D2 by their orthogonal projections on the substrate. The first direction D1 and the second direction D2 intersect; exemplarily, the first direction D1 and the second direction D2 can be perpendicularly intersecting.

[0218] In an exemplary implementation, such as Figure 10 and Figure 11 As shown, the display substrate may further include: multiple first initial signal lines INITL1, multiple second initial signal lines INITL2, and multiple third initial signal lines INITL3 disposed on the substrate.

[0219] In an exemplary implementation, such as Figure 10 and Figure 11 As shown, at least one of the plurality of first initial signal lines INITL1, the plurality of second initial signal lines INITL2, and the plurality of third initial signal lines INITL3 extends at least partially along the first direction D1.

[0220] In an exemplary implementation, such as Figure 10 and Figure 11 As shown, the orthographic projection of the first initial signal line INITL1 connected to at least one pixel driving circuit on the substrate is located on the side where the orthographic projection of the first reset signal line RL1 on the substrate is far from the orthographic projection of the first scan signal line GL1 on the substrate.

[0221] In an exemplary implementation, such as Figure 10 and Figure 11 As shown, the orthographic projection of the second initial signal line INITL2, which is connected to at least one pixel driving circuit, on the substrate is located on the side where the orthographic projection of the second reset signal line RL2 on the substrate is far from the orthographic projection of the light emission signal line EL on the substrate.

[0222] In an exemplary implementation, such as Figure 10 and Figure 11 As shown, at least a portion of the orthographic projection of the third initial signal line INITL3 connected to at least one pixel driving circuit on the substrate overlaps at least a portion of the orthographic projection of the second reset signal line RL2 on the substrate, and is located between the orthographic projection of the light emission signal line EL on the substrate and the orthographic projection of the second initial signal line INITL2 on the substrate.

[0223] In an exemplary implementation, such as Figure 11 As shown, at least one first reset signal line RL1 includes: a first reset connection line RL11 and a second reset connection line RL12, which are disposed on different layers and interconnected. The orthographic projection of the first reset connection line RL11 on the substrate at least partially overlaps with the orthographic projection of the second reset connection line RL12 on the substrate, and the first reset connection line RL11 of the at least one first reset signal line RL1 is located on the side of the second reset connection line RL12 closer to the substrate.

[0224] In an exemplary implementation, such as Figure 11 As shown, at least one second scan signal line GL2 includes: a first scan connection line GL21 and a second scan connection line GL22 that are disposed on different layers and interconnected. The orthographic projection of the first scan connection line GL21 on the substrate of at least one second scan signal line GL2 at least partially overlaps with the orthographic projection of the second scan connection line GL22 on the substrate, and the first scan connection line GL21 of at least one second scan signal line GL2 is located on the side of the second scan connection line GL22 closer to the substrate.

[0225] In an exemplary embodiment, the control electrode of at least one N-type transistor includes: a first control electrode and a second control electrode.

[0226] In an exemplary embodiment, the display substrate may further include: a circuit structure layer disposed on the substrate, the circuit structure layer including: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, and a fourth conductive layer.

[0227] In an exemplary embodiment, the first conductive layer includes at least: a plurality of first initial signal lines INITL1, a plurality of light emission signal lines EL, a plurality of second reset signal lines RL2, and the control electrode of at least one of the third transistors T3 to the eighth transistor T8 located in at least one pixel driving circuit.

[0228] In an exemplary embodiment, the second conductive layer includes at least: a plurality of first scan signal lines GL1, a first reset connection line RL11 of a plurality of first reset signal lines RL1, a first scan connection line GL21 of a plurality of second scan signal lines GL2, and a control electrode of a ninth transistor T9 and a first control electrode of at least one N-type transistor (e.g., the first control electrode of the first transistor T1 and the first control electrode of the second transistor T2) located in at least one pixel driving circuit.

[0229] In an exemplary embodiment, the third conductive layer includes at least: multiple second initial signal lines INITL2, multiple third initial signal lines INITL3, multiple first reset signal lines RL1 second reset connection lines RL12, multiple second scan signal lines GL2 second scan connection lines GL22, and at least one second control electrode (e.g., the second control electrode of the first transistor T1 and the second control electrode of the second transistor T2) located in at least one pixel driving circuit.

[0230] In an exemplary embodiment, the fourth conductive layer includes at least: a first electrode and a second electrode of at least one transistor located in at least one pixel driving circuit.

[0231] In an exemplary embodiment, the control electrode of the ninth transistor T9 in at least one pixel driving circuit may also be disposed on at least one film layer of the second conductive layer on the side away from the substrate. Exemplarily, the control electrode of the ninth transistor T9 in at least one pixel driving circuit may also be disposed on a third conductive layer, or it may be disposed on a fourth conductive layer.

[0232] In an exemplary embodiment, the circuit structure layer may further include a fifth conductive layer located on the side of the fourth conductive layer away from the substrate. The fifth conductive layer may include at least a plurality of first power lines and a plurality of data signal lines.

[0233] In an exemplary embodiment, at least one of the plurality of first power lines is electrically connected to a first power terminal in at least one pixel driving circuit, and at least one of the plurality of data signal lines is electrically connected to a data signal terminal in at least one pixel driving circuit.

[0234] In an exemplary embodiment, at least one of the plurality of first power lines and plurality of data signal lines extends at least partially along a second direction.

[0235] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0236] Figures 12 to 23 A schematic diagram of the fabrication process of a display substrate provided for an exemplary embodiment. Figures 12 to 23 This explanation uses a four-column pixel driving circuit as an example.

[0237] The following is based on... Figures 12 to 23 As shown, the fabrication process of the display substrate provided in this disclosure may include:

[0238] (1) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming a first semiconductor layer pattern may include: depositing a first semiconductor thin film on a substrate, and patterning the first semiconductor thin film using a patterning process to form a first semiconductor layer pattern, such as... Figure 12 As shown, Figure 12 This is a schematic diagram of the pattern of the first semiconductor layer.

[0239] In an exemplary implementation, such as Figure 12 As shown, the first semiconductor layer pattern may include at least: an active pattern of at least one P-type transistor located in at least one pixel driving circuit. Figure 12 The following description uses at least one P-type transistor with active patterns including: active pattern 31 of the third transistor, active pattern 41 of the fourth transistor, active pattern 51 of the fifth transistor, active pattern 61 of the sixth transistor, active pattern 71 of the seventh transistor, active pattern 81 of the eighth transistor, and active pattern 91 of the ninth transistor as an example.

[0240] In an exemplary embodiment, the active pattern of at least one P-type transistor of at least one pixel driving circuit located in the same row is symmetrically arranged with respect to the active pattern of at least one P-type transistor of an adjacent sub-pixel with respect to a virtual straight line extending along the second direction D2.

[0241] In an exemplary embodiment, for at least one pixel driving circuit, the active patterns 31 of the third transistor, 41 of the fourth transistor, 51 of the fifth transistor, 61 of the sixth transistor, and 71 of the seventh transistor are integrally formed. The active patterns 81 of the eighth transistor and 91 of the ninth transistor are separately configured.

[0242] In an exemplary embodiment, in the first direction D1, the active patterns 41 of the fourth transistor and 51 of the fifth transistor of at least one column of pixel driving circuits are located on the side of the active pattern 31 of the third transistor of the same column of pixel driving circuits near the previous column of pixel driving circuits, and the active pattern 61 of the sixth transistor of at least one column of pixel driving circuits is located on the side of the active pattern 31 of the third transistor of the same column of pixel driving circuits near the next column of pixel driving circuits. In the second direction D2, the active patterns 41 of the fourth transistor and 91 of the ninth transistor of at least one row of pixel driving circuits are located on the side of the active pattern 31 of the third transistor of the same row of pixel driving circuits near the previous row of pixel driving circuits, and the active patterns 51, 61, 71, and 81 of the fifth transistor, sixth transistor, seventh transistor, and eighth transistor of at least one row of pixel driving circuits are near the side of the next row of pixel driving circuits.

[0243] In an exemplary embodiment, the active pattern 31 of the third transistor may be in the shape of an inverted “Ω”.

[0244] In an exemplary embodiment, the active pattern 41 of the fourth transistor, the active pattern 51 of the fifth transistor, the active pattern 71 of the seventh transistor, and the active pattern 91 of the ninth transistor can be in the shape of an "I".

[0245] In an exemplary embodiment, the active pattern 61 of the sixth transistor and the active pattern 81 of the eighth transistor can be in the shape of a horizontally flipped "L".

[0246] In an exemplary embodiment, the active pattern of each transistor may include a first region, a second region, and a channel region located between the first region and the second region.

[0247] In an exemplary embodiment, for at least one pixel driving circuit, the first region 31-1 of the active pattern 31 of the third transistor can simultaneously serve as the second region 41-2 of the active pattern 41 of the fourth transistor and the second region 51-2 of the active pattern 51 of the fifth transistor. The second region 31-2 of the active pattern 31 of the third transistor can simultaneously serve as the first region 61-1 of the active pattern 61 of the sixth transistor. The first region 41-1 of the active pattern 41 of the fourth transistor, the first region 51-1 of the active pattern 51 of the fifth transistor, the first region 71-1 of the active pattern 71 of the seventh transistor, the first region 81-1 and the second region 81-2 of the active pattern 81 of the eighth transistor, and the first region 91-1 and the second region 91-2 of the active pattern 91 of the ninth transistor can be configured individually.

[0248] In an exemplary embodiment, the first region 51-1 of the active pattern 51 of the fifth transistor in at least one pixel driving circuit and the first region 81-1 of the active pattern 81 of the eighth transistor are arranged along the second direction D2.

[0249] In an exemplary embodiment, the first region 51-1 of the active pattern 51 of the fifth transistor of at least one pixel driving circuit is the same region as the first region 51-1 of the active pattern 51 of the fifth transistor of the first adjacent pixel driving circuit, and the first region 81-1 of the active pattern 81 of the eighth transistor of at least one pixel driving circuit is the same region as the first region 81-1 of the active pattern 81 of the eighth transistor of the first adjacent pixel driving circuit.

[0250] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a first insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; and patterning the first insulating film and the first conductive film using a patterning process to form a first insulating layer pattern and a first conductive layer pattern located on the first insulating layer, such as... Figure 13 and Figure 14 As shown, where, Figure 13 This is a schematic diagram of the pattern of the first conductive layer. Figure 14 This is a schematic diagram showing the formation of the first conductive layer pattern. In an exemplary embodiment, the first conductive layer may be referred to as the first gate metal (GATE1) layer.

[0251] In an exemplary implementation, such as Figure 13 and Figure 14 As shown, the first conductive layer pattern may include: a light-emitting signal line EL, a second reset signal line RL2, a first initial signal line INITL1, and the control electrode of at least one P-type transistor located in at least one pixel driving circuit and the first plate C11 of the first capacitor. Wherein, Figure 13 The following explanation is based on an example of at least one P-type transistor, including the control electrode 32 of the third transistor, the control electrode 42 of the fourth transistor, the control electrode 52 of the fifth transistor, the control electrode 62 of the sixth transistor, the control electrode 72 of the seventh transistor, and the control electrode 82 of the eighth transistor.

[0252] In an exemplary embodiment, the control electrode of at least one P-type transistor of at least one pixel driving circuit located in the same row and the first plate C11 of the first capacitor of the first P-type transistor of at least one pixel driving circuit of the adjacent sub-pixel are symmetrically arranged with respect to a virtual straight line extending along the second direction D2.

[0253] In an exemplary embodiment, the control electrode 42 of the fourth transistor in at least one pixel driving circuit is the same electrode as the control electrode 42 of the fourth transistor in the first adjacent pixel driving circuit.

[0254] In an exemplary embodiment, for at least one row of sub-pixels, the first initial signal line INITL1, the light emission signal line EL, and the second reset signal line RL2 connected to the pixel driving circuit are arranged sequentially along the second direction D2.

[0255] In an exemplary embodiment, the first initial signal line INITL1 connected to at least one row of pixel driving circuits is located on the side of the first plate C11 of the first capacitor of the pixel driving circuit that is close to the previous row of pixel driving circuits.

[0256] In an exemplary embodiment, the shape of the first initial signal line INITL1 can be a line shape in which the main body extends along the first direction D1.

[0257] In an exemplary embodiment, the light-emitting signal line EL and the second reset signal line RL2 connected to at least one row of pixel driving circuits are located on the side of the first plate C11 of the first capacitor of the pixel driving circuit closer to the next row of pixel driving circuits, and the second reset signal line RL2 connected to at least one row of pixel driving circuits is located on the side of the light-emitting signal line EL connected to at least one row of pixel driving circuits away from the first plate C11 of the first capacitor of the pixel driving circuit.

[0258] In an exemplary embodiment, the shape of the light-emitting signal line EL can be a line shape in which the main body extends along the first direction D1. The area where the light-emitting signal line EL connected to at least one pixel driving circuit overlaps with the active pattern of the fifth transistor can be the control electrode 52 of the fifth transistor, and the area where the light-emitting signal line EL connected to at least one pixel driving circuit overlaps with the active pattern of the sixth transistor can be the control electrode 62 of the sixth transistor.

[0259] In an exemplary embodiment, the shape of the second reset signal line RL2 can be a line shape in which the main body extends along the first direction D1. The area where the second reset signal line RL2 connected to at least one pixel driving circuit overlaps with the active pattern of the seventh transistor can be the control electrode 72 of the seventh transistor, and the area where the second reset signal line RL2 connected to at least one pixel driving circuit overlaps with the active pattern of the eighth transistor can be the control electrode 82 of the eighth transistor.

[0260] In an exemplary embodiment, the first plate C11 of the first capacitor in at least one pixel driving circuit can be rectangular in shape, and the corners of the rectangle can be chamfered. Exemplarily, the first plate C11 of the first capacitor can serve as the control electrode 32 of the third transistor.

[0261] In an exemplary embodiment, the control electrode 42 of the fourth transistor in at least one pixel driving circuit can be provided separately. The control electrode 42 of the fourth transistor can be strip-shaped and at least partially extends along the first direction.

[0262] In an exemplary embodiment, the light-emitting signal line EL, the second reset signal line RL2, and the first initial signal line INITL1 can be designed with equal width or with non-equal width, and can be straight lines or broken lines. This not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines. This disclosure does not limit the scope of the invention.

[0263] In an exemplary embodiment, after the first conductive layer pattern is formed, the first conductive layer can be used as a shield to conduct the first semiconductor layer. The first semiconductor layer in the area shielded by the first conductive layer is referred to as the channel region of the third transistor, fourth transistor, fifth transistor, sixth transistor, seventh transistor, and eighth transistor. The first semiconductor layer in the area not shielded by the first conductive layer is conducted.

[0264] In an exemplary embodiment, since the first conductive layer pattern does not include the gate electrode of the ninth transistor, when performing ion doping on a semiconductor layer, the mobility of the ninth transistor channel can be adjusted by adjusting the concentration of dopant ions. For example, the ion doping concentration can be increased so that the mobility of the active pattern of the ninth transistor is greater than the mobility of the channel region of at least one of the third, fourth, fifth, sixth, seventh, and eighth transistors. Alternatively, the mobility of the ninth transistor can be improved by, for example, by doping to make the entire active pattern of the ninth transistor conductive.

[0265] In an exemplary embodiment, the control electrode of the third transistor is disposed across the active pattern of the third transistor, the control electrode of the fourth transistor is disposed across the active pattern of the fourth transistor, the control electrode of the fifth transistor is disposed across the active pattern of the fifth transistor, the control electrode of the sixth transistor is disposed across the active pattern of the sixth transistor, the control electrode of the seventh transistor is disposed across the active pattern of the seventh transistor, and the control electrode of the eighth transistor is disposed across the active pattern of the eighth transistor. That is, the extension direction of the control electrode of at least one transistor is perpendicular to the extension direction of the active pattern.

[0266] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a second insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed, and patterning the second insulating film and the second conductive film using a patterning process to form a second insulating layer pattern and a second conductive layer pattern located on the second insulating layer. Figure 15 and Figure 16 As shown, Figure 15 This is a schematic diagram of the pattern of the second conductive layer. Figure 16 This is a schematic diagram showing the formation of the second conductive layer pattern. In an exemplary embodiment, the second conductive layer may be referred to as the second gate metal (GATE2) layer.

[0267] In an exemplary implementation, such as Figure 15 and Figure 16 As shown, the second conductive layer pattern may include: a first scan signal line GL1, a first reset connection line RL11 of a first reset signal line, a first scan connection line GL21 of a second scan signal line, a second electrode C12 of a first capacitor located in at least one pixel driving circuit, a control electrode 92 of a ninth transistor, and a first control electrode of at least one N-type transistor. The first control electrode of the at least one N-type transistor may include: a first control electrode 12A of a first transistor and a first control electrode 22A of a second transistor.

[0268] In an exemplary embodiment, the second plate C12 of the first capacitor, the control electrode 92 of the ninth transistor, and the first control electrode of the at least one N-type transistor in the at least one pixel driving circuit are symmetrically arranged with respect to the virtual straight line extending along the second direction D2 of the adjacent sub-pixel with respect to the second plate C12 of the first capacitor, the control electrode 92 of the ninth transistor, and the first control electrode of the at least one N-type transistor in the at least one pixel driving circuit.

[0269] In an exemplary embodiment, the first reset connection line RL11 of the first reset signal line, the first scan signal line GL1, and the first scan connection line GL21 of the second scan signal line, which are connected to at least one pixel driving circuit, are arranged sequentially along the second direction D2.

[0270] In an exemplary embodiment, the orthographic projection of at least one of the first reset connection line RL11 of the first reset signal line, the first scan signal line GL1, and the first scan connection line GL21 of the second scan signal line connected to at least one pixel driving circuit is located between the orthographic projection of the first initial signal line on the substrate and the orthographic projection of the light emission signal line on the substrate.

[0271] In an exemplary embodiment, the orthographic projection of the first reset connection line RL11 of the first reset signal line connected to at least one pixel driving circuit on the substrate is located between the orthographic projection of the first initial signal line on the substrate and the orthographic projection of the first scan signal line GL1 on the substrate, and the orthographic projection of the first scan connection line GL21 of the second scan signal line connected to at least one pixel driving circuit on the substrate is located between the orthographic projection of the light emission signal line on the substrate and the orthographic projection of the first scan signal line GL1 on the substrate.

[0272] In an exemplary embodiment, the shape of the first reset connection line RL11 of the first reset signal line can be a line shape in which the main body extends along the first direction D1. The area where the first reset connection line RL11 of the first reset signal line intersects with the active pattern of the first transistor can be the first control electrode 12A of the first transistor.

[0273] In an exemplary embodiment, the shape of the first scan connection line GL21 of the second scan signal line can be a line shape in which the main body extends along the first direction D1. The area where the first scan connection line GL21 of the second scan signal line intersects with the active pattern of the second transistor can be the first control electrode 22A of the second transistor.

[0274] In an exemplary embodiment, the shape of the first scan signal line GL1 connected to at least one pixel driving circuit can be a line shape in which the main body extends along the first direction D1. The area where the first scan signal line GL1 connected to at least one pixel driving circuit intersects with the active pattern of the ninth transistor can be the control electrode 92 of the ninth transistor.

[0275] In an exemplary embodiment, the orthographic projection of the first scan signal line GL1 connected to at least one pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the control electrode of the fourth transistor on the substrate. Exemplarily, the orthographic projection of the first scan signal line GL1 connected to at least one pixel driving circuit on the substrate covers the channel region of the active pattern of the fourth transistor.

[0276] In an exemplary embodiment, the main outline of the second electrode C12 of the first capacitor can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the main body of the second electrode C12 on the substrate at least partially overlaps with the orthographic projection of the first electrode of the first capacitor on the substrate. The second electrode C12 of the first capacitor is provided with an opening V, which can be rectangular in shape and located in the middle of the second electrode C12, so that the second electrode C12 of the first capacitor forms a ring structure. The opening V exposes the second insulating layer covering the first electrode of the first capacitor, and the orthographic projection of the first electrode of the first capacitor on the substrate covers the orthographic projection of the opening V on the substrate. In the exemplary embodiment, the opening V exposes the first electrode of the first capacitor, so that the first electrode of the subsequently formed second transistor is connected to the first electrode of the first capacitor.

[0277] In an exemplary embodiment, the second plate C12 of the first capacitor of the adjacent pixel driving circuit located in the same row is electrically connected.

[0278] In an exemplary embodiment, the first initial signal line INIT1 and the first scan line Gate2A of the second scan signal line Gate2 can be designed with equal width or with non-equal width, and can be straight lines or broken lines. This not only facilitates the layout of the pixel structure for the first scan signal line GL1, the first reset connection line RL11 of the first reset signal line, and the first scan connection line GL21 of the second scan signal line, but also reduces the parasitic capacitance between the signal lines. This disclosure does not limit the scope of the invention.

[0279] (4) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming the second semiconductor layer pattern may include: on the substrate on which the aforementioned pattern is formed, including: sequentially depositing a third insulating film and a second semiconductor film on the substrate, and patterning the third insulating film and the second semiconductor film through a patterning process to form a third insulating layer pattern and a second semiconductor layer pattern located on the third insulating layer, such as... Figure 17and Figure 18 As shown, Figure 17 This is a schematic diagram of the pattern of the second semiconductor layer. Figure 18 This is a schematic diagram after the second semiconductor layer pattern has been formed.

[0280] In an exemplary implementation, such as Figure 17 and Figure 18 As shown, the second semiconductor layer pattern may include: an active pattern of at least one N-type transistor located in at least one pixel driving circuit. The active pattern of the at least one N-type transistor includes: an active pattern 11 of a first transistor and an active pattern 21 of a second transistor.

[0281] In an exemplary embodiment, the active pattern of at least one N-type transistor in at least one pixel driving circuit located in the same row is symmetrically arranged with respect to the active pattern of at least one N-type transistor in at least one adjacent pixel driving circuit with respect to a virtual straight line extending along the second direction D2.

[0282] In an exemplary embodiment, the active pattern 11 of the first transistor and the active pattern 21 of the second transistor are an integral structure.

[0283] In an exemplary embodiment, the active pattern 11 of the first transistor and the active pattern 21 of the second transistor are in the shape of an "I" and are arranged along the second direction D2.

[0284] In an exemplary embodiment, the active pattern of each transistor may include a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, for at least one pixel driving circuit, the second region 11-2 of the first transistor may serve as the first region 21-1 of the second transistor, and the first region 11-1 of the active pattern of the first transistor and the second region 21-2 of the active pattern 21 of the second transistor are configured separately.

[0285] In an exemplary embodiment, the active pattern 11 of the first transistor is disposed across the first control electrode of the first transistor, and the active pattern 21 of the second transistor is disposed across the first control electrode of the second transistor.

[0286] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming a second semiconductor layer pattern may include: sequentially depositing a fourth insulating film and a third conductive film on a substrate on which the aforementioned pattern is formed, and patterning the fourth insulating film and the third conductive film using a patterning process to form a fourth insulating layer pattern and a third conductive layer pattern located on the fourth insulating layer. Figure 19 and Figure 20 As shown, Figure 19 This is a schematic diagram of the pattern of the third conductive layer. Figure 20This is a schematic diagram showing the formation of the third conductive layer pattern. In an exemplary embodiment, the third conductive layer may be referred to as the third gate metal (GATE3) layer.

[0287] In an exemplary implementation, such as Figure 19 and Figure 20 As shown, the third conductive layer pattern may include: a second scan connection line GL22 of the second scan signal line Gate2, a second reset connection line RL12 of the first reset signal line, a second initial signal line INITL2, a third initial signal line INITL3, and a second control electrode of at least one N-type transistor located in at least one pixel driving circuit. The first control electrode of at least one N-type transistor may include: a second control electrode 12B of the first transistor and a second control electrode 22B of the second transistor.

[0288] In an exemplary embodiment, the second control electrode of at least one N-type transistor in at least one pixel driving circuit located in the same row is symmetrically arranged with respect to the second control electrode of at least one N-type transistor in at least one adjacent sub-pixel with respect to a virtual straight line extending along the second direction D2.

[0289] In an exemplary embodiment, the second reset connection line RL12 of the first reset signal line, the second scan connection line GL22 of the second scan signal line Gate2, the third initial signal line INITL3, and the second initial signal line INITL2 connected to at least one pixel driving circuit are arranged sequentially along the second direction D2.

[0290] In an exemplary embodiment, the shape of the second reset connection line RL12 of the first reset signal line to which at least one pixel driving circuit is connected can be a line shape in which the main part extends along the first direction D1. The orthographic projection of the second reset connection line RL12 of the first reset signal line to which at least one pixel driving circuit is connected on the substrate at least partially overlaps with the orthographic projection of the first reset connection line of the first reset signal line to which at least one pixel driving circuit is connected on the substrate. The area where the second reset connection line RL12 of the first reset signal line to which at least one pixel driving circuit is connected overlaps with the active pattern of the first transistor can serve as the second control electrode 12B of the first transistor.

[0291] In an exemplary embodiment, the shape of the second scan connection line GL22 of the second scan signal line to which at least one pixel driving circuit is connected can be a line shape in which the main body extends along the first direction D1. The orthographic projection of the second scan connection line GL22 of the second scan signal line to which at least one pixel driving circuit is connected on the substrate at least partially overlaps with the orthographic projection of the first scan connection line of the second scan signal line to which at least one pixel driving circuit is connected on the substrate. The area where the second scan connection line GL22 of the second scan signal line to which at least one pixel driving circuit is connected overlaps with the active pattern of the second transistor can serve as the second control electrode 22B of the second transistor.

[0292] In an exemplary embodiment, the shape of the third initial signal line INITL3 can be a line shape in which the main body extends along the first direction D1. At least a portion of the orthographic projection of the third initial signal line INITL3 connected to at least one pixel driving circuit on the substrate overlaps at least partially with the orthographic projection of the second reset signal line on the substrate, and is located between the orthographic projection of the light emission signal line on the substrate and the orthographic projection of the second initial signal line INITL2 on the substrate.

[0293] In an exemplary embodiment, the shape of the second initial signal line INITL2 can be a line shape in which the main body extends along the first direction D1. The orthographic projection of the second initial signal line INITL2, to which at least one pixel driving circuit is connected, is located on the side of the orthographic projection of the third initial signal line INITL3 on the substrate that is away from the orthographic projection of the light-emitting signal line on the substrate.

[0294] In an exemplary embodiment, the second scan connection line GL22 of the second scan signal line Gate2, the second reset connection line RL12 of the first reset signal line, the second initial signal line INITL2, and the third initial signal line INITL3 can be designed with equal width or with non-equal width, and can be straight lines or broken lines. This not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between signal lines. This disclosure does not limit the scope of the invention.

[0295] (6) Forming a fifth insulating layer pattern includes: depositing a fifth insulating film on a substrate having the aforementioned pattern, and patterning the fifth insulating film using a patterning process to form a fifth insulating layer pattern covering the aforementioned pattern. The fifth insulating layer has multiple via patterns, such as... Figure 21 As shown, Figure 21 This is a schematic diagram showing the formation of the fifth insulating layer pattern.

[0296] In an exemplary implementation, such as Figure 21 As shown, the plurality of vias in the fifth insulating layer pattern include at least: a first via V1 to a twentieth via V20 located in at least one pixel driving circuit.

[0297] In an exemplary embodiment, the first vias V1 to V19 of at least one pixel driving circuit located in the same row are symmetrically arranged with respect to the first vias V1 to V19 of at least one adjacent pixel driving circuit with respect to a virtual straight line extending along the second direction D2.

[0298] In an exemplary embodiment, the fourth via V4 exposed in at least one pixel driving circuit is the same via as the fourth via V4 exposed in the first adjacent pixel driving circuit, the eighth via V8 exposed in at least one pixel driving circuit is the same via as the eighth via V8 exposed in the first adjacent pixel driving circuit, and the fifteenth via V15 exposed in at least one pixel driving circuit is the same via as the fifteenth via V15 exposed in the first adjacent pixel driving circuit.

[0299] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate lies within the range of the orthographic projection of the first region of the active pattern of the third transistor (which is also the second region of the active pattern of the fourth transistor and the second region of the active pattern of the fifth transistor) onto the substrate. The fourth, third, second, and first insulating layers within the first via V1 are etched away, exposing the surface of the first region of the active pattern of the third transistor (which is also the second region of the active pattern of the fourth transistor and the second region of the active pattern of the fifth transistor). The first via V1 is configured to allow the first electrode of the subsequently formed third transistor (which is also the second electrode of the fourth transistor, the second electrode of the fifth transistor, and the second electrode of the eighth transistor) to be connected to the first region of the active pattern of the third transistor (which is also the second region of the active pattern of the fourth transistor and the second region of the active pattern of the fifth transistor) through the via.

[0300] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate lies within the orthographic projection of the second region of the active pattern of the third transistor (which is also the first region of the active pattern of the sixth transistor) onto the substrate. The fourth, third, second, and first insulating layers within the second via V2 are etched away, exposing the surface of the second region of the active pattern of the third transistor (which is also the second region of the active pattern of the sixth transistor). The second via V2 is configured to allow the second electrode of the subsequently formed second transistor (the second electrode of the third transistor and the first electrode of the sixth transistor) to be connected to the second region of the active pattern of the third transistor (which is also the second region of the active pattern of the sixth transistor) through the via.

[0301] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate is within the orthographic projection range of the first region of the active pattern of the fourth transistor onto the substrate. The fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the third via V3 are etched away, exposing the surface of the first region of the active pattern of the fourth transistor. The third via V3 is configured to allow the first electrode of the subsequently formed fourth transistor to be connected to the first region of the active pattern of the fourth transistor through the via.

[0302] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate is within the orthographic projection of the first region of the active pattern of the fifth transistor onto the substrate. The fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the fourth via V4 are etched away, exposing the surface of the first region of the active pattern of the fifth transistor. The fourth via V4 is configured to allow the first electrode of the subsequently formed fifth transistor to be connected to the first region of the active pattern of the fifth transistor through the via.

[0303] In an exemplary embodiment, the orthogonal projection of the fifth via V5 onto the substrate is located within the orthogonal projection of the second region of the active pattern of the sixth transistor (which is also the second region of the active pattern of the seventh transistor) onto the substrate. The fourth, third, second, and first insulating layers within the fifth via V5 are etched away, exposing the surface of the second region of the active pattern of the sixth transistor (which is also the second region of the active pattern of the seventh transistor). The fifth via V5 is configured to allow the second electrode of the subsequently formed sixth transistor (which is also the second electrode of the seventh transistor) to be connected to the second region of the active pattern of the sixth transistor (which is also the second region of the active pattern of the seventh transistor) through the via.

[0304] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate is within the orthographic projection of the first region of the active pattern of the seventh transistor onto the substrate. The fourth, third, second, and first insulating layers within the sixth via V6 are etched away, exposing the surface of the first region of the active pattern of the seventh transistor. The sixth via V6 is configured to allow the first electrode of the subsequently formed seventh transistor to be connected to the first region of the active pattern of the seventh transistor through the via.

[0305] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate is within the orthographic projection of the first region of the active pattern of the eighth transistor onto the substrate. The fourth, third, second, and first insulating layers within the seventh via V7 are etched away, exposing the surface of the first region of the active pattern of the eighth transistor. The seventh via V7 is configured to allow the first electrode of the subsequently formed eighth transistor to be connected to the first region of the active pattern of the eighth transistor through the via.

[0306] In an exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate is within the orthographic projection of the second region of the active pattern of the eighth transistor onto the substrate. The fourth, third, second, and first insulating layers within the eighth via V8 are etched away, exposing the surface of the second region of the active pattern of the eighth transistor. The eighth via V8 is configured to allow the first terminal of the subsequently formed third transistor (which is also the second terminal of the fourth, fifth, and eighth transistors) to be connected to the second region of the active pattern of the eighth transistor through the via.

[0307] In an exemplary embodiment, the orthographic projection of the ninth via V9 onto the substrate is within the orthographic projection of the first region of the active pattern of the ninth transistor onto the substrate. The fourth, third, second, and first insulating layers within the ninth via V9 are etched away, exposing the surface of the first region of the active pattern of the ninth transistor. The ninth via V9 is configured to allow the first electrode of the subsequently formed ninth transistor to be connected to the first region of the active pattern of the ninth transistor through the via.

[0308] In an exemplary embodiment, the orthographic projection of the tenth via V10 onto the substrate lies within the orthographic projection of the second region of the active pattern of the ninth transistor onto the substrate. The fourth, third, second, and first insulating layers within the tenth via V10 are etched away, exposing the surface of the second region of the active pattern of the ninth transistor. The tenth via V10 is configured to allow the second electrode of the subsequently formed first transistor (which is also the first electrode of the second transistor, the second electrode of the ninth transistor, and the first plate of the second capacitor) to be connected to the second region of the active pattern of the ninth transistor through the via.

[0309] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate is located within the orthographic projection of the first electrode of the first capacitor (which is also the second electrode of the third transistor) onto the substrate. The fourth, third, and second insulating layers within the eleventh via V11 are etched away, exposing the surface of the first electrode of the first capacitor (which is also the second electrode of the third transistor). The eleventh via V11 is configured to allow the first electrode of the subsequently formed ninth transistor to be connected to the first electrode of the first capacitor (which is also the second electrode of the third transistor) through the via.

[0310] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate is within the range of the orthographic projection of the first initial signal line on the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the twelfth via V12 are etched away, exposing the surface of the first initial signal line. The twelfth via V12 is configured to allow the first electrode of the subsequently formed first transistor to be connected to the first initial signal line through the via.

[0311] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 onto the substrate is located within the range of the orthographic projections of the gate electrode of the fourth transistor and the first scan signal line onto the substrate. The fourth, third, and second insulating layers within the thirteenth via V13 are etched away, exposing the surface of the control electrode of the fourth transistor. The fourth and third insulating layers within the thirteenth via V13 are etched away, exposing the surface of the first scan signal line. The thirteenth via V13 is configured to allow subsequently formed connection electrodes to be connected to the gate electrode of the fourth transistor and the first scan signal line through the via.

[0312] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the substrate is within the range of the orthographic projection of the first scan signal line on the substrate. The fourth and third insulating layers within the fourteenth via V14 are etched away, exposing the surface of the first scan signal line. The fourteenth via V14 is configured to allow subsequently formed connection electrodes to be connected to the first scan signal line through the via.

[0313] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the substrate is located within the orthographic projection of the second plate of the first capacitor on the substrate. The fourth and third insulating layers within the fifteenth via V15 are etched away, exposing the surface of the second plate of the first capacitor. The fifteenth via V15 is configured to allow the first electrode of the subsequently formed fifth transistor to be connected to the second plate of the first capacitor through the via.

[0314] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 onto the substrate is within the orthographic projection range of the first region of the active pattern of the first transistor onto the substrate. The fourth insulating layer within the sixteenth via V16 is etched away, exposing the surface of the first region of the active pattern of the first transistor. The sixteenth via V16 is configured to allow the first electrode of the subsequently formed first transistor to be connected to the first region of the active pattern of the first transistor through the via.

[0315] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 onto the substrate is located within the orthographic projection range of the second region of the active pattern of the first transistor (the first region of the active pattern of the second transistor) onto the substrate. The fourth insulating layer within the seventeenth via V17 is etched away, exposing the surface of the second region of the active pattern of the first transistor (the first region of the active pattern of the second transistor). The seventeenth via V17 is configured to allow the second electrode of the subsequently formed first transistor (which is also the first electrode of the second transistor, the second electrode of the ninth transistor, and the first plate of the second capacitor) to be connected to the second region of the active pattern of the first transistor (the first region of the active pattern of the second transistor) through the via.

[0316] In an exemplary embodiment, the orthographic projection of the eighteenth via V18 onto the substrate is within the range of the orthographic projection of the second region of the active pattern of the second transistor onto the substrate. The fourth insulating layer within the eighteenth via V18 is etched away, exposing the surface of the second region of the active pattern of the second transistor. The eighteenth via V18 is configured to allow the second terminal of the subsequently formed second transistor (which is also the second terminal of the third transistor and the first terminal of the sixth transistor) to be connected to the second region of the active pattern of the second transistor through the via.

[0317] In an exemplary embodiment, the orthographic projection of the nineteenth via V19 on the substrate is within the range of the orthographic projection of the second initial signal line on the substrate. The nineteenth via V19 exposes the surface of the second initial signal line. The nineteenth via V19 is configured to allow the first electrode of the subsequently formed seventh transistor to be connected to the second initial signal line through the via.

[0318] In an exemplary embodiment, the orthographic projection of the twentieth via V20 onto the substrate is located within the range of at least a portion of the orthographic projection of the third initial signal line onto the substrate. The twentieth via V20 exposes the surface of the third initial signal line. The twentieth via V20 is configured to allow the first electrode of the subsequently formed eighth transistor to be connected to the third initial signal line through the via.

[0319] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fourth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer pattern, such as... Figure 22 and Figure 23 As shown, Figure 22 This is a schematic diagram of the pattern of the fourth conductive layer. Figure 23 This is a schematic diagram showing the formation of the fourth conductive layer pattern. In an exemplary embodiment, the fourth conductive layer may be referred to as the first source / drain metal (SD1) layer.

[0320] In an exemplary implementation, such as Figure 22 and Figure 23 As shown, the fourth conductive layer pattern may include: the first electrode 13 and the second electrode 14 of the first transistor to the first electrode 93 and the second electrode 94 of the ninth transistor located in at least one pixel driving circuit, and the first electrode C21 of the second capacitor.

[0321] In an exemplary embodiment, the first pole 13 and second pole 14 of the first transistor of at least one pixel driving circuit located in the same row to the first pole 93 and second pole 94 of the ninth transistor and the first plate C21 of the second capacitor are symmetrically arranged with respect to a virtual straight line extending along the second direction D2.

[0322] In an exemplary embodiment, the first electrode 53 of the fifth transistor of at least one pixel driving circuit and the first electrode 53 of the fifth transistor of the first adjacent pixel driving circuit are the same electrode, and the first electrode 83 of the eighth transistor of at least one pixel driving circuit and the first electrode 83 of the eighth transistor of the first adjacent pixel driving circuit are the same electrode. The first electrode 13 of the first transistor of at least one pixel driving circuit and the first electrode 13 of the first transistor of the second adjacent pixel driving circuit are the same electrode.

[0323] In an exemplary embodiment, in at least one pixel driving circuit, the first electrode 13 of the first transistor is separately disposed and is shaped as a strip extending at least partially along the first direction D1. The first electrode 13 of the first transistor is connected to the first region of the active pattern of the first transistor through a sixteenth via and is electrically connected to the first initial signal line through a twelfth via.

[0324] In an exemplary embodiment, the second electrode 14 of the first transistor, the first electrode 23 of the second transistor, the second electrode 94 of the ninth transistor, and the first plate C21 of the second capacitor are integral structures and extend at least partially along the first direction D1. The second electrode 14 of the first transistor (which is also the first electrode 23 of the second transistor, the second electrode 94 of the ninth transistor, and the first plate C21 of the second capacitor) is connected to the second region of the active pattern of the first transistor (the first region of the active pattern of the second transistor) through a seventeenth via, and to the second region of the active pattern of the ninth transistor through a tenth via.

[0325] In an exemplary embodiment, the second electrode 24 of the second transistor, the second electrode 34 of the third transistor, and the first electrode 63 of the sixth transistor are integral structures and extend at least partially along the second direction D2. The second electrode 24 of the second transistor (which is also the second electrode 34 of the third transistor and the first electrode 63 of the sixth transistor) is connected to the second region of the active pattern of the third transistor (which is also the second region of the active pattern of the sixth transistor) through a second via, and is connected to the second region of the active pattern of the second transistor through an eighteenth via.

[0326] In an exemplary embodiment, the first electrode 33 of the third transistor, the second electrode 44 of the fourth transistor, the second electrode 54 of the fifth transistor, and the second electrode 84 of the eighth transistor are integral structures and extend at least partially along the second direction D2. The first electrode 33 of the third transistor (which is also the second electrode 44 of the fourth transistor, the second electrode 54 of the fifth transistor, and the second electrode 84 of the eighth transistor) is connected to the first region of the active pattern of the third transistor (which is also the second region of the active pattern of the fourth transistor and the second region of the active pattern of the fifth transistor) through a first via, and is connected to the second region of the active pattern of the eighth transistor through an eighth via.

[0327] In an exemplary embodiment, the first electrode 43 of the fourth transistor is separately disposed and is block-shaped. The first electrode 43 of the fourth transistor is connected to the first region of the active pattern of the fourth transistor through a third via.

[0328] In an exemplary embodiment, the first electrode 53 of the fifth transistor is separately disposed and is shaped like a "T". The first electrode 53 of the fifth transistor is connected to the first region of the active pattern of the fifth transistor through a fourth via and to the second electrode of the first capacitor through a fifteenth via.

[0329] In an exemplary embodiment, the second electrode 64 of the sixth transistor (which is also the second electrode 74 of the seventh transistor) is a single, integral structure. The second electrode 64 of the sixth transistor (which is also the second electrode 74 of the seventh transistor) is connected to the second region of the active pattern of the sixth transistor (which is also the second region of the active pattern of the seventh transistor) through a fifth via.

[0330] In an exemplary embodiment, the first electrode 73 of the seventh transistor is separately provided and is in the shape of a strip extending at least partially along the second direction D2. The first electrode 73 of the seventh transistor is connected to the first region of the active pattern of the seventh transistor through a sixth via and to the second initial signal line through a nineteenth via.

[0331] In an exemplary embodiment, the first electrode 83 of the eighth transistor is separately provided and is in the shape of a strip extending at least partially along the second direction D2. The first electrode 83 of the eighth transistor is connected to the first region of the active pattern of the eighth transistor through a seventh via and to the third initial signal line through a twentieth via.

[0332] In an exemplary embodiment, the first electrode 93 of the ninth transistor is provided separately and is in the shape of a strip extending at least partially along the second direction D2. The first electrode 93 of the ninth transistor is connected to the first region of the active pattern of the ninth transistor through the ninth via and to the first plate of the first capacitor (which is also the second electrode of the third transistor) through the eleventh via.

[0333] In an exemplary embodiment, the connecting electrode L is provided separately and is in the shape of a strip that extends at least partially along the first direction D1. The connecting electrode L is electrically connected to the control electrode of the fourth transistor and the first scan signal line through the thirteenth via, and electrically connected to the first scan signal line through the fourteenth via.

[0334] (8) Forming a planarization layer pattern. In an exemplary embodiment, forming a planarization layer pattern may include: depositing a sixth insulating film on a substrate on which the aforementioned pattern is formed, patterning the sixth insulating film using a patterning process to form a sixth insulating layer, coating a planarization film on the sixth insulating layer, and patterning the planarization film using a patterning process to form a planarization layer pattern covering the aforementioned pattern, wherein the planarization layer has a plurality of via patterns.

[0335] In an exemplary embodiment, the plurality of via patterns on the planarization layer pattern include: via twenty-first to via twenty-third.

[0336] In an exemplary embodiment, the orthogonal projection of the 21st via onto the substrate is within the range of the orthogonal projection of the first electrode of the fourth transistor onto the substrate. The sixth insulating layer within the 21st via is etched away, exposing the surface of the first electrode of the fourth transistor. The 21st via is configured to allow subsequently formed data signal lines to be connected to the first electrode of the fourth transistor through the via.

[0337] In an exemplary embodiment, the orthographic projection of the 22nd via on the substrate is within the range of the orthographic projection of the first electrode of the fifth transistor on the substrate. The sixth insulating layer within the 22nd via is etched away, exposing the surface of the first electrode of the fifth transistor. The 22nd via is configured to allow a subsequently formed first power line to be connected to the first electrode of the fifth transistor through the via.

[0338] In an exemplary embodiment, the orthogonal projection of the 23rd via onto the substrate is located within the orthogonal projection of the second electrode of the 6th transistor (which is also the second electrode of the 7th transistor) onto the substrate. The 6th insulating layer within the 23rd via is etched away, exposing the surface of the second electrode of the 6th transistor (which is also the second electrode of the 7th transistor). The 23rd via is configured to allow the subsequently formed anode connection electrode to be connected to the second electrode of the 6th transistor (which is also the second electrode of the 7th transistor) through the via.

[0339] (9) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming a fifth conductive layer pattern may include: depositing a fifth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the fifth conductive film using a patterning process to form a fifth conductive layer pattern.

[0340] In an exemplary embodiment, the fifth conductive layer pattern may include at least: a data signal line, a first power line, and an anode connection electrode and a second plate of a second capacitor located in at least one pixel driving circuit.

[0341] In an exemplary embodiment, the data signal line may be a line shape in which the main body extends along the second direction, and is electrically connected to the first electrode of the fourth transistor through the twenty-first via.

[0342] In an exemplary embodiment, the first power line can be a line shape in which the main body extends along the second direction. The area where the first power line overlaps with the second electrode of the ninth transistor can serve as the second electrode of the second capacitor, and the first power line is electrically connected to the first electrode of the fifth transistor through the twenty-second via.

[0343] In an exemplary embodiment, the anode connection electrode is electrically connected to the second electrode of the sixth transistor (which is also the second electrode of the seventh transistor) through the twenty-third via.

[0344] At this point, the circuit structure layer is fabricated on the substrate. In a plane parallel to the display substrate, the circuit structure layer may include multiple pixel driving circuits and multiple signal lines connected to the pixel driving circuits. In a plane perpendicular to the display substrate, the circuit structure layer may be disposed on the substrate. The pixel driving circuit for at least one sub-pixel includes at least one P-type transistor, at least one N-type transistor, and at least one capacitor, the capacitor including a first electrode and a second electrode.

[0345] The pixel driving circuit layer may include a first semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a second semiconductor layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a fourth conductive layer, a sixth insulating layer, a planarization layer, and a fifth conductive layer, which are sequentially disposed on the substrate.

[0346] In an exemplary embodiment, the first semiconductor layer may be an amorphous silicon layer or a polycrystalline silicon layer.

[0347] In an exemplary embodiment, the second semiconductor layer may be a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon and indium and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0348] In an exemplary embodiment, at least one of the first to fifth conductive layers may be a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. For example, the material used to fabricate the first conductive layer may include molybdenum.

[0349] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.

[0350] In an exemplary embodiment, the planarization layer may be made of organic materials.

[0351] In an exemplary embodiment, after the circuit structure layer is fabricated, a light-emitting structure layer is fabricated on the circuit structure layer. The fabrication process of the light-emitting structure layer may include the following operations.

[0352] On the substrate with the aforementioned pattern, an anodic conductive film is deposited, and the anodic conductive film is patterned using a patterning process to form an anodic conductive layer pattern disposed on a second planarization layer. On the substrate with the aforementioned pattern, a pixel definition film is deposited, and the pixel definition film is patterned using a patterning process to form a pixel definition layer pattern that exposes the anodic conductive layer pattern. On the substrate with the pixel definition layer pattern, an organic light-emitting material is coated, and the organic light-emitting material is patterned using a patterning process to form an organic structure layer pattern. On the substrate with the organic material layer pattern, a cathode conductive film is deposited, and the cathode conductive film is patterned using a patterning process to form a cathode conductive layer.

[0353] At this point, the luminescent structure layer has been successfully fabricated on the substrate.

[0354] In an exemplary embodiment, the anode conductive layer includes at least the anodes of a plurality of light-emitting devices.

[0355] In an exemplary embodiment, the anode conductive layer adopts a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or it can adopt a multi-layer composite structure, such as ITO / Ag / ITO.

[0356] In an exemplary embodiment, the organic structure layer may include at least an organic light-emitting layer of a light-emitting device.

[0357] In an exemplary embodiment, the cathode conductive layer may include at least the cathodes of a plurality of light-emitting devices.

[0358] In an exemplary embodiment, the cathode layer can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or the aforementioned conductive alloy materials, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. Exemplarily, the fourth conductive layer can be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0359] In an exemplary embodiment, the subsequent preparation process may include: forming an encapsulation structure layer on the cathode conductive layer. The encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer.

[0360] The display substrate described in this embodiment can be used in display products of any resolution.

[0361] This disclosure also provides a method for preparing a display substrate, configured to prepare the display substrate provided in any of the foregoing embodiments. The method for preparing the display substrate includes the following steps:

[0362] Step 201: Form a first semiconductor layer on the substrate and lightly dope the first semiconductor layer, wherein the first semiconductor layer includes: an active pattern of at least one P-type transistor.

[0363] Step 202: Form a first conductive layer on the substrate on which the first semiconductor layer is formed. The first conductive layer includes: the control electrode of the fourth transistor.

[0364] Step 203: The first semiconductor layer is heavily doped to form the channel region, the first region and the second region of the active pattern of at least one P-type transistor.

[0365] Step 204: Form a second conductive layer on the substrate on which the first conductive layer is formed. The second conductive layer includes: multiple first scan signal lines and the control electrode of at least one ninth transistor in a pixel driving circuit.

[0366] In an exemplary embodiment, heavily doping the first semiconductor layer includes: using the first semiconductor layer as a mask to heavily dope the first semiconductor layer, or using the first semiconductor layer as a first mask and a halftone mask as a second mask to heavily dope the first semiconductor layer.

[0367] In an exemplary embodiment, the method for preparing a display substrate may further include: step 205, sequentially forming a third conductive layer and a fourth conductive layer on a substrate on which a second conductive layer has been formed.

[0368] In an exemplary embodiment, the first conductive layer further includes: a plurality of first initial signal lines, a plurality of light-emitting signal lines, a plurality of second reset signal lines, and a control electrode of at least one of the third, fifth to eighth transistors located in at least one pixel driving circuit.

[0369] In an exemplary embodiment, the second conductive layer further includes: a first reset connection line of a plurality of first reset signal lines and a first scan connection line of a plurality of second scan signal lines, and a control electrode of at least one of the ninth transistors located in at least one pixel driving circuit.

[0370] In an exemplary embodiment, the third conductive layer includes at least: a plurality of second initial signal lines, a plurality of third initial signal lines, a second reset connection line of a plurality of first reset signal lines, and a second scan connection line of a plurality of second scan signal lines.

[0371] In an exemplary embodiment, the fourth conductive layer further includes: a first electrode and a second electrode of at least one transistor in at least one pixel driving circuit.

[0372] The accompanying drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0373] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0374] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A pixel driving circuit, characterized in that, include: The first control sub-circuit, the second control sub-circuit, the third control sub-circuit, the fourth control sub-circuit, and the drive sub-circuit; The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving signal to the third node under the control of the signals of the first node and the second node. The first control sub-circuit is electrically connected to the first scan signal terminal, the first power supply terminal, the first node and the fifth node respectively, and is configured to connect the first node and the fifth node under the control of the signal of the first scan signal terminal, and store the voltage difference between the signals of the first node and the first power supply terminal and the voltage difference between the signals of the fifth node and the first power supply terminal. The second control sub-circuit is electrically connected to the first reset signal terminal, the second scan signal terminal, the first initial signal terminal, the third node, and the fifth node, respectively, and is configured to provide the first initial signal terminal or the third node signal to the fifth node under the control of the signals of the first reset signal terminal and the second scan signal terminal; The third control sub-circuit is electrically connected to the first scan signal terminal, the second reset signal terminal, the data signal terminal, the second initial signal terminal, the third initial signal terminal, the second node, and the fourth node, respectively. It is configured to provide the data signal terminal or the third initial signal terminal to the second node and the second initial signal terminal to the fourth node under the control of the signals of the first scan signal terminal and the second reset signal terminal. The fourth control sub-circuit is electrically connected to the light-emitting signal terminal, the first power supply terminal, the second node, the third node, and the fourth node, respectively, and is configured to provide the first power supply terminal signal to the second node and the third node signal to the fourth node under the control of the light-emitting signal terminal signal.

2. The pixel driving circuit according to claim 1, characterized in that, The first control sub-circuit includes: a first storage sub-circuit, a second storage sub-circuit, and a connection sub-circuit; The connecting sub-circuit is electrically connected to the first scanning signal terminal, the first node, and the fifth node, respectively, and is configured to connect the first node and the fifth node under the control of the signal from the first scanning signal terminal. The first storage sub-circuit is electrically connected to the first node and the first power supply terminal respectively, and is configured to store the voltage difference between the signals of the first node and the first power supply terminal. The second storage sub-circuit is electrically connected to the fifth node and the first power supply terminal respectively, and is configured to store the voltage difference between the signals of the fifth node and the first power supply terminal.

3. The pixel driving circuit according to claim 2, characterized in that, The connecting sub-circuit includes a ninth transistor; the first storage sub-circuit includes a first capacitor; the second storage sub-circuit includes a second capacitor; both the first capacitor and the second capacitor include a first electrode and a second electrode. The control electrode of the ninth transistor is electrically connected to the first scan signal terminal, the first electrode of the ninth transistor is electrically connected to the first node, and the second electrode of the ninth transistor is electrically connected to the fifth node. The first plate of the first capacitor is electrically connected to the first node, and the second plate of the first capacitor is electrically connected to the first power supply terminal. The first plate of the second capacitor is electrically connected to the fifth node, and the second plate of the second capacitor is electrically connected to the first power supply terminal.

4. The pixel driving circuit according to claim 1, characterized in that, The second control sub-circuit includes: a first transistor and a second transistor; The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the first initial signal terminal, and the second electrode of the first transistor is electrically connected to the fifth node. The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the fifth node, and the second electrode of the second transistor is electrically connected to the third node. The type of at least one of the first transistor and the second transistor is opposite to the type of at least one transistor in the first control sub-circuit.

5. The pixel driving circuit according to claim 1, characterized in that, The third control sub-circuit includes: a fourth transistor, a seventh transistor, and an eighth transistor; The control electrode of the fourth transistor is electrically connected to the first scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the second node. The control terminal of the seventh transistor is electrically connected to the second reset signal terminal, the first terminal of the seventh transistor is electrically connected to the second initial signal terminal, and the second terminal of the seventh transistor is electrically connected to the fourth node. The control terminal of the eighth transistor is electrically connected to the second reset signal terminal, the first terminal of the eighth transistor is electrically connected to the third initial signal terminal, and the second terminal of the eighth transistor is electrically connected to the second node. The voltage value of the signal at the third initial signal terminal is greater than the voltage value of the signal at the first power supply terminal.

6. The pixel driving circuit according to claim 1, characterized in that, The driving sub-circuit includes a third transistor; the first control sub-circuit includes a ninth transistor, a first capacitor, and a second capacitor; the second control sub-circuit includes a first transistor and a second transistor; the third control sub-circuit includes a fourth transistor, a seventh transistor, and an eighth transistor; the fourth control sub-circuit includes a fifth transistor and a sixth transistor; and both the first capacitor and the second capacitor include a first electrode and a second electrode. The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the first initial signal terminal, and the second electrode of the first transistor is electrically connected to the fifth node. The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the fifth node, and the second electrode of the second transistor is electrically connected to the third node. The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node. The control electrode of the fourth transistor is electrically connected to the first scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the second node. The control electrode of the fifth transistor is electrically connected to the light-emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node. The control electrode of the sixth transistor is electrically connected to the light-emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node. The control terminal of the seventh transistor is electrically connected to the second reset signal terminal, the first terminal of the seventh transistor is electrically connected to the second initial signal terminal, and the second terminal of the seventh transistor is electrically connected to the fourth node. The control terminal of the eighth transistor is electrically connected to the second reset signal terminal, the first terminal of the eighth transistor is electrically connected to the third initial signal terminal, and the second terminal of the eighth transistor is electrically connected to the second node. The control electrode of the ninth transistor is electrically connected to the first scan signal terminal, the first electrode of the ninth transistor is electrically connected to the first node, and the second electrode of the ninth transistor is electrically connected to the fifth node. The first plate of the first capacitor is electrically connected to the first node, and the second plate of the first capacitor is electrically connected to the first power supply terminal. The first plate of the second capacitor is electrically connected to the fifth node, and the second plate of the second capacitor is electrically connected to the first power supply terminal.

7. The pixel driving circuit according to claim 6, characterized in that, The type of at least one of the first and second transistors is opposite to the type of at least one of the third to ninth transistors; At least one of the first transistor and the second transistor is an N-type transistor, and at least one of the third to the ninth transistors is a P-type transistor.

8. The pixel driving circuit according to claim 6, characterized in that, At least one of the first to ninth transistors includes an active pattern, the active pattern including a channel region, a first region and a second region, the first region and the second region being located on opposite sides of the channel region; The doping concentration of the channel region in the active pattern of the ninth transistor is greater than the doping concentration of the channel region in the active pattern of at least one of the first to eighth transistors.

9. The pixel driving circuit according to claim 8, characterized in that, The doping concentration of at least one of the first and second regions in the active pattern of the ninth transistor is greater than or equal to the doping concentration of the channel region in the active pattern of the ninth transistor.

10. The pixel driving circuit according to claim 1, characterized in that, In at least one display frame, the time period during which the signal at the second reset signal terminal is an effective level signal includes: a first time period and a second time period with an interval set, wherein the first time period occurs before the second time period; The time period during which the signal at at least one of the first scan signal terminal, the second scan signal terminal, and the first reset signal terminal is an effective level signal is located between the first time period and the second time period.

11. The pixel driving circuit according to claim 10, characterized in that, The time period during which the signal at the first scanning signal terminal is an effective level signal includes: a third time period and a fourth time period set at intervals, wherein the third time period occurs before the fourth time period, and the third time period includes: multiple sub-time periods set at intervals; The time period during which the signal at the first reset signal terminal is at an effective level overlaps at least partially with the time period during which the signal at the second scan signal terminal is at an effective level; the time period during which the signal at the first reset signal terminal is at an effective level overlaps at least partially with the third time period; and the time period during which the signal at the second scan signal terminal is at an effective level overlaps at least partially with the fourth time period.

12. The pixel driving circuit according to claim 11, characterized in that, The start time of the period when the signal at the first reset signal terminal is at an effective level is earlier than the start time of the period when the signal at the second scan signal terminal is at an effective level. The end time of the period when the signal at the first reset signal terminal is at an effective level is later than the start time of the period when the signal at the second scan signal terminal is at an effective level, but earlier than the end time of the period when the signal at the second scan signal terminal is at an effective level. The start time of the third time period is later than the start time of the time period when the signal at the first reset signal terminal is at an effective level, and the end time of the third time period is earlier than the start time of the time period when the signal at the second scan signal terminal is at an effective level. The start time of the fourth time period is later than the end time of the time period when the signal at the first reset signal terminal is at an effective level, and the end time of the fourth time period is later than the end time of the time period when the signal at the second scan signal terminal is at an effective level.

13. A display substrate, characterized in that, Includes: a substrate and a plurality of pixel driving circuits as described in any one of claims 1 to 12 and a plurality of first scan signal lines disposed on the substrate, wherein the pixel driving circuit includes: at least one P-type transistor, and the at least one P-type transistor includes: a fourth transistor and a ninth transistor; At least one of the plurality of first scan signal lines is electrically connected to the control electrode of the fourth transistor and the control electrode of the ninth transistor in at least one pixel driving circuit, and at least one of the plurality of first scan signal lines extends at least partially along the first direction; The control electrode of the fourth transistor in at least one pixel driving circuit is located on the side of the plurality of first scan signal lines and the control electrode of the ninth transistor in at least one pixel driving circuit close to the substrate.

14. The display substrate according to claim 13, characterized in that, The orthographic projection of at least one of the plurality of first scan signal lines on the substrate at least partially overlaps with the orthographic projection of the control electrode of the fourth transistor in at least one pixel driving circuit on the substrate.

15. The display substrate according to claim 13, characterized in that, Also includes: Multiple light-emitting signal lines and multiple second reset signal lines are disposed on the substrate; the at least one P-type transistor further includes: a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. At least one of the plurality of light-emitting signal lines is electrically connected to the control electrode of the fifth transistor and the control electrode of the sixth transistor in at least one pixel driving circuit, and at least one of the plurality of second reset signal lines is electrically connected to the control electrode of the seventh transistor and the control electrode of the eighth transistor in at least one pixel driving circuit. At least a portion of the plurality of light-emitting signal lines and the plurality of second reset signal lines extend along a first direction. The control electrode of the plurality of light-emitting signal lines, the plurality of second reset signal lines, and at least one of the fifth, sixth, seventh, and eighth transistors in at least one pixel driving circuit is disposed on the same layer as the control electrode of the fourth transistor.

16. The display substrate according to claim 15, characterized in that, Also includes: Multiple first reset signal lines and multiple second scan signal lines are disposed on the substrate; The pixel driving circuit includes at least one N-type transistor, and the at least one N-type transistor further includes a first transistor and a second transistor; At least one of the plurality of first reset signal lines is electrically connected to the control electrode of a first transistor in at least one pixel driving circuit, and at least one of the plurality of second scan signal lines is electrically connected to the control electrode of a second transistor in at least one pixel driving circuit. At least a portion of the plurality of first reset signal lines and the plurality of second scan signal lines extend along a first direction. At least one of the plurality of first reset signal lines and the plurality of second scan signal lines is located on the side of the plurality of light emission signal lines and the plurality of second reset signal lines that is away from the substrate; The orthographic projections of the active patterns of the fourth transistor and the ninth transistor of at least one pixel driving circuit onto the substrate at least partially overlap with the orthographic projections of at least one of the first and second scan signal lines onto the substrate.

17. The display substrate according to claim 16, characterized in that, The first reset signal line, the first scan signal line, the second scan signal line, the light emission signal line, and the second reset signal line connected to at least one pixel driving circuit are arranged sequentially along a second direction on the substrate, and the first direction and the second direction intersect.

18. The display substrate according to claim 17, characterized in that, Also includes: Multiple first initial signal lines, multiple second initial signal lines, and multiple third initial signal lines are disposed on the substrate; At least one of the plurality of first initial signal lines, plurality of second initial signal lines, and plurality of third initial signal lines extends at least partially along a first direction; The orthographic projection of the first initial signal line connected to at least one pixel driving circuit on the substrate is located on the side of the orthographic projection of the first reset signal line on the substrate that is away from the orthographic projection of the first scan signal line on the substrate. The orthographic projection of the second initial signal line connected to at least one pixel driving circuit on the substrate is located on the side of the orthographic projection of the second reset signal line on the substrate that is away from the orthographic projection of the light emission signal line on the substrate. At least a portion of the orthographic projection of the third initial signal line connected to at least one pixel driving circuit on the substrate overlaps at least a portion of the orthographic projection of the second reset signal line on the substrate, and is located between the orthographic projection of the light emission signal line on the substrate and the orthographic projection of the second initial signal line on the substrate.

19. The display substrate according to claim 18, characterized in that, Also includes: A circuit structure layer disposed on the substrate, the circuit structure layer comprising: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, and a fourth conductive layer; at least one first reset signal line comprising: a first reset connection line and a second reset connection line disposed on different layers and interconnected thereto; at least one second scan signal line comprising: a first scan connection line and a second scan connection line disposed on different layers and interconnected thereto; and at least one control electrode of an N-type transistor comprising: a first control electrode and a second control electrode. The first conductive layer includes at least: multiple first initial signal lines, multiple light-emitting signal lines, multiple second reset signal lines, and the control electrode of at least one of the third to eighth transistors located in at least one pixel driving circuit; The second conductive layer includes at least: a plurality of first scan signal lines, a first reset connection line of a plurality of first reset signal lines, a first scan connection line of a plurality of second scan signal lines, and a control electrode of a ninth transistor and a first control electrode of at least one N-type transistor located in at least one pixel driving circuit; The third conductive layer includes at least: multiple second initial signal lines, multiple third initial signal lines, a second reset connection line of multiple first reset signal lines, a second scan connection line of multiple second scan signal lines, and a second control electrode of at least one N-type transistor located in at least one pixel driving circuit; The fourth conductive layer includes at least: a first electrode and a second electrode of at least one transistor located in at least one pixel driving circuit.

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