Display module and display device

Abstract

The invention discloses a display module and a display device, a display panel comprises a gate drive circuit, a plurality of scanning lines and a plurality of switching circuits, the output ends of odd-numbered gate drive units are connected with the first ends of the switching circuits, and the output ends of even-numbered gate drive units are connected with the second ends of the switching circuits. The control end of the switching circuit is configured to access a control signal. In the first display mode, the switching circuit is in a conducting state, and two adjacent scanning lines are connected to the same scanning signal output by the odd-numbered-stage gate driving unit or the even-numbered-stage gate driving unit. When the display device is in the first display mode, in the same picture frame, only one of the odd-level gate driving units and the even-level gate driving units outputs scanning signals, and the other one is idle and does not work, so that the risk of too fast temperature rise of the device can be reduced.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display module and display device. Background Technology

[0002] To improve the refresh rate, existing LCD panels mainly control two adjacent scan lines to be turned on simultaneously. The main principle is that the level conversion device controls the timing of the gate drive circuit. By controlling two adjacent clock signals to be output simultaneously, the two scan lines can be turned on at the same time.

[0003] However, the increase in panel refresh rate leads to an increase in the operating frequency of the gate drive circuit, which causes the traces (such as clock signal lines) and level conversion devices related to the gate drive circuit to heat up too quickly, increasing the risk of panel damage. Summary of the Invention

[0004] This application provides a display module and display device to reduce the risk of excessively rapid device temperature rise while achieving a high refresh rate, thereby at least partially solving the above-mentioned technical problems.

[0005] To achieve the above objectives, according to a first aspect of this application, a display module is provided, comprising: The display panel includes a gate driving circuit, multiple scan lines, and multiple switching circuits. The gate driving circuit includes multiple gate driving units. The output terminal of one gate driving unit is electrically connected to one scan line. In two adjacent gate driving units, the output terminal of the odd-numbered gate driving unit is connected to the first terminal of the switching circuit, and the output terminal of the even-numbered gate driving unit is connected to the second terminal of the switching circuit. The control terminal of the switching circuit is configured to receive a control signal. The display module has a first display mode and a second display mode. The refresh rate of the first display mode is higher than that of the second display mode. In the first display mode, the switching circuit is in the on state, and two adjacent scan lines are connected to the same scan signal output by the odd-numbered level gate driving unit or the even-numbered level gate driving unit.

[0006] Optionally, in some embodiments of this application, the switching circuit includes a switching transistor, the gate of the switching transistor is the control terminal of the switching circuit, the first terminal of the switching transistor is connected to the odd-numbered gate driving units, and the second terminal of the switching transistor is connected to the even-numbered gate driving units.

[0007] Optionally, in some embodiments of this application, the switching transistor is an N-type transistor.

[0008] Optionally, in some embodiments of this application, the switching circuit includes a first switching transistor and a second switching transistor, the gates of the first switching transistor and the second switching transistor are connected to form the control terminal of the switching circuit, the first terminal of the first switching transistor is connected to the odd-numbered gate driving unit, the first terminal of the first switching transistor is connected to the first terminal of the second switching transistor, and the second terminal of the second switching transistor is connected to the even-numbered gate driving unit.

[0009] Optionally, in some embodiments of this application, one of the switching circuits is disposed between the scan lines connected to adjacent odd-numbered gate driving units and the scan lines connected to even-numbered gate driving units.

[0010] Optionally, in some embodiments of this application, the control terminals of all the switching circuits are connected to the same control signal line.

[0011] Optionally, in some embodiments of this application, in the second display mode, the switching circuit is in an off state, and the odd-numbered gate driving units and the even-numbered gate driving units sequentially output scanning signals.

[0012] Optionally, in some embodiments of this application, the display module includes a timing controller and a level shifter. The timing controller is connected to the level shifter, and the level shifter is connected to the gate driving circuit and the switching circuit. The level shifter is configured to control the switching circuit to be turned on or off and to send a clock signal to the gate driving unit according to a control signal issued by the timing controller. The gate driving unit is configured to send the scan signal to the scan line according to the clock signal.

[0013] Optionally, in some embodiments of this application, in the first display mode, the level converter is configured to send a conduction signal to the control terminal of the switching circuit according to a first trigger signal issued by the timing controller, and to send the clock signal to the odd-numbered gate driving unit or the even-numbered gate driving unit; the gate driving unit is configured to output the scan signal according to the clock signal, the switching circuit is in the conduction state, and two adjacent scan lines are simultaneously connected to the same scan signal; In the second display mode, the level converter is configured to send a disconnect signal to the control terminal of the switching circuit and to send the clock signal to all the gate driving units according to the second trigger signal issued by the timing controller; the gate driving unit is configured to output the scan signal according to the clock signal, the switching circuit is in the disconnected state, and each scan line is connected to an independent scan signal.

[0014] Optionally, in some embodiments of this application, the gate driving circuit includes a plurality of gate driving groups, the gate driving group includes at least two gate driving units, the display panel includes a plurality of clock signal lines connected to the level converter, and in the gate driving group, one gate driving unit is connected to one clock signal line. The gate driving unit includes a clock terminal for receiving the clock signal, a trigger terminal for receiving an initial trigger signal or a trigger signal from the previous gate driving unit, a pull-down terminal for receiving a scan signal from the next gate driving unit, and an output terminal connected to the corresponding scan line.

[0015] According to a second aspect of this application, a display device is provided, including a housing and a display module as described in any of the above embodiments, the display module being disposed within the housing.

[0016] In the display module and display device of this application embodiment, the display panel includes a gate driving circuit, multiple scan lines, and multiple switching circuits. The gate driving circuit includes multiple levels of gate driving units. The output terminal of one gate driving unit is electrically connected to one scan line. In two adjacent levels of gate driving units, the output terminal of the odd-numbered level gate driving unit is connected to the first terminal of the switching circuit, and the output terminal of the even-numbered level gate driving unit is connected to the second terminal of the switching circuit. The control terminal of the switching circuit is configured to receive a control signal. The display module has a first display mode and a second display mode. The refresh rate of the first display mode is higher than the refresh rate of the second display mode. In the first display mode, the switching circuit is in a conducting state, and two adjacent scan lines are connected to the same scan signal output by the odd-numbered level gate driving unit or the even-numbered level gate driving unit.

[0017] It is understood that, in the first display mode (high refresh rate mode) of this application embodiment, only one of the odd-numbered gate driving units and the even-numbered gate driving units outputs a scan signal, while the other remains idle. Based on the switching circuit connecting the output terminals of adjacent odd-numbered and even-numbered gate driving units, the scan signal output by a single-stage gate driving unit is transmitted to two scan lines, thereby achieving a high refresh rate. Furthermore, since only one of the odd-numbered and even-numbered gate driving units operates in the same frame during high refresh rate mode, the risk of excessively rapid device temperature rise can be reduced.

[0018] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0021] Figure 1 This is a schematic diagram of the structure of the display module provided in an exemplary embodiment of this disclosure; Figure 2 yes Figure 1 An enlarged schematic diagram of part A in the middle; Figure 3 This is a timing diagram of the display module in the first display mode provided in an exemplary embodiment of this disclosure; Figure 4 yes Figure 1 Another enlarged schematic diagram of part A in the middle; Figure 5 This is a schematic diagram of the structure of a display device provided in an exemplary embodiment of this disclosure.

[0022] Explanation of reference numerals in the attached figures: Display module 100; display panel 10; timing controller 20; level converter 30; circuit board assembly 40; gate drive circuit 10a; scan line s1; gate drive unit goa; switching circuit 10b; switching transistor Ts; control signal line k1; frequency multiplier control port DLG; first low frequency clock port LC1; second low frequency clock port LC2; low level voltage port VSS; trigger control port SV; clock control port CKn; gate drive group au; clock signal line sz; clock terminal CK; initial trigger signal STV; trigger terminal ST; pull-down terminal RT; output terminal OUT; first clock signal line sz1; second clock signal line sz2; third clock signal line sz3; fourth clock signal line sz4; first switching transistor Ts1; second switching transistor Ts2; display device 1000; housing 200. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0024] This application provides a display module 100; please refer to [link / reference]. Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the structure of the display module 100 provided in an exemplary embodiment of this disclosure; Figure 2 yes Figure 1 An enlarged schematic diagram of part A in the middle.

[0025] This application provides a display module 100, which includes a display panel 10, a timing controller 20, a level converter 30, and a circuit board assembly 40.

[0026] The circuit board assembly 40 is bonded to the display panel 10, the level converter 30 is electrically connected to the display panel 10 through the circuit board assembly 40, and the timing controller 20 is connected to the level converter 30.

[0027] Optionally, the circuit board assembly 40 includes a flexible circuit board and a printed circuit board, with one end of the flexible circuit board connected to the display panel 10 and the other end of the flexible circuit board connected to the printed circuit board.

[0028] Optionally, the display panel 10 is either a liquid crystal panel or an electroluminescent panel.

[0029] The display panel 10 includes a gate driving circuit 10a and multiple scan lines s1. The gate driving circuit 10a includes multiple gate driving units goa, and the output terminal OUT of one gate driving unit goa is electrically connected to one scan line s1.

[0030] The display panel 10 includes multiple switching circuits 10b. In two adjacent gate driving units goa, the output terminal OUT of the odd-numbered gate driving unit goa is connected to the first terminal of the switching circuit 10b, and the output terminal OUT of the even-numbered gate driving unit goa is connected to the second terminal of the switching circuit 10b. The control terminal of the switching circuit 10b is configured to receive a control signal.

[0031] The display module 100 has a first display mode and a second display mode, wherein the refresh rate of the first display mode is higher than that of the second display mode. In the first display mode, the switching circuit 10b is in the on state, and two adjacent scan lines s1 are connected to the same scan signal output by either the odd-numbered gate driving unit goa or the even-numbered gate driving unit goa.

[0032] It should be noted that the refresh rate of the first display mode is higher than that of the second display mode. Therefore, the first display mode can be a high refresh rate mode, and the second display mode can be a low refresh rate mode. For example, the refresh rate of the first display mode is 120 Hz, and the refresh rate of the second display mode is 60 Hz, but it is not limited to this.

[0033] Additionally, the odd-numbered gate driving units goa exemplarily include the 1st-level gate driving unit goa, the 3rd-level gate driving unit goa, the 5th-level gate driving unit goa, the 7th-level gate driving unit goa, and the 9th-level gate driving unit goa, etc., the (2n-1)th-level gate driving unit goa, where n ≥ 1 and n is an integer. The even-numbered gate driving units goa exemplarily include the 2nd-level gate driving unit goa, the 4th-level gate driving unit goa, the 6th-level gate driving unit goa, the 8th-level gate driving unit goa, and the 10th-level gate driving unit goa, etc., the (2n)th-level gate driving unit goa.

[0034] It is understood that when the display module 100 of this embodiment is in the first display mode (high refresh rate mode), only one of the odd-level gate driving unit goa and the even-level gate driving unit goa outputs a scan signal, while the other remains idle. Based on the switching circuit 10b conducting the output terminals OUT and OUT of adjacent odd-level gate driving units goa, the scan signal output by a single-level gate driving unit goa is transmitted to two scan lines s1, thereby achieving a high refresh rate. Furthermore, since only one of the odd-level gate driving unit goa and the even-level gate driving unit goa works in the same frame during high refresh rate mode, the risk of excessively rapid device temperature rise can be reduced.

[0035] Optionally, in some embodiments, a level shifter 30 is connected to the gate drive circuit 10a and the switching circuit 10b. The level shifter 30 is configured to control the switching circuit 10b to turn on or off and to supply a clock signal to the gate drive unit goa according to a control signal issued by the timing controller 20. The gate drive unit goa is configured to supply the scan signal to the scan line s1 according to the clock signal.

[0036] It should be noted that the control signals issued by the timing controller 20 include a first trigger signal and a second trigger signal. The first trigger signal corresponds to the first display mode, and the second trigger signal corresponds to the second display mode.

[0037] For example, when the display module 100 needs to be in high refresh rate mode (first display mode), the timing controller 20 will send a first trigger signal to the level converter 30; when the display module 100 needs to be in low refresh rate mode (second display mode), the timing controller 20 will send a second trigger signal to the level converter 30.

[0038] Optionally, in some embodiments of this application, in the first display mode, the level converter 30 is configured to send a conduction signal to the control terminal of the switching circuit 10b according to a first trigger signal issued by the timing controller 20, and to send the clock signal to the odd-level gate driving unit goa or the even-level gate driving unit goa. The gate driving unit goa is configured to output the scan signal according to the clock signal. The switching circuit 10b is in the conduction state. Two adjacent scan lines s1 are simultaneously connected to the same scan signal.

[0039] In the second display mode, the level converter 30 is configured to send a disconnect signal to the control terminal of the switching circuit 10b according to the second trigger signal issued by the timing controller 20, and to send the clock signal to all gate driving units goa; the gate driving unit goa is configured to output the scan signal according to the clock signal, the switching circuit 10b is in the disconnected state, and each scan line s1 is connected to an independent scan signal.

[0040] Understandably, in the same frame, in the first display mode (high refresh rate mode), only one of the odd-numbered gate drive units (goa) and the even-numbered gate drive units (goa) receives the clock signal and enters the working state, while the other is in an idle state. Since the number of working gate drive units (goa) is reduced, the risk of the device overheating too quickly can be reduced in the first display mode.

[0041] Optionally, in some embodiments, in the odd-numbered frame of two adjacent frame frames in the first display mode (high refresh rate mode), only one of the odd-numbered gate driving unit goa and the even-numbered gate driving unit goa receives the clock signal and enters the working state; in the even-numbered frame of two adjacent frame frames, only the other of the odd-numbered gate driving unit goa and the even-numbered gate driving unit goa receives the clock signal and enters the working state.

[0042] In other words, in the first display mode, one of the odd-numbered gate driving unit goa and the even-numbered gate driving unit goa operates in odd-numbered frame intervals, while the other operates in even-numbered frame intervals. This method of alternating the output of scan signals by the odd-numbered and even-numbered gate driving units goa in different frame intervals further reduces the risk of the device overheating.

[0043] Optionally, in some embodiments of this application, in the second display mode, the switching circuit 10b is in the off state, and the odd-numbered gate driving unit goa and the even-numbered gate driving unit goa output scanning signals in sequence.

[0044] Understandably, in the second display mode, the switching circuit 10b is turned off, causing the odd-numbered gate drive unit goa to output a scan signal separately to control the sub-pixels of the odd-numbered rows; the even-numbered gate drive unit goa outputs a scan signal separately to control the sub-pixels of the even-numbered rows, thereby achieving a low refresh rate mode.

[0045] Optionally, in some embodiments of this application, the switching circuit 10b includes a switching transistor Ts, the gate of the switching transistor Ts is the control terminal of the switching circuit 10b, the first terminal of the switching transistor Ts is connected to the odd-level gate driving unit goa, and the second terminal of the switching transistor Ts is connected to the even-level gate driving unit goa.

[0046] Understandably, using a single switching transistor Ts as the switching circuit 10b simplifies the switching circuit 10b, reduces the area required to arrange the switching circuit 10b, and facilitates the implementation of a narrow bezel.

[0047] Optionally, in some embodiments of this application, the switching transistor Ts is an N-type transistor, but is not limited thereto; for example, the switching transistor Ts can be a P-type transistor.

[0048] Taking an N-type transistor as an example, the switching transistor Ts is turned on when a high-level signal is applied to its gate and turned off when a low-level signal is applied. That is, in the first display mode, the turn-on signal sent by the level converter 30 to the switching circuit 10b is a high-level signal; in the second display mode, the turn-off signal sent by the level converter 30 to the switching circuit 10b is a low-level signal.

[0049] Optionally, in some embodiments of this application, the switching transistor Ts is a thin-film transistor, which is disposed on the same layer as at least part of the gate drive circuit 10a to save on manufacturing processes.

[0050] Optionally, in some embodiments of this application, a switching circuit 10b is correspondingly disposed between the scan line s1 connected to the adjacent odd-numbered gate driving unit goa and the scan line s1 connected to the even-numbered gate driving unit goa.

[0051] It is understandable that the switching circuit 10b is placed between the two scan lines s1 adjacent to the gate drive circuit 10a in order to save layout area and facilitate the realization of a narrow bezel.

[0052] Optionally, in some embodiments of this application, the control terminals of all switching circuits 10b are connected to the same control signal line k1.

[0053] It is understood that the display module 100 in this embodiment connects the control terminals of all switching circuits 10b through a single control signal line k1, which saves the layout area of ​​the control signal line k1 and facilitates the realization of a narrow bezel. At the same time, the level converter 30 does not need to be equipped with multiple frequency multiplication control ports DLG, thereby reducing the number of breaks in the level converter 30.

[0054] Optionally, in some embodiments, the level shifter 30 further includes a first low-frequency clock port LC1, a second low-frequency clock port LC2, a low-level voltage port VSS, and a trigger control port SV for starting the first gate drive unit goa.

[0055] The first low-frequency clock port LC1, the second low-frequency clock port LC2, the low-level voltage port VSS, and the trigger control port SV for starting the first gate drive unit goa are each connected to the gate drive circuit 10a through traces within the display panel 10.

[0056] Optionally, in some embodiments of this application, the gate driving circuit 10a includes multiple gate driving groups au, and each gate driving group au includes at least two gate driving units goa. The display panel 10 includes multiple clock signal lines sz connected to the level converter 30. In each gate driving group au, one gate driving unit goa is connected to one clock signal line sz.

[0057] The gate driving unit goa includes a clock terminal CK for receiving the clock signal, a trigger terminal ST for receiving the initial trigger signal STV or the trigger signal of the previous gate driving unit goa, a pull-down terminal RT for receiving the scan signal of the next gate driving unit goa, and an output terminal OUT connected to the corresponding scan line s1.

[0058] It is understood that in the display module 100 of this application embodiment, the plurality of gate driving units goa in the gate driving circuit 10a are cascaded. The trigger signal of the previous stage gate driving unit goa is the scan signal output from the output terminal OUT of the previous stage gate driving unit goa.

[0059] Optionally, in some embodiments of this application, the level converter 30 further includes multiple clock control ports CKn. Each clock control port CKn is connected to a corresponding clock signal line sz.

[0060] Optionally, the gate drive group au includes four gate drive units goa, and the multiple clock signal lines sz include a first clock signal line sz1, a second clock signal line sz2, a third clock signal line sz3, and a fourth clock signal line sz4.

[0061] In each gate drive group au, the first gate drive unit goa is connected to the first clock signal line sz1, the second gate drive unit goa is connected to the second clock signal line sz2, the third gate drive unit goa is connected to the third clock signal line sz3, and the fourth gate drive unit goa is connected to the fourth clock signal line sz4.

[0062] Optionally, in some embodiments of this application, in the first display mode, each clock signal line without a clock signal is grounded through a control circuit to reduce the likelihood of the gate drive unit (GOA) without a clock signal being activated due to interference signals. The control circuit includes a thin-film transistor, the control electrode of each thin-film transistor is connected to the second control port of the level converter 30, the first terminal of each thin-film transistor is connected to a clock signal line without a clock signal, and the second terminal of each thin-film transistor is grounded.

[0063] For example, in the first display mode, the odd-numbered gate driving units goa are connected to a clock signal, while the even-numbered gate driving units goa are not connected to a clock signal. Therefore, the clock signal lines sz corresponding to the even-numbered gate driving units goa are each connected to one of the control circuits. At this time, the control circuit is in the ON state, so that the even-numbered clock signal lines sz are grounded. In the second display mode, the control circuit is in the OFF state, and the odd-numbered clock signal lines sz and even-numbered clock signal lines sz are normally connected to the clock signal.

[0064] Optionally, in some embodiments, the gate drive group au may also include two gate drive units goa, and the multiple clock signal lines sz include a first clock signal line sz1 and a second clock signal line sz2. The first gate drive unit goa of each gate drive group au is connected to the first clock signal line sz1, and the second gate drive unit goa of each gate drive group au is connected to the second clock signal line sz2.

[0065] For example, in some embodiments, the gate drive group au may include eight gate drive units goa, and the multiple clock signal lines sz include a first clock signal line sz1, a second clock signal line sz2, a third clock signal line sz3, a fourth clock signal line sz4, a fifth clock signal line, a sixth clock signal line, a seventh clock signal line, and an eighth clock signal line. Specifically, the first gate drive unit goa of each gate drive group au is connected to the first clock signal line sz1, the second gate drive unit goa of each gate drive group au is connected to the second clock signal line sz2, the third gate drive unit goa of each gate drive group au is connected to the third clock signal line sz3, and the fourth gate drive unit goa of each gate drive group au is connected to the fourth clock signal line sz4. The fifth gate drive unit goa of each gate drive group au is connected to the fifth clock signal line, the sixth gate drive unit goa of each gate drive group au is connected to the sixth clock signal line, the seventh gate drive unit goa of each gate drive group au is connected to the seventh clock signal line, and the eighth gate drive unit goa of each gate drive group au is connected to the eighth clock signal line.

[0066] Please refer to Figure 3 The display module 100 in this embodiment is illustrated by taking the gate drive group au, which includes 4 gate drive units goa, as an example, but is not limited thereto.

[0067] In a single frame of the first display mode, the first clock signal line sz1 and the third clock signal line sz3 are connected to the clock signal, while the second clock signal line sz2 and the fourth clock signal line sz4 are not connected to the clock signal, in order to achieve a high refresh rate mode while reducing the risk of excessive heat generation.

[0068] Please refer to Figure 4 , Figure 4 yes Figure 1 Another enlarged schematic diagram of part A. Figure 4 The following text will describe the parts that differ from the above embodiments in order to avoid redundancy.

[0069] Optionally, in some embodiments of this application, the switching circuit 10b includes a first switching transistor Ts1 and a second switching transistor Ts2. The gates of the first switching transistor Ts1 and the second switching transistor Ts2 are connected to form the control terminal of the switching circuit 10b. The first terminal of the first switching transistor Ts1 is connected to the odd-numbered gate driving unit goa. The first terminal of the first switching transistor Ts1 is connected to the first terminal of the second switching transistor Ts2. The second terminal of the second switching transistor Ts2 is connected to the even-numbered gate driving unit goa.

[0070] It is understandable that dual-switch transistors are used in series as the switching circuit 10b to improve the control capability of the switching circuit 10b and reduce the risk of leakage current.

[0071] Optionally, the first switching transistor Ts1 and the second switching transistor Ts2 are transistors of the same type, such as both being P-type transistors or N-type transistors.

[0072] Optionally, in some embodiments of this application, the first switching transistor Ts1 and the second switching transistor Ts2 are thin-film transistors, which are disposed on the same layer as at least part of the gate driving circuit 10a to save on manufacturing processes.

[0073] Please refer to Figure 5 , Figure 5 This is a schematic diagram of the structure of the display device 1000 provided in an exemplary embodiment of this disclosure.

[0074] This application provides a display device 1000, including a housing 200 and a display module 100 as described in any of the above embodiments, wherein the display module 100 is disposed within the housing 200.

[0075] It should be noted that the structure of the display module 100 of the display device 1000 in this application embodiment is similar to or the same as the structure of the display module 100 in the above embodiments. For details, please refer to... Figures 1 to 4 Therefore, the relevant explanations will not be repeated here.

[0076] Optionally, the display device 1000 can be at least one of the following: smartphone, tablet, mobile phone, video phone, e-book reader, desktop computer, laptop, netbook, workstation, server, personal digital assistant, portable media player, MP3 player, television, mobile medical device, camera, game console, digital camera, car navigation system, in-vehicle display, electronic billboard, ATM, or wearable device, VR device, AR device.

[0077] In the display device 1000 of this application embodiment, the display panel 10 includes a gate driving circuit 10a, multiple scan lines s1, and multiple switching circuits 10b. The gate driving circuit 10a includes multiple gate driving units goa. The output terminal OUT of one gate driving unit goa is electrically connected to a scan line s1. In two adjacent gate driving units goa, the output terminal OUT of the odd-numbered gate driving unit goa is connected to the first terminal of the switching circuit 10b, and the output terminal OUT of the even-numbered gate driving unit goa is connected to the second terminal of the switching circuit 10b. The control terminal of the switching circuit 10b is configured to receive a control signal. The display module 100 has a first display mode and a second display mode. The refresh rate of the first display mode is higher than the refresh rate of the second display mode. In the first display mode, the switching circuit 10b is in the on state, and two adjacent scan lines s1 are connected to the same scan signal output by the odd-numbered or even-numbered gate driving units goa.

[0078] It is understood that, in the first display mode (high refresh rate mode) of this application embodiment, only one of the odd-level gate driving unit goa and the even-level gate driving unit goa outputs a scan signal, while the other remains idle. Based on the switching circuit 10b conducting the output terminals OUT of adjacent odd-level gate driving units goa and even-level gate driving units goa, the scan signal output by a single-level gate driving unit goa is transmitted to the two scan lines s1, thereby achieving a high refresh rate. Furthermore, since only one of the odd-level gate driving unit goa and the even-level gate driving unit goa works in the same frame in high refresh rate mode, the risk of excessively rapid device temperature rise can be reduced.

[0079] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0080] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0081] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0082] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display module, characterized in that, include: The display panel includes a gate driving circuit, multiple scan lines, and multiple switching circuits. The gate driving circuit includes multiple gate driving units. The output terminal of one gate driving unit is electrically connected to one scan line. In two adjacent gate driving units, the output terminal of the odd-numbered gate driving unit is connected to the first terminal of the switching circuit, and the output terminal of the even-numbered gate driving unit is connected to the second terminal of the switching circuit. The control terminal of the switching circuit is configured to receive a control signal. The display module has a first display mode and a second display mode. The refresh rate of the first display mode is higher than that of the second display mode. In the first display mode, the switching circuit is in the on state, and two adjacent scan lines are connected to the same scan signal output by the odd-numbered level gate driving unit or the even-numbered level gate driving unit.

2. The display module according to claim 1, characterized in that, The switching circuit includes a switching transistor, the gate of which is the control terminal of the switching circuit. The first terminal of the switching transistor is connected to the odd-numbered gate driving units, and the second terminal of the switching transistor is connected to the even-numbered gate driving units.

3. The display module according to claim 2, characterized in that, The switching transistor is an N-type transistor.

4. The display module according to claim 1, characterized in that, The switching circuit includes a first switching transistor and a second switching transistor. The gates of the first switching transistor and the second switching transistor are connected to form the control terminal of the switching circuit. The first terminal of the first switching transistor is connected to the odd-numbered gate driving unit, the first terminal of the first switching transistor is connected to the first terminal of the second switching transistor, and the second terminal of the second switching transistor is connected to the even-numbered gate driving unit.

5. The display module according to claim 1, characterized in that, The switching circuit is correspondingly disposed between the scan lines connected to the gate driving units of adjacent odd-numbered levels and the scan lines connected to the gate driving units of even-numbered levels.

6. The display module according to claim 1, characterized in that, The control terminals of all the aforementioned switching circuits are connected to the same control signal line.

7. The display module according to claim 1, characterized in that, In the second display mode, the switching circuit is in the off state, and the odd-numbered gate driving units and the even-numbered gate driving units output scanning signals in sequence.

8. The display module according to any one of claims 1-7, characterized in that, The display module includes a timing controller and a level converter. The timing controller is connected to the level converter, which is connected to the gate driving circuit and the switching circuit. The level converter is configured to control the switching circuit to turn on or off and to send a clock signal to the gate driving unit according to a control signal issued by the timing controller. The gate driving unit is configured to send the scan signal to the scan line according to the clock signal.

9. The display module according to claim 8, characterized in that, In the first display mode, the level converter is configured to send a conduction signal to the control terminal of the switching circuit according to a first trigger signal issued by the timing controller, and to send the clock signal to the odd-numbered gate driving unit or the even-numbered gate driving unit; the gate driving unit is configured to output the scan signal according to the clock signal, the switching circuit is in the conduction state, and two adjacent scan lines are simultaneously connected to the same scan signal. In the second display mode, the level converter is configured to send a disconnect signal to the control terminal of the switching circuit and to send the clock signal to all the gate driving units according to the second trigger signal issued by the timing controller; the gate driving unit is configured to output the scan signal according to the clock signal, the switching circuit is in the disconnected state, and each scan line is connected to an independent scan signal.

10. A display device, characterized in that, It includes a housing and a display module as described in any one of claims 1-9, wherein the display module is disposed within the housing.

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