DC-DC converter and chip

Abstract

This disclosure provides a DC-DC converter and chip, wherein the DC-DC converter includes a bootstrap boost circuit, a charge pump boost circuit, a high-side drive circuit, a low-side drive circuit, a high-side power transistor, and a low-side power transistor. The bootstrap boost circuit provides a first boost voltage to the high-side drive circuit. The high-side drive circuit outputs a first high-side drive voltage to the control electrode of the high-side power transistor based on the first boost voltage. The charge pump boost circuit generates a second boost voltage through a charge pump and outputs a second high-side drive voltage to the control electrode of the high-side power transistor based on the second boost voltage. The second boost voltage is greater than the first boost voltage. The first electrode of the high-side power transistor is coupled to the input voltage terminal, and the second electrode is coupled to the first electrode of the low-side power transistor via a switching node. The high-side power transistor is turned on or off according to the first and second high-side drive voltages. One end of the bootstrap boost circuit and one end of the charge pump boost circuit are respectively coupled to the switching node.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, specifically to a DC-DC converter and chip. Background Technology

[0002] With the expanding integrated circuit market, DC-DC converters have developed rapidly. As a switching power supply technology, DC-DC converters have advantages such as fast dynamic response and simple control, and have a wide range of applications.

[0003] Currently, when NMOS is selected as the power transistor in a BUCK-type DC-DC converter, a bootstrap capacitor is required to power the driving section of the power transistor. However, in order to obtain a lower high-side power transistor on-resistance, the capacitance value and area of ​​the bootstrap capacitor are often large, resulting in higher chip costs.

[0004] There is currently no effective technical solution to the problem of high chip cost due to the large capacitance and area of ​​the bootstrap capacitor in BUCK-type DC-DC converters. Summary of the Invention

[0005] The main objective of this disclosure is to provide a DC-DC converter and chip to solve the problem that the large capacitance and area of ​​the bootstrap capacitor in the BUCK-type DC-DC converter lead to high chip cost.

[0006] To achieve the above objectives, a first aspect of this disclosure provides a DC-DC converter, including a bootstrap boost circuit, a charge pump boost circuit, a high-side drive circuit, a low-side drive circuit, a high-side power transistor, and a low-side power transistor.

[0007] The bootstrap boost circuit is configured to provide a first boost voltage to the high-side drive circuit based on the input voltage at the input voltage terminal;

[0008] The high-side drive circuit is configured to output a first high-side drive voltage to the control electrode of the high-side power transistor based on the pulse width modulation signal at the modulation signal terminal.

[0009] The charge pump boost circuit is configured to generate a second boost voltage via a charge pump and output a second high-side drive voltage to the control electrode of the high-side power transistor based on the second boost voltage, wherein the second boost voltage is greater than the first boost voltage;

[0010] The low-side drive circuit is configured to output a low-side drive voltage to the control electrode of the low-side power transistor based on the pulse width modulation signal at the modulation signal terminal.

[0011] The first terminal of the high-side power transistor is coupled to the input voltage terminal, and the second terminal of the high-side power transistor is coupled to the first terminal of the low-side power transistor via a switching node. The high-side power transistor is configured to be turned on or off according to the first high-side drive voltage and the second high-side drive voltage, and the low-side power transistor is configured to be turned on or off according to the low-side drive voltage.

[0012] One end of the bootstrap boost circuit and one end of the charge pump boost circuit are respectively coupled to a switching node.

[0013] Optionally, the bootstrap circuit includes a first diode and a first bootstrap capacitor;

[0014] The first end of the first diode is coupled to the input voltage terminal, and the second end of the first diode is coupled to the first end of the first bootstrap capacitor and the first end of the high-side drive circuit via the first bootstrap node.

[0015] The second terminal of the first bootstrap capacitor is coupled to the second terminal of the switching node and the high-side drive circuit, respectively. The first bootstrap capacitor is configured to charge based on the input voltage when the pulse width modulation signal is low and to provide a first boost voltage to the high-side drive circuit when the pulse width modulation signal is high.

[0016] Furthermore, the charge pump boost circuit includes a charge pump, a unidirectional rectifier circuit, a second bootstrap capacitor, and a high-voltage drive circuit;

[0017] The charge pump is configured to charge the second bootstrap capacitor to N times the input voltage via a unidirectional rectifier circuit, where N is a positive integer greater than 1.

[0018] The first end of the unidirectional rectifier circuit is coupled to the charge pump, and the second end of the unidirectional rectifier circuit is coupled to the first end of the second bootstrap capacitor and the first end of the high voltage drive circuit via the second bootstrap node.

[0019] The second end of the second bootstrap capacitor is coupled to the switching node. The second bootstrap capacitor is configured to charge based on a charge pump when the pulse width modulation signal is low, and to provide a second boost voltage to the high voltage drive circuit when the pulse width modulation signal is high and the voltage of the switching node rises to the input voltage.

[0020] The second terminal of the high-voltage drive circuit is coupled to the control electrode of the high-side power transistor. The high-voltage drive circuit is configured to output a second high-side drive voltage to the control electrode of the high-side power transistor based on the second boost voltage.

[0021] Optionally, the unidirectional rectifier circuit includes a unidirectional conducting switch.

[0022] Optionally, the unidirectional rectifier circuit includes a second diode.

[0023] Furthermore, when N is 3, the charge pump includes a digital receiver, a first transistor, a second transistor, and a third transistor;

[0024] The first terminal of the digital receiver is coupled to the modulation signal terminal, the second terminal of the digital receiver is coupled to the bootstrap control signal terminal, the third terminal of the digital receiver is coupled to the control electrode of the first transistor, and the fourth terminal of the digital receiver is coupled to the control electrode of the second transistor. The digital receiver is configured to control the first transistor and the second transistor to turn on or off according to the pulse width modulation signal of the modulation signal terminal and the bootstrap control signal of the bootstrap control signal terminal.

[0025] The first terminal of the first transistor is coupled to the first terminal of the second transistor, the first terminal of the third transistor and the second terminal of the first bootstrap capacitor, respectively. The second terminal of the first transistor is coupled to the input voltage terminal and the first terminal of the first diode, respectively. The second terminal of the second transistor is grounded.

[0026] The control electrode of the third transistor is coupled to the modulation signal terminal, and the second electrode of the third transistor is coupled to the switching node. The pulse width modulation signal at the modulation signal terminal controls the turning on or off of the third transistor.

[0027] Furthermore, the high-voltage drive circuit includes a fourth transistor, a third diode, a fourth diode, and a third bootstrap capacitor;

[0028] The first terminal of the third bootstrap capacitor is coupled to the second terminal of the third diode, the first terminal of the fourth diode, and the control electrode of the fourth transistor, respectively. The second terminal of the third bootstrap capacitor is grounded. The third bootstrap capacitor is configured to output a signal to the control electrode of the fourth transistor.

[0029] The first terminal of the fourth transistor is coupled to the control terminal of the high-side power transistor, and the second terminal of the fourth transistor is coupled to the second bootstrap node. The fourth transistor is configured to turn on or off based on the voltage difference between the control terminal voltage and the second terminal voltage of the fourth transistor.

[0030] The first end of the third diode is coupled to the first end of the first bootstrap node and the first end of the second diode, respectively, and the second end of the fourth diode is coupled to the second end of the second diode and the second bootstrap node, respectively.

[0031] Furthermore, when the pulse width modulation signal at the modulation signal terminal is low, the bootstrap control signal at the bootstrap control signal terminal is a square wave signal, the first transistor and the second transistor are turned on, the third transistor is turned off, the high-side power transistor is turned off, the low-side power transistor is turned on, the first bootstrap capacitor is configured to charge the second bootstrap capacitor to twice the input voltage via the second diode, and the third bootstrap capacitor is charged to twice the input voltage via the third diode, and the fourth transistor is turned off.

[0032] When the pulse width modulation signal at the modulation signal terminal is high, the first and second transistors are off, the third transistor is on, the high-side power transistor is on, the low-side power transistor is off, and the switching node voltage rises. When the switching node voltage rises to a preset threshold, the fourth transistor is on. When the switching node voltage rises to the input voltage, the voltage on the upper plate of the second bootstrap capacitor is raised to three times the input voltage, where the preset threshold is less than the input voltage.

[0033] Optionally, the DC-DC converter also includes an output circuit, one end of which is coupled to a switching node, and the output circuit is configured to generate an output voltage;

[0034] The output circuit includes an inductor, an output capacitor, an equivalent series resistor, and an output resistor;

[0035] The first end of the inductor is coupled to the switching node, and the second end of the inductor is coupled to the first end of the equivalent series resistor, the first end of the output resistor, and the output voltage terminal, respectively. The output voltage is generated at the output voltage terminal based on the inductance current flowing through the inductor.

[0036] The second end of the equivalent series resistor is coupled to the first end of the output capacitor, and the second end of the output capacitor and the second end of the output resistor are respectively grounded.

[0037] A second aspect of this disclosure provides a chip that includes any of the DC-DC converters of the first aspect.

[0038] A third aspect of this disclosure provides an electronic device that includes the chip of the second aspect.

[0039] In the DC-DC converter provided in this embodiment, a charge pump boost circuit is introduced to generate a second boost voltage, which is greater than the first boost voltage provided by the bootstrap boost circuit. The high-side drive circuit outputs a first high-side drive voltage to the control electrode of the high-side power transistor based on the first boost voltage, and the charge pump boost circuit outputs a second high-side drive voltage to the control electrode of the high-side power transistor based on the second boost voltage. The output second high-side drive voltage is greater than the first high-side drive voltage, thereby increasing the control electrode voltage of the high-side power transistor. This disclosure generates a second boost voltage greater than the first boost voltage through the charge pump boost circuit, thereby increasing the control electrode voltage of the high-side power transistor. This allows a smaller bootstrap capacitor to obtain a higher gate-source voltage of the high-side power transistor, reducing the capacitance value of the built-in bootstrap capacitor in the DC-DC converter, reducing the area of ​​the built-in bootstrap capacitor, and thus reducing the chip cost. This solves the problem of high chip cost caused by the large capacitance value and area of ​​the bootstrap capacitor in BUCK-type DC-DC converters. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a circuit diagram of a BUCK-type DC-DC converter in related technologies;

[0042] Figure 2 An exemplary block diagram of a DC-DC converter provided in an embodiment of this disclosure;

[0043] Figure 3 An exemplary circuit diagram of a DC-DC converter provided in an embodiment of this disclosure;

[0044] Figure 4 An exemplary circuit diagram of a DC-DC converter provided in yet another embodiment of this disclosure. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0046] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0047] In all embodiments of this disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. The transistors used in the embodiments of this disclosure are primarily switching transistors. Furthermore, for the sake of consistency, in this context, the base of a bipolar junction transistor (BJT) is referred to as the control terminal, the emitter of the BJT as the first terminal, and the collector of the BJT as the second terminal. Additionally, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0048] Currently, when NMOS is selected as the power transistor in a BUCK-type DC-DC converter, a bootstrap capacitor (BST capacitor) is required to power the driving section of the power transistor. Figure 1 This diagram illustrates a circuit diagram of a low-voltage BUCK-type DC-DC converter in the related art. The PWM signal is a pulse width modulation signal, Vin is the input voltage (low voltage, ranging from 2.5V to 5.5V), Vout is the output voltage, SBD is a Schottky diode, BST and SW represent the bootstrap node and switching node in the circuit, respectively, Cbst is the bootstrap capacitor, Driver_Hside is the high-side drive circuit, HS is the high-side power transistor, Driver_Lside is the low-side drive circuit, LS is the low-side power transistor, L is an inductor, Cout is the output capacitor, Resr is the equivalent series resistance, and R... L For output resistance;

[0049] To achieve a lower on-resistance of the high-side power transistor (HS), the bootstrap capacitor Cbst is typically large. Traditionally, an external bootstrap capacitor Cbst is added, which requires an additional BST pin. To avoid this additional BST pin, the bootstrap capacitor Cbst is integrated into the chip.

[0050] Since the on-resistance of a MOSFET is inversely proportional to its gate-source voltage Vgs, a higher gate-source voltage Vgs is required to achieve a lower on-resistance for the same MOSFET area. The gate-source voltage Vgs of the high-side power transistor HS in a BUCK-type DC-DC converter with a built-in bootstrap capacitor Cbst can be calculated as follows:

[0051] 1: Assuming the total charge of the high-side power transistor HS is Qt, and the voltage after driving is Vgs, then Qt = Vgs * Cgs, and an equivalent gate capacitance of Cgs can be obtained.

[0052] 2: After the bootstrap capacitor Cbst is charged by the input voltage Vin, its voltage becomes Vin. Assuming that the drive stage losses are ignored, and the bootstrap capacitor Cbst is used directly to provide the drive voltage to the gate of HS, a shared charge process can be obtained:

[0053] Vin*Cbst=Vgs*(Cgs+Cbst), that is, the gate-source voltage Vgs is Vgs=Vin*Cbst / (Cgs+Cbst);

[0054] As can be seen, if Cgs = Cbst, then Vgs = 1 / 2 * Vin. To obtain a higher Vgs, a larger bootstrap capacitor Cbst is required.

[0055] However, since the capacitance value is proportional to the area of ​​the capacitor plates, the larger the capacitance value of the bootstrap capacitor Cbst, the larger the area of ​​the bootstrap capacitor Cbst, which leads to higher chip costs.

[0056] The inventors discovered that in order to reduce chip costs, it is necessary to reduce or optimize the area of ​​the built-in bootstrap capacitor and reduce or avoid increasing the capacitance value of the bootstrap capacitor Cbst. A higher gate-source voltage Vgs of the high-side power transistor HS can be obtained with a smaller bootstrap capacitor Cbst, thereby obtaining a lower on-resistance of the high-side power transistor HS. Therefore, it is urgent to achieve a higher gate-source voltage Vgs of the high-side power transistor HS with a smaller bootstrap capacitor Cbst.

[0057] Regarding the charge sharing process in the above calculation method, if the capacitance value of the bootstrap capacitor Cbst is doubled, i.e., Cbst = 2 * Cgs, then Vgs = 2 / 3 * Vin; if the initial voltage of the bootstrap capacitor Cbst is doubled, i.e., the initial voltage is 2 * Vin, then Vgs = 2 * Vin * Cbst / (Cgs + Cbst) = Vin, and the gate-source voltage Vgs is also doubled.

[0058] The above analysis shows that increasing the initial voltage of the bootstrap capacitor Cbst is more effective than increasing the area of ​​the bootstrap capacitor Cbst in improving the gate-source voltage Vgs of the high-side power transistor HS.

[0059] Therefore, this embodiment adds a built-in second bootstrap capacitor C_BST2 to the original first bootstrap capacitor C_BST1. Compared with the initial voltage of the original first bootstrap capacitor C_BST1, the initial voltage of the second bootstrap capacitor C_BST2 is increased by the charge pump in the charge pump boost circuit. The second bootstrap capacitor C_BST2 uses a higher initial voltage, and can share more charge during the driving process with the same capacitor area, resulting in a higher driving voltage of the high-side power transistor HS gate. This embodiment provides a higher initial voltage for the second bootstrap capacitor C_BST2, so that the area of ​​the second bootstrap capacitor C_BST2 is smaller while obtaining the same high-side power transistor HS gate-source voltage Vgs, thus achieving an optimized design of the built-in bootstrap capacitor area and reducing chip cost.

[0060] This disclosure provides a DC-DC converter, an exemplary block diagram of which is shown below. Figure 2 As shown, it includes a bootstrap boost circuit, a charge pump boost circuit, a high-side drive circuit Driver_Hside, a low-side drive circuit Driver_Lside, a high-side power transistor HS, and a low-side power transistor LS;

[0061] The bootstrap boost circuit is configured to provide a first boost voltage to the high-side drive circuit Driver_Hside based on the input voltage Vin at the input voltage terminal;

[0062] The high-side drive circuit Driver_Hside is configured to output a first high-side drive voltage to the control electrode of the high-side power transistor HS based on the pulse width modulation (PWM) signal at the modulation signal terminal. The PWM signal can be directly output to the control electrode of the high-side power transistor HS, or it can be matched to the level converter of the high-side power transistor HS and output to the control electrode of the high-side power transistor HS via the level converter. The control electrode corresponds to the gate of the MOS transistor.

[0063] The charge pump boost circuit is configured to generate a second boost voltage via a charge pump and output a second high-side drive voltage to the control electrode of the high-side power transistor HS based on the second boost voltage, wherein the second boost voltage is greater than the first boost voltage. The generation of a second boost voltage greater than the first boost voltage by the charge pump boost circuit allows a smaller bootstrap capacitor value to achieve a higher gate-source voltage Vgs for the high-side power transistor HS, thereby resulting in a lower on-resistance for the high-side power transistor HS. The second high-side drive voltage output to the control electrode of the high-side power transistor HS based on the second boost voltage is greater than the first high-side drive voltage output to the control electrode of the high-side power transistor HS based on the first boost voltage.

[0064] The low-side drive circuit Driver_Lside is configured to output a low-side drive voltage to the control electrode of the low-side power transistor LS based on the pulse width modulation (PWM) signal at the modulation signal terminal.

[0065] The first terminal of the high-side power transistor HS is coupled to the input voltage terminal, and the second terminal of the high-side power transistor HS is coupled to the first terminal of the low-side power transistor LS via a switching node. The high-side power transistor HS is configured to be turned on or off according to the first high-side drive voltage and the second high-side drive voltage, and the low-side power transistor LS is configured to be turned on or off according to the low-side drive voltage. The second terminal of the low-side power transistor LS is grounded.

[0066] One end of the bootstrap boost circuit and one end of the charge pump boost circuit are respectively coupled to the switching node SW.

[0067] Figure 2 The DC-DC converter shown also includes an output circuit, one end of which is coupled to a switching node SW, and the output circuit is configured to generate an output voltage.

[0068] Under the premise of obtaining the same gate-source voltage of the high-side power transistor, the embodiment of this disclosure can greatly reduce the area of ​​the bootstrap capacitor by boosting the starting voltage through the charge pump in the charge pump boost circuit. The same gate-source voltage of the high-side power transistor can be obtained with the smallest bootstrap capacitor, thereby achieving optimized design of the built-in bootstrap capacitor area and reducing chip cost.

[0069] An exemplary circuit diagram of the DC-DC converter provided in this disclosure is shown below. Figure 3 As shown, the bootstrap boost circuit includes a first diode D1 and a first bootstrap capacitor C_BST1; wherein the first diode D1 can be a Schottky diode;

[0070] The first terminal of the first diode D1 is coupled to the input voltage terminal, and the second terminal of the first diode D1 is coupled to the first terminal of the first bootstrap capacitor C_BST1 and the first terminal of the high-side drive circuit Driver_Hside via the first bootstrap node BST1.

[0071] The second terminal of the first bootstrap capacitor C_BST1 is coupled to the second terminal of the switching node SW and the high-side drive circuit Driver_Hside, respectively. The first bootstrap capacitor C_BST1 is configured to charge based on the input voltage Vin when the pulse width modulation PWM signal is low, and to provide a first boost voltage to the high-side drive circuit Driver_Hside when the pulse width modulation PWM signal is high.

[0072] Among them, the first diode D1 plays a rectification role. When the pulse width modulation (PWM) signal is high, the high-side power transistor HS is turned on and the low-side power transistor LS is turned off. The voltage at the switching node SW is Vin. The voltage of the upper plate of the first bootstrap capacitor C_BST1 is raised to be greater than Vin. The first diode D1 can prevent the upper plate of the first bootstrap capacitor C_BST1 from discharging to the input voltage terminal.

[0073] Figure 3 In the process, the charge pump boost circuit includes a charge pump, a unidirectional rectifier circuit, a second bootstrap capacitor C_BST2, and a high-voltage drive circuit;

[0074] The charge pump is configured to charge the second bootstrap capacitor C_BST2 to N times the input voltage Vin via a unidirectional rectifier circuit, where N is a positive integer greater than 1; provided that the same gate-source voltage Vgs of the high-side power transistor HS is obtained, the higher the initial voltage N*Vin at which the charge pump charges the second bootstrap capacitor C_BST2, the smaller the area of ​​the second bootstrap capacitor C_BST2.

[0075] The first end of the unidirectional rectifier circuit is coupled to the charge pump, and the second end of the unidirectional rectifier circuit is coupled to the first end of the second bootstrap capacitor C_BST2 and the first end of the high voltage drive circuit via the second bootstrap node BST2.

[0076] The second end of the second bootstrap capacitor C_BST2 is coupled to the switching node SW. The second bootstrap capacitor C_BST2 is configured to charge based on the charge pump when the pulse width modulation PWM signal is low, and to provide a second boost voltage for the high voltage drive circuit when the pulse width modulation PWM signal is high and the voltage of the switching node SW rises to the input voltage Vin.

[0077] The second terminal of the high-voltage drive circuit is coupled to the control electrode of the high-side power transistor HS. The high-voltage drive circuit is configured to output a second high-side drive voltage to the control electrode of the high-side power transistor HS based on the second boost voltage.

[0078] Specifically, when the pulse width modulation (PWM) signal is low, the charge pump charges the second bootstrap capacitor C_BST2; when the PWM signal is high, the first bootstrap capacitor C_BST1 initially supplies power to the high-side drive circuit Driver_Hside, providing the first boost voltage to Driver_Hside, which in turn drives the high-side power transistor HS, causing HS to turn on and the low-side power transistor LS to turn off. The voltage at the switching node SW begins to rise, and the voltage at the first bootstrap node BST1 and the second bootstrap node BST2 are gradually increased.

[0079] When the pulse width modulation (PWM) signal is high and the voltage at the switching node SW rises to Vin, the second bootstrap capacitor C_BST2 supplies power to the high-voltage drive circuit, providing a second boost voltage to the high-voltage drive circuit. The high-voltage drive circuit then outputs a second high-side drive voltage to the control electrode of the high-side power transistor HS, driving the high-side power transistor HS to raise the voltage at the first bootstrap node BST1 and the voltage at the second bootstrap node BST2 by 1 Vin.

[0080] In one optional embodiment of this disclosure, the unidirectional rectifier circuit includes a unidirectional conducting switch. The unidirectional rectifier circuit can be a unidirectional conducting switch with appropriate logic control.

[0081] Figure 3 In this circuit, the unidirectional rectifier circuit includes a second diode D2. Alternatively, the unidirectional rectifier circuit can also consist of a second diode D2.

[0082] Figure 3 In the circuit, the output circuit includes an inductor L, an output capacitor Cout, an equivalent series resistor Resr, and an output resistor R. L Where Resr is the parasitic resistance of the output capacitor Cout;

[0083] The first terminal of inductor L is coupled to the switching node SW, and the second terminal of inductor L is coupled to the first terminal of the equivalent series resistor Resr and the output resistor R. L The first terminal and the output voltage terminal generate the output voltage Vout at the output voltage terminal based on the inductor current flowing through the inductor L;

[0084] The second terminal of the equivalent series resistor Resr is coupled to the first terminal of the output capacitor Cout, and the second terminal of the output capacitor Cout is coupled to the output resistor R. L The second end is grounded respectively.

[0085] The following is combined Figure 3 An exemplary circuit diagram of a DC-DC converter illustrates the working principle of a DC-DC converter.

[0086] During the Toff period, the PWM signal is low, the high-side power transistor HS is off, the low-side power transistor LS is on, the voltage at the switching node SW is 0, and the charge pump charges the second bootstrap capacitor C_BST2 to N*Vin, where N is a positive number greater than 1, such as 2, 3, 4, or 5. Among these, under the premise of obtaining the same gate-source voltage Vgs of the high-side power transistor HS, the higher the initial voltage N*Vin of the charge pump charging the second bootstrap capacitor C_BST2, the smaller the area of ​​the second bootstrap capacitor C_BST2.

[0087] During the Ton period, the PWM signal is high, the high-side power transistor HS is turned on, and the low-side power transistor LS is turned off. Initially, the first bootstrap capacitor C_BST1 provides the first boost voltage to the high-side drive circuit Driver_Hside, powering the high-side drive circuit Driver_Hside. The high-side drive circuit Driver_Hside outputs the first high-side drive voltage to the gate of the high-side power transistor HS until the voltage at the switching node SW rises to Vin. At this time, the second bootstrap capacitor C_BST2 provides the second boost voltage to the high-voltage drive circuit, powering the high-voltage drive circuit. The high-voltage drive circuit outputs the second high-side drive voltage to the gate of the high-side power transistor HS.

[0088] Under the premise of obtaining the same gate-source voltage Vgs of the high-side power transistor, the second bootstrap capacitor C_BST2 is charged to N*Vin by the charge pump, which increases the starting voltage of the second bootstrap capacitor C_BST2. This can greatly reduce the area of ​​the second bootstrap capacitor C_BST2. The same gate-source voltage Vgs of the high-side power transistor is obtained with the smallest second bootstrap capacitor C_BST2, thus achieving the optimized design of the area of ​​the built-in second bootstrap capacitor C_BST2, which completes the optimized design of the area of ​​the built-in bootstrap capacitor.

[0089] In one optional embodiment of this disclosure, for an initial voltage N*Vin used to charge the second bootstrap capacitor C_BST2, when N is 3, an exemplary circuit diagram of the DC-DC converter is shown below. Figure 4 As shown, the charge pump includes a digital receiver DR, a first transistor P1, a second transistor P2, and a third transistor P3;

[0090] Specifically, the first transistor P1 is an enhancement-mode MOSFET with P-type compensation, which separates the P-type base region and the N-type channel region, thus preventing reverse breakdown of the PN junction and improving the stability and controllability of the MOSFET.

[0091] The first terminal of the digital receiver DR is coupled to the modulation signal terminal, the second terminal of the digital receiver DR is coupled to the bootstrap control signal terminal, the third terminal of the digital receiver DR is coupled to the control electrode of the first transistor P1, and the fourth terminal of the digital receiver DR is coupled to the control electrode of the second transistor P2. The digital receiver DR is configured to control the first transistor P1 and the second transistor P2 to turn on or off according to the pulse width modulation PWM signal of the modulation signal terminal and the bootstrap control signal BST_Control of the bootstrap control signal terminal.

[0092] The first terminal of the first transistor P1 is coupled to the first terminal of the second transistor P2, the first terminal of the third transistor P3 and the second terminal of the first bootstrap capacitor C_BST1, respectively. The second terminal of the first transistor P1 is coupled to the input voltage terminal and the first terminal of the first diode D1, respectively. The second terminal of the second transistor P2 is grounded.

[0093] The control electrode of the third transistor P3 is coupled to the modulation signal terminal, and the second electrode of the third transistor P3 is coupled to the switching node SW. The pulse width modulation (PWM) signal at the modulation signal terminal controls the turning on or off of the third transistor P3.

[0094] Figure 4 In this embodiment, the high-voltage drive circuit includes a fourth transistor P4, a third diode D3, a fourth diode D4, and a third bootstrap capacitor C_BST3. The fourth transistor P4 is an enhancement-mode MOS transistor with P-type compensation, separating the P-type base region from the N-type channel region to prevent reverse breakdown of the PN junction and improve the stability and controllability of the MOS transistor. Furthermore, the fourth transistor P4 is a high-voltage PMOS transistor (HVPMOS transistor). In this embodiment, it is assumed that the forward voltage drop of each diode is 0. When precise calculations are required for the application scenario, values ​​can be assigned to the forward voltage drops of each diode.

[0095] The first terminal of the third bootstrap capacitor C_BST3 is coupled to the second terminal of the third diode D3, the first terminal of the fourth diode D4, and the control electrode of the fourth transistor P4, respectively. The second terminal of the third bootstrap capacitor C_BST3 is grounded. The third bootstrap capacitor C_BST3 is configured to output a signal to the control electrode of the fourth transistor P4.

[0096] The first terminal of the fourth transistor P4 is coupled to the control terminal of the high-side power transistor HS, and the second terminal of the fourth transistor P4 is coupled to the second bootstrap node BST2. The fourth transistor P4 is configured to turn on or off based on the voltage difference between the control terminal voltage and the second terminal voltage of the fourth transistor P4.

[0097] The first terminal of the third diode D3 is coupled to the first terminal of the first bootstrap node BST1 and the first terminal of the second diode D2, respectively. The second terminal of the fourth diode D4 is coupled to the second terminal of the second diode D2 and the second bootstrap node BST2, respectively.

[0098] In a preferred embodiment of this disclosure, when the pulse width modulation (PWM) signal at the modulation signal terminal is low, the bootstrap control signal BST_Control at the bootstrap control signal terminal is a square wave signal, the first transistor P1 and the second transistor P2 are turned on, the third transistor P3 is turned off, the high-side power transistor HS is turned off, the low-side power transistor LS is turned on, the first bootstrap capacitor C_BST1 is configured to charge the second bootstrap capacitor C_BST2 to twice the input voltage Vin via the second diode D2, and the third bootstrap capacitor C_BST3 is charged to twice the input voltage Vin via the third diode D3, and the fourth transistor P4 is turned off.

[0099] When the pulse width modulation (PWM) signal at the modulation signal terminal is high, the first transistor P1 and the second transistor P2 are turned off, the third transistor P3 is turned on, the high-side power transistor HS is turned on, the low-side power transistor LS is turned off, and the voltage of the switching node SW increases. When the voltage of the switching node SW increases to a preset threshold, the fourth transistor P4 is turned on. When the voltage of the switching node SW increases to the input voltage Vin, the voltage of the upper plate of the second bootstrap capacitor C_BST2 is raised to 3 times the input voltage Vin, where the preset threshold is less than the input voltage Vin.

[0100] The following is combined Figure 4 An exemplary circuit diagram of a DC-DC converter illustrates the working principle of a DC-DC converter.

[0101] Figure 4 It is assumed that the forward voltage drop of each diode is 0. When the application requires accurate calculation of the forward voltage drop of each diode, a value can be assigned to the forward voltage drop of each diode. In a low-voltage BUCK DC-DC converter, the input voltage Vin is 2.5V to 5V. For the initial voltage N*Vin charged to the second bootstrap capacitor C_BST2, when the initial voltage N*Vin is 3*Vin, the working principle of the DC-DC converter is as follows:

[0102] During the Toff period, the PWM signal is low, the bootstrap control signal BST_Control is set to a square wave signal, the first transistor P1 and the second transistor P2 are turned on, the third transistor P3 is turned off, the high-side power transistor HS is turned off, and the low-side power transistor LS is turned on. The first bootstrap capacitor C_BST1 charges both the second bootstrap capacitor C_BST2 and the third bootstrap capacitor C_BST3 to 2*Vin. The voltage of the upper plate of the second bootstrap capacitor C_BST2 and the third bootstrap capacitor C_BST3 is the voltage at the first bootstrap node BST1, i.e., 2*Vin. The third bootstrap capacitor C_BST3 controls the gate voltage Vg of the fourth transistor P4. The gate-source voltage Vgs of the fourth transistor P4 is 0, so it is always in the off state.

[0103] In the initial stage of Ton, after the PWM signal changes from low to high, the first transistor P1 and the second transistor P2 are turned off, and the third transistor P3 is turned on. The first bootstrap capacitor C_BST1 supplies power to the drive stage of the high-side power transistor HS, thereby outputting a drive voltage to the gate of the high-side power transistor HS. The high-side power transistor HS is turned on, and the low-side power transistor LS is turned off. The voltage at the switching node SW gradually increases until it reaches Vin. At the same time as the voltage at the switching node SW increases, the voltage at the second bootstrap node BST2 is also raised. When the voltage at the second bootstrap node BST2 is higher than the gate voltage Vg of the third transistor P4 by a preset threshold Vgs(th), the fourth transistor P4 is turned on, and the second bootstrap capacitor C_BST2 outputs a drive voltage to the gate of the high-side power transistor HS. The voltage at the second bootstrap node BST2 can reach a maximum of 3*Vin. At this time, the voltage of the upper plate of the second bootstrap capacitor C_BST2 is raised to 3*Vin, while the voltage of the upper plate of the third bootstrap capacitor C_BST3 remains at 2*Vin.

[0104] The embodiments disclosed herein employ an extremely simple circuit structure to fulfill the requirement of providing drive voltage to the high-side power transistor HS with 3*Vin. Under the premise of obtaining the same gate-source voltage Vgs of the high-side power transistor HS, the area of ​​the bootstrap capacitor Cbst can be greatly reduced, thereby reducing chip cost.

[0105] This disclosure also provides a chip that includes a DC-DC converter according to embodiments of this disclosure, and the chip may be a chip with embedded efuse IP.

[0106] This disclosure also provides an electronic device that includes a chip according to embodiments of this disclosure, and the electronic device may be a programming device.

[0107] As can be seen from the above description, this disclosure achieves the following technical effects:

[0108] This disclosure generates a second boost voltage greater than the first boost voltage through a charge pump boost circuit, thereby increasing the control electrode voltage of the high-side power transistor. This allows a smaller bootstrap capacitor to obtain a higher gate-source voltage of the high-side power transistor, reducing the capacitance value of the built-in bootstrap capacitor in the DC-DC converter and reducing the area of ​​the built-in bootstrap capacitor, thereby reducing the chip cost. This solves the problem that the large capacitance value and area of ​​the bootstrap capacitor in the BUCK-type DC-DC converter lead to a high chip cost.

[0109] Under the premise of obtaining the same gate-source voltage of the high-side power transistor, this disclosure increases the starting voltage of the bootstrap capacitor by a charge pump, thereby reducing the capacitance value of the bootstrap capacitor. Since the capacitance value is proportional to the area of ​​the capacitor plates, the area of ​​the bootstrap capacitor can be reduced, optimizing the area of ​​the built-in bootstrap capacitor and thus reducing the chip cost.

[0110] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatuses and methods according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction, which contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0111] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusive. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0112] Further aspects and scope will become apparent from the description provided herein. It should be understood that various aspects of this disclosure may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are intended for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0113] Although embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A DC-DC converter, characterized in that, It includes a bootstrap boost circuit, a charge pump boost circuit, a high-side drive circuit, a low-side drive circuit, a high-side power transistor, and a low-side power transistor; The bootstrap boost circuit is configured to provide a first boost voltage to the high-side drive circuit based on the input voltage at the input voltage terminal; The high-side drive circuit is configured to output a first high-side drive voltage to the control electrode of the high-side power transistor based on the pulse width modulation signal at the modulation signal terminal. The charge pump boost circuit is configured to generate a second boost voltage via a charge pump and output a second high-side drive voltage to the control electrode of the high-side power transistor based on the second boost voltage, wherein the second boost voltage is greater than the first boost voltage. The low-side drive circuit is configured to output a low-side drive voltage to the control electrode of the low-side power transistor based on the pulse width modulation signal of the modulation signal terminal. The first terminal of the high-side power transistor is coupled to the input voltage terminal, and the second terminal of the high-side power transistor is coupled to the first terminal of the low-side power transistor via a switching node. The high-side power transistor is configured to be turned on or off according to the first high-side drive voltage and the second high-side drive voltage, and the low-side power transistor is configured to be turned on or off according to the low-side drive voltage. One end of the bootstrap boost circuit and one end of the charge pump boost circuit are respectively coupled to the switching node.

2. The DC-DC converter according to claim 1, characterized in that, The bootstrap boost circuit includes a first diode and a first bootstrap capacitor; The first end of the first diode is coupled to the input voltage terminal, and the second end of the first diode is coupled to the first end of the first bootstrap capacitor and the first end of the high-side drive circuit via the first bootstrap node. The second terminal of the first bootstrap capacitor is coupled to the switching node and the second terminal of the high-side drive circuit, respectively. The first bootstrap capacitor is configured to charge based on the input voltage when the pulse width modulation signal is low and to provide a first boost voltage to the high-side drive circuit when the pulse width modulation signal is high.

3. The DC-DC converter according to claim 2, characterized in that, The charge pump boost circuit includes the charge pump, a unidirectional rectifier circuit, a second bootstrap capacitor, and a high-voltage drive circuit. The charge pump is configured to charge the second bootstrap capacitor to N times the input voltage via the unidirectional rectifier circuit, where N is a positive integer greater than 1. The first end of the unidirectional rectifier circuit is coupled to the charge pump, and the second end of the unidirectional rectifier circuit is coupled to the first end of the second bootstrap capacitor and the first end of the high voltage drive circuit via the second bootstrap node. The second end of the second bootstrap capacitor is coupled to the switching node. The second bootstrap capacitor is configured to charge based on the charge pump when the pulse width modulation signal is low, and to provide a second boost voltage to the high voltage drive circuit when the pulse width modulation signal is high and the voltage of the switching node rises to the input voltage. The second terminal of the high-voltage drive circuit is coupled to the control electrode of the high-side power transistor, and the high-voltage drive circuit is configured to output the second high-side drive voltage to the control electrode of the high-side power transistor based on the second boost voltage.

4. The DC-DC converter according to claim 3, characterized in that, The unidirectional rectifier circuit includes a unidirectional conduction switch.

5. The DC-DC converter according to claim 3, characterized in that, The unidirectional rectifier circuit includes a second diode.

6. The DC-DC converter according to claim 5, characterized in that, When N is 3, the charge pump includes a digital receiver, a first transistor, a second transistor, and a third transistor; The first terminal of the digital receiver is coupled to the modulation signal terminal, the second terminal of the digital receiver is coupled to the bootstrap control signal terminal, the third terminal of the digital receiver is coupled to the control electrode of the first transistor, and the fourth terminal of the digital receiver is coupled to the control electrode of the second transistor. The digital receiver is configured to control the first transistor and the second transistor to turn on or off according to the pulse width modulation signal of the modulation signal terminal and the bootstrap control signal of the bootstrap control signal terminal. The first terminal of the first transistor is coupled to the first terminal of the second transistor, the first terminal of the third transistor, and the second terminal of the first bootstrap capacitor. The second terminal of the first transistor is coupled to the input voltage terminal and the first terminal of the first diode. The second terminal of the second transistor is grounded. The control electrode of the third transistor is coupled to the modulation signal terminal, and the second electrode of the third transistor is coupled to the switching node. The pulse width modulation signal of the modulation signal terminal controls the turning on or off of the third transistor.

7. The DC-DC converter according to claim 6, characterized in that, The high-voltage drive circuit includes a fourth transistor, a third diode, a fourth diode, and a third bootstrap capacitor; The first terminal of the third bootstrap capacitor is coupled to the second terminal of the third diode, the first terminal of the fourth diode, and the control electrode of the fourth transistor, respectively. The second terminal of the third bootstrap capacitor is grounded. The third bootstrap capacitor is configured to output a signal to the control electrode of the fourth transistor. The first terminal of the fourth transistor is coupled to the control terminal of the high-side power transistor, and the second terminal of the fourth transistor is coupled to the second bootstrap node. The fourth transistor is configured to turn on or off based on the voltage difference between the control terminal voltage and the second terminal voltage of the fourth transistor. The first end of the third diode is coupled to the first end of the first bootstrap node and the second diode, respectively, and the second end of the fourth diode is coupled to the second end of the second diode and the second bootstrap node, respectively.

8. The DC-DC converter according to claim 7, characterized in that, When the pulse width modulation signal at the modulation signal terminal is low, the bootstrap control signal at the bootstrap control signal terminal is a square wave signal. The first transistor and the second transistor are turned on, the third transistor is turned off, the high-side power transistor is turned off, the low-side power transistor is turned on, the first bootstrap capacitor is configured to charge the second bootstrap capacitor to twice the input voltage via the second diode, and the third bootstrap capacitor is charged to twice the input voltage via the third diode. The fourth transistor is turned off. When the pulse width modulation signal at the modulation signal terminal is high, the first and second transistors are turned off, the third transistor is turned on, the high-side power transistor is turned on, the low-side power transistor is turned off, and the switching node voltage increases. When the switching node voltage increases to a preset threshold, the fourth transistor is turned on. When the switching node voltage increases to the input voltage, the voltage of the upper plate of the second bootstrap capacitor is raised to three times the input voltage, wherein the preset threshold is less than the input voltage.

9. The DC-DC converter according to claim 1, characterized in that, The DC-DC converter further includes an output circuit, one end of which is coupled to the switching node, and the output circuit is configured to generate an output voltage; The output circuit includes an inductor, an output capacitor, an equivalent series resistor, and an output resistor. The first end of the inductor is coupled to the switching node, and the second end of the inductor is coupled to the first end of the equivalent series resistor, the first end of the output resistor, and the output voltage terminal, respectively. The output voltage is generated at the output voltage terminal according to the inductance current flowing through the inductor. The second end of the equivalent series resistor is coupled to the first end of the output capacitor, and the second end of the output capacitor and the second end of the output resistor are respectively grounded.

10. A chip, characterized in that, Includes the DC-DC converter according to any one of claims 1-9.

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