A semiconductor structure, manufacturing method and electronic device
By forming air gap sidewall structures on both sides of the DRAM protrusion structure, the problem of reduced sidewall dielectric constant after DRAM size reduction is solved, the bit line capacitance is reduced and the induction margin is maintained, and the risk of short circuit is reduced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2020-06-22
- Publication Date
- 2026-05-26
AI Technical Summary
As DRAM size shrinks, bit line capacitance (CBL) characteristics need to maintain sensing margin, and the dielectric constant of the sidewalls needs to be reduced to reduce CBL characteristics, but existing technologies are difficult to achieve effectively.
A first sidewall and a second sidewall are formed on both sides of the protruding structure, with an air gap in the middle. The air gap sidewall structure with a low dielectric constant is formed by etching to reduce the bit line capacitance.
It effectively reduces bit line capacitance, improves induction margin, reduces short circuit probability, solves structural distribution problems, and reduces CBL value.
Smart Images
Figure CN113903736B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, specifically to a semiconductor structure, manufacturing method, and electronic device. Background Technology
[0002] Among the key characteristics of DRAM, the bit line capacitance (CBL) is closely related to the data sensing margin. Although DRAM sizes are decreasing, the sensing margin needs to be maintained at the same level as previous generations. To achieve this, the CBL characteristics need to be continuously reduced. The most significant factor determining the CBL characteristics is the dielectric constant of the bit line sidewalls. Therefore, in recent DRAM architectures, it is necessary to reduce the dielectric constant of the sidewalls to mitigate the CBL characteristics. Summary of the Invention
[0003] The purpose of this application is to provide a semiconductor structure, manufacturing method, and electronic device. To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general description, nor is it intended to identify key / important components or describe the scope of protection of these embodiments. Its sole purpose is to present some concepts in a simple form as a prelude to the detailed description that follows.
[0004] According to one aspect of the embodiments of this application, a semiconductor structure is provided, comprising:
[0005] Semiconductor substrate;
[0006] Several protruding structures located on the semiconductor substrate; and
[0007] Sidewall stacks located on both sides of the protruding structure; the sidewall stacks include a first sidewall located on the sidewall of the protruding structure and a second sidewall located outside the first sidewall; the upper part of the second sidewall is connected to the upper part of the first sidewall; an air gap exists between the lower part of the second sidewall and the lower part of the first sidewall;
[0008] At least a portion of the air gap in the protrusion structure extends below the surface of the semiconductor substrate.
[0009] According to another aspect of the embodiments of this application, a method for manufacturing a semiconductor structure is provided, comprising:
[0010] A semiconductor substrate is provided, on which a plurality of protrusion structures are formed, such that a portion of the protrusion structures includes a portion below the surface of the semiconductor substrate;
[0011] First sidewalls are formed on both sides of the protruding structure;
[0012] A sacrificial layer is formed on the lower outer side of the first sidewall;
[0013] A second sidewall is formed outside the first sidewall and the sacrificial layer; the lower part of the second sidewall is located outside the sacrificial layer.
[0014] The sacrificial layer is etched to create an air gap between the lower part of the second sidewall and the lower part of the first sidewall.
[0015] According to another aspect of the embodiments of this application, an electronic device is provided, including the semiconductor structure described above.
[0016] One aspect of the technical solution provided in this application embodiment may include the following beneficial effects:
[0017] The semiconductor structure provided in this application includes a semiconductor substrate and a protrusion structure. The upper part of the second sidewall of the protrusion structure is located above the upper part of the first sidewall, and there is an air gap between the lower part of the second sidewall and the lower part of the first sidewall. The dielectric constant of the air gap sidewall structure is low, which greatly reduces the capacitance of the protrusion structure.
[0018] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description, or some features and advantages may be inferred from the description or determined without question, or may be learned by practicing embodiments of this application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description
[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0020] Figure 1 A schematic diagram of the structure of a semiconductor substrate in one embodiment of the present disclosure is shown;
[0021] Figure 2 It shows in Figure 1 A schematic diagram of the structure after the first nitride layer is formed on the substrate;
[0022] Figure 3 It shows in Figure 2 A schematic diagram of the structure after the first oxide layer is formed on the substrate;
[0023] Figure 4 It shows in Figure 3A schematic diagram of the structure after the formation of the second nitride layer on the base;
[0024] Figure 5 It shows in Figure 4 A schematic diagram of the structure after a portion of the second nitride layer has been etched onto the substrate;
[0025] Figure 6 It shows in Figure 5 A schematic diagram of the structure after the formation of the second oxide layer on the substrate;
[0026] Figure 7 It shows in Figure 6 A schematic diagram of the structure after the formation of the SOH layer on the substrate;
[0027] Figure 8 It shows in Figure 7 A schematic diagram of the structure after removing part of the SOH layer;
[0028] Figure 9 It shows in Figure 8 A schematic diagram of the structure after the exposed second oxide layer is etched away.
[0029] Figure 10 It shows in Figure 9 A schematic diagram of the structure after removing the remaining part of the SOH layer;
[0030] Figure 11 It shows in Figure 10 A schematic diagram of the structure after thinning the horizontal portion of the second oxide layer;
[0031] Figure 12 It shows in Figure 11 A schematic diagram of the structure after the formation of the third nitride layer on the foundation;
[0032] Figure 13 It shows in Figure 12 A schematic diagram of the structure after the horizontal portion of the third nitride layer has been etched away;
[0033] Figure 14 It shows in Figure 13 Based on the above, a schematic diagram of the air gap and the structure after the gap is obtained;
[0034] Figure 15 It shows in Figure 14 A schematic diagram of the structure after the formation of the fourth nitride layer on the foundation;
[0035] Figure 16 It shows in Figure 15 A schematic diagram of the structure after forming unit contact components based on the above. Detailed Implementation
[0036] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.
[0037] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.
[0038] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.
[0039] One embodiment of this disclosure provides a method for manufacturing a semiconductor structure.
[0040] like Figure 1 As shown, a semiconductor substrate 1 is provided. The semiconductor substrate 1 has a plurality of contact grooves 101, and a substrate protrusion 102 is formed between two adjacent contact grooves 101. A polysilicon layer 103 is provided on the bottom surface of each contact groove 101, and the top surface of the polysilicon layer 103 is flush with the top surface of the substrate protrusion 102. A protrusion structure 2 is provided on the top surface of each substrate protrusion 102 and the top surface of each polysilicon layer 103. The bottom surface of the protrusion structure 2 has the same shape as the top surface of the polysilicon layer 103, and the two are connected together. The polysilicon layer 103 serves as a contact plug. In some embodiments, other types of contact plugs besides polysilicon layers may also be used.
[0041] The protrusion structure 2 can be a bit line or a gate. The semiconductor substrate 1 can be made of silicon. When the protrusion structure 2 is a bit line, 103 is a bit line node contact, such as polycrystalline, 202 is a bit line metal, such as metal W, and 201 is a dielectric isolation layer, such as silicon nitride.
[0042] like Figure 2As shown, a first nitride layer 3 is deposited and formed on the semiconductor substrate 1 and the protrusion structure 2. The first nitride layer 3 covers the contact groove 101, the substrate boss 102, the polysilicon layer 103, and the exposed surface portion of the protrusion structure 2. The first nitride layer 3 serves as a first dielectric layer. The vertical portions of the first dielectric layer located on both sides of the protrusion structure 2 serve as first sidewalls.
[0043] like Figure 3 As shown, a first oxide layer 4 is deposited on the surface of the first nitride layer 3, and the first oxide layer 4 is used as a first sacrificial layer.
[0044] like Figure 4 As shown, a second nitride layer 5 is formed on the surface of the first oxide layer 4. The second nitride layer 5 covers the surface of the first oxide layer 4 and fills the groove 101.
[0045] like Figure 5 As shown, the second nitride layer 5 is etched into the groove, leaving a portion of the second nitride layer 5, namely the remaining portion 5' of the second nitride layer. The top surface of the remaining portion 5' of the second nitride layer is lower than the top surface of the substrate boss 102.
[0046] like Figure 6 As shown, a second oxide layer 6 is deposited to form. The second oxide layer 6 covers the top surface of the remaining portion 5' of the second nitride layer and the outer surface portion of the first oxide layer 4 that is exposed. The second oxide layer 6 serves as a second sacrificial layer.
[0047] like Figure 7 As shown, an SOH layer 7 is deposited on the second oxide layer 6. The top surface of the SOH layer 7 is horizontal and higher than the top surface of the second oxide layer 6. The SOH layer 7 serves as a third sacrificial layer. The SOH layer 7 is made of a hard mask material (SOH, spin-on-hardmask).
[0048] like Figure 8 As shown, a portion of the SOH layer 7 is removed down to below the top surface of the second oxide layer 6, leaving a portion of the SOH layer 7, resulting in the remaining portion 7' of the SOH layer, exposing a portion of the second oxide layer 6. The top surface of the remaining portion 7' of the SOH layer extends approximately to half the height of the second oxide layer 6. The SOH layer 7 is then partially removed using an ashing process.
[0049] like Figure 9 As shown, the exposed portion of the second oxide layer 6 is etched away.
[0050] like Figure 10 As shown, the remaining portion 7' of the SOH layer is removed. The remaining portion 7' of the SOH layer is removed using an ashing process. At this point, the top surface of the first sacrificial layer is essentially flush with the top surface of the second sacrificial layer.
[0051] like Figure 11 As shown, the horizontal portion 6' of the second oxide layer 6 is etched to thin it. The thinning operation step can reduce the thickness of the opening pore 10 that forms the air gap 9.
[0052] like Figure 12 As shown, a third nitride layer 8 is deposited to form. The third nitride layer 8 covers the exposed portions of the second oxide layer 6 and the exposed portions of the first nitride layer 3, and fills the grooves.
[0053] like Figure 13 As shown, the horizontal portion of the third nitride layer 8 (including the portion located on the horizontal portion 6' and the portion located on the top surface of the first oxide layer 3) is etched away, leaving the remaining portion 8' of the third nitride layer, exposing the silicon oxide layer in the horizontal portion. The remaining portion 8' of the third nitride layer is the second sidewall 8'.
[0054] like Figure 14 As shown, the portion of the first oxide layer 4 above the remaining portion 5' of the second nitride layer and the remaining portion of the second oxide layer 6 are etched away, resulting in an air gap 9 and a gap 10 located between the lower end of the remaining portion 8' of the third nitride layer and the remaining portion 5' of the second nitride layer. The air gap 9 is located between the lower part of the remaining portion 8' of the third nitride layer and the first nitride layer 3. The gap 10 serves as an opening for the air gap 9, connecting it to the outside. A portion of the air gap 9 extends into the contact groove 101, located below the surface of the semiconductor substrate 1.
[0055] like Figure 15 As shown, a fourth nitride layer 11 is deposited. The fourth nitride layer 11 covers the outer surface of the sidewall of the third nitride layer 8 and the exposed portion of the first nitride layer 3, and extends into the voids to block the air gaps. The fourth nitride layer 11 serves as the third sidewall.
[0056] like Figure 16 As shown, a unit contact 12 is formed. One end of the unit contact 12 is inserted into the semiconductor substrate 1.
[0057] In this embodiment, each nitride layer can be made of silicon nitride material, and each oxide layer can be made of silicon oxide material.
[0058] This embodiment proposes a method for forming air gap sidewalls for bit lines, which can minimize the value of bit line capacitance.
[0059] This embodiment proposes an air gap sidewall structure that solves the structural distribution problem and simultaneously reduces the CBL value.
[0060] The method in this embodiment differs from the prior art; the air gap sidewall is formed first, and then the unit contact is manufactured.
[0061] In this embodiment, the air gap opening is located at the bottom of the air gap, which has the advantage of making it easy to seal the opening.
[0062] like Figure 14 As shown, another embodiment of this application provides a semiconductor structure, including:
[0063] Semiconductor substrate 1; Semiconductor substrate 1 has a plurality of contact grooves 101, and a substrate protrusion 102 is provided between two adjacent contact grooves 101; Semiconductor substrate 1 may be made of silicon material;
[0064] A polycrystalline silicon layer 103 is located on the bottom surface of the contact groove 101;
[0065] Several protrusion structures 2; a protrusion structure 2 is provided on each substrate boss 102 and each polysilicon layer 103;
[0066] A first dielectric layer is located on the semiconductor substrate 1 and the protrusion structure 2; the first dielectric layer includes vertical portions located on both sides of the protrusion structure 2, a horizontal portion located on the top surface of the protrusion structure 2, and a horizontal portion located on the semiconductor substrate 1; the vertical portions of the first dielectric layer located on both sides of the protrusion structure 2 constitute a first sidewall; in this embodiment, the first dielectric layer is a first nitride layer 3;
[0067] The second sidewall 8' is located on both sides of the first sidewall; the upper part of the second sidewall 8' is located above the first sidewall (i.e., the upper part of the second sidewall 8' is combined with the upper part of the first sidewall); there is an air gap 9 between the lower part of the second sidewall 8' and the lower part of the first sidewall. The air gap 9 greatly reduces the bit line capacitance value, thus minimizing the bit line capacitance value.
[0068] There is a gap 10 between the bottom of the second sidewall 8' and the remaining portion 5' of the second nitride layer. The gap 10 is an opening that connects the air gap 9 to the outside. The gap 10 is located at the bottom of the air gap 9 and faces outward, which has the advantage of being easy to seal.
[0069] The upper end of the second sidewall 8' is flush with the top surface of the first medium layer.
[0070] In some implementations, such as Figure 15 As shown, the semiconductor structure also includes a fourth nitride layer 11, which covers the outer side of the second sidewall 8', the top surface of the first sidewall, and the portion of the first dielectric layer located on the semiconductor substrate 1. The bottom of the fourth nitride layer 11 extends into the gap 10 to seal the gap 10.
[0071] like Figure 16As shown, in some embodiments, the semiconductor structure further includes a unit contact 12 disposed between two adjacent protrusions 2, one end of which is inserted into the semiconductor substrate 1.
[0072] The upper end of the second side wall 8' is flush with the upper end of the first side wall.
[0073] In some implementations, the protrusion structure 2 can be a gate or a bit line, for example, a bit line of a DRAM.
[0074] Here, we take protrusion structure 2 as an example of a DRAM bit line.
[0075] A second nitride layer 5' is provided within the contact groove 101. A first oxide layer 4 is provided between the second nitride layer 5' and the first dielectric layer. The top surface of the second nitride layer 5' is lower than the top surface of the substrate boss 102. The first oxide layer 4 is flush with the upper end of the second nitride layer 5'. A gap 10 is provided between the top surface of the second nitride layer 5' and the lower end of the second sidewall 8'.
[0076] In this embodiment, the air gap sidewall structure formed on the bit line area connected to the bit line contact extends to the contact groove of the semiconductor substrate, which greatly reduces the bit line capacitance. The thickness and height of the formed air gap sidewall are easily adjusted. By adjusting the re-etching process parameters of the SOH layer, the height of the first and second sacrificial layers can be determined, thereby controlling the height of the air gap. By adjusting the thickness of the second sacrificial layer, the thickness of the air gap can be adjusted. After the air gap is formed, in the capping process step to seal the entrance, since the opening of the air gap is located at the bottom and the opening direction is outward, it is easy to seal. Furthermore, by etching and thinning the horizontal portion of the second sacrificial layer, a smaller opening can be made. During the formation of the air gap sidewall, no conductor is exposed, greatly reducing the probability of short circuits.
[0077] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.
[0078] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.
Claims
1. A semiconductor structure, characterized in that, Comprising: A semiconductor substrate; A plurality of protruding structures located on the semiconductor substrate; And Sidewall stacks located on both sides of the protruding structures, the sidewall stacks comprising a first sidewall on the sidewall of the protruding structure and a second sidewall outside the first sidewall; the upper part of the second sidewall is joined to the upper part of the first sidewall; there is an air gap between the lower part of the second sidewall and the lower part of the first sidewall; The air gap of at least part of the protruding structures extends below the surface of the semiconductor substrate; The protruding structures include bit lines; there are a plurality of contact grooves on the semiconductor substrate that are lower than the surface of the semiconductor substrate, and contact plugs connected to the bit lines are provided in the contact grooves; The air gap of at least part of the protruding structures extends into the contact grooves; A first dielectric layer is provided on the semiconductor substrate and the protruding structures; the vertical portions of the first dielectric layer on both sides of the protruding structures constitute the first sidewall.
2. The semiconductor structure according to claim 1, wherein The first dielectric layer is a nitride layer.
3. The semiconductor structure according to claim 1, wherein The bottom of the second sidewall and the substrate constitute an opening of the air gap, and the semiconductor structure further includes a third sidewall on the first dielectric layer and outside the second sidewall, and the third sidewall extends on the substrate to the opening and seals the opening.
4. The semiconductor structure according to claim 1, wherein An oxide layer and a first nitride layer are sequentially provided above the first dielectric layer around the contact plug in the groove of the contact groove.
5. The semiconductor structure according to claim 3, wherein The third sidewall is a nitride layer.
6. A manufacturing method of a semiconductor structure as described in any one of claims 1-5, comprising: Providing a semiconductor substrate, forming a plurality of protruding structures on the semiconductor substrate, and making part of the protruding structures include portions lower than the surface of the semiconductor substrate; Forming a first sidewall on both sides of the protruding structures; Forming a sacrificial layer outside the lower part of the first sidewall; Forming a second sidewall outside the first sidewall and the sacrificial layer; the lower part of the second sidewall is located outside the sacrificial layer; Etching the sacrificial layer, thereby forming an air gap between the lower part of the second sidewall and the lower part of the first sidewall; The protruding structures include bit lines; before forming the bit lines, etching a plurality of contact grooves on the semiconductor substrate, and forming contact plugs in the grooves.
7. The method according to claim 6, wherein At the grooves, making the formed first sidewall and second sidewall both extend to the contact plug in the groove.
8. The method according to claim 6, wherein The forming a first sidewall on both sides of the protruding structures includes: Forming a first dielectric layer on the semiconductor substrate and the protruding structures; the vertical portions of the first dielectric layer on both sides of the protruding structures constitute the first sidewall.
9. The method according to claim 8, wherein The forming a sacrificial layer outside the lower part of the first sidewall includes: Forming a first sacrificial layer on the first dielectric layer; Forming a first nitride layer in the contact groove, making the first nitride layer on both sides of the contact plug, on the first sacrificial layer, and the top surface of the first nitride layer lower than the top surface of the semiconductor substrate; A second sacrificial layer is formed on both sides of the first sidewall; such that the second sacrificial layer includes a vertical portion and a middle portion connected to each other, the vertical portion of the second sacrificial layer is located on the outer side of the lower part of the first sidewall, and the middle portion is located on the top surface of the first dielectric layer and the top surface of the first nitride layer on the semiconductor substrate; The portion of the first sacrificial layer above the top surface of the first nitride layer and the second sacrificial layer constitute the sacrificial layer.
10. The method according to claim 9, wherein The formation of a second sacrificial layer on both sides of the first sidewall includes: An oxide layer is deposited over the entire semiconductor structure; A hard mask layer is deposited over the entire semiconductor structure, covering the top of the oxide layer; By etching and removing the hard mask layer, the oxide layer is etched to a predetermined height on both sides of the protrusion structure to form a second sacrificial layer.
11. The method according to claim 10, wherein The formation of a second sidewall outside the first sidewall includes: A first nitride layer is deposited on the protruding structure and the second sacrificial layer; The first nitride layer is etched to form the second sidewall.
12. The method according to claim 10, wherein Before forming the second sidewall outside the first sidewall, the method further includes: The horizontal portion of the second sacrificial layer is thinned by etching.
13. The method according to claim 6, wherein The method further includes: A second nitride layer is deposited on the semiconductor structure to seal the bottom opening of the air gap.
14. The manufacturing method according to claim 6, characterized in that, The method further includes: A trench is formed on the semiconductor substrate between two adjacent protrusion structures; A unit contact is deposited within the trench, the top surface of which is higher than the semiconductor substrate and lower than the top surface of the second sidewall.
15. An electronic device comprising a semiconductor structure as claimed in any one of claims 1 to 5.
16. The electronic device according to claim 15, including a smartphone, a computer, a wearable smart device, an artificial intelligence device, and a power bank.