Pseudo resistance circuit, RC filter circuit, current mirror circuit and chip
By combining pseudo-resistor circuits and bias circuits, the problems of large RC filter area and large PVT influence are solved, achieving small area, high resistance and stable filtering effect, and reducing capacitor area and leakage current sensitivity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 3PEAK INC
- Filing Date
- 2022-09-20
- Publication Date
- 2026-06-30
AI Technical Summary
In existing technologies, RC filters require a large chip area and cost, and the resistance value is greatly affected by process-voltage-temperature (PVT), making it difficult to achieve small area, high resistance and stable filtering effect.
A pseudo-resistor circuit is adopted, using the first MOSFET as a pseudo-resistor, and a subthreshold bias voltage is provided to its gate and source through a bias circuit to adjust its resistance value. Combined with the bias circuit composed of a current source and a MOSFET, a high resistance value is achieved, and the influence of PVT is reduced by parameter setting.
It achieves high resistance values in a small area, reduces capacitor area requirements, and maintains stable filtering performance when PVT changes, avoiding leakage current sensitivity and resistance fluctuations.
Smart Images
Figure CN115459727B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuits, and in particular to a pseudo-resistor circuit, an RC filter circuit, a current mirror circuit, and a chip. Background Technology
[0002] For low-noise circuits within a chip, an RC filter is often needed to filter out noise from bias current / voltage, etc. To achieve better filtering performance, larger resistors and capacitors are often required, which means a larger chip area and higher cost.
[0003] Furthermore, if a high-resistance resistor can be achieved with a smaller area, we can use a larger resistance value and a smaller capacitance value to achieve the same filtering effect as an RC filter. This means that the overall area of the RC filter can be greatly reduced. Therefore, a small-area, high-resistance resistor solution is very valuable for low-noise circuits.
[0004] Figure 1 For commonly used RC filter circuits, in semiconductor processes, polysilicon or active regions are usually used as resistors. Such resistor solutions have small resistance values, and the semiconductor process level limits the minimum width of the resistor, which means that the area efficiency is not high. Such RC filters will occupy a large chip area.
[0005] Figure 2 To use a linear region metal-oxide-semiconductor (MOS) transistor as a resistor, multiple MOS transistors need to be connected in series to increase the resistance value. This still requires a large chip area to achieve a high resistance value resistor.
[0006] Figure 3 To use a subthreshold MOSFET as a resistor, the gate-source voltage of the MOSFET is almost 0V in a steady state, resulting in a huge resistance value (~100GΩ). Such a large resistor is quite sensitive to leakage current, and its resistance value changes significantly under PVT conditions.
[0007] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention
[0008] The purpose of this invention is to provide a pseudo-resistor circuit, an RC filter circuit, a current mirror circuit, and a chip, which can obtain a high-resistance resistor with a small area cost, and the resistance value of the resistor is less affected by process-voltage-temperature (PVT).
[0009] To achieve the above objectives, embodiments of the present invention provide a pseudo-resistor circuit, including: a first MOS transistor and a bias circuit.
[0010] The bias circuit is connected to the gate and source of the first MOS transistor to provide a bias voltage between the gate and source of the first MOS transistor to enable the first MOS transistor to operate in the subthreshold region, and the resistance of the first MOS transistor is adjusted by adjusting the bias voltage.
[0011] The bias circuit includes a second MOS transistor, a resistor, and a first current source connected in sequence.
[0012] In one or more embodiments of the present invention, the source of the second MOS transistor is connected to the source of the first MOS transistor, the drain of the second MOS transistor is connected to the first end of a resistor and the gate of the first MOS transistor, the second end of the resistor is connected to the gate of the second MOS transistor, and the connection point is connected to ground voltage or power supply voltage through a first current source.
[0013] In one or more embodiments of the present invention, the source and substrate of the first MOS transistor are shorted, and / or the source and substrate of the second MOS transistor are shorted.
[0014] In one or more embodiments of the present invention, the resistor includes a passive resistor or an active resistor.
[0015] The present invention also discloses an RC filter circuit, including the aforementioned pseudo-resistor circuit and a capacitor connected to the pseudo-resistor circuit.
[0016] The present invention also discloses a current mirror circuit, including the aforementioned RC filter circuit, an input circuit, and an output circuit. The input circuit is connected to an external circuit to receive the input current provided by the external circuit. The RC filter circuit is connected to the input circuit to filter the input current. The output circuit is connected to the RC filter circuit to replicate the input current and output it.
[0017] In one or more embodiments of the present invention, the input circuit includes a third MOS transistor, the output circuit includes a fourth MOS transistor, the gate and drain of the third MOS transistor are shorted and connected to an external circuit, the gate of the third MOS transistor is connected to the first terminal of an RC filter circuit, and the gate of the fourth MOS transistor is connected to the second terminal of an RC filter circuit.
[0018] In one or more embodiments of the present invention, the current mirror circuit further includes a second current source, the first terminal of the second current source being connected to the power supply voltage and the first terminal of the external circuit, the second terminal of the second current source being connected to the second terminal of the external circuit, the gate and drain of the third MOS transistor, and the second current source being used to provide the same bias current as the first current source.
[0019] In one or more embodiments of the present invention, the input current provided by the external circuit is much greater than the bias current provided by the first current source in the RC filter circuit.
[0020] The present invention also discloses a chip, including the aforementioned pseudo-resistor circuit, the aforementioned RC filter circuit, and / or the aforementioned current mirror circuit.
[0021] Compared with existing technologies, the pseudo-resistor circuit, RC filter circuit, current mirror circuit, and chip of the present invention use a first MOSFET as a pseudo-resistor and provide a bias voltage between the gate and source of the first MOSFET through a bias circuit to enable the first MOSFET to operate in the subthreshold region. By adjusting this bias voltage, the resistance value of the first MOSFET can be adjusted, thereby obtaining a high-resistance resistor with a smaller area. This reduces the resistor area, and to achieve the same RC time constant, the capacitor value can be reduced, thus reducing the capacitor area. Furthermore, the resistance value of this pseudo-resistor is less affected by process voltage-temperature (PVT), ensuring that the filtering effect of the RC filter does not change significantly with variations in PVT. By employing this pseudo-resistor scheme, the resistance value of the pseudo-resistor can be easily adjusted to a reasonable value, avoiding both excessively small resistance that degrades the filtering effect and excessively large resistance that is overly sensitive to leakage current. Attached Figure Description
[0022] Figure 1 This is a circuit diagram of an existing RC filter circuit.
[0023] Figure 2 This is the circuit diagram of an existing RC filter using a pseudo-resistor.
[0024] Figure 3 This is the circuit diagram of an RC filter using a pseudo-resistor, which is the third existing technology.
[0025] Figure 4 This is a circuit diagram of a pseudo-resistor circuit according to Embodiment 1 of the present invention.
[0026] Figure 5 This is a circuit diagram of a pseudo-resistor circuit according to Embodiment 2 of the present invention.
[0027] Figure 6 This is a circuit diagram of the RC filter circuit according to Embodiment 3 of the present invention.
[0028] Figure 7 This is a circuit diagram of the current mirror circuit according to Embodiment 4 of the present invention. Detailed Implementation
[0029] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments.
[0030] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.
[0031] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected to" or "connected to" another element, or when an element / circuit is said to be "connected" between two nodes, it may be directly coupled to or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between them.
[0032] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0033] Example 1
[0034] like Figure 4 As shown, a pseudo-resistor circuit includes a first MOS transistor M1 and a bias circuit 10. In this embodiment, the first MOS transistor M1 is a P-channel MOS transistor.
[0035] The bias circuit 10 is connected to the gate and source of the first MOS transistor M1 to provide a bias voltage between the gate and source of the first MOS transistor M1 to enable the first MOS transistor M1 to operate in the subthreshold region. The resistance value of the first MOS transistor M1 is adjusted by adjusting the bias voltage. That is, the resistance value of the first MOS transistor M1 is determined by determining the gate-source voltage of the first MOS transistor M1.
[0036] like Figure 4 As shown, the bias circuit 10 includes a second MOSFET M2, a resistor R1, and a first current source A1. The source of the second MOSFET M2 is connected to the source of the first MOSFET M1. The drain of the second MOSFET M2 is connected to the first terminal of the resistor R1 and the gate of the first MOSFET M1. The second terminal of the resistor R1 is connected to the gate of the second MOSFET M2, and this connection point is connected to ground voltage through the first current source A1.
[0037] In this embodiment, the second MOSFET M2 is a P-channel MOSFET. Resistor R1 is a poly resistor; in other embodiments, resistor R1 can be other passive or active resistors.
[0038] In this embodiment, the gate-source voltage of the first MOSFET M1 is equal to the gate-source voltage of the second MOSFET M2 minus the voltage across resistor R1. Therefore, the resistance of the first MOSFET M1 can be easily adjusted by adjusting either the gate-source voltage of the second MOSFET M2 or the voltage across resistor R1.
[0039] |V gsM1 |=|V gsM2 |-I1*R1 (1),
[0040] |V gsM1 |V represents the gate-source voltage of the first MOSFET M1. gsM2 | represents the gate-source voltage of the second MOSFET M2, I1 represents the bias current provided by the first current source A1 to the second MOSFET M2 and resistor R1, and R1 represents the resistance value of resistor R1.
[0041] If the resistance of the first MOSFET M1 needs to be increased, then |V needs to be decreased. gsM1 | This can be achieved by increasing the value of I1*R1, or by setting the width-to-length ratio of the first MOSFET M1 and the second MOSFET M2. The smaller the width-to-length ratio of the first MOSFET M1, the larger the resistance of the first MOSFET M1; the larger the width-to-length ratio of the second MOSFET M2, the larger the resistance of the first MOSFET M1.
[0042] In this embodiment, the first current source A1 can be implemented using an N-channel MOS transistor or other circuit structures that can act as actual current sources.
[0043] In this embodiment, in order to reduce leakage current, the source and substrate of the first MOS transistor M1 and the source and substrate of the second MOS transistor M2 can be shorted.
[0044] From formula (1), we can obtain:
[0045] |V dsatM1 |+|V thM1 |=|V dsatM2 |+|V thM2 |-I1*R1 (2),
[0046] Among them, |V dsatM1 |V represents the saturation voltage of the first MOSFET M1. thM1 | is the threshold voltage of the first MOSFET M1, |V dsatM2 |V represents the saturation voltage of the second MOSFET M2. thM2 | represents the threshold voltage of the second MOSFET M2.
[0047] In this embodiment, the threshold voltage |V of the first MOS transistor M1 thM1|Threshold voltage of the second MOSFET M2|V thM2 |Approximately equal, in semiconductor processes, the threshold voltage of the same type of MOS transistor is consistent due to the influence of the process. Because it is on both sides of formula (2), the threshold voltage of the first MOS transistor M1 is |V thM1 |V with the threshold voltage of the second MOSFET M2| thM2 The effects of the process can be mutually canceled out, as can be obtained from formula (2):
[0048] |V dsatM2 |=|V dsatM1 |+I1*R1 (3).
[0049] The saturation voltage of the first MOSFET M1 is |V dsatM2 | and the saturation voltage of the second MOSFET M2| V dsatM2 It is less affected by process voltage-temperature (PVT). At the same time, I1 is obtained by dividing the reference voltage provided by the bandgap reference circuit by a resistor, and the resistor R1 is proportional to this resistor, which can also cancel out the process voltage-temperature (PVT) effect on the resistor.
[0050] Based on the above analysis, the bias voltage provided between the gate and source of the first MOS transistor M1 is equal to the threshold voltage |V of the first MOS transistor M1. thM1 The relevant voltage allows the bias circuit 10 to track the threshold voltage of the first MOSFET M1. thM1 As the process voltage-temperature (PVT) varies, the resistance of the first MOSFET M1 can be kept relatively constant under different PVT conditions. This avoids the problem of large and unstable resistance variations in the first MOSFET M1 caused by applying a fixed voltage between its gate and drain (when the first MOSFET M1 is in the subthreshold region) and making it act as a large resistor under different PVT conditions.
[0051] Example 2
[0052] like Figure 5 As shown, the difference between this embodiment and Embodiment 1 is that the first MOSFET M1 is an N-channel MOSFET, and the second MOSFET M2 is an N-channel MOSFET. Correspondingly, the connection method within the bias circuit 10 is also changed accordingly.
[0053] Specifically, the source of the second MOSFET M2 is connected to the source of the first MOSFET M1, the drain of the second MOSFET M2 is connected to the first terminal of resistor R1 and the gate of the first MOSFET M1, the second terminal of resistor R1 is connected to the gate of the second MOSFET M2, and this connection point is connected to the power supply voltage through the first current source A1.
[0054] Example 3
[0055] like Figure 6 As shown, this embodiment discloses an RC filter circuit, including a pseudo-resistor circuit and a capacitor C1 connected to the pseudo-resistor circuit. The first terminal of capacitor C1 is connected to the drain of the first MOSFET M1, and the second terminal of capacitor C1 is connected to ground.
[0056] Example 4
[0057] like Figure 7 As shown, this embodiment discloses a current mirror circuit, including as follows: Figure 6 The RC filter circuit, input circuit, and output circuit shown are configured such that the input circuit is connected to the external circuit 20 to receive the input current I2 provided by the external circuit 20, the RC filter circuit is connected to the input circuit to filter the input current I2, and the output circuit is connected to the RC filter circuit to replicate the input current I2 and output it.
[0058] In this embodiment, the input circuit includes a third MOSFET M3, and the output circuit includes a fourth MOSFET M4. In other embodiments, the input and output circuits can form a multi-layer cascade structure.
[0059] In this embodiment, both the third MOS transistor M3 and the fourth MOS transistor M4 are NMOS transistors.
[0060] Specifically, the gate and drain of the third MOSFET M3 are connected together and also connected to the source of the first MOSFET M1 and the external circuit 20. The external circuit 20 can be a current mirror, a current source, or other circuit structures. The drain of the third MOSFET M3 is used to receive the input current I2 provided by the external circuit 20, and the source of the third MOSFET M3 is connected to ground. The gate of the fourth MOSFET M4 is connected to the first terminal of capacitor C1 and the drain of the first MOSFET M1. The second terminal of capacitor C1 is connected to ground, the source of the fourth MOSFET is connected to ground, and the drain of the fourth MOSFET M4 is used to output current.
[0061] The RC filter circuit can filter high-frequency noise through capacitor C1, while for low-frequency signals, the gates of the third and fourth MOSFETs can be considered to be shorted together.
[0062] In other embodiments, the third MOSFET M3 and the fourth MOSFET M4 can both be PMOS transistors, and correspondingly, they can be used... Figure 5 The RC filter circuit shown.
[0063] In this embodiment, the current mirror circuit further includes a second current source A2. The first terminal of the second current source A2 is connected to the power supply voltage, and the second terminal of the second current source A2 is connected to the gate and drain of the third MOS transistor M3. The second current source A2 is used to provide the same bias current I1 provided by the first current source A1.
[0064] Typically, for a current mirror circuit, it is desirable for the input current I2 of the external circuit 20 to be replicated as accurately as possible by the current mirror circuit. However, the bias current I1 generated by the first current source A1 in the pseudo-resistor circuit will become a source of error in the current mirror circuit's image.
[0065] Therefore, a second current source A2 is set up. When the current mirror circuit in this embodiment is connected to the external circuit 20, the current I1 generated by the second current source A2 compensates for the bias current I1 generated by the first current source A1, so that the input current I2 of the external circuit 20 can be accurately replicated by the current mirror circuit.
[0066] In other embodiments, the input current I2 provided by the external circuit 20 can be much larger than the bias current I1 provided by the first current source A1 in the RC filter circuit, thereby reducing the error caused by the bias current I1.
[0067] Example 5
[0068] This embodiment discloses a chip, including a pseudo-resistor circuit, an RC filter circuit, and / or a current mirror circuit.
[0069] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments of the invention, as well as various different choices and variations. The scope of the invention is intended to be defined by the claims and their equivalents.
Claims
1. A current mirror circuit, characterized in that, The circuit includes an RC filter circuit, an input circuit, and an output circuit. The input circuit is connected to an external circuit to receive input current provided by the external circuit. The RC filter circuit is connected to the input circuit to filter the input current. The output circuit is connected to the RC filter circuit to replicate the input current and output it. The RC filter circuit includes a pseudo-resistor circuit and a capacitor connected to the pseudo-resistor circuit. The pseudo-resistor circuit includes: The first MOSFET; and A bias circuit is connected to the gate and source of the first MOSFET to provide a bias voltage between the gate and source of the first MOSFET to enable the first MOSFET to operate in the subthreshold region, and the resistance of the first MOSFET is adjusted by adjusting the bias voltage. The bias circuit includes a second MOSFET, a resistor, and a first current source connected in sequence. The input circuit includes a third MOS transistor, and the output circuit includes a fourth MOS transistor. The gate and drain of the third MOS transistor are shorted and connected to an external circuit. The gate of the third MOS transistor is connected to the first terminal of an RC filter circuit, and the gate of the fourth MOS transistor is connected to the second terminal of an RC filter circuit. The current mirror circuit further includes a second current source. The first end of the second current source is connected to the power supply voltage and the first end of the external circuit. The second end of the second current source is connected to the second end of the external circuit, the gate and drain of the third MOS transistor. The second current source is used to provide the same bias current as the first current source.
2. The current mirror circuit as described in claim 1, characterized in that, The input current provided by the external circuit is much greater than the bias current provided by the first current source in the RC filter circuit.
3. The current mirror circuit as described in claim 1, characterized in that, The source of the second MOS transistor is connected to the source of the first MOS transistor, the drain of the second MOS transistor is connected to the first end of the resistor and the gate of the first MOS transistor, the second end of the resistor is connected to the gate of the second MOS transistor, and this connection point is connected to ground voltage or power supply voltage through a first current source.
4. The current mirror circuit as described in claim 1, characterized in that, The source and substrate of the first MOS transistor are shorted, and / or the source and substrate of the second MOS transistor are shorted.
5. The current mirror circuit as described in claim 1, characterized in that, The resistor may be a passive resistor or an active resistor.
6. A chip, characterized in that, Includes the current mirror circuit as described in any one of claims 1 to 5.