Package structure and method of forming the same

Abstract

A forming method of a packaging structure includes: providing a re-distribution board, the re-distribution board including a first re-distribution layer, the first re-distribution layer including a first group of conductive pads and a second group of conductive pads; providing a device substrate, the device substrate including a passive device layer and a second re-distribution layer covering the passive device layer, the passive device layer including at least one passive device, the second re-distribution layer including a third group of conductive pads and a fourth group of conductive pads, the other end of the third group of conductive pads being electrically connected with the passive device; using a hybrid bonding process to bond the re-distribution board and the device substrate with the first surface of the first re-distribution layer and the first surface of the second re-distribution layer as bonding surfaces; removing part of the passive device layer from the surface of the device substrate away from the re-distribution board to expose the fourth group of conductive pads; and disposing at least one chip on the surface of the device substrate away from the re-distribution board, the chip being electrically connected with the fourth group of conductive pads. The method directly integrates the passive device in the re-distribution board or on the surface layer, improving process compatibility.

Description

Technical Field

[0001] This invention relates to the field of packaging, and more particularly to a packaging structure and a method for forming the same. Background Technology

[0002] With the continuous evolution of advanced packaging technologies, chiplet technology based on advanced packaging technologies has become an important way to drive the improvement of design efficiency. Chiplet technology refers to pre-manufactured, functional, and combinable dies. Using system-in-package (SiP) technology, chips with different functions and manufactured at different process nodes are packaged together to form a system-on-a-chip through effective inter-chip interconnection and packaging architecture.

[0003] Currently, using adapter boards is one of the effective ways to achieve electrical interconnection between chips and between chips and substrates. However, existing adapter boards do not integrate passive components (such as capacitors). Passive components need to be connected to the adapter board through additional surface mount technology (SMT) processes. This is incompatible with the flip-chip process between chips and between chips and substrates. In addition, the size of passive components is relatively large, resulting in wasted adapter board area and hindering the miniaturization of the packaging structure.

[0004] Therefore, how to achieve the packaging between passive components and adapter boards has become the focus of research. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a packaging structure and a method for forming the same, which can improve the compatibility of packaging processes and facilitate the miniaturization of the packaging structure.

[0006] To address the aforementioned problems, the present invention provides a method for forming a packaging structure, comprising: providing an adapter board, the adapter board including a first redistribution layer, the first redistribution layer including a first set of conductive pads and a second set of conductive pads, wherein one end of each of the first set of conductive pads and the second set of conductive pads is exposed on a first surface of the first redistribution layer; providing a device substrate, the device substrate including a passive device layer and a second redistribution layer covering the passive device layer, the passive device layer including at least one passive device, the second redistribution layer including a third set of conductive pads and a fourth set of conductive pads, wherein one end of each of the third set of conductive pads and the fourth set of conductive pads is exposed on a first surface of the first redistribution layer; and providing a device substrate, the device substrate including a passive device layer and a second redistribution layer covering the passive device layer, the passive device layer including at least one passive device, the second redistribution layer including a third set of conductive pads and a fourth set of conductive pads, wherein one end of each of the third set of conductive pads and the fourth set of conductive pads is exposed on a first surface of the first redistribution layer. The first surface of the double wiring layer is used as the bonding surface, and the other end of the third set of conductive pads is electrically connected to the passive device. The adapter plate and the device substrate are bonded using a hybrid bonding process with the first surface of the first wiring layer and the first surface of the second wiring layer as bonding surfaces. The first set of conductive pads is electrically connected to the third set of conductive pads, and the second set of conductive pads is electrically connected to the fourth set of conductive pads. A portion of the passive device layer is removed from the surface of the device substrate away from the adapter plate to expose the fourth set of conductive pads. At least one chip is disposed on the surface of the device substrate away from the adapter plate, and the chip is electrically connected to the fourth set of conductive pads.

[0007] In one embodiment, prior to the step of bonding the adapter to the device substrate using a hybrid bonding process, the method includes: planarizing a first surface of the first redistribution layer, and / or planarizing a first surface of the second redistribution layer.

[0008] In one embodiment, prior to the step of bonding the adapter to the device substrate using a hybrid bonding process, the method includes: activating a first surface of the first redistribution layer and / or a first surface of the second redistribution layer.

[0009] In one embodiment, the first redistribution layer includes a first dielectric layer, and the first set of conductive pads and the second set of conductive pads are disposed within the first dielectric layer and exposed on the surface of the first dielectric layer; the second redistribution layer includes a second dielectric layer, and the third set of conductive pads and the fourth set of conductive pads are disposed within the second dielectric layer and exposed on the surface of the second dielectric layer; in the step of bonding the adapter board to the device substrate using a hybrid bonding process, the first dielectric layer is also bonded to the second dielectric layer; in the step of removing a portion of the passive device layer from the surface of the device substrate away from the adapter board, the second dielectric layer is also exposed.

[0010] In one embodiment, the step of placing a chip on the surface of the device substrate opposite to the adapter plate includes: electrically connecting the chip to the fourth set of conductive pads on the surface of the device substrate opposite to the adapter plate using a flip-chip process.

[0011] In one embodiment, prior to the step of placing the chip on the surface of the device substrate opposite to the adapter plate, the method further includes: forming a third wiring layer on the surface of the device substrate opposite to the adapter plate, the third wiring layer covering the device substrate, the third wiring layer including a fifth set of conductive pads, the fifth set of conductive pads being electrically connected to the fourth set of conductive pads, and the fifth set of conductive pads being exposed on a first surface of the third wiring layer; and electrically connecting the chip to the fifth set of conductive pads on the first surface of the third wiring layer using a flip-chip process.

[0012] In one embodiment, the step of electrically connecting the chip to the fifth set of conductive pads using a flip-chip process on the first surface of the third wiring layer includes: forming a sixth set of conductive pads on the first surface of the third wiring layer, wherein the sixth set of conductive pads is electrically connected to the fifth set of conductive pads; and electrically connecting the chip to the sixth set of conductive pads using a flip-chip process.

[0013] In one embodiment, the step of providing the adapter board further includes: providing a carrier substrate and forming a sacrificial layer on the carrier substrate; forming a first redistribution layer on the sacrificial layer; and after the step of placing a chip on the surface of the device substrate opposite to the adapter board, removing the carrier substrate using the sacrificial layer as a separation layer.

[0014] This invention also provides a packaging structure, including: an adapter board, the adapter board including a first rewiring layer, the first rewiring layer including a first set of conductive pads and a second set of conductive pads; a device substrate including a passive device layer and a second rewiring layer covering the passive device layer, the passive device layer including at least one passive device, the second rewiring layer and the first rewiring layer being co-bonded together, the second rewiring layer including a third set of conductive pads and a fourth set of conductive pads, one end of the third set of conductive pads being electrically connected to the first set of conductive pads and the other end being electrically connected to the passive device, one end of the fourth set of conductive pads being electrically connected to one end of the second set of conductive pads and the other end being exposed to the passive device layer; and at least one chip disposed on the surface of the device substrate opposite to the adapter board, the chip being electrically connected to the other end of the fourth set of conductive pads.

[0015] In one embodiment, the first redistribution layer includes a first dielectric layer, and the first set of conductive pads and the second set of conductive pads are disposed within the first dielectric layer; the second redistribution layer includes a second dielectric layer, and the third set of conductive pads and the fourth set of conductive pads are disposed within the second dielectric layer; the first dielectric layer is also bonded to the second dielectric layer, and the material of the first dielectric layer is the same as the material of the second dielectric layer, and / or the material of the first set of conductive pads is the same as the material of the third set of conductive pads.

[0016] In one embodiment, a third wiring layer is further included, which covers the surface of the device substrate facing away from the adapter plate. The third wiring layer includes a fifth set of conductive pads, one end of which is electrically connected to the other end of the fourth set of conductive pads. The chip is disposed on the surface of the fifth wiring layer and is electrically connected to the other end of the fifth set of conductive pads.

[0017] In one embodiment, a sixth set of conductive pads is further included. The sixth set of conductive pads is disposed on the surface of the third wiring layer opposite to the device substrate, and one end of the sixth set of conductive pads is electrically connected to the other end of the fifth conductive pad. The chip is electrically connected to the other end of the sixth set of conductive pads.

[0018] The method for forming the packaging structure of this invention enables the direct integration of passive devices inside or on the surface of the adapter board using wafer-level packaging technology before the chip is placed, eliminating the need for additional surface mount technology to connect the passive devices to the adapter board, thus greatly improving process compatibility. Furthermore, the passive devices formed by this method are small in size, significantly saving the area of ​​the adapter board and facilitating the miniaturization of the packaging structure. With the chip and the passive devices positioned on the same side of the adapter board, the proximity of the passive devices to the chip allows for local energy storage near the chip, significantly improving the power integrity of high-speed circuits with this packaging structure. Additionally, the parameters of the passive devices can be adjusted during the manufacturing process of the passive devices in the device substrate, for example, by changing the processing technology or adjusting the capacitance value by adjusting the area of ​​the capacitor matrix, so that the parameters of the passive devices tend to the calculated values ​​in the simulation design, achieving precise matching between the passive devices and the chip. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1This is a schematic diagram of the steps in a method for forming a packaging structure according to an embodiment of the present invention;

[0021] Figures 2A to 2G This is a schematic diagram of the structure formed by the main steps of the forming method provided in an embodiment of the present invention;

[0022] Figures 3A-3B This is a schematic diagram of the structure formed by the main steps of the forming method provided in another embodiment of the present invention;

[0023] Figures 4A-4B This is a schematic diagram of the structure formed by the main steps of the forming method provided in another embodiment of the present invention. Detailed Implementation

[0024] The specific embodiments of the packaging structure and its formation method provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0025] Figure 1 This is a schematic diagram illustrating the steps of a method for forming a packaging structure according to an embodiment of the present invention. Please refer to [link / reference]. Figure 1 The forming method includes: step S10, providing an adapter board, the adapter board including a first redistribution layer, the first redistribution layer including a first group of conductive pads and a second group of conductive pads, and one end of each of the first group of conductive pads and the second group of conductive pads being exposed on a first surface of the first redistribution layer; step S11, providing a device substrate, the device substrate including a passive device layer and a second redistribution layer covering the passive device layer, the passive device layer including at least one passive device, the second redistribution layer including a third group of conductive pads and a fourth group of conductive pads, one end of each of the third group of conductive pads and the fourth group of conductive pads being exposed on a first surface of the second redistribution layer, and the first group of conductive pads and the second group of conductive pads being exposed on a first surface of the second redistribution layer, and the second ... The other end of the third set of conductive pads is electrically connected to the passive device; in step S12, using the first surface of the first redistribution layer and the first surface of the second redistribution layer as bonding surfaces, a hybrid bonding process is used to bond the adapter plate to the device substrate, wherein the first set of conductive pads is electrically connected to the third set of conductive pads, and the second set of conductive pads is electrically connected to the fourth set of conductive pads; in step S13, a portion of the passive device layer is removed from the surface of the device substrate away from the adapter plate to expose the fourth set of conductive pads; in step S14, at least one chip is disposed on the surface of the device substrate away from the adapter plate, and the chip is electrically connected to the fourth set of conductive pads.

[0026] In a method for forming a packaging structure provided in an embodiment of the present invention, passive devices are directly integrated inside or on the surface of the adapter board using a wafer-level packaging process before the chip is set, without the need for an additional surface mount process to connect the passive devices to the adapter board, which greatly improves process compatibility; and the passive devices formed by this method are small in size, which greatly saves the area of ​​the adapter board and is conducive to the miniaturization of the packaging structure.

[0027] In high-speed circuits, the instantaneous current from the simultaneous switching of numerous devices can cause voltage fluctuations on the power supply and ground planes, affecting power integrity. Capacitors are typically added to enhance the transient response capability of the power supply in localized areas. The closer the capacitor is to the chip pins, the more effective it is at local energy storage near the chip, significantly improving the power integrity of high-speed circuits. In the method of this invention, the chip and the passive device are positioned on the same side of the adapter board, resulting in a closer distance between the passive device and the chip. This allows for local energy storage near the chip, significantly improving the power integrity of high-speed circuits with the aforementioned packaging structure.

[0028] In addition, the parameters of passive devices can be adjusted during the manufacturing process of passive devices on the device substrate. For example, the capacitance value can be adjusted by changing the processing technology or adjusting the area of ​​the capacitor matrix, so that the parameters of passive devices can approach the calculated values ​​in the simulation design, thereby achieving precise matching between passive devices and chips.

[0029] Figures 2A to 2G This is a schematic diagram of the structure formed by the main steps of the forming method provided in an embodiment of the present invention.

[0030] Please see Figure 1 and Figure 2B In step S10, an adapter board 200 is provided. The adapter board 200 includes a first redistribution layer 210. The first redistribution layer 210 includes a first set of conductive pads 211 and a second set of conductive pads 212, and one end of each of the first set of conductive pads 211 and the second set of conductive pads 212 is exposed on a first surface 210A of the first redistribution layer 210. The first set of conductive pads 211 and the second set of conductive pads 212 serve as external connection areas of the first redistribution layer 210. Each of the first set of conductive pads 211 and the second set of conductive pads 212 may include multiple conductive pads.

[0031] In some embodiments, the first redistribution layer 210 includes a first dielectric layer 213, and the first set of conductive pads 211 and the second set of conductive pads 212 are disposed within the first dielectric layer 213 and exposed on the surface of the first dielectric layer 213. In this embodiment, the first set of conductive pads 211 and the second set of conductive pads 212 are exposed on the top surface of the first dielectric layer 213, which serves as the first surface 210A of the first redistribution layer 210.

[0032] In some embodiments, the first dielectric layer 213 is an organic dielectric layer, and the material of the organic dielectric layer may be an organic resin, including but not limited to: epoxy resin (FR4), BT resin (bismaleimide triazine resin), PPE resin (polyphenylene ether resin), and PI resin (polyimide resin).

[0033] In some embodiments, the first set of conductive pads 211 and the second set of conductive pads 212 may both be metal bumps, and their materials may be the same or different. For example, in this embodiment, the first set of conductive pads 211 and the second set of conductive pads 212 are both copper bumps.

[0034] In some embodiments, the first redistribution layer 210 further includes conductive interconnects 214 and at least one bottom conductive pad 215. The conductive interconnects 214 are disposed within the first dielectric layer 213, and the first set of conductive pads 211 and the second set of conductive pads 212 are electrically connected to the conductive interconnects 214. The bottom conductive pads 215 are disposed within the first dielectric layer 213, and the bottom conductive pads 215 are electrically connected to the conductive interconnects 214. The other end of the bottom conductive pads 215 is exposed on the bottom surface of the first dielectric layer 213, serving as an external connection area at the bottom of the adapter board 200. The bottom surface of the first dielectric layer 213 serves as the second surface 210B of the first redistribution layer 210, and the second surface 210B is disposed opposite to the first surface 210A. The first set of conductive pads 211 and the second set of conductive pads 212 can be electrically connected via the conductive interconnects 214.

[0035] In some embodiments, the step of providing the adapter board 200 further includes:

[0036] Please see Figure 2A A carrier substrate 220 is provided, and a sacrificial layer 221 is formed on the carrier substrate 220. The carrier substrate 220 may be a carrier wafer, which provides support for the subsequently formed adapter plate 200, and the sacrificial layer 221 is used as a release layer when the adapter plate 200 is separated from the carrier substrate 220.

[0037] Please see Figure 2B The first redistribution layer 210 is formed on the sacrificial layer 221. In this step, multiple redistribution processes can be performed to form the bottom conductive pad 215, the conductive interconnect 214, the first set of conductive pads 211, and the second set of conductive pads 212. The second surface 210B of the first redistribution layer 210 is in contact with the sacrificial layer 221.

[0038] Please see Figure 1 and Figure 2C In step S11, a device substrate 230 is provided. The device substrate 230 includes a passive device layer 240 and a second redistribution layer 250 covering the passive device layer 240. The passive device layer 240 includes at least one passive device 241. The second redistribution layer 250 includes a third set of conductive pads 251 and a fourth set of conductive pads 252. One end of the third set of conductive pads 251 and the fourth set of conductive pads 252 are exposed on the first surface 250A of the second redistribution layer 250, and the other end of the third set of conductive pads 251 is electrically connected to the passive device 241.

[0039] The passive device 241 includes, but is not limited to, resistors, capacitors, and inductors. For example, in this embodiment, the passive device 241 is a capacitor, and the passive device layer 240 is a capacitor layer, which can be obtained by fabricating a capacitor on a wafer using semiconductor processes. The capacitor includes, but is not limited to, deep trench capacitors.

[0040] The third set of conductive pads 251 is electrically connected to the passive device 241, serving as pins of the passive device 241. The fourth set of conductive pads 252 is not electrically connected to the passive device 241, but serves as the electrical connection structure between the adapter plate 200 and the chip 260 in the package structure formed by the forming method. In some embodiments, both the third set of conductive pads 251 and the fourth set of conductive pads 252 may include multiple conductive pads. In this embodiment, the third set of conductive pads 251 includes multiple conductive pads, the passive device 241 is a capacitor, and the conductive pads are electrically connected to the positive or negative terminal of the capacitor, serving as pins of the positive or negative terminal of the capacitor.

[0041] In some embodiments, the second redistribution layer 250 includes a second dielectric layer 253, and the third set of conductive pads 251 and the fourth set of conductive pads 252 are disposed within the second dielectric layer 253 and exposed on the surface of the second dielectric layer 253. In this embodiment, the third set of conductive pads 251 and the fourth set of conductive pads 252 are exposed on the top surface of the second dielectric layer 253, which serves as the first surface 250A of the second redistribution layer 250. The bottom surface of the second dielectric layer 253 is disposed opposite to the top surface and contacts the passive device layer 240, serving as the second surface 250B of the second redistribution layer 250.

[0042] In some embodiments, the second dielectric layer 253 is an organic dielectric layer, and the material of the organic dielectric layer may be an organic resin, including but not limited to: epoxy resin (FR4), BT resin (bismaleimide triazine resin), PPE resin (polyphenylene ether resin), and PI resin (polyimide resin). In some embodiments, the first dielectric layer 213 and the second dielectric layer 253 are made of the same material, then in subsequent bonding processes, the first dielectric layer 213 and the second dielectric layer 253 will have a stronger bond.

[0043] In some embodiments, the third set of conductive pads 251 and the fourth set of conductive pads 252 may both be metal pads, and their materials may be the same or different. For example, in this embodiment, the third set of conductive pads 251 and the fourth set of conductive pads 252 are both copper pads. In some embodiments, the third set of conductive pads 251 and the first set of conductive pads 211 may be made of the same material, and the fourth set of conductive pads 252 and the second set of conductive pads 212 may be made of the same material. In this case, the bonding strength between the third set of conductive pads 251 and the first set of conductive pads 211, and between the fourth set of conductive pads 252 and the second set of conductive pads 212, is higher in the subsequent bonding process.

[0044] In this embodiment, both the third group of conductive pads 251 and the fourth group of conductive pads 252 penetrate the second dielectric layer 253, with their ends exposed on the first surface 250A and the second surface 250B of the second redistribution layer 250, respectively. In other embodiments, the third group of conductive pads 251 and the fourth group of conductive pads 252 are only disposed in a portion of the area below the first surface 250A of the second redistribution layer 250, and are electrically led out to the second surface 250B of the second redistribution layer 250 through conductive interconnects disposed in the second dielectric layer 253. That is, the third group of conductive pads 251 are electrically connected to the passive device 241 through conductive interconnects, and the fourth group of conductive pads 252 are led out to the second surface 250B of the second redistribution layer 250 through conductive interconnects.

[0045] In the forming method provided in the embodiments of the present invention, the parameters of the passive device 241, such as the capacitance value, can be adjusted during the manufacturing process of the passive device 241 in the device substrate 230 to achieve precise matching between the passive device 241 and the subsequently set chip 260.

[0046] Please see Figure 1 and Figure 2D In step S12, using the first surface 210A of the first redistribution layer 210 and the first surface 250A of the second redistribution layer 250 as bonding surfaces, a hybrid bonding process is used to bond the adapter plate 200 to the device substrate 230. Specifically, the first group of conductive pads 211 is electrically connected to the third group of conductive pads 251, and the second group of conductive pads 212 is electrically connected to the fourth group of conductive pads 252. The structure formed using the hybrid bonding process has higher current carrying capacity and better thermal performance. In some embodiments, the top surface of the first dielectric layer 213 is also bonded to the top surface of the second dielectric layer 253.

[0047] The hybrid bonding process includes: bonding the first surface of the first redistribution layer 210 of the adapter board 200 to the first surface 250A of the second redistribution layer 250 of the device substrate 230, wherein the first dielectric layer 213 is bonded to the second dielectric layer 253; performing annealing treatment, bonding the first group of conductive pads 211 to the third group of conductive pads 251, and bonding the second group of conductive pads 212 to the fourth group of conductive pads 252 to form a bonding structure.

[0048] In some embodiments, the first surface 210A of the first redistribution layer 210 is planarized before the bonding process, and / or the first surface 250A of the second redistribution layer 250 is planarized. That is, both the first surface 210A of the first redistribution layer 210 and the first surface 250A of the second redistribution layer 250 are planarized before the bonding process, or one of the first surface 210A of the first redistribution layer 210 or the first surface 250A of the second redistribution layer 250 is planarized to reduce surface roughness and improve the bonding strength of the package structure formed by bonding. The planarization process includes, but is not limited to, chemical mechanical polishing (CMP).

[0049] In some embodiments, activating the first surface 210A of the first redistribution layer 210 and / or the first surface 250A of the second redistribution layer 250 before performing the bonding process can form activation sites on the first surface 210A of the first redistribution layer 210 and / or the first surface 250A of the second redistribution layer 250, thereby improving the bonding strength between the first redistribution layer 210 and the second redistribution layer 250 in hybrid bonding. The activation process includes, but is not limited to, plasma activation. Specifically, activating the first surface 210A of the first redistribution layer 210 and / or the first surface 250A of the second redistribution layer 250 before performing the bonding process can form activation sites on the surfaces of the first dielectric layer 213 and / or the second dielectric layer 253, thereby improving the bonding strength between the first dielectric layer 213 and the second dielectric layer 253.

[0050] In one embodiment, the first surface 210A of the first redistribution layer 210 and the first surface 250A of the second redistribution layer 250 are activated before the bonding process is performed; in another embodiment, one of the first surface 210A of the first redistribution layer 210 or the first surface 250A of the second redistribution layer 250 is activated before the bonding process is performed.

[0051] Please see Figure 1 and Figure 2E In step S13, a portion of the passive device layer 240 is removed from the surface of the device substrate 230 away from the adapter plate 200 to expose the fourth set of conductive pads 252.

[0052] The fourth set of conductive pads 252 corresponds to the area of ​​the passive device layer 240 that does not have the passive device 241. In this step, the area of ​​the passive device layer 240 that does not have the passive device 241 is removed from the surface of the device substrate 230 away from the adapter plate 200 to expose the fourth set of conductive pads 252.

[0053] Methods for removing a portion of the passive device layer 240 include, but are not limited to, etching processes. For example, in some embodiments, the method for removing a portion of the passive device layer 240 includes: forming a patterned mask layer on the surface of the device substrate 230 opposite to the adapter plate 200, the mask layer obscuring the area of ​​the passive device layer 240 where the passive device is located and exposing the area of ​​the passive device layer 240 corresponding to the fourth group of conductive pads 252; using the mask layer as a mask, etching the passive device layer 240 until the fourth group of conductive pads 252 is exposed; and removing the mask layer.

[0054] Please see Figure 1and Figure 2F In step S14, at least one chip 260 is disposed on the surface of the device substrate 230 opposite to the adapter plate 200. The chip 260 is electrically connected to the fourth set of conductive pads 252. The chip 260 and the passive device 241 are disposed on the same side of the adapter plate 200, so that the passive device 241 and the chip 260 are close to each other, enabling local energy storage near the chip.

[0055] There may be one or more chips 260, all of which are disposed on the first surface 250A of the second redistribution layer 250. The conductive pads of the chip 260 facing the device substrate 230 are electrically connected to the fourth set of conductive pads 252, thereby realizing the electrical connection between the chip 260 and the adapter board 200. In some embodiments, a flip-chip process can be used to electrically connect the chip 260 to the fourth set of conductive pads 252.

[0056] Furthermore, in some embodiments, the formation method further includes the step of removing the carrier substrate 220 using the sacrificial layer 221 as a separation layer. See also... Figure 2G The carrier substrate 220 is removed by using the sacrificial layer 221 as a separation layer, and the second surface 210B of the first redistribution layer 210 is exposed, as is the bottom conductive pad 215, so that it can be electrically connected to the external substrate.

[0057] The method for removing the carrier substrate 220 can be determined based on the material of the sacrificial layer 221. For example, if the sacrificial layer 221 is a soluble substance, it can be removed by soaking in a stripping solution, thereby removing the carrier substrate 220; if the sacrificial layer 221 is a laser-sensitive substance, it can be modified by irradiating the sacrificial layer 221 with a laser, thereby removing the carrier substrate 220.

[0058] The method of the present invention enables the direct integration of passive devices 241 inside or on the surface of the adapter board 200 using wafer-level packaging technology before the chip 260 is exposed, without the need for additional surface mount technology to connect the passive devices 241 to the adapter board 200, which greatly improves process compatibility and saves a lot of area of ​​the adapter board 200, which is beneficial to the miniaturization of the packaging structure.

[0059] In some embodiments, after the fourth set of conductive pads 252, the chip 260 can be directly mounted to form a package structure, such as... Figure 2F As shown. In other embodiments, before the step of setting the chip 260 on the surface of the device substrate 230 opposite to the adapter plate 200, a step of forming a third wiring layer 300 is included, and the chip 260 is mounted after the third wiring layer 300 is formed.

[0060] Specifically, please refer to Figure 3A , in Figure 2E Based on the structure shown, a third wiring layer 300 is formed on the surface of the device substrate 230 opposite to the adapter plate 200. The third wiring layer 300 covers the device substrate 230. The third wiring layer 300 includes a fifth set of conductive pads 301, which are electrically connected to the fourth set of conductive pads 252. The fifth set of conductive pads 301 are exposed on the first surface 300A of the third wiring layer 300. Please refer to [reference needed]. Figure 3B On the first surface 300A of the third wiring layer 300, the chip 260 is electrically connected to the fifth set of conductive pads 301 using a flip-chip process. The conductive pads on the side of the chip 260 facing the device substrate 230 are electrically connected to the fifth set of conductive pads 301, thereby realizing the electrical connection between the chip 260 and the adapter board 200.

[0061] The third redistribution layer 300 covers the exposed surfaces of the passive device layer 240 and the second redistribution layer 250. In some embodiments, the third redistribution layer 300 includes a third dielectric layer 302, which covers the surfaces of the passive device layer 240 and the second redistribution layer 250, with the top surface of the third dielectric layer 302 serving as the first surface 300A of the third redistribution layer 300. The fifth set of conductive pads 301 penetrates the third dielectric layer 302, with one end connected to the fourth set of conductive pads 252 and the other end exposed on the surface of the third dielectric layer 302. In some embodiments, the third dielectric layer 302 is an organic dielectric layer made of the same material as the second dielectric layer 253, and the fifth set of conductive pads 301 is a metallic conductive pad made of the same material as the fourth set of conductive pads 252.

[0062] In other embodiments, the formation of a sixth set of conductive pads 400 is further included after the formation of the third wiring layer 300. Specifically, please refer to... Figure 4A , in Figure 3A Based on the structure shown, a sixth group of conductive pads 400 is formed on the first surface of the third wiring layer 300, and the sixth group of conductive pads 400 is electrically connected to the fifth group of conductive pads 301. (See also...) Figure 4B The chip 260 is electrically connected to the sixth set of conductive pads 400 using a flip-chip process.

[0063] The sixth set of conductive pads 400 is disposed on the surface of the third dielectric layer 302 and is electrically connected to the fifth set of conductive pads 301. It can fan out the fifth set of conductive pads 301 to achieve the packaging integration of a chip 260 with a smaller external size.

[0064] The present invention also provides a packaging structure formed using the above-described forming method. Please refer to [link / reference]. Figures 2A to 2G The packaging structure includes: an adapter board 200, the adapter board 200 including a first redistribution layer 210, the first redistribution layer 210 including a first set of conductive pads 211 and a second set of conductive pads 212; a device substrate 230, including a passive device layer 240 and a second redistribution layer 250 covering the passive device layer 240, the passive device layer 240 including at least one passive device 241, the second redistribution layer 250 being co-bonded with the first redistribution layer 210, and the second redistribution layer 250 including a third set of conductive pads 212. The third group of conductive pads 251 and the fourth group of conductive pads 252 are provided. One end of the third group of conductive pads 251 is electrically connected to the first group of conductive pads 211, and the other end is electrically connected to the passive device 241. One end of the fourth group of conductive pads 252 is electrically connected to one end of the second group of conductive pads 212, and the other end is exposed on the passive device layer 240. At least one chip 260 is disposed on the surface of the device substrate 230 away from the adapter plate 200, and the chip 260 is electrically connected to the other end of the fourth group of conductive pads 252.

[0065] In the packaging structure provided by this embodiment of the invention, the passive device 241 is integrated inside or on the surface of the adapter board 200. The passive device 241 using the above integration method greatly saves the area of ​​the adapter board 200, which is beneficial to the miniaturization of the packaging structure. The chip 260 and the passive device 241 are disposed on the same side of the adapter board 200, so that the passive device 241 and the chip 260 are close to each other, and local energy storage can be achieved near the chip. Furthermore, the passive device 241 and the chip 260 can be precisely matched, improving the performance of the packaging structure.

[0066] In one embodiment, the first redistribution layer 210 includes a first dielectric layer 213, and a first set of conductive pads 211 and a second set of conductive pads 212 are disposed within the first dielectric layer 213. In some embodiments, the first redistribution layer 210 further includes conductive interconnects 214 and at least one bottom conductive pad 215. The conductive interconnects 214 are disposed within the first dielectric layer 213, and the first set of conductive pads 211 and the second set of conductive pads 212 are electrically connected to the conductive interconnects 214. The bottom conductive pad 215 is disposed within the first dielectric layer 213, and the bottom conductive pad 215 is electrically connected to the conductive interconnects 214. The other end of the bottom conductive pad 215 is exposed on the bottom surface of the first dielectric layer 213, serving as an external connection area on the bottom of the adapter board 200.

[0067] The passive device 241 includes, but is not limited to, resistors, capacitors, and inductors. For example, in this embodiment, the passive device 241 is a capacitor, and the passive device layer 240 is a capacitor layer. The second redistribution layer 250 includes a second dielectric layer 253, and the third set of conductive pads 251 and the fourth set of conductive pads 252 are disposed within the second dielectric layer 253. The third set of conductive pads 251 is electrically connected to the passive device 241, and the first dielectric layer 213 is also bonded to the second dielectric layer 253.

[0068] In one embodiment, the material of the first dielectric layer 213 is the same as the material of the second dielectric layer 253, and / or the material of the first group of conductive pads 211 is the same as the material of the third group of conductive pads 251. For example, both the first dielectric layer 213 and the second dielectric layer 253 are organic dielectric layers, and both the first group of conductive pads 211 and the third group of conductive pads 251 are copper pads. In some embodiments, the material of the fourth group of conductive pads 252 and the second group of conductive pads 212 may be the same, for example, both are copper pads.

[0069] The chip 260 and the passive device 241 are disposed on the same side of the adapter plate 200, making the passive device 241 and the chip 260 close together, enabling local energy storage near the chip. In one embodiment, the conductive pads on the side of the chip 260 facing the device substrate 230 are electrically connected to the fourth set of conductive pads 252, thereby realizing the electrical connection between the chip 260 and the adapter plate 200.

[0070] In the above embodiment, the chip 260 is directly electrically connected to the fourth set of conductive pads 252. In another embodiment, the chip 260 is electrically connected to the fourth set of conductive pads 252 through a third wiring layer 300. For details, please refer to... Figure 3BThe semiconductor structure further includes a third wiring layer 300. The third wiring layer 300 covers the surface of the device substrate 230 opposite to the adapter plate 200. The third wiring layer 300 includes a fifth set of conductive pads 301. One end of the fifth set of conductive pads 301 is electrically connected to the other end of the fourth set of conductive pads 252. The chip 260 is disposed on the surface of the fifth wiring layer and is electrically connected to the other end of the fifth set of conductive pads 301.

[0071] In some embodiments, the third redistribution layer 300 includes a third dielectric layer 302, which covers the surface of the passive device layer 240 and the surface of the second redistribution layer 250. The fifth set of conductive pads 301 penetrates the third dielectric layer 302, with one end connected to the fourth set of conductive pads 252 and the other end electrically connected to the chip 260. In some embodiments, the material of the third dielectric layer 302 is the same as the material of the second dielectric layer 253, and the material of the fifth set of conductive pads 301 is the same as the material of the fourth set of conductive pads 252.

[0072] In some embodiments, the packaging structure further includes a sixth set of conductive pads 400. Specifically, please refer to... Figure 4B The sixth group of conductive pads 400 is disposed on the surface of the third redistribution layer 300 facing away from the device substrate 230, and one end of the sixth group of conductive pads 400 is electrically connected to the other end of the fifth group of conductive pads 301. The chip 260 is electrically connected to the other end of the sixth group of conductive pads 400. The sixth group of conductive pads 400 is disposed on the surface of the third dielectric layer 302 and is electrically connected to the fifth group of conductive pads 301. It can fan out the fifth group of conductive pads 301 to achieve the packaging integration of a chip 260 with a smaller external size.

[0073] It should be noted that the terms "comprising" and "having," and their variations, used in this invention document are intended to cover non-exclusive inclusion. The terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless explicitly indicated by the context; it should be understood that such use of data can be interchanged where appropriate. The term "one or more" depends at least in part on the context and can be used to describe features, structures, or characteristics in a singular sense, or in a plural sense to describe combinations of features, structures, or characteristics. The term "based on" can be understood as not necessarily intended to express an exclusive set of factors, but can instead, also at least in part on the context, allow for the presence of other factors that are not necessarily explicitly described. Furthermore, embodiments and features in embodiments of this invention can be combined with each other without conflict. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this invention. In the various embodiments described above, each embodiment focuses on its differences from other embodiments; similar / identical parts between embodiments can be referred to mutually.

[0074] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for forming an encapsulation structure, characterized in that, include: An adapter board is provided, the adapter board including a first rewiring layer, the first rewiring layer including a first set of conductive pads and a second set of conductive pads, and one end of the first set of conductive pads and the second set of conductive pads are exposed on a first surface of the first rewiring layer. A device substrate is provided, the device substrate including a passive device layer and a second redistribution layer covering the passive device layer, the passive device layer including at least one passive device, the second redistribution layer including a third group of conductive pads and a fourth group of conductive pads, one end of the third group of conductive pads and the fourth group of conductive pads being exposed on a first surface of the second redistribution layer, and the other end of the third group of conductive pads being electrically connected to the passive device. Using the first surface of the first redistribution layer and the first surface of the second redistribution layer as bonding surfaces, the adapter board is bonded to the device substrate using a hybrid bonding process, wherein the first group of conductive pads is electrically connected to the third group of conductive pads, and the second group of conductive pads is electrically connected to the fourth group of conductive pads. A portion of the passive device layer is removed from the surface of the device substrate away from the adapter plate to expose the fourth set of conductive pads, and the removed passive device layer does not have the passive device. At least one chip is disposed on the surface of the device substrate opposite to the adapter plate, and the chip is electrically connected to the fourth set of conductive pads.

2. The method for forming the packaging structure according to claim 1, characterized in that, Prior to the step of bonding the adapter plate to the device substrate using a hybrid bonding process, the following steps are included: The first surface of the first redistribution layer is planarized, and / or the first surface of the second redistribution layer is planarized.

3. The method for forming the packaging structure according to claim 1, characterized in that, Prior to the step of bonding the adapter plate to the device substrate using a hybrid bonding process, the following steps are included: The first surface of the first redistribution layer and / or the first surface of the second redistribution layer are activated.

4. The method for forming the packaging structure according to claim 1, characterized in that, The first redistribution layer includes a first dielectric layer, and the first set of conductive pads and the second set of conductive pads are disposed within the first dielectric layer and exposed on the surface of the first dielectric layer; the second redistribution layer includes a second dielectric layer, and the third set of conductive pads and the fourth set of conductive pads are disposed within the second dielectric layer and exposed on the surface of the second dielectric layer. In the step of bonding the adapter plate to the device substrate using a hybrid bonding process, the first dielectric layer is also bonded to the second dielectric layer. In the step of removing a portion of the passive device layer from the surface of the device substrate away from the adapter plate, the second dielectric layer is also exposed.

5. The method for forming the packaging structure according to claim 1, characterized in that, The step of setting a chip on the surface of the device substrate opposite to the adapter plate includes: On the surface of the device substrate facing away from the adapter plate, the chip is electrically connected to the fourth set of conductive pads using a flip-chip process.

6. The method for forming the packaging structure according to claim 1, characterized in that, The step of placing the chip on the surface of the device substrate opposite to the adapter plate includes the following steps: A third wiring layer is formed on the surface of the device substrate opposite to the adapter plate. The third wiring layer covers the device substrate. The third wiring layer includes a fifth set of conductive pads. The fifth set of conductive pads is electrically connected to the fourth set of conductive pads, and the fifth set of conductive pads is exposed on the first surface of the third wiring layer. On the first surface of the third wiring layer, the chip is electrically connected to the fifth set of conductive pads using a flip-chip process.

7. The method for forming the packaging structure according to claim 6, characterized in that, The step of electrically connecting the chip to the fifth set of conductive pads using a flip-chip process on the first surface of the third wiring layer includes: A sixth set of conductive pads is formed on the first surface of the third wiring layer, and the sixth set of conductive pads is electrically connected to the fifth set of conductive pads. The chip is electrically connected to the sixth set of conductive pads using a flip-chip process.

8. The method for forming the packaging structure according to claim 1, characterized in that, The step of providing the adapter board further includes: providing a carrier substrate and forming a sacrificial layer on the carrier substrate; forming the first redistribution layer on the sacrificial layer; After the step of setting the chip on the surface of the device substrate away from the adapter plate, the carrier substrate is removed using the sacrificial layer as a separation layer.

9. A packaging structure, characterized in that, include: The adapter board includes a first rewiring layer, which includes a first set of conductive pads and a second set of conductive pads. A device substrate includes a passive device layer and a second redistribution layer covering the passive device layer. The passive device layer includes at least one passive device. The second redistribution layer is co-bonded with the first redistribution layer. The second redistribution layer includes a third set of conductive pads and a fourth set of conductive pads. One end of the third set of conductive pads is electrically connected to the first set of conductive pads, and the other end is electrically connected to the passive device. One end of the fourth set of conductive pads is electrically connected to one end of the second set of conductive pads. By removing a portion of the passive device layer from the surface of the device substrate away from the adapter plate, the other end of the fourth set of conductive pads is exposed to the passive device layer, and the removed passive device layer does not have the passive device. At least one chip is disposed on the surface of the device substrate opposite to the adapter plate, and the chip is electrically connected to the other end of the fourth set of conductive pads.

10. The packaging structure according to claim 9, characterized in that, The first redistribution layer includes a first dielectric layer, and the first set of conductive pads and the second set of conductive pads are disposed within the first dielectric layer; the second redistribution layer includes a second dielectric layer, and the third set of conductive pads and the fourth set of conductive pads are disposed within the second dielectric layer; the first dielectric layer is also bonded to the second dielectric layer, and the material of the first dielectric layer is the same as the material of the second dielectric layer, and / or the material of the first set of conductive pads is the same as the material of the third set of conductive pads.

11. The packaging structure according to claim 10, characterized in that, It also includes a third wiring layer that covers the surface of the device substrate away from the adapter plate. The third wiring layer includes a fifth set of conductive pads. One end of the fifth set of conductive pads is electrically connected to the other end of the fourth set of conductive pads. The chip is disposed on the surface of the third wiring layer and is electrically connected to the other end of the fifth set of conductive pads.

12. The packaging structure according to claim 11, characterized in that, It also includes a sixth set of conductive pads, which are disposed on the surface of the third wiring layer away from the device substrate, and one end of the sixth set of conductive pads is electrically connected to the other end of the fifth set of conductive pads, and the chip is electrically connected to the other end of the sixth set of conductive pads.

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