Multi-channel comparison circuit and power management chip

Abstract

The embodiment of the present disclosure provides a multi-channel comparison circuit and a power management chip. The multi-channel comparison circuit includes an input control module, an output control module, a single cooperative comparator and a multi-channel comparator module. When the multi-channel comparator module receives N channel voltage pairs, it compensates the N channel voltage pairs according to the N channel offset voltages and obtains N channel comparison signals. When receiving a common voltage and N-1 channel voltage pairs, it samples the target channel offset voltage, and compensates the N-1 other channel voltage pairs according to the N-1 other channel offset voltages, and obtains N-1 channel comparison signals. The cooperative comparator samples the cooperative offset voltage when receiving the common voltage, and compensates the target channel voltage pair according to the cooperative offset voltage when receiving the target channel voltage pair, and obtains the cooperative comparison signal. The multi-channel comparison circuit can realize high-precision multi-channel power supply voltage monitoring for the entire period of time, and can also reduce the circuit area.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of integrated circuit technology, and in particular to a multi-channel comparison circuit and a power management chip. Background Art

[0002] Power Management Integrated Circuit (PMIC) is a highly integrated power supply device, mainly used to manage and regulate the power supply of electronic systems. Due to its high integration, small size, low cost and high efficiency, it is widely used in terminal equipment in many fields such as automobiles, communications, electronics and radar. An important indicator of PMIC is voltage monitoring accuracy. Voltage monitoring can be achieved by sending a feedback voltage that indicates the output voltage to a comparator for comparison with a reference voltage. The voltage monitoring accuracy depends on the accuracy of the comparator, and the accuracy of the comparator is mainly limited by the offset voltage of the comparator.

[0003] In the prior art, a comparator is usually added on the basis of the self-zeroing technology, and the sampling timing of the added comparator is opposite to that of the original comparator, so that high-precision voltage monitoring can be achieved throughout the entire period. However, since PMIC can provide multi-channel power supply, if the prior art is used, multiple additional comparators need to be added, resulting in an increase in circuit area. Summary of the invention

[0004] The present disclosure provides a multi-channel comparison circuit and a power management chip, which can realize high-precision multi-channel power supply voltage monitoring throughout the entire period and can also reduce the circuit area.

[0005] In a first aspect, the present disclosure provides a multi-channel comparison circuit, including an input control module, an output control module, a single cooperative comparator and a multi-channel comparator module.

[0006] The input control module is configured to receive a common voltage and N channel voltage pairs, and connect the common voltage and the N channel voltage pairs to the cooperative comparator and the multi-channel comparator module, where N is an integer greater than or equal to 2. The cooperative comparator is configured to sample the cooperative offset voltage when receiving the common voltage; when receiving the target channel voltage pair, compensate the target channel voltage pair according to the cooperative offset voltage, and compare the compensated target channel voltage pairs to obtain a cooperative comparison signal.

[0007] The multi-channel comparator module is configured to, when receiving N channel voltage pairs, compensate the N channel voltage pairs according to the N channel offset voltages, and compare each of the compensated channel voltage pairs to obtain N channel comparison signals; when receiving the common voltage and N-1 channel voltage pairs, sample the target channel offset voltage, compensate N-1 other channel voltage pairs according to N-1 other channel offset voltages, and compare each of the compensated other channel voltage pairs to obtain N-1 channel comparison signals. The output control module is configured to output part of all comparison signals, and all comparison signals include the collaborative comparison signal and the N channel comparison signals.

[0008] Among them, the target channel voltage pair is any one of the N channel voltage pairs, and the N channel voltage pairs include the target channel voltage pair and N-1 other channel voltages; the target channel offset voltage is any one of the N channel offset voltages, and the N channel offset voltages include the target channel offset voltage and N-1 other channel offset voltages.

[0009] In a second aspect, the present disclosure provides a power management chip, comprising any multi-channel comparison circuit provided in the first aspect.

[0010] The technical solution disclosed in the present invention provides a multi-channel comparison circuit, including an input control module, an output control module, a single cooperative comparator and a multi-channel comparator module. When the multi-channel comparator module receives N channel voltage pairs, it compensates the N channel voltage pairs according to the N channel offset voltages, and compares each compensated channel voltage pair to obtain N channel comparison signals. When a common voltage and N-1 channel voltage pairs are received, the target channel offset voltage is sampled, and the N-1 other channel voltage pairs are compensated according to the N-1 other channel offset voltages, and each other channel voltage pair is compared after compensation to obtain N-1 channel comparison signals. When the cooperative comparator receives the common voltage, it samples the cooperative offset voltage, and when the target channel voltage pair is received, it compensates the target channel voltage pair according to the cooperative offset voltage, and compares the compensated target channel voltage pair to obtain the cooperative comparison signal. In this way, a single cooperative comparator can take over the comparison work of the channel comparator in the sampling stage in the multi-channel comparator module to realize high-precision multi-channel power supply voltage monitoring in the whole period, which can reduce the number of comparators, reduce the circuit complexity, and thus reduce the circuit area. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. It should be noted that the drawings described below only relate to some embodiments of the present disclosure, rather than limiting the present disclosure, wherein:

[0012] Figure 1 A schematic diagram of the structure of a comparator provided in an embodiment of the present disclosure;

[0013] Figure 2 for Figure 1 Schematic diagram of voltage waveforms of input signal and output signal of the comparator shown;

[0014] Figure 3 A schematic diagram of the structure of a multi-channel comparison circuit provided by an embodiment of the present disclosure;

[0015] Figure 4 A schematic diagram of the structure of another multi-channel comparison circuit provided by an embodiment of the present disclosure;

[0016] Figure 5 A schematic diagram of a collaborative clock signal and a channel clock signal provided in an embodiment of the present disclosure;

[0017] Figure 6 A circuit diagram of a multi-channel comparison circuit provided by an embodiment of the present disclosure;

[0018] Figure 7 A circuit diagram of another multi-channel comparison circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0020] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person skilled in the art to which the subject matter of the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" together shall mean that the parts are joined together directly or through one or more intermediate components.

[0021] Reference to "embodiments" in this disclosure means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase "embodiments" in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described in this disclosure may be combined with other embodiments.

[0022] In addition, the terms "first", "second", etc. in the specification and claims of the present disclosure or the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.

[0023] The term "and / or" in this disclosure is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0024] In the description of the present disclosure, unless otherwise specified, "plurality" and "at least two" mean more than two (including two). Similarly, "plurality groups" and "at least two groups" mean more than two groups (including two).

[0025] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0026] PMIC integrates a multi-channel direct current (DC)-DC converter, a low dropout regulator (LDO), a high-side / low-side switch and a charging controller, etc., which can realize voltage conversion, current control and power management, and can also provide multi-channel power supply to meet the power requirements of different subsystems.

[0027] An important indicator of PMIC is voltage monitoring accuracy, which means that it can accurately indicate when the provided channel power supply voltage is higher or lower than a certain value. It is often used for monitoring channel power supply overvoltage, undervoltage and loss of voltage. Voltage monitoring mainly sends a feedback voltage that can indicate the channel power supply voltage to a comparator for comparison with a reference voltage. When the feedback voltage is higher or lower than the reference voltage, the comparator outputs different comparison signals.

[0028] Figure 1 A schematic diagram of a comparator provided in an embodiment of the present disclosure is shown in FIG. Figure 1As shown, the non-inverting input terminal of the comparator CMP receives the reference voltage Vfef, the inverting input terminal of the comparator CMP receives the feedback voltage Vfb, and the comparator CMP itself has an offset voltage Voffset, which can be superimposed on the non-inverting input terminal of the comparator CMP.

[0029] Figure 2 for Figure 1 The voltage waveform diagram of the input signal and output signal of the comparator shown in FIG. Figure 2 As shown, when the feedback voltage Vfb is slightly higher than the reference voltage Vref, the actual comparison signal Scmp_offset output by the comparator CMP is a low level signal. When the feedback voltage Vfb is greater than the sum of the reference voltage Vref and the offset voltage Voffset of the comparator CMP, the actual comparison signal Scmp_offset will jump to a high level signal.

[0030] Obviously, the smaller the offset voltage Voffset of the comparator CMP is, the higher the accuracy of the comparator CMP is, and the higher the voltage monitoring accuracy of the PMIC is. Therefore, in order to improve the voltage monitoring accuracy, the offset voltage Voffset of the comparator CMP needs to be reduced to make the actual comparison signal Scmp_offset as close to the ideal comparison signal Scmp_ideal as possible.

[0031] It should be noted that Figure 1 It is only exemplarily shown that the offset voltage Voffset is superimposed on the non-inverting input terminal of the comparator CMP. In actual applications, the offset voltage Voffset may also be superimposed on the inverting input terminal of the comparator CMP.

[0032] In the prior art, the offset voltage Voffset of the comparator CMP can be reduced by increasing the area of ​​the input pair tube and / or improving the transconductance to reduce the mismatch. However, this method greatly increases the circuit area and complexity, and it is difficult to reduce the offset voltage Voffset to the uV level. At the same time, the offset voltage Voffset varies greatly with temperature. Therefore, a self-zeroing technology is proposed to reduce the offset voltage Voffset of the comparator CMP.

[0033] The implementation process of the self-zeroing technology can be roughly divided into two stages. In the first stage, the offset voltage Voffset of the comparator CMP is sampled. In the second stage, the offset voltage Voffset is subtracted from the input and output of the comparator CMP, which can reduce the offset voltage Voffset to the uV level. However, the comparator CMP cannot perform comparisons during the sampling of the offset voltage Voffset, so that the comparator CMP cannot achieve full-time comparison function during working hours. In order to make up for this shortcoming, an additional comparator is usually added to work with the original comparator. The sampling timing and comparison timing of the original comparator are opposite to those of the added comparator, that is, when one comparator is sampling, another comparator is comparing.

[0034] However, the PMIC can provide multiple channel power supplies. If the above technology is used, multiple additional comparators need to be added, resulting in a more complex comparison circuit and a larger circuit area.

[0035] In view of this, the present disclosure provides a multi-channel comparison circuit, including an input control module, an output control module, a single cooperative comparator and a multi-channel comparator module. When the multi-channel comparator module receives N channel voltage pairs, it compensates the N channel voltage pairs according to the N channel offset voltages, and compares each compensated channel voltage pair to obtain N channel comparison signals. When a common voltage and N-1 channel voltage pairs are received, the target channel offset voltage is sampled, and the N-1 other channel voltage pairs are compensated according to the N-1 other channel offset voltages, and each other channel voltage pair after compensation is compared to obtain N-1 channel comparison signals. When the cooperative comparator receives the common voltage, it samples the cooperative offset voltage, and when the target channel voltage pair is received, it compensates the target channel voltage pair according to the cooperative offset voltage, and compares the compensated target channel voltage pairs to obtain the cooperative comparison signal. In this way, a single cooperative comparator can take over the comparison work of the channel comparator in the sampling stage in the multi-channel comparator module to realize high-precision multi-channel power supply voltage monitoring in the whole time period, which can reduce the number of comparators, reduce circuit complexity, and thus reduce circuit area.

[0036] The technical solution of the present disclosure is described in detail below with reference to several specific embodiments.

[0037] Figure 3 A schematic diagram of a multi-channel comparison circuit provided in an embodiment of the present disclosure is shown in FIG. Figure 3 As shown, the multi-channel comparison circuit 100 includes: a multi-channel comparator module 110, an input control module 120, an output control module 130 and a single cooperative comparator CMP_co.

[0038] The N pairs of input terminals of the input control module 120 are connected to the N channel voltage pairs in a one-to-one correspondence, the N pairs of channel output terminals of the input control module 120 are connected to the N pairs of input terminals of the multi-channel comparator module 110 in a one-to-one correspondence, the coordinated output terminal of the input control module 120 is connected to the input terminal of the coordinated comparator CMP_co, the common terminal of the input control module 120 is connected to the common voltage Vcom, the output terminal of the coordinated comparator CMP_co is connected to the coordinated input terminal of the output control module 130, the N output terminals of the multi-channel comparator module 110 are connected to the N channel input terminals of the output control module 130 in a one-to-one correspondence, and the N output terminals of the output control module 130 are connected to the N output terminals of the multi-channel comparison circuit 100 in a one-to-one correspondence, and N is an integer greater than or equal to 2.

[0039] The input control module 120 is configured to receive a common voltage Vom and N channel voltage pairs, and connect the common voltage Vom and the N channel voltage pairs to the cooperative comparator CMP_co and the multi-channel comparator module 110. The cooperative comparator CMP_co is configured to sample the cooperative offset voltage Voffset_co when receiving the common voltage Vom; when receiving the target channel voltage pair, compensate the target channel voltage pair according to the cooperative offset voltage Voffset_co, and compare the compensated target channel voltage pair to obtain a cooperative comparison signal Scmp_co.

[0040] The multi-channel comparator module 110 is configured to, when receiving N channel voltage pairs, compensate the N channel voltage pairs according to the N channel offset voltages Voffset_ch, and compare each compensated channel voltage pair to obtain N channel comparison signals Scmp_ch; when receiving the common voltage Vom and N-1 channel voltage pairs, sample the target channel offset voltage, compensate N-1 other channel voltage pairs according to the N-1 other channel offset voltages, and compare each other channel voltage pair after compensation to obtain N-1 other channel comparison signals. The output control module 130 is configured to output part of all comparison signals, and all comparison signals include the collaborative comparison signal Scmp_co and the N channel comparison signals Scmp_ch.

[0041] The target channel voltage pair is any one of the N channel voltage pairs, and the N channel voltage pairs include the target channel voltage pair and N-1 other channel voltage pairs. The target channel offset voltage is any one of the N channel offset voltages Voffset_ch, and the N channel offset voltages Voffset_ch include the target channel offset voltage and N-1 other channel offset voltages.

[0042] Exemplarily, each pair of input terminals of the input control module 120 includes a positive input terminal and a negative input terminal, and each channel voltage pair includes a channel reference voltage Vref_ch and a channel feedback voltage Vfb_ch. Then, the i-th positive input terminal of the input control module 120 is connected to the i-th channel reference voltage Vref_chi, and the i-th negative input terminal of the input control module 120 is connected to the i-th channel feedback voltage Vfb_chi, where 1≤i≤N and i is an integer.

[0043] Each pair of channel output terminals of the input control module 120 includes a channel positive phase output terminal and a channel negative phase output terminal, and each pair of input terminals of the multi-channel comparator module 110 includes a positive phase input terminal and a negative phase input terminal. The i-th channel positive phase output terminal of the input control module 120 is connected to the i-th positive phase input terminal of the multi-channel comparator module 110, and the i-th channel negative phase output terminal of the input control module 120 is connected to the i-th negative phase input terminal of the multi-channel comparator module 110.

[0044] The coordinated output end of the input control module 120 includes a coordinated positive phase output end and a coordinated negative phase output end, the input end of the coordinated comparator CMP_co includes a positive phase input end and a negative phase input end, the coordinated positive phase output end of the input control module 120 is connected to the positive phase input end of the coordinated comparator CMP_co, and the coordinated negative phase output end of the input control module 120 is connected to the negative phase input end of the coordinated comparator CMP_co.

[0045] The input control module 120 can connect the common end of the input control module 120 with the positive input end and the negative input end of the cooperative comparator CMP_co to connect the common voltage Vcom to the cooperative comparator CMP_co, and at the same time connect the i-th positive input end of the input control module 120 with the i-th positive input end of the multi-channel comparator module 110, and the i-th negative input end of the input control module 120 with the i-th negative input end of the multi-channel comparator module 110 to connect the i-th channel reference voltage Vref_chi and the i-th channel feedback voltage Vfb_chi to the multi-channel comparator module 110.

[0046] The input control module 120 can also connect the common end of the input control module 120 with the i-th positive input end and the i-th negative input end of the multi-channel comparator module 110 to connect the common voltage Vcom to the multi-channel comparator module 110, connect the i-th positive input end of the input control module 120 with the positive input end of the collaborative comparator CMP_co, and connect the i-th negative input end of the input control module 120 with the negative input end of the collaborative comparator CMP_co to connect the i-th channel reference voltage Vref_chi and the i-th channel feedback voltage Vfb_chi to the collaborative comparator CMP_co.

[0047] At the same time, the jth positive input terminal of the input control module 120 and the jth positive input terminal of the multi-channel comparator module 110, the jth inverting input terminal of the input control module 120 and the jth inverting input terminal of the multi-channel comparator module 110 are turned on, 1≤j≤N, i≠j and j is an integer, so as to connect the jth channel reference voltage Vref_chj and the jth channel feedback voltage Vfb_chj to the multi-channel comparator module 110.

[0048] For example, when N=3, Figure 3 As shown, the first positive input terminal of the input control module 120 is connected to the first channel reference voltage Vref_ch1, the first negative input terminal of the input control module 120 is connected to the first channel feedback voltage Vfb_ch1, the second positive input terminal of the input control module 120 is connected to the second channel reference voltage Vref_ch2, ​​the second negative input terminal of the input control module 120 is connected to the second channel feedback voltage Vfb_ch2, ​​the third positive input terminal of the input control module 120 is connected to the third channel reference voltage Vref_ch3, and the third negative input terminal of the input control module 120 is connected to the third channel feedback voltage Vfb_ch3.

[0049] The first channel positive phase output terminal of the input control module 120 is connected to the first positive phase input terminal of the multi-channel comparator module 110, the first channel negative phase output terminal of the input control module 120 is connected to the first negative phase input terminal of the multi-channel comparator module 110, the second channel positive phase output terminal of the input control module 120 is connected to the second positive phase input terminal of the multi-channel comparator module 110, the second channel negative phase output terminal of the input control module 120 is connected to the second negative phase input terminal of the multi-channel comparator module 110, the third channel positive phase output terminal of the input control module 120 is connected to the third positive phase input terminal of the multi-channel comparator module 110, and the third channel negative phase output terminal of the input control module 120 is connected to the third negative phase input terminal of the multi-channel comparator module 110.

[0050] The input control module 120 can connect the common end of the input control module 120 with the positive input end and the negative input end of the cooperative comparator CMP_co to connect the common voltage Vcom to the cooperative comparator CMP_co, connect the first positive input end of the input control module 120 with the first positive input end of the multi-channel comparator module 110, and connect the first negative input end of the input control module 120 with the first negative input end of the multi-channel comparator module 110 to connect the first channel reference voltage Vref_ch1 and the first channel feedback voltage Vfb_ch1 to the multi-channel comparator module 110.

[0051] At the same time, the second positive input terminal of the input control module 120 is connected to the second positive input terminal of the multi-channel comparator module 110, and the second inverting input terminal of the input control module 120 is connected to the second inverting input terminal of the multi-channel comparator module 110, so as to connect the second channel reference voltage Vref_ch2 and the second channel feedback voltage Vfb_ch2 to the multi-channel comparator module 110, and the third positive input terminal of the input control module 120 is connected to the third positive input terminal of the multi-channel comparator module 110, and the third inverting input terminal of the input control module 120 is connected to the third inverting input terminal of the multi-channel comparator module 110, so as to connect the third channel reference voltage Vref_ch3 and the third channel feedback voltage Vfb_ch3 to the multi-channel comparator module 110.

[0052] The input control module 120 can connect the common end of the input control module 120 with the first positive input end and the first negative input end of the multi-channel comparator module 110 to connect the common voltage Vcom to the multi-channel comparator module 110, connect the first positive input end of the input control module 120 with the positive input end of the cooperative comparator CMP_co, and connect the first negative input end of the input control module 120 with the negative input end of the cooperative comparator CMP_co to connect the first channel reference voltage Vref_ch1 and the first channel feedback voltage Vfb_ch1 to the cooperative comparator CMP_co.

[0053] At the same time, the second positive input terminal of the input control module 120 is connected to the second positive input terminal of the multi-channel comparator module 110, and the second inverting input terminal of the input control module 120 is connected to the second inverting input terminal of the multi-channel comparator module 110, so as to connect the second channel reference voltage Vref_ch2 and the second channel feedback voltage Vfb_ch2 to the multi-channel comparator module 110, and the third positive input terminal of the input control module 120 is connected to the third positive input terminal of the multi-channel comparator module 110, and the third inverting input terminal of the input control module 120 is connected to the third inverting input terminal of the multi-channel comparator module 110, so as to connect the third channel reference voltage Vref_ch3 and the third channel feedback voltage Vfb_ch3 to the multi-channel comparator module 110.

[0054] The input control module 120 can connect the common end of the input control module 120 with the second positive input end and the second negative input end of the multi-channel comparator module 110 to connect the common voltage Vcom to the multi-channel comparator module 110, connect the second positive input end of the input control module 120 with the positive input end of the cooperative comparator CMP_co, and connect the second negative input end of the input control module 120 with the negative input end of the cooperative comparator CMP_co to connect the second channel reference voltage Vref_ch2 and the second channel feedback voltage Vfb_ch2 to the cooperative comparator CMP_co.

[0055] At the same time, the first positive input terminal of the input control module 120 is connected to the first positive input terminal of the multi-channel comparator module 110, and the first inverting input terminal of the input control module 120 is connected to the first inverting input terminal of the multi-channel comparator module 110, so as to connect the first channel reference voltage Vref_ch1 and the first channel feedback voltage Vfb_ch1 to the multi-channel comparator module 110, and the third positive input terminal of the input control module 120 is connected to the third positive input terminal of the multi-channel comparator module 110, and the third inverting input terminal of the input control module 120 is connected to the third inverting input terminal of the multi-channel comparator module 110, so as to connect the third channel reference voltage Vref_ch3 and the third channel feedback voltage Vfb_ch3 to the multi-channel comparator module 110.

[0056] The input control module 120 can connect the common end of the input control module 120 with the third positive input end and the third negative input end of the multi-channel comparator module 110 to connect the common voltage Vcom to the multi-channel comparator module 110, connect the third positive input end of the input control module 120 with the positive input end of the cooperative comparator CMP_co, and connect the third negative input end of the input control module 120 with the negative input end of the cooperative comparator CMP_co to connect the third channel reference voltage Vref_ch3 and the third channel feedback voltage Vfb_ch3 to the cooperative comparator CMP_co.

[0057] At the same time, the first positive input terminal of the input control module 120 is connected to the first positive input terminal of the multi-channel comparator module 110, and the first inverting input terminal of the input control module 120 is connected to the first inverting input terminal of the multi-channel comparator module 110, so as to connect the first channel reference voltage Vref_ch1 and the first channel feedback voltage Vfb_ch1 to the multi-channel comparator module 110, and the second positive input terminal of the input control module 120 is connected to the second positive input terminal of the multi-channel comparator module 110, and the second inverting input terminal of the input control module 120 is connected to the second inverting input terminal of the multi-channel comparator module 110, so as to connect the second channel reference voltage Vref_ch2 and the second channel feedback voltage Vfb_ch2 to the multi-channel comparator module 110.

[0058] It should be noted that Figure 3 The multi-channel comparison circuit 100 is illustrated by taking N=3 as an example. In practical applications, N may also be equal to 2. Figure 4 As shown, Figure 4 This is a schematic diagram of the structure of another multi-channel comparison circuit provided in an embodiment of the present disclosure, or N can also be any integer greater than 3, and the present disclosure does not make any specific limitation on this.

[0059] For example, see Figure 3 and Figure 4 The multi-channel comparator module 110 includes N channel comparators CMP_ch, each of which includes a positive input terminal and a negative input terminal. The positive input terminal of the i-th channel comparator CMP_chi is connected to the i-th channel positive output terminal of the input control module 120, the negative input terminal of the i-th channel comparator CMP_chi is connected to the i-th channel negative output terminal of the input control module 120, and the output terminal of the i-th channel comparator CMP_chi is connected to the i-th channel input terminal of the output control module 130.

[0060] When the cooperative comparator CMP_co receives the common voltage Vcom, the i-th channel comparator CMP_chi receives the i-th channel reference voltage Vref_chi and the i-th channel feedback voltage Vfb_chi, then the cooperative comparator CMP_co is in the sampling phase, and the i-th channel comparator CMP_chi is in the comparison phase.

[0061] At this time, the collaborative comparator CMP_co can sample its own offset voltage, that is, the collaborative offset voltage Voffset_co, and the i-th channel comparator CMP_chi can compensate the i-th channel reference voltage Vref_chi according to the i-th channel offset voltage Voffset_chi, and compare the i-th channel feedback voltage Vfb_chi with the compensated i-th channel reference voltage Vref_chi to obtain the i-th channel comparison signal Scmp_chi.

[0062] When the collaborative comparator CMP_co receives the i-th channel reference voltage Vref_chi and the i-th channel feedback voltage Vfb_chi, the i-th channel comparator CMP_chi receives the common voltage Vcom, and the j-th channel comparator CMP_chj receives the j-th channel reference voltage Vref_chj and the j-th channel feedback voltage Vfb_chj, the i-th channel comparator CMP_chi is in the sampling stage, and the j-th channel comparator CMP_chj and the collaborative comparator CMP_co are in the comparison stage.

[0063] At this time, the i-th channel comparator CMP_chi can sample its own offset voltage, that is, the i-th channel offset voltage Voffset_chi, and the j-th channel comparator CMP_chj can compensate the j-th channel reference voltage Vref_chj according to the j-th channel offset voltage Voffset_chj, and compare the j-th channel feedback voltage Vfb_chj with the compensated j-th channel reference voltage Vref_chj to obtain the j-th channel comparison signal Scmp_chj. The cooperative comparator CMP_co can compensate the i-th channel reference voltage Vref_chi according to the cooperative offset voltage Voffset_co, and compare the i-th channel feedback voltage Vfb_chi with the compensated i-th channel reference voltage Vref_chi to obtain the cooperative comparison signal Scmp_co to take over the comparison work of the i-th channel comparator CMP_chi in the sampling stage.

[0064] For example, Figure 3 As shown, the multi-channel comparator module 110 includes a 1st channel comparator CMP_ch1, a 2nd channel comparator CMP_ch2 and a 3rd channel comparator CMP_ch3, wherein a positive input terminal of the 1st channel comparator CMP_ch1 is connected to a 1st channel positive output terminal of the input control module 120, an inverting input terminal of the 1st channel comparator CMP_ch1 is connected to a 1st channel inverting output terminal of the input control module 120, and an output terminal of the 1st channel comparator CMP_ch1 is connected to a 1st channel input terminal of the output control module 130.

[0065] The non-inverting input terminal of the second channel comparator CMP_ch2 is connected to the non-inverting output terminal of the second channel of the input control module 120, the inverting input terminal of the second channel comparator CMP_ch2 is connected to the inverting output terminal of the second channel of the input control module 120, and the output terminal of the second channel comparator CMP_ch2 is connected to the second channel input terminal of the output control module 130. The non-inverting input terminal of the third channel comparator CMP_ch3 is connected to the non-inverting output terminal of the third channel of the input control module 120, the inverting input terminal of the third channel comparator CMP_ch3 is connected to the inverting output terminal of the third channel of the input control module 120, and the output terminal of the third channel comparator CMP_ch3 is connected to the third channel input terminal of the output control module 130.

[0066] When the cooperative comparator CMP_co receives the common voltage Vcom, the 1st channel comparator CMP_ch1 receives the 1st channel reference voltage Vref_ch1 and the 1st channel feedback voltage Vfb_ch1, the 2nd channel comparator CMP_ch2 receives the 2nd channel reference voltage Vref_ch2 and the 2nd channel feedback voltage Vfb_ch2, ​​and the 3rd channel comparator CMP_ch3 receives the 3rd channel reference voltage Vref_ch3 and the 3rd channel feedback voltage Vfb_ch3.

[0067] The cooperative comparator CMP_co can sample the cooperative offset voltage Voffset_co, and the first channel comparator CMP_ch1 can compensate the first channel reference voltage Vref_ch1 according to the first channel offset voltage Voffset_ch1, and compare the first channel feedback voltage Vfb_ch1 with the compensated first channel reference voltage Vref_ch1 to obtain the first channel comparison signal Scmp_ch1.

[0068] The second channel comparator CMP_ch2 can compensate the second channel reference voltage Vref_ch2 according to the second channel offset voltage Voffset_ch2, ​​and compare the second channel feedback voltage Vfb_ch2 with the compensated second channel reference voltage Vref_ch2 to obtain the second channel comparison signal Scmp_ch2. The third channel comparator CMP_ch3 can compensate the third channel reference voltage Vref_ch3 according to the third channel offset voltage Voffset_ch3, and compare the third channel feedback voltage Vfb_ch3 with the compensated third channel reference voltage Vref_ch3 to obtain the third channel comparison signal Scmp_ch3.

[0069] When the cooperative comparator CMP_co receives the 1st channel reference voltage Vref_ch1 and the 1st channel feedback voltage Vfb_ch1, the 1st channel comparator CMP_ch1 receives the common voltage Vcom, the 2nd channel comparator CMP_ch2 receives the 2nd channel reference voltage Vref_ch2 and the 2nd channel feedback voltage Vfb_ch2, ​​and the 3rd channel comparator CMP_ch3 receives the 3rd channel reference voltage Vref_ch3 and the 3rd channel feedback voltage Vfb_ch3.

[0070] The 1st channel comparator CMP_ch1 can sample the 1st channel offset voltage Voffset_ch1, and the cooperative comparator CMP_co can compensate the 1st channel reference voltage Vref_ch1 according to the cooperative offset voltage Voffset_co, and compare the 1st channel feedback voltage Vfb_ch1 with the compensated 1st channel reference voltage Vref_ch1 to obtain the cooperative comparison signal Scmp_co to take over the comparison work of the 1st channel comparator CMP_ch1.

[0071] The second channel comparator CMP_ch2 can compensate the second channel reference voltage Vref_ch2 according to the second channel offset voltage Voffset_ch2, ​​and compare the second channel feedback voltage Vfb_ch2 with the compensated second channel reference voltage Vref_ch2 to obtain the second channel comparison signal Scmp_ch2. The third channel comparator CMP_ch3 can compensate the third channel reference voltage Vref_ch3 according to the third channel offset voltage Voffset_ch3, and compare the third channel feedback voltage Vfb_ch3 with the compensated third channel reference voltage Vref_ch3 to obtain the third channel comparison signal Scmp_ch3.

[0072] When the cooperative comparator CMP_co receives the 2nd channel reference voltage Vref_ch2 and the 2nd channel feedback voltage Vfb_ch2, ​​the 2nd channel comparator CMP_ch2 receives the common voltage Vcom, the 1st channel comparator CMP_ch1 receives the 1st channel reference voltage Vref_ch1 and the 1st channel feedback voltage Vfb_ch1, and the 3rd channel comparator CMP_ch3 receives the 3rd channel reference voltage Vref_ch3 and the 3rd channel feedback voltage Vfb_ch3.

[0073] The second channel comparator CMP_ch2 can sample the second channel offset voltage Voffset_ch2, ​​and the cooperative comparator CMP_co can compensate the second channel reference voltage Vref_ch2 according to the cooperative offset voltage Voffset_co, and compare the second channel feedback voltage Vfb_ch2 with the compensated second channel reference voltage Vref_ch2 to obtain the cooperative comparison signal Scmp_co to take over the comparison work of the second channel comparator CMP_ch2.

[0074] The first channel comparator CMP_ch1 can compensate the first channel reference voltage Vref_ch1 according to the first channel offset voltage Voffset_ch1, and compare the first channel feedback voltage Vfb_ch1 with the compensated first channel reference voltage Vref_ch1 to obtain the first channel comparison signal Scmp_ch1. The third channel comparator CMP_ch3 can compensate the third channel reference voltage Vref_ch3 according to the third channel offset voltage Voffset_ch3, and compare the third channel feedback voltage Vfb_ch3 with the compensated third channel reference voltage Vref_ch3 to obtain the third channel comparison signal Scmp_ch3.

[0075] When the cooperative comparator CMP_co receives the 3rd channel reference voltage Vref_ch3 and the 3rd channel feedback voltage Vfb_ch3, the 3rd channel comparator CMP_ch3 receives the common voltage Vcom, the 1st channel comparator CMP_ch1 receives the 1st channel reference voltage Vref_ch1 and the 1st channel feedback voltage Vfb_ch1, and the 2nd channel comparator CMP_ch2 receives the 2nd channel reference voltage Vref_ch2 and the 2nd channel feedback voltage Vfb_ch2.

[0076] The 3rd channel comparator CMP_ch3 can sample the 3rd channel offset voltage Voffset_ch3, and the cooperative comparator CMP_co can compensate the 3rd channel reference voltage Vref_ch3 according to the cooperative offset voltage Voffset_co, and compare the 3rd channel feedback voltage Vfb_ch3 with the compensated 3rd channel reference voltage Vref_ch3 to obtain the cooperative comparison signal Scmp_co to take over the comparison work of the 3rd channel comparator CMP_ch3.

[0077] The first channel comparator CMP_ch1 can compensate the first channel reference voltage Vref_ch1 according to the first channel offset voltage Voffset_ch1, and compare the first channel feedback voltage Vfb_ch1 with the compensated first channel reference voltage Vref_ch1 to obtain the first channel comparison signal Scmp_ch1. The second channel comparator CMP_ch2 can compensate the second channel reference voltage Vref_ch2 according to the second channel offset voltage Voffset_ch2, ​​and compare the second channel feedback voltage Vfb_ch2 with the compensated second channel reference voltage Vref_ch2 to obtain the second channel comparison signal Scmp_ch2.

[0078] In other implementations, the i-th channel comparator CMP_chi may compensate the i-th channel feedback voltage Vfb_chi according to the i-th channel offset voltage Voffset_chi, and compare the i-th channel reference voltage Vref_chi with the compensated i-th channel feedback voltage Vfb_chi to obtain the i-th channel comparison signal.

[0079] In this way, when the i-th channel comparator CMP_chi receives the common voltage Vcom, the i-th channel comparator CMP_chi can sample the i-th channel offset voltage Voffset_chi. When the i-th channel comparator CMP_chi receives the i-th channel voltage pair, the i-th channel comparator CMP_chi can compensate the i-th channel voltage pair according to the i-th channel offset voltage Voffset_chi, and compare the compensated i-th channel voltage pair to obtain the i-th channel comparison signal Scmp_chi.

[0080] When the cooperative comparator CMP_co receives the i-th channel voltage pair, the cooperative comparator CMP_co can compensate the i-th channel voltage pair according to the cooperative offset voltage Voffset_co, and compare the compensated i-th channel voltage pair to obtain a cooperative comparison signal Scmp_co to take over the comparison work of the i-th channel comparator CMP_chi.

[0081] Exemplarily, when the cooperative comparator CMP_co receives the common voltage Vcom, the output control module 130 can turn on the i-th channel input terminal of the output control module 130 and the i-th output terminal of the multi-channel comparison circuit 100 to output the i-th channel comparison signal Scmp_chi, so that N channel comparison signals Scmp_ch can be output.

[0082] When the cooperative comparator CMP_co receives the i-th channel reference voltage Vref_chi and the i-th channel feedback voltage Vfb_chi, the output control module 130 can conduct the j-th channel input terminal of the output control module 130 and the j-th output terminal of the multi-channel comparison circuit 100 to output the j-th channel comparison signal Scmp_chi, so that N-1 channel comparison signals Scmp_ch can be output. At the same time, the cooperative input terminal of the output control module 130 and the i-th output terminal of the multi-channel comparison circuit 100 are conducted to output the cooperative comparison signal Scmp_co.

[0083] For example, Figure 3As shown, the first channel input terminal of the output control module 130 is connected to the output terminal of the first channel comparator CMP_ch1, the second channel input terminal of the output control module 130 is connected to the output terminal of the second channel comparator CMP_ch2, ​​the third channel input terminal of the output control module 130 is connected to the output terminal of the third channel comparator CMP_ch3, the first output terminal of the output control module 130 is connected to the first output terminal of the multi-channel comparison circuit 100, the second output terminal of the output control module 130 is connected to the second output terminal of the multi-channel comparison circuit 100, and the third output terminal of the output control module 130 is connected to the third output terminal of the multi-channel comparison circuit 100.

[0084] When the cooperative comparator CMP_co receives the common voltage Vcom, the output control module 130 can turn on the first channel input terminal of the output control module 130 and the first output terminal of the multi-channel comparison circuit 100, the second channel input terminal of the output control module 130 and the second output terminal of the multi-channel comparison circuit 100, and the third channel input terminal of the output control module 130 and the third output terminal of the multi-channel comparison circuit 100 to output the first channel comparison signal Scmp_ch1, the second channel comparison signal Scmp_ch2, ​​and the third channel comparison signal Scmp_ch3.

[0085] When the collaborative comparator CMP_co receives the 1st channel reference voltage Vref_ch1 and the 1st channel feedback voltage Vfb_ch1, the output control module 130 can turn on the collaborative input terminal of the output control module 130 and the 1st output terminal of the multi-channel comparison circuit 100, the 2nd channel input terminal of the output control module 130 and the 2nd output terminal of the multi-channel comparison circuit 100, and the 3rd channel input terminal of the output control module 130 and the 3rd output terminal of the multi-channel comparison circuit 100 to output the collaborative comparison signal Scmp_co, the 2nd channel comparison signal Scmp_ch2 and the 3rd channel comparison signal Scmp_ch3.

[0086] When the collaborative comparator CMP_co receives the second channel reference voltage Vref_ch2 and the second channel feedback voltage Vfb_ch2, ​​the output control module 130 can turn on the collaborative input terminal of the output control module 130 and the second output terminal of the multi-channel comparison circuit 100, the first channel input terminal of the output control module 130 and the first output terminal of the multi-channel comparison circuit 100, and the third channel input terminal of the output control module 130 and the third output terminal of the multi-channel comparison circuit 100 to output the collaborative comparison signal Scmp_co, the first channel comparison signal Scmp_ch1 and the third channel comparison signal Scmp_ch3.

[0087] When the collaborative comparator CMP_co receives the 3rd channel reference voltage Vref_ch3 and the 3rd channel feedback voltage Vfb_ch3, the output control module 130 can turn on the collaborative input terminal of the output control module 130 and the 3rd output terminal of the multi-channel comparison circuit 100, the 1st channel input terminal of the output control module 130 and the 1st output terminal of the multi-channel comparison circuit 100, and the 2nd channel input terminal of the output control module 130 and the 2nd output terminal of the multi-channel comparison circuit 100 to output the collaborative comparison signal Scmp_co, the 1st channel comparison signal Scmp_ch1 and the 2nd channel comparison signal Scmp_ch2.

[0088] To sum up, a single collaborative comparator can take over the comparison work of the channel comparator in the sampling stage in the multi-channel comparator module to achieve high-precision multi-channel power supply voltage monitoring throughout the entire period, which can reduce the number of comparators, reduce circuit complexity, and thus reduce circuit area.

[0089] In some embodiments, the multi-channel comparison circuit 100 also includes a signal generating module, the signal generating module includes a collaborative control output terminal and N channel control output terminals, the input control module 120 includes a collaborative control terminal and N channel control terminals, wherein the i-th channel control output terminal of the signal generating module is connected to the i-th channel control terminal of the input control module 120, and the collaborative control output terminal of the signal generating module is connected to the collaborative control terminal of the input control module 120.

[0090] The signal generation module is configured to generate a coordinated clock signal CLK_co, and generate N channel clock signals CLK_ch according to the coordinated clock signal CLK_co. The input control module 120 is further configured to connect the common voltage Vcom to the coordinated comparator CMP_co and the N channel voltage pairs to the multi-channel comparator module 110 according to the coordinated clock signal CLK_co and the N channel clock signals CLK_ch; or connect one channel voltage pair to the coordinated comparator CMP_co, and connect the common voltage Vcom and the N-1 channel voltage pairs to the multi-channel comparator module 110.

[0091] For example, Figure 5 A schematic diagram of a cooperative clock signal and a channel clock signal provided in an embodiment of the present disclosure, such as Figure 5 As shown, the signal generation module first generates the coordinated clock signal CLK_co, and then at the falling edge of the first cycle of the coordinated clock signal CLK_co, the first channel clock signal CLK_ch1 is pulled high and maintained for a period of t before being pulled low, where t is half of the cycle of the coordinated clock signal CLK_co.

[0092] Continue to see Figure 5Then, at the falling edge of the second cycle of the collaborative clock signal CLK_co, the second channel clock signal CLK_ch2 is pulled high and maintained for a period of t before being pulled low. At the falling edge of the third cycle of the collaborative clock signal CLK_co, the third channel clock signal CLK_ch3 is pulled high and maintained for a period of t before being pulled low.

[0093] In this way, at the falling edge in the N+1th cycle, the 1st channel clock signal CLK_ch1 is pulled high again and maintained for a period of time t before being pulled low. For example, when N=3, the generated coordinated clock signal CLK_co, the 1st channel clock signal CLK_ch1, the 2nd channel clock signal CLK_ch2 and the 3rd channel clock signal CLK_ch3 are as follows: Figure 5 shown.

[0094] For example, Figure 6 A circuit diagram of a multi-channel comparison circuit provided by an embodiment of the present disclosure, combined with Figure 3 and Figure 6 As shown, the input control module 120 includes a collaborative input control unit 121 and N channel input control units 122, wherein the i-th positive input terminal of the collaborative input control unit 121 is connected to the i-th channel reference voltage Vref_chi, the i-th inverting input terminal of the collaborative input control unit 121 is connected to the i-th channel feedback voltage Vfb_chi, the positive output terminal of the collaborative input control unit 121 is connected to the positive input terminal of the collaborative comparator CMP_co, the inverting output terminal of the collaborative input control unit 121 is connected to the inverting input terminal of the collaborative comparator CMP_co, the common terminal of the collaborative input control unit 121 is connected to the common voltage Vcom, the i-th channel control terminal of the collaborative input control unit 121 is connected to the i-th channel control output terminal of the signal generating module, and the collaborative control terminal of the collaborative input control unit 121 is connected to the collaborative control output terminal of the signal generating module.

[0095] The collaborative input control unit 121 is controlled by the 1st channel clock signal CLK_ch1 to the Nth channel clock signal CLK_chN and the collaborative clock signal CLK_co. When the collaborative clock signal CLK_co is a high-level signal, the N channel clock signals CLK_ch are all low-level signals. The collaborative input control unit 121 can connect the common voltage Vcom to the collaborative comparator CMP_co to enable the collaborative comparator CMP_co to enter the sampling stage.

[0096] When the collaborative clock signal CLK_co is a low-level signal and the i-th channel clock signals CLK_chi are all high-level signals, all j-th channel clock signals CLK_chi are low-level signals, and the collaborative input control unit 121 can connect the i-th channel reference voltage Vref_chi and the i-th channel feedback voltage Vfb_chi to the collaborative comparator CMP_co, so that the collaborative comparator CMP_co enters the comparison stage and takes over the comparison work of the i-th channel comparator CMP_chi.

[0097] In this way, the collaborative input control unit 121 can connect the common voltage Vcom to the collaborative comparator CMP_co according to the collaborative clock signal CLK_co and the N channel clock signals CLK_ch, so that the collaborative comparator CMP_co enters the sampling stage; or connect the i-th channel reference voltage Vref_chi and the i-th channel feedback voltage Vfb_chi to the collaborative comparator CMP_co, so that the collaborative comparator CMP_co enters the comparison stage and takes over the comparison work of the i-th channel comparator CMP_chi.

[0098] The positive input terminal of the i-th channel input control unit 122 is connected to the i-th channel reference voltage Vref_chi, the inverting input terminal of the i-th channel input control unit 122 is connected to the i-th channel feedback voltage Vfb_chi, the positive output terminal of the i-th channel input control unit 122 is connected to the positive input terminal of the i-th channel comparator CMP_chi, the inverting output terminal of the i-th channel input control unit 122 is connected to the inverting input terminal of the i-th channel comparator CMP_chi, the common terminal of the i-th channel input control unit 122 is connected to the common voltage Vcom, and the control terminal of the i-channel input control unit 122 is connected to the i-th channel control output terminal of the signal generating module.

[0099] The i-th channel input control unit 122 is controlled by the i-th channel clock signal CLK_chi. When the i-th channel clock signal CLK_chi is a high level signal, the i-th channel input control unit 122 can connect the common voltage Vcom to the i-th channel comparator CMP_chi to make the i-th channel comparator CMP_chi enter the sampling phase.

[0100] When the i-th channel clock signal CLK_chi is a low level signal, the i-th channel input control unit 122 may connect the i-th channel reference voltage and the i-th channel feedback voltage to the i-th channel comparator CMP_chi, so that the i-th channel comparator CMP_chi enters the comparison stage.

[0101] In this way, the i-th channel input control unit 122 can connect the common voltage Vcom to the i-th channel comparator CMP_chi according to the i-th channel clock signal CLK_chi, so that the i-th channel comparator CMP_chi enters the sampling stage; or connect the i-th channel reference voltage Vref_chi and the i-th channel feedback voltage Vfb_chi to the i-th channel comparator CMP_chi, so that the i-th channel comparator CMP_chi enters the comparison stage.

[0102] In some embodiments, see Figure 6 The cooperative input control unit 121 includes a cooperative positive phase common switch Kp_co+, a cooperative negative phase common switch Kp_co-, N cooperative positive phase input switches K_co+ and N cooperative negative phase input switches K_co-.

[0103] Among them, the first end of the coordinated positive phase common switch Kp_co+ and the first end of the coordinated negative phase common switch Kp_co- are connected to the common voltage Vcom, the second end of the coordinated positive phase common switch Kp_co+ is connected to the positive phase input end of the coordinated comparator CMP_co, the second end of the coordinated negative phase common switch Kp_co- is connected to the negative phase input end of the coordinated comparator CMP_co, and the control end of the coordinated positive phase common switch Kp_co+ and the control end of the coordinated negative phase common switch Kp_co- are connected to the coordinated control output end of the signal generation module.

[0104] The first end of the i-th collaborative positive phase input switch K_coi+ is connected to the i-th channel reference voltage Vref_chi, the second end of the i-th collaborative positive phase input switch K_coi+ is connected to the positive phase input end of the collaborative comparator CMP_co, the first end of the i-th collaborative negative phase input switch K_coi- is connected to the i-th channel feedback voltage Vfb_chi, the second end of the i-th collaborative negative phase input switch K_coi- is connected to the negative phase input end of the collaborative comparator CMP_co, and the control end of the i-th collaborative positive phase input switch K_coi+ and the control end of the i-th collaborative negative phase input switch K_coi- are connected to the i-th channel control output end of the signal generation module.

[0105] The i-th collaborative positive phase input switch K_coi+ and the i-th collaborative negative phase input switch K_coi- are both controlled by the i-th channel clock signal CLK_chi, and the collaborative positive phase common switch Kp_co+ and the collaborative negative phase common switch Kp_co- are both controlled by the collaborative clock signal CLK_co. When the collaborative clock signal CLK_co is a low-level signal, the i-th channel clock signal CLK_chi is a high-level signal, the i-th collaborative positive phase input switch K_coi+ and the i-th collaborative negative phase input switch K_coi- are both turned on, and the collaborative positive phase common switch Kp_co+ and the collaborative negative phase common switch Kp_co- are both turned off to connect to the i-th channel feedback voltage Vfb_chi and the i-th channel reference voltage Vref_chi.

[0106] When the i-th channel clock signal CLK_chi is a low level signal, the collaborative clock signal CLK_co is a high level signal, the i-th collaborative positive phase input switch K_coi+ and the i-th collaborative negative phase input switch K_coi- are both turned off, and the collaborative positive phase common switch Kp_co+ and the collaborative negative phase common switch Kp_co- are both turned on to access the common voltage Vcom.

[0107] For example, when N=3, Figure 6 As shown, the first end of the 1st collaborative positive phase input switch K_co1+ is connected to the 1st channel reference voltage Vref_ch1, the second end of the 1st collaborative positive phase input switch K_co1+ is connected to the positive phase input end of the collaborative comparator CMP_co, the first end of the 1st collaborative negative phase input switch K_co1- is connected to the 1st channel feedback voltage Vfb_ch1, the second end of the 1st collaborative negative phase input switch K_co1- is connected to the negative phase input end of the collaborative comparator CMP_co, and the control end of the 1st collaborative positive phase input switch K_co1+ and the control end of the 1st collaborative negative phase input switch K_co1- are connected to the 1st channel control output end of the signal generating module.

[0108] The first collaborative positive phase input switch K_co1+ and the first collaborative negative phase input switch K_co1- are both controlled by the first channel clock signal CLK_ch1. When the first channel clock signal CLK_ch1 is a high level signal, the first collaborative positive phase input switch K_co1+ and the first collaborative negative phase input switch K_co1- are both turned on to connect to the first channel feedback voltage Vfb_ch1 and the first channel reference voltage Vref_ch1.

[0109] The first end of the second collaborative positive phase input switch K_co2+ is connected to the second channel reference voltage Vref_ch2, ​​the second end of the second collaborative positive phase input switch K_co2+ is connected to the positive phase input terminal of the collaborative comparator CMP_co, the first end of the second collaborative negative phase input switch K_co2- is connected to the second channel feedback voltage Vfb_ch2, ​​the second end of the second collaborative negative phase input switch K_co2- is connected to the negative phase input terminal of the collaborative comparator CMP_co, and the control end of the second collaborative positive phase input switch K_co2+ and the control end of the second collaborative negative phase input switch K_co2- are connected to the second channel control output terminal of the signal generating module.

[0110] The second collaborative positive phase input switch K_co2+ and the second collaborative negative phase input switch K_co2- are both controlled by the second channel clock signal CLK_ch2. When the second channel clock signal CLK_ch2 is a high level signal, the second collaborative positive phase input switch K_co2+ and the second collaborative negative phase input switch K_co2- are both turned on to connect to the second channel feedback voltage Vfb_ch2 and the second channel reference voltage Vref_ch2.

[0111] The first end of the 3rd collaborative positive phase input switch K_co3+ is connected to the 3rd channel reference voltage Vref_ch3, the second end of the 3rd collaborative positive phase input switch K_co3+ is connected to the positive phase input end of the collaborative comparator CMP_co, the first end of the 3rd collaborative negative phase input switch K_co3- is connected to the 3rd channel feedback voltage Vfb_ch3, the second end of the 3rd collaborative negative phase input switch K_co3- is connected to the negative phase input end of the collaborative comparator CMP_co, and the control end of the 3rd collaborative positive phase input switch K_co3+ and the control end of the 3rd collaborative negative phase input switch K_co3- are connected to the 3rd channel control output end of the signal generating module.

[0112] The 3rd collaborative positive phase input switch K_co3+ and the 3rd collaborative negative phase input switch K_co3- are both controlled by the 3rd channel clock signal CLK_ch3. When the 3rd channel clock signal CLK_ch3 is a high level signal, the 3rd collaborative positive phase input switch K_co3+ and the 3rd collaborative negative phase input switch K_co3- are both turned on to connect to the 3rd channel feedback voltage Vfb_ch3 and the 3rd channel reference voltage Vref_ch3.

[0113] It should be noted that Figure 6 The multi-channel comparison circuit 100 is illustrated by taking N=3 as an example. In practical applications, N may also be equal to 2. Figure 7 As shown, Figure 7 This is a circuit diagram of another multi-channel comparison circuit provided in an embodiment of the present disclosure, or N can also be any integer greater than 3, and the present disclosure does not make any specific limitation on this.

[0114] For example, see Figure 6 and Figure 7 The i-th channel input control unit 122 includes an i-th channel positive phase input switch K_chi+, an i-th channel negative phase input switch K_chi-, an i-th channel positive phase common switch Kp_chi+ and an i-th channel negative phase common switch Kp_chi-.

[0115] Among them, the first end of the i-th channel positive phase common switch Kp_chi+ and the first end of the i-th channel negative phase common switch Kp_chi- are connected to the common voltage Vcom, the second end of the i-th channel positive phase common switch Kp_chi+ is connected to the positive phase input end of the i-th channel comparator CMP_chi, the second end of the i-th channel negative phase common switch Kp_chi- is connected to the negative phase input end of the i-th channel comparator CMP_chi, and the control end of the i-th channel positive phase common switch Kp_chi+ and the control end of the i-channel negative phase common switch Kp_chi- are connected to the i-th channel control output end of the signal generating module.

[0116] A first end of the i-th channel positive phase input switch K_chi+ is connected to the i-th channel reference voltage Vref_chi, a second end of the i-th channel positive phase input switch K_chi+ is connected to the positive phase input end of the i-th channel comparator CMP_chi, a first end of the i-th channel negative phase input switch K_chi- is connected to the i-th channel feedback voltage Vfb_chi, a second end of the i-channel negative phase input switch K_chi- is connected to the negative phase input end of the i-channel comparator CMP_chi, and a control end of the i-channel positive phase input switch K_chi+ and a control end of the i-channel negative phase input switch K_chi- are connected to the negative phase signal of the i-channel clock signal CLK_chi.

[0117] The i-th channel positive phase input switch K_chi+ and the i-th channel negative phase input switch K_chi- are both controlled by the negative phase signal of the i-th channel clock signal CLK_chi, the i-th channel positive phase common switch Kp_chi+ and the i-th channel negative phase common switch Kp_chi- are both controlled by the i-th channel clock signal CLK_chi, when the i-th channel clock signal CLK_chi is a high level signal, the i-th channel positive phase input switch K_chi+ and the i-th channel negative phase input switch K_chi- are both turned off, and the i-th channel positive phase common switch Kp_chi+ and the i-th channel negative phase common switch Kp_chi- are both turned on to access the common voltage Vcom.

[0118] When the i-th channel clock signal CLK_chi is a low level signal, the i-th channel positive phase common switch Kp_chi+ and the i-th channel negative phase common switch Kp_chi- are both turned off, and the i-th channel positive phase input switch K_chi+ and the i-th channel negative phase input switch K_chi- are both turned on to connect to the i-th channel feedback voltage Vfb_chi and the i-th channel reference voltage Vref_chi.

[0119] For example, Figure 6 As shown, a first end of the 1st channel positive phase common switch Kp_ch1+ and a first end of the 1st channel negative phase common switch Kp_ch1- are connected to the common voltage Vcom, a second end of the 1st channel positive phase common switch Kp_ch1+ is connected to the positive phase input end of the 1st channel comparator CMP_ch1, a second end of the 1st channel negative phase common switch Kp_ch1- is connected to the negative phase input end of the 1st channel comparator CMP_ch1, and a control end of the 1st channel positive phase common switch Kp_ch1+ and a control end of the 1st channel negative phase common switch Kp_ch1- are connected to the 1st channel control output end of the signal generating module.

[0120] The first channel positive phase common switch Kp_ch1+ and the first channel negative phase common switch Kp_ch1- are both controlled by the first channel clock signal CLK_ch1. When the first channel clock signal CLK_ch1 is a high level signal, the first channel positive phase common switch Kp_ch1+ and the first channel negative phase common switch Kp_ch1- are both turned on. When the first channel clock signal CLK_ch1 is a low level signal, the first channel positive phase common switch Kp_ch1+ and the first channel negative phase common switch Kp_ch1- are both turned off.

[0121] A first end of the second channel positive phase common switch Kp_ch2+ and a first end of the second channel negative phase common switch Kp_ch2- are connected to the common voltage Vcom, a second end of the second channel positive phase common switch Kp_ch2+ is connected to the positive phase input end of the second channel comparator CMP_ch2, ​​a second end of the second channel negative phase common switch Kp_ch2- is connected to the negative phase input end of the second channel comparator CMP_ch2, ​​and a control end of the second channel positive phase common switch Kp_ch2+ and a control end of the second channel negative phase common switch Kp_ch2- are connected to the second channel control output end of the signal generating module.

[0122] The second channel positive phase common switch Kp_ch2+ and the second channel negative phase common switch Kp_ch2- are both controlled by the second channel clock signal CLK_ch2. When the second channel clock signal CLK_ch2 is a high level signal, the second channel positive phase common switch Kp_ch2+ and the second channel negative phase common switch Kp_ch2- are both turned on. When the second channel clock signal CLK_ch2 is a low level signal, the second channel positive phase common switch Kp_ch2+ and the second channel negative phase common switch Kp_ch2- are both turned off.

[0123] A first end of the 3rd channel positive phase common switch Kp_ch3+ and a first end of the 3rd channel negative phase common switch Kp_ch3- are connected to the common voltage Vcom, a second end of the 3rd channel positive phase common switch Kp_ch3+ is connected to the positive phase input end of the 3rd channel comparator CMP_ch3, a second end of the 3rd channel negative phase common switch Kp_ch3- is connected to the negative phase input end of the 3rd channel comparator CMP_ch3, and a control end of the 3rd channel positive phase common switch Kp_ch3+ and a control end of the 3rd channel negative phase common switch Kp_ch3- are connected to the 3rd channel control output end of the signal generating module.

[0124] The third channel positive phase common switch Kp_ch3+ and the third channel negative phase common switch Kp_ch3- are both controlled by the third channel clock signal CLK_ch3. When the third channel clock signal CLK_ch3 is a high level signal, the third channel positive phase common switch Kp_ch3+ and the third channel negative phase common switch Kp_ch3- are both turned on. When the third channel clock signal CLK_ch3 is a low level signal, the third channel positive phase common switch Kp_ch3+ and the third channel negative phase common switch Kp_ch3- are both turned off.

[0125] A first end of the 1st channel positive phase input switch K_ch1+ is connected to the 1st channel reference voltage Vref_ch1, a second end of the 1st channel positive phase input switch K_ch1+ is connected to the positive phase input end of the 1st channel comparator CMP_ch1, a first end of the 1st channel negative phase input switch K_ch1- is connected to the 1st channel feedback voltage Vfb_ch1, a second end of the 1st channel negative phase input switch K_ch1- is connected to the negative phase input end of the 1st channel comparator CMP_ch1, and a control end of the 1st channel positive phase input switch K_ch1+ and a control end of the 1st channel negative phase input switch K_ch1- are connected to the negative phase signal of the 1st channel clock signal CLK_ch1.

[0126] The 1st channel positive phase input switch K_ch1+ and the 1st channel negative phase input switch K_ch1- are both controlled by the negative phase signal of the 1st channel clock signal CLK_ch1. When the 1st channel clock signal CLK_ch1 is a high level signal, the 1st channel positive phase input switch K_ch1+ and the 1st channel negative phase input switch K_ch1- are both turned off. When the 1st channel clock signal CLK_ch1 is a low level signal, the 1st channel positive phase input switch K_ch1+ and the 1st channel negative phase input switch K_ch1- are both turned on.

[0127] A first end of the second channel positive phase input switch K_ch2+ is connected to the second channel reference voltage Vref_ch2, ​​a second end of the second channel positive phase input switch K_ch2+ is connected to the positive phase input terminal of the second channel comparator CMP_ch2, ​​a first end of the second channel negative phase input switch K_ch2- is connected to the second channel feedback voltage Vfb_ch2, ​​a second end of the second channel negative phase input switch K_ch2- is connected to the negative phase input terminal of the second channel comparator CMP_ch2, ​​and a control end of the second channel positive phase input switch K_ch2+ and a control end of the second channel negative phase input switch K_ch2- are connected to the negative phase signal of the second channel clock signal CLK_ch2.

[0128] The second channel positive phase input switch K_ch2+ and the second channel negative phase input switch K_ch2- are both controlled by the negative phase signal of the second channel clock signal CLK_ch2. When the second channel clock signal CLK_ch2 is a high level signal, the second channel positive phase input switch K_ch2+ and the second channel negative phase input switch K_ch2- are both turned off. When the second channel clock signal CLK_ch2 is a low level signal, the second channel positive phase input switch K_ch2+ and the second channel negative phase input switch K_ch2- are both turned on.

[0129] A first end of the 3rd channel positive phase input switch K_ch3+ is connected to the 3rd channel reference voltage Vref_ch3, a second end of the 3rd channel positive phase input switch K_ch3+ is connected to the positive phase input end of the 3rd channel comparator CMP_ch3, a first end of the 3rd channel negative phase input switch K_ch3- is connected to the 3rd channel feedback voltage Vfb_ch3, a second end of the 3rd channel negative phase input switch K_ch3- is connected to the negative phase input end of the 3rd channel comparator CMP_ch3, and a control end of the 3rd channel positive phase input switch K_ch3+ and a control end of the 3rd channel negative phase input switch K_ch3- are connected to the negative phase signal of the 3rd channel clock signal CLK_ch3.

[0130] The 3rd channel positive phase input switch K_ch3+ and the 3rd channel negative phase input switch K_ch3- are both controlled by the negative phase signal of the 3rd channel clock signal CLK_ch3. When the 3rd channel clock signal CLK_ch3 is a high level signal, the 3rd channel positive phase input switch K_ch3+ and the 3rd channel negative phase input switch K_ch3- are both turned off. When the 3rd channel clock signal CLK_ch3 is a low level signal, the 3rd channel positive phase input switch K_ch3+ and the 3rd channel negative phase input switch K_ch3- are both turned on.

[0131] In some embodiments, in combination Figure 3 , Figure 4 , Figure 6 and Figure 7 As shown, the output control module 130 includes N control terminals, and the i-th control terminal of the output control module 130 is connected to the i-th channel control output terminal of the signal generation module. The output control module 130 is further configured to output N channel comparison signals Scmp_ch according to the N channel clock signals CLK_ch; or output the coordinated comparison signal Scmp_co and N-1 channel comparison signals Scmp_ch.

[0132] Exemplary, combined Figure 3 , Figure 4 , Figure 6 and Figure 7 As shown, the output control module 130 includes a collaborative output control unit 131 and N channel output control units 132, the input end of the collaborative output control unit 131 is connected to the output end of the collaborative comparator CMP_co, the i-th output end of the collaborative output control unit 131 is connected to the i-th output end of the multi-channel comparison circuit 100, and the i-th control end of the collaborative output control unit 131 is connected to the i-th channel control output end of the signal generation module.

[0133] The coordinated output control unit 131 is controlled by the 1st channel clock signal CLK_ch1 to the Nth channel clock signal CLK_chN. When the i-th channel clock signal CLK_chi is a high-level signal, the coordinated output control unit 131 can conduct the output end of the coordinated comparator CMP_co and the i-th output end of the multi-channel comparison circuit 100 to output the coordinated comparison signal Scmp_co. When the N channel clock signals CLK_ch are all low-level signals, the coordinated output control unit 131 can disconnect the output end of the coordinated comparator CMP_co and the i-th output end of the multi-channel comparison circuit 100 to not output the coordinated comparison signal Scmp_co.

[0134] The input end of the i-th channel output control unit 132 is connected to the output end of the i-th channel comparator CMP_chi, the output end of the i-th channel output control unit 132 is connected to the i-th output end of the multi-channel comparison circuit 100, and the control end of the i-th channel output control unit 132 is connected to the i-th channel control output end of the signal generating module.

[0135] The i-th channel output control unit 132 is controlled by the i-th channel clock signal CLK_chi. When the i-th channel clock signal CLK_chi is a low-level signal, the i-th channel output control unit 132 can conduct the output end of the i-th channel comparator CMP_chi and the i-th output end of the multi-channel comparison circuit 100 to output the i-th channel comparison signal Scmp_chi. When the i-th channel clock signal CLK_chi is a high-level signal, the i-th channel output control unit 132 can disconnect the connection between the output end of the i-th channel comparator CMP_chi and the i-th output end of the multi-channel comparison circuit 100 to not output the i-th channel comparison signal Scmp_chi.

[0136] In some embodiments, see Figure 6 and Figure 7 The collaborative output control unit 131 includes N collaborative output switches K'_co, wherein the first end of the i-th collaborative output switch K'_coi is connected to the output end of the collaborative comparator CMP_co, the second end of the i-th collaborative output switch K'_coi is connected to the i-th output end of the multi-channel comparison circuit 100, and the control end of the i-th collaborative output switch K'_coi is connected to the i-th channel control output end of the signal generation module.

[0137] The i-th collaborative output switch K'_coi is controlled by the i-th channel clock signal CLK_chi. When the i-th channel clock signal CLK_chi is a high-level signal, the i-th collaborative output switch K'_coi is turned on to output the collaborative comparison signal Scmp_co through the i-th output terminal of the multi-channel comparison circuit 100. When the i-th channel clock signal CLK_chi is a low-level signal, the i-th collaborative output switch K'_coi is turned off.

[0138] For example, Figure 6As shown, the first end of the first coordinated output switch K'_co1 is connected to the output end of the coordinated comparator CMP_co, the second end of the first coordinated output switch K'_co1 is connected to the first output end of the multi-channel comparison circuit 100, and the control end of the first coordinated output switch K'_co1 is connected to the first channel control output end of the signal generation module. The first coordinated output switch K'_co1 is controlled by the first channel clock signal CLK_ch1. When the first channel clock signal CLK_ch1 is a high-level signal, the first coordinated output switch K'_co1 is turned on to output the coordinated comparison signal Scmp_co through the first output end of the multi-channel comparison circuit 100. When the first channel clock signal CLK_ch1 is a low-level signal, the first coordinated output switch K'_co1 is turned off.

[0139] The first end of the second coordinated output switch K'_co2 is connected to the output end of the coordinated comparator CMP_co, the second end of the second coordinated output switch K'_co2 is connected to the second output end of the multi-channel comparison circuit 100, and the control end of the second coordinated output switch K'_co2 is connected to the second channel control output end of the signal generation module. The second coordinated output switch K'_co2 is controlled by the second channel clock signal CLK_ch2. When the second channel clock signal CLK_ch2 is a high-level signal, the second coordinated output switch K'_co2 is turned on to output the coordinated comparison signal Scmp_co through the second output end of the multi-channel comparison circuit 100. When the second channel clock signal CLK_ch2 is a low-level signal, the second coordinated output switch K'_co2 is turned off.

[0140] The first end of the third coordinated output switch K'_co3 is connected to the output end of the coordinated comparator CMP_co, the second end of the third coordinated output switch K'_co3 is connected to the third output end of the multi-channel comparison circuit 100, and the control end of the third coordinated output switch K'_co3 is connected to the third channel control output end of the signal generation module. The third coordinated output switch K'_co3 is controlled by the third channel clock signal CLK_ch3. When the third channel clock signal CLK_ch3 is a high level signal, the third coordinated output switch K'_co3 is turned on to output the coordinated comparison signal Scmp_co through the third output end of the multi-channel comparison circuit 100. When the third channel clock signal CLK_ch3 is a low level signal, the third coordinated output switch K'_co3 is turned off.

[0141] Continue to see Figure 6 and Figure 7The i-th channel output control unit 132 includes an i-th channel output switch K'_chi, a first end of the i-th channel output switch K'_chi is connected to the output end of the i-th channel comparator CMP_chi, a second end of the i-th channel output switch K'_chi is connected to the i-th output end of the multi-channel comparison circuit 100, and a control end of the i-channel output switch K'_chi is connected to the inverted signal of the i-th channel clock signal CLK_chi.

[0142] The i-th channel output switch K'_chi is controlled by the inverted signal of the i-th channel clock signal CLK_chi. When the i-th channel clock signal CLK_chi is a high-level signal, the i-th channel output switch K'_chi is turned off to not output the i-th channel comparison signal Scmp_chi. When the i-th channel clock signal CLK_chi is a low-level signal, the i-th channel output switch K'_chi is turned on to output the i-th channel comparison signal Scmp_chi.

[0143] For example, Figure 6 As shown, the first end of the first channel output switch K'_ch1 is connected to the output end of the first channel comparator CMP_ch1, the second end of the first channel output switch K'_ch1 is connected to the first output end of the multi-channel comparison circuit 100, and the control end of the first channel output switch K'_ch1 is connected to the inverted signal of the first channel clock signal CLK_ch1. The first channel output switch K'_ch1 is controlled by the inverted signal of the first channel clock signal CLK_ch1. When the first channel clock signal CLK_ch1 is a high level signal, the first channel output switch K'_ch1 is turned off. When the first channel clock signal CLK_ch1 is a low level signal, the first channel output switch K'_ch1 is turned on to output the first channel comparison signal Scmp_ch1 through the first output end of the multi-channel comparison circuit 100.

[0144] The first end of the second channel output switch K'_ch2 is connected to the output end of the second channel comparator CMP_ch2, ​​the second end of the second channel output switch K'_ch2 is connected to the second output end of the multi-channel comparison circuit 100, and the control end of the second channel output switch K'_ch2 is connected to the inverted signal of the second channel clock signal CLK_ch2. The second channel output switch K'_ch2 is controlled by the inverted signal of the second channel clock signal CLK_ch2. When the second channel clock signal CLK_ch2 is a high level signal, the second channel output switch K'_ch2 is turned off, and when the second channel clock signal CLK_ch2 is a low level signal, the second channel output switch K'_ch2 is turned on to output the second channel comparison signal Scmp_ch2 through the second output end of the multi-channel comparison circuit 100.

[0145] The first end of the third channel output switch K'_ch3 is connected to the output end of the third channel comparator CMP_ch3, the second end of the third channel output switch K'_ch3 is connected to the third output end of the multi-channel comparison circuit 100, and the control end of the third channel output switch K'_ch3 is connected to the inverted signal of the third channel clock signal CLK_ch3. The third channel output switch K'_ch3 is controlled by the inverted signal of the third channel clock signal CLK_ch3. When the third channel clock signal CLK_ch3 is a high level signal, the third channel output switch K'_ch3 is turned off, and when the third channel clock signal CLK_ch3 is a low level signal, the third channel output switch K'_ch3 is turned on to output the third channel comparison signal Scmp_ch3 through the third output end of the multi-channel comparison circuit 100.

[0146] An embodiment of the present disclosure further provides a power management chip, comprising the multi-channel comparison circuit 100 provided in any of the above embodiments.

[0147] The power management chip provided in the embodiments of the present disclosure includes the multi-channel comparison circuit 100 provided in any of the above embodiments, and has the same functional modules and beneficial effects as the multi-channel comparison circuit 100, which will not be described in detail here.

[0148] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural form and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive, unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, the "example" is merely illustrative and should not be considered exclusive or comprehensive.

[0149] Several embodiments of the present disclosure are described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the attached claims.

Claims

1. A multi-channel comparison circuit, characterized in that: include: Input control module, output control module, single cooperative comparator and multi-channel comparator module; The input control module is configured to receive a common voltage and N channel voltage pairs, and connect the common voltage and the N channel voltage pairs to the cooperative comparator and the multi-channel comparator module, where N is an integer greater than or equal to 2; The multi-channel comparator module includes N channel comparators; When the common voltage is connected to the cooperative comparator, the i-th channel voltage pair is connected to the i-th channel comparator, 1≤i≤N, i is an integer, and the cooperative comparator is configured to sample the cooperative offset voltage; The i-th channel comparator is configured to compensate the i-th channel voltage pair according to the i-th channel offset voltage, and compare the compensated i-th channel voltage pair to obtain an i-th channel comparison signal; The output control module is configured to output N channel comparison signals; When the i-th channel voltage pair is connected to the cooperative comparator, the common voltage is connected to the i-th channel comparator, the j-th channel voltage pair is connected to the j-th channel comparator, 1≤j≤N, i≠j and j is an integer, the i-th channel comparator is configured to sample the i-th channel offset voltage, the j-th channel comparator is configured to compensate the j-th channel voltage pair according to the j-th channel offset voltage, and compare the compensated j-th channel voltage pair to obtain the j-th channel comparison signal; the cooperative comparator is configured to compensate the i-th channel voltage pair according to the cooperative offset voltage, and compare the compensated i-th channel voltage pair to take over the comparison work of the i-channel comparator to obtain the cooperative comparison signal; the output control module is configured to output the cooperative comparison signal and N-1 channel comparison signals.

2. The multi-channel comparison circuit according to claim 1, characterized in that: The input control module includes N channel positive phase output terminals and N channel negative phase output terminals, and the output control module includes N channel input terminals; The positive input of the i-th channel comparator is connected to the i-th channel positive output of the input control module, the negative input of the i-th channel comparator is connected to the i-th channel negative output of the input control module, and the output of the i-th channel comparator is connected to the i-th channel input of the output control module.

3. The multi-channel comparison circuit according to claim 2, characterized in that: The multi-channel comparison circuit further includes a signal generation module, the signal generation module includes a coordinated control output terminal and N channel control output terminals, and the input control module further includes a coordinated control terminal and N channel control terminals; The i-th channel control output terminal of the signal generation module is connected to the i-th channel control terminal of the input control module, and the cooperative control output terminal of the signal generation module is connected to the cooperative control terminal of the input control module; The signal generating module is configured to generate a coordinated clock signal, and generate N channel clock signals according to the coordinated clock signal; The input control module is further configured to connect the common voltage to the cooperative comparator and the N channel voltage pairs to the multi-channel comparator module according to the cooperative clock signal and the N channel clock signals; Alternatively, one of the channel voltage pairs is connected to the cooperative comparator, and the common voltage and N-1 channel voltage pairs are connected to the multi-channel comparator module.

4. The multi-channel comparison circuit according to claim 3, characterized in that: The input control module includes a collaborative input control unit and N channel input control units; The i-th positive input terminal of the collaborative input control unit is connected to the i-th channel reference voltage, the i-th inverting input terminal of the collaborative input control unit is connected to the i-th channel feedback voltage, the positive output terminal of the collaborative input control unit is connected to the positive input terminal of the collaborative comparator, the inverting output terminal of the collaborative input control unit is connected to the inverting input terminal of the collaborative comparator, the common terminal of the collaborative input control unit is connected to the common voltage, the i-th channel control terminal of the collaborative input control unit is connected to the i-th channel control output terminal of the signal generating module, and the collaborative control terminal of the collaborative input control unit is connected to the collaborative control output terminal of the signal generating module; The positive phase input terminal of the i-th channel input control unit is connected to the i-th channel reference voltage, the negative phase input terminal of the i-th channel input control unit is connected to the i-th channel feedback voltage, the positive phase output terminal of the i-th channel input control unit is connected to the positive phase input terminal of the i-th channel comparator, the negative phase output terminal of the i-th channel input control unit is connected to the negative phase input terminal of the i-th channel comparator, the common terminal of the i-th channel input control unit is connected to the common voltage, and the control terminal of the i-th channel input control unit is connected to the i-th channel control output terminal of the signal generating module; The i-th channel input control unit is configured to connect the common voltage to the i-th channel comparator according to the i-th channel clock signal; Alternatively, the i-th channel reference voltage and the i-th channel feedback voltage are connected to the i-th channel comparator; The cooperative input control unit is configured to connect the common voltage to the cooperative comparator according to the cooperative clock signal and the N channel clock signals; or connect the i-th channel reference voltage and the i-th channel feedback voltage to the cooperative comparator.

5. The multi-channel comparison circuit according to claim 4, characterized in that: The coordinated input control unit includes a coordinated positive-phase common switch, a coordinated negative-phase common switch, N coordinated positive-phase input switches, and N coordinated negative-phase input switches; A first end of the i-th cooperative positive phase input switch is connected to the i-th channel reference voltage, a second end of the i-th cooperative positive phase input switch is connected to the positive phase input end of the cooperative comparator, a first end of the i-th cooperative negative phase input switch is connected to the i-th channel feedback voltage, a second end of the i-th cooperative negative phase input switch is connected to the negative phase input end of the cooperative comparator, and a control end of the i-th cooperative positive phase input switch and a control end of the i-th cooperative negative phase input switch are connected to the i-th channel control output end of the signal generating module; The first end of the collaborative positive common switch and the first end of the collaborative negative common switch are connected to the common voltage, the second end of the collaborative positive common switch is connected to the positive input end of the collaborative comparator, the second end of the collaborative negative common switch is connected to the negative input end of the collaborative comparator, and the control end of the collaborative positive common switch and the control end of the collaborative negative common switch are connected to the collaborative control output end of the signal generating module.

6. The multi-channel comparison circuit according to claim 4, characterized in that: The i-th channel input control unit includes an i-th channel positive phase input switch, an i-th channel negative phase input switch, an i-th channel positive phase common switch, and an i-th channel negative phase common switch; A first end of the i-th channel positive phase input switch is connected to the i-th channel reference voltage, a second end of the i-th channel positive phase input switch is connected to the positive phase input end of the i-th channel comparator, a first end of the i-th channel negative phase input switch is connected to the i-th channel feedback voltage, a second end of the i-th channel negative phase input switch is connected to the negative phase input end of the i-th channel comparator, and a control end of the i-th channel positive phase input switch and a control end of the i-th channel negative phase input switch are connected to the negative phase signal of the i-th channel clock signal; The first end of the i-th channel positive phase common switch and the first end of the i-th channel negative phase common switch are connected to the common voltage, the second end of the i-th channel positive phase common switch is connected to the positive phase input end of the i-th channel comparator, the second end of the i-th channel negative phase common switch is connected to the negative phase input end of the i-th channel comparator, and the control end of the i-channel positive phase common switch and the control end of the i-channel negative phase common switch are connected to the i-th channel control output end of the signal generating module.

7. The multi-channel comparison circuit according to claim 3, characterized in that: The output control module includes N control terminals; The i-th control terminal of the output control module is connected to the i-th channel control output terminal of the signal generation module; The output control module is further configured to output the N channel comparison signals according to the N channel clock signals; or to output the cooperative comparison signal and N-1 channel comparison signals.

8. The multi-channel comparison circuit according to claim 7, characterized in that: The output control module includes a coordinated output control unit and N channel output control units; The input end of the cooperative output control unit is connected to the output end of the cooperative comparator, the i-th output end of the cooperative output control unit is connected to the i-th output end of the multi-channel comparison circuit, and the i-th control end of the cooperative output control unit is connected to the i-th channel control output end of the signal generation module; An input end of the i-th channel output control unit is connected to the output end of the i-th channel comparator, an output end of the i-th channel output control unit is connected to the i-th output end of the multi-channel comparison circuit, and a control end of the i-th channel output control unit is connected to the i-th channel control output end of the signal generating module; The coordinated output control unit is configured to output the coordinated comparison signal when the i-th channel clock signal is a high-level signal; The i-th channel output control unit is configured to output the i-th channel comparison signal when the i-th channel clock signal is a low level signal.

9. The multi-channel comparison circuit according to claim 8, characterized in that: The coordinated output control unit includes N coordinated output switches; A first end of the i-th cooperative output switch is connected to the output end of the cooperative comparator, a second end of the i-th cooperative output switch is connected to the i-th output end of the multi-channel comparison circuit, and a control end of the i-th cooperative output switch is connected to the i-th channel control output end of the signal generation module; The i-th channel output control unit includes an i-th channel output switch, a first end of the i-th channel output switch is connected to the output end of the i-th channel comparator, a second end of the i-th channel output switch is connected to the i-th output end of the multi-channel comparison circuit, and a control end of the i-th channel output switch is connected to the inverted signal of the i-th channel clock signal.

10. A power management chip, characterized in that: The invention comprises the multi-channel comparison circuit as described in any one of claims 1 to 9.

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