Array substrate and display panel

Abstract

The present application provides an array substrate and a display panel, wherein the array substrate includes a plurality of sub-pixels arranged in an array, a data line is located between two adjacent columns of sub-pixels and is connected to at least one column of sub-pixels, a scan line is located between a first pixel electrode and a second pixel electrode in each row of sub-pixels and is connected to a first gate of a first transistor and a second gate of a second transistor, the first gate and the second gate are located on the same side of the scan line, the first pixel electrode is connected to the first transistor through a first via hole, and the second pixel electrode is connected to the second transistor through a second via hole, and within each sub-pixel, the first via hole is located on a side of the first gate close to the data line connected to the sub-pixel, and the second via hole is located on a side of the second gate away from the first gate, so as to improve the problem of low aperture ratio existing in existing liquid crystal display panels using multi-domain display technology.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] Thin film transistor-liquid crystal display (TFT-LCD) panels are widely used due to their long lifespan, mature technology, and low price. However, due to the large differences in the birefringence of the liquid crystal molecules in LCD panels at different viewing angles, color shift occurs at wide viewing angles. Currently, the main method to improve color shift at wide viewing angles is to use multi-domain display technology, such as 3T8 domain display technology, in which each sub-pixel controls eight display domains through three thin-film transistors. However, LCD panels using multi-domain display technology suffer from a low aperture ratio. Summary of the Invention

[0003] The present application provides an array substrate and a display panel to alleviate the technical problem of low aperture ratio existing in existing liquid crystal display panels using multi-domain display technology.

[0004] To solve the above problems, the technical solutions provided by this application are as follows:

[0005] An embodiment of the present application provides an array substrate, comprising a substrate and a plurality of sub-pixels arranged in an array on the substrate, wherein each sub-pixel comprises a first pixel electrode, a second pixel electrode, and a plurality of transistors located between the first pixel electrode and the second pixel electrode, wherein the plurality of transistors comprises a first transistor and a second transistor, wherein the first pixel electrode is connected to the first transistor through a first via hole, and the second pixel electrode is connected to the second transistor through a second via hole; the array substrate further comprises:

[0006] a plurality of data lines arranged on the substrate at intervals along a first direction, each of the data lines being located on one side of the sub-pixel and connected to the corresponding sub-pixel, and the first pixel electrode and the second pixel electrode of each sub-pixel being arranged in sequence in a second direction;

[0007] a plurality of scan lines arranged on the substrate at intervals along the second direction, each of the scan lines being located between the first pixel electrode and the second pixel electrode of each row of the sub-pixels and connected to the first gate of the first transistor and the second gate of the second transistor of each sub-pixel, the first gate and the second gate being arranged sequentially in the first direction, and being located on the same side of the scan line to which they are connected;

[0008] In each of the sub-pixels, the first via hole is located on a side of the first gate close to the data line connected to the sub-pixel, the second via hole is located on a side of the second gate away from the first gate, and the first via hole and the second via hole are located on the same side of the scan line.

[0009] In the array substrate provided in an embodiment of the present application, the first pixel electrode includes a first overlapping portion connected to the first source of the first transistor, and the first overlapping portion is located in the first via hole; the second pixel electrode includes a second overlapping portion connected to the second source of the second transistor, and the second overlapping portion is located in the second via hole;

[0010] In the first direction, the first overlapping portion at least partially overlaps with the first gate, and the second overlapping portion at least partially overlaps with the second gate.

[0011] In the array substrate provided in the embodiment of the present application, the first gate and the second gate are integrally provided; a line connecting the center point of the first overlapping portion and the center point of the second overlapping portion is parallel to the first direction.

[0012] In the array substrate provided in an embodiment of the present application, the array substrate further includes a common electrode line extending in the same direction as the scan line, one of the common electrode line and the scan line is close to the first pixel electrode, and the other is close to the second pixel electrode, and the first overlapping portion, the second overlapping portion, the first gate and the second gate are all located between the common electrode line and the scan line.

[0013] In the array substrate provided in the embodiment of the present application, the array substrate further includes a first shielding electrode connected to the common electrode line. The first shielding electrode includes a first shielding portion located between the first overlapping portion and the adjacent data line.

[0014] In the array substrate provided by the embodiment of the present application, the first shielding electrode further includes a second shielding portion connected to the first shielding portion, and the second shielding portion is located between the first overlapping portion and the adjacent scanning line.

[0015] In the array substrate provided in the embodiment of the present application, the array substrate further includes a second shielding electrode connected to the common electrode line, and the second shielding electrode is located on a side of the second overlapping portion away from the first overlapping portion.

[0016] In the array substrate provided in the embodiment of the present application, the first pixel electrode includes a first trunk electrode, a first frame electrode, and a first branch electrode connected to the first trunk electrode and the first frame electrode; the second pixel electrode includes a second trunk electrode, a second frame electrode, and a second branch electrode connected to the second trunk electrode and the second frame electrode;

[0017] The array substrate further includes a third shielding electrode extending in the same direction as the data line, the third shielding electrode is arranged corresponding to the first frame electrode, and the third shielding electrode is connected to the common electrode;

[0018] And / or, the array substrate further includes a fourth shielding electrode extending in the same direction as the data line, the fourth shielding electrode is arranged corresponding to the second frame electrode, and a gap is provided between the fourth shielding electrode and the common electrode.

[0019] In the array substrate provided in the embodiment of the present application, the first trunk electrode includes a first sub-electrode portion in the same extending direction as the data line, and the second trunk electrode includes a second sub-electrode portion in the same extending direction as the data line;

[0020] The plurality of transistors further include a third transistor, a third drain of the third transistor being connected to the second source of the second transistor, a third gate of the third transistor being connected to the scan line, and the third gate and the first gate being located on the same side of the scan line;

[0021] The array substrate further includes a shared discharge rod, which is located between two adjacent data lines and corresponding to the first sub-electrode portion and the second sub-electrode portion. The shared discharge rod is connected to the third source of the third transistor.

[0022] In the array substrate provided in the embodiment of the present application, the array substrate also includes a first light-shielding electrode arranged corresponding to the first sub-electrode portion and a second light-shielding electrode arranged corresponding to the second sub-electrode portion, the first light-shielding electrode is located on the side of the shared discharge rod away from the first sub-electrode portion, the first light-shielding electrode is connected to the third shielding electrode and the common electrode, the second light-shielding electrode is located on the side of the shared discharge rod away from the second sub-electrode portion, and the second light-shielding electrode is connected to the fourth shielding electrode.

[0023] In the array substrate provided in the embodiment of the present application, the array substrate further includes:

[0024] a first conductive layer, disposed on the substrate, wherein the scan line, the common electrode line, the first gate and the second gate are formed on the first conductive layer;

[0025] a second conductive layer, disposed on a side of the first conductive layer away from the substrate, the second conductive layer being formed with the data line, the first source electrode, and the second source electrode;

[0026] a planar layer, disposed on a side of the second conductive layer away from the substrate, the planar layer being provided with a first via hole at a position corresponding to the first source electrode and a second via hole at a position corresponding to the second source electrode;

[0027] a third conductive layer, disposed on a side of the planar layer away from the substrate, the first pixel electrode and the second pixel electrode being formed on the third conductive layer;

[0028] The first overlapping portion is located in the first via hole, the second overlapping portion is located in the second via hole, the orthographic projection of the first overlapping portion on the substrate is separated from the orthographic projection of the first conductive layer on the substrate, and the orthographic projection of the second overlapping portion on the substrate is separated from the orthographic projection of the first conductive layer on the substrate.

[0029] In the array substrate provided in the embodiment of the present application, the first drain of the first transistor and the second drain of the second transistor are both connected to the same data line, and the first drain and the second drain are both U-shaped, and the U-shaped openings are the same.

[0030] An embodiment of the present application further provides a display panel, which includes the array substrate of one of the aforementioned embodiments.

[0031] The present application has the following beneficial effects: in the array substrate and display panel provided by the present application, the array substrate includes a plurality of sub-pixels arranged in an array, the data line is located on one side of the sub-pixels and connected to the corresponding sub-pixels, the scan line is located between the first pixel electrode and the second pixel electrode of each row of sub-pixels and connected to the first gate of the first transistor and the second gate of the second transistor, the first gate and the second gate are located on the same side of the scan line, the first pixel electrode is connected to the first transistor through a first via hole, and the second pixel electrode is connected to the second transistor through a second via hole, in each sub-pixel, the first via hole is located on the side of the first gate close to the data line connected to the sub-pixel, the second via hole is located on the side of the second gate away from the first gate, and the first via hole and the second via hole are located on the same side of the scan line; thus, by arranging the first and second gates on the same side of the scan line and arranging the first and second via holes on opposite sides of the first gate, the distances between the first and second gates and the opening area can be reduced, thereby reducing the area of ​​the non-opening area, improving the aperture ratio, and improving the technical problem of low aperture ratio existing in existing liquid crystal display panels using multi-domain display technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 A schematic diagram of the planar structure of a sub-pixel on a liquid crystal display panel is shown.

[0034] Figure 2 A schematic diagram of a planar structure of an array substrate in an embodiment of the present application is shown.

[0035] Figure 3 Shown Figure 2 Schematic diagram of the planar structure of a sub-pixel.

[0036] Figure 4 Shown Figure 3 Detailed diagram of some structures in the middle.

[0037] Figure 5 Shown Figure 3 Schematic diagram of part of the film layer structure of the neutron pixel.

[0038] Figure 6 A schematic cross-sectional structure diagram of a display panel in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0039] The following descriptions of the embodiments are with reference to the attached diagrams to illustrate specific embodiments that the present application can be implemented in. The directional terms mentioned in this application, such as [up], [down], [front], [back], [left], [right], [inside], [outside], [side], etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present application, rather than to limit the present application. In the figures, units with similar structures are represented by the same reference numerals. In the accompanying drawings, the thickness of some layers and areas is exaggerated for clarity of understanding and ease of description. That is, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present application is not limited to this.

[0040] In view of the problem of low aperture ratio of the existing liquid crystal display panel using multi-domain display technology, the inventors of this application found in their research that: Figure 1 , Figure 1The schematic diagram shows the planar structure of a subpixel on a liquid crystal display panel. The subpixel includes a first pixel electrode 20', a second pixel electrode 30', and multiple transistors, including a first transistor T1' and a second transistor T2'. The first pixel electrode 20' connects to the first transistor T1' through a first via hole H1', ​​and the second pixel electrode 30' connects to the second transistor T2' through a second via hole H2'. The first via hole H1' and the second via hole H2' are located on opposite sides of a scan line SL'. The scan line SL' is located between two adjacent common electrode lines CL'. Both the scan line SL' and the common electrode line CL' extend along a first direction X. The first pixel electrode 20', the multiple transistors, and the second pixel electrode 30' are arranged sequentially in a second direction Y. One of the two common electrode lines CL' forms a first capacitor C1' with the first pixel electrode 20' at a location corresponding to the first via hole H1'. The other common electrode line CL' forms a second capacitor C2' with the second pixel electrode 30' at a location corresponding to the second via hole H2'. The first via hole H1' and the second via hole H2' are located on opposite sides of the scan line SL', resulting in a plurality of transistors occupying a larger area in the second direction Y, making the non-opening area larger, thereby resulting in a lower aperture ratio of the liquid crystal display panel.

[0041] To this end, the present application provides an array substrate and a display panel.

[0042] Please refer to Figures 2 to 5 , Figure 2 FIG. 1 shows a schematic planar structure diagram of an array substrate in an embodiment of the present application. Figure 3 Shown Figure 2 Schematic diagram of the planar structure of a sub-pixel in Figure 4 Shown Figure 3 Detailed diagram of the structure in the middle part. Figure 5 Shown Figure 3 Schematic diagram of part of the film structure of the neutron pixel. Figure 2 The array substrate 100 includes a substrate 10 and a plurality of gate scan lines GL and a plurality of data lines DL arranged on the substrate 10. The plurality of gate scan lines GL extend along a first direction X and are arranged at intervals along a second direction Y. The plurality of data lines DL extend along the second direction Y and are arranged at intervals along the first direction X. The first direction X and the second direction Y are different. For example, the first direction X is a row direction, and the second direction Y is a column direction.

[0043] The array substrate 100 also includes a plurality of sub-pixels SP arranged in an array on the substrate 10. Each data line DL is located on one side of a sub-pixel SP and is connected to a corresponding sub-pixel SP. For example, each data line DL is connected to a column of sub-pixels SP, and some data lines DL are located between two adjacent columns of sub-pixels SP. Each gate scan line SL spans a row of sub-pixels SP and is connected to at least one sub-pixel SP in that row. Every three adjacent sub-pixels SP constitute a pixel P. For example, any three adjacent sub-pixels SP in the second direction Y constitute a pixel P. That is, each pixel P includes three sub-pixels SP arranged sequentially in the second direction Y. The three sequentially arranged sub-pixels SP emit different luminous colors, for example, one sub-pixel SP emitting red light, one sub-pixel SP emitting green light, and one sub-pixel SP emitting blue light. Of course, in some embodiments, each pixel P may also include three sub-pixels SP arranged sequentially in the first direction X.

[0044] The structure of the array substrate 100 is described in detail below by taking a sub-pixel SP as an example.

[0045] Reference Figure 3 Each sub-pixel SP includes a first pixel electrode 20, a second pixel electrode 30, and a plurality of transistors located between the first pixel electrode 20 and the second pixel electrode 30. The plurality of transistors includes a first transistor T1 and a second transistor T2. The first pixel electrode 20 is connected to the first transistor T1 through a first via hole H1, and the second pixel electrode 30 is connected to the second transistor T2 through a second via hole H2. The first pixel electrode 20 and the second pixel electrode 30 of each sub-pixel SP are arranged sequentially in the second direction Y.

[0046] Each scan line SL is located between the first pixel electrode 20 and the second pixel electrode 30 of each row of sub-pixels SP and is connected to the first gate G1 of the first transistor T1 and the second gate G2 of the second transistor T2 of each sub-pixel SP. The first gate G1 and the second gate G2 are arranged sequentially in the first direction X, and the first gate G1 and the second gate G2 are located on the same side of the scan line SL to which they are connected. In each sub-pixel SP, the first via hole H1 is located on a side of the first gate G1 that is close to the data line DL connected to the sub-pixel SP, and the second via hole H2 is located on a side of the second gate G2 that is away from the first gate G1. The first via hole H1 and the second via hole H2 are located on the same side of the scan line SL.

[0047] In this way, by arranging the first gate G1 and the second gate G2 on the same side of the scan line SL, and locating the first via H1 and the second via H2 on opposite sides of the first gate G1, the space in the region where the multiple transistors are located in the first direction X is fully utilized, thereby reducing the space in the region where the multiple transistors are located in the second direction Y. This reduces the distance between the first gate G1, the second gate G2, and the opening region, thereby reducing the area of ​​the non-opening region, improving the aperture ratio, and improving the technical problem of low aperture ratio in existing liquid crystal display panels using multi-domain display technology. The region where the multiple transistors are located is the non-opening region, and the region where the first pixel electrode 20 and the second pixel electrode 30 are located is the opening region. Within the unit area of ​​the sub-pixel SP, by reducing the area occupied by the non-opening region, the area where the opening region is located can be increased, thereby improving the aperture ratio.

[0048] Optionally, continue with reference to Figure 3 The first pixel electrode 20 includes a first main electrode 21, a first frame electrode 22, and a first branch electrode 23 connected to the first main electrode 21 and the first frame electrode 22. The first main electrode 21 includes a first sub-electrode portion 211 extending in the same direction as the data line DL and a third sub-electrode portion 212 extending in the same direction as the scan line SL. The first sub-electrode portion 211 passes through the midpoint of the third sub-electrode portion 212, and the first sub-electrode portion 211 and the third sub-electrode portion 212 intersect vertically to divide the first pixel electrode 20 into four display domains. The first branch electrodes 23 in each display domain extend in different directions from the first sub-electrode portion 211 or the third sub-electrode portion 212, and the first branch electrodes 23 in each display domain extend in the same direction. The first branch electrodes 23 in two adjacent display domains are symmetrical about the first sub-electrode portion 211 or the third sub-electrode portion 212.

[0049] The second pixel electrode 30 includes a second main electrode 31, a second frame electrode 32, and a second branch electrode 33 connected to the second main electrode 31 and the second frame electrode 32. The second main electrode 31 includes a second sub-electrode portion 311 extending in the same direction as the data line DL and a fourth sub-electrode portion 312 extending in the same direction as the scan line SL. In the second direction Y, the length of the second sub-electrode portion 311 is greater than the length of the first sub-electrode portion 211; in the first direction X, the length of the fourth sub-electrode portion 312 is equal to the length of the third sub-electrode portion 212. The second sub-electrode portion 311 passes through the midpoint of the fourth sub-electrode portion 312, and the second sub-electrode portion 311 and the fourth sub-electrode portion 312 intersect vertically to divide the second pixel electrode 30 into four display domains. The second branch electrodes 33 in each of the display domains extend in different directions from the second sub-electrode portion 311 or the fourth sub-electrode portion 312, and the extension direction of the second branch electrodes 33 in each of the display domains is the same, and the second branch electrodes 33 in two adjacent display domains are symmetrical about the second sub-electrode portion 311 or the fourth sub-electrode portion 312.

[0050] Of course, in some other embodiments, the first trunk electrode 21 of the first pixel electrode 20 may not include the third sub-electrode portion 212. In this case, the first pixel electrode 20 is divided into two display domains by the first sub-electrode portion 211, and accordingly, the second pixel electrode 30 may also include two display domains. In addition, the first pixel electrode 20 may not include the first border electrode 22, and the second pixel electrode 30 may not include the second border electrode 32.

[0051] Optionally, the first pixel electrode 20 and the second pixel electrode 30 are arranged in the same layer. In this application, "arranged in the same layer" means that in the preparation process, a film layer formed by the same material is patterned to obtain at least two different structures, and the at least two different structures are arranged in the same layer. For example, the first pixel electrode 20 and the second pixel electrode 30 of this embodiment are obtained by patterning the same conductive film layer, and the first pixel electrode 20 and the second pixel electrode 30 are arranged in the same layer. The materials of the first pixel electrode 20 and the second pixel electrode 30 both include transparent conductive materials such as indium tin oxide (ITO).

[0052] The plurality of transistors are located between the first pixel electrode 20 and the second pixel electrode 30. The plurality of transistors include a first transistor T1 and a second transistor T2, wherein the first transistor T1 is electrically connected to the first pixel electrode 20, and the second transistor T2 is electrically connected to the second pixel electrode 30. The first transistor T1 and the second transistor T2 are both thin film transistors. The first transistor T1 is used to provide a driving voltage to the first pixel electrode 20, and the second transistor T2 is used to provide a driving voltage to the second pixel electrode 30, and the driving voltage provided by the first transistor T1 to the first pixel electrode 20 is different from the driving voltage provided by the second transistor T2 to the second pixel electrode 30. In this way, the brightness difference between the corresponding areas of the first pixel electrode 20 and the second pixel electrode 30 can be adjusted by adjusting the voltage ratio between the first pixel electrode 20 and the second pixel electrode 30, thereby forming a complementary viewing angle and improving the viewing angle.

[0053] Specifically, the first drain S1 of the first transistor T1 is connected to the data line DL, and the first source D1 of the first transistor T1 is connected to the first pixel electrode 20. The first drain S1 is located on a side of the first gate G1 away from the substrate 10. The second drain S2 of the second transistor T2 is connected to the same data line DL as the first drain S1 of the first transistor T1, and the second source D2 of the second transistor T2 is connected to the second pixel electrode 30. The second drain S2 is located on a side of the second gate G2 away from the substrate 10. The first drain S1 and the second drain S2 are both arranged on the same layer as the data line DL. The first drain S1 and the second drain S2 are both U-shaped, and the U-shaped openings are the same.

[0054] The first pixel electrode 20 is connected to the first transistor T1 through the first via hole H1. For example, the first pixel electrode 20 includes a first overlapping portion 24 connected to the first source D1 of the first transistor T1. The first overlapping portion 24 is located in the first via hole H1 and contacts the first source D1. The connection point between the first pixel electrode 20 and the first transistor T1 is the location of the first overlapping portion 24, that is, the location of the first via hole H1. The second pixel electrode 30 is connected to the second transistor T2 through the second via hole H2. For example, the second pixel electrode 30 includes a second overlapping portion 34 connected to the second source D2 of the second transistor T2. The second overlapping portion 34 is located in the second via hole H2 and contacts the second source D2. The connection point between the second pixel electrode 30 and the second transistor T2 is the location of the second overlapping portion 34, that is, the location of the second via hole H2.

[0055] Optionally, the first pixel electrode 20 further includes a first extended electrode 25 connected between the first overlapping portion 24 and the first branch electrode 23, wherein the first extended electrode 25 is formed by extending the first branch electrode 23 toward the first overlapping portion 24. The second pixel electrode 30 further includes a second extended electrode 35 connected between the second overlapping portion 34 and the second branch electrode 33, wherein the second extended electrode 35 is formed by extending the second branch electrode 33 toward the second overlapping portion 34.

[0056] In the first direction X, the first overlapping portion 24 at least partially overlaps with the first gate G1, and the second overlapping portion 34 at least partially overlaps with the second gate G2, so that the first overlapping portion 24, the first gate G1, the second gate G2 and the second overlapping portion 34 are arranged in sequence in the first direction X to fully utilize the space of the non-opening area in the first direction X, thereby reducing the space of the non-opening area in the second direction Y and improving the aperture ratio.

[0057] Optionally, the first gate G1 and the second gate G2 are integrally formed. In the first direction X, the first overlapping portion 24 and the second overlapping portion 34 at least partially overlap. For example, a line connecting the center points of the first overlapping portion 24 and the second overlapping portion 34 is parallel to the first direction X, thereby further reducing the space of the non-opening area in the second direction Y and improving the aperture ratio.

[0058] The array substrate 100 also includes a common electrode line CL extending in the same direction as the scan line SL. The common electrode is disposed on the same layer as the scan line SL. One of the common electrode line CL and the scan line SL is adjacent to the first pixel electrode 20, while the other is adjacent to the second pixel electrode 30. For example, the common electrode is adjacent to the first pixel electrode 20, while the scan line SL is adjacent to the second pixel electrode 30. The orthographic projection of the first pixel electrode 20 on the substrate 10 overlaps the edge of the orthographic projection of the common electrode on the substrate 10, and the orthographic projection of the second pixel electrode 30 on the substrate 10 overlaps the edge of the orthographic projection of the scan line SL on the substrate 10. The first overlapping portion 24, the second overlapping portion 34, the first gate G1, and the second gate G2 are all located between the common electrode line CL and the scan line SL, and each has a gap between them and the common electrode. The first gate G1 and the second gate G2 are formed by the scan line SL protruding toward the common electrode.

[0059] In one embodiment, the array substrate 100 further includes a first shielding electrode 41 connected to the common electrode line CL. The first shielding electrode 41 includes a first shielding portion 411. The first shielding portion 411 is located between the first overlapping portion 24 and the adjacent data line DL to shield the electric field between the first overlapping portion 24 and the corresponding data line DL, thereby reducing the parasitic capacitance between the first overlapping portion 24 and the corresponding data line DL, and thereby improving the crosstalk problem caused by the parasitic capacitance. The temporary data line DL refers to the data line DL that is closer to the first overlapping portion 24 among the two data lines DL adjacent to the first overlapping portion 24. To reduce the wiring length, the data line DL adjacent to the first overlapping portion 24 also refers to the data line DL connected to the first transistor T1.

[0060] Optionally, the first shielding electrode 41 further includes a second shielding portion 412 connected to the first shielding portion 411. The second shielding portion 412 is located between the first overlapping portion 24 and the adjacent scan line SL, so that the first shielding electrode 41 forms a structure that semi-encloses the first overlapping portion 24, thereby further reducing parasitic capacitance between the first overlapping portion 24 and the corresponding data line DL. In the first direction X, the second shielding portion 412 overlaps with the first gate G1, and a gap is formed between the second shielding portion 412 and the first gate G1.

[0061] Optionally, the surface shape of the first shielding electrode 41 includes L-shape or arc shape, etc. The first shielding electrode 41 is provided in the same layer as the common electrode, for example, the first shielding electrode 41 can be formed by extending the common electrode toward the direction close to the scanning line SL.

[0062] In one embodiment, the array substrate 100 further includes a second shielding electrode 42 connected to the common electrode line CL. The second shielding electrode 42 is located on a side of the second overlapping portion 34 away from the first overlapping portion 24 to shield the electric field between the second overlapping portion 34 and the corresponding data line DL, thereby reducing parasitic capacitance between the second overlapping portion 34 and the corresponding data line DL, thereby improving crosstalk caused by parasitic capacitance. Optionally, the second shielding electrode 42 is disposed on the same layer as the common electrode. For example, the second shielding electrode 42 can be formed by extending the common electrode toward the direction close to the scan line SL.

[0063] In one embodiment, the array substrate 100 further includes a third shielding electrode 43 extending in the same direction as the data line DL. The third shielding electrode 43 is disposed corresponding to the first frame electrode 22 and is connected to the common electrode. The third shielding electrode 43 is located between the first pixel electrode 20 and the adjacent data line DL to shield the electric field between the first pixel electrode 20 and the adjacent data line DL, thereby reducing the parasitic capacitance between the first pixel electrode 20 and the adjacent data line DL, and thereby improving the crosstalk problem caused by the parasitic capacitance. Optionally, the third shielding electrode 43 is disposed in the same layer as the common electrode. For example, the third shielding electrode 43 can be formed by extending the common electrode in a direction away from the scan line SL.

[0064] In one embodiment, the array substrate 100 further includes a fourth shielding electrode 44 extending in the same direction as the data line DL. The fourth shielding electrode 44 is disposed corresponding to the second frame electrode 32, and a gap is formed between the fourth shielding electrode 44 and the common electrode. The fourth shielding electrode 44 is located between the second pixel electrode 30 and the adjacent data line DL to shield the electric field between the second pixel electrode 30 and the adjacent data line DL, thereby reducing parasitic capacitance between the second pixel electrode 30 and the adjacent data line DL, and thereby improving crosstalk caused by parasitic capacitance. Optionally, the fourth shielding electrode 44 is disposed on the same layer as the common electrode.

[0065] In one embodiment, the plurality of transistors further include a third transistor T3, the type of the third transistor T3 being the same as the first transistor T1 and / or the second transistor T2. The third transistor T3 is connected in series with the second transistor T2 and is configured to divide the voltage of the second transistor T2 so that the driving voltage provided by the second transistor T2 to the second pixel electrode 30 is lower than the driving voltage provided by the first transistor T1 to the first pixel electrode 20, thereby causing the voltage on the second pixel electrode 30 to be lower than the voltage on the first pixel electrode 20. Specifically, a third drain S3 of the third transistor T3 is connected to the second source D2 of the second transistor T2, a third gate G3 of the third transistor T3 is connected to the scan line SL, and the third gate G3 and the first gate G1 are located on the same side of the scan line SL.

[0066] The array substrate 100 also includes a shared discharge bar SB, which is located between two adjacent data lines DL and corresponds to the first sub-electrode portion 211 and the second sub-electrode portion 311. In the first direction X, the width of the shared discharge bar SB is less than or equal to the width of the first sub-electrode portion 211 and the second sub-electrode portion 311 to avoid affecting the transmittance of the opening area. The shared discharge bar SB is connected to the third source D3 of the third transistor T3, so that the third transistor T3 divides the voltage of the second transistor T2. The shared discharge bar SB is provided on the same layer as the data lines DL.

[0067] Optionally, combined Figure 3 and Figure 4 The array substrate 100 further includes a first light-shielding electrode 51 corresponding to the first sub-electrode portion 211 and a second light-shielding electrode 52 corresponding to the second sub-electrode portion 311. The first light-shielding electrode 51 is located on a side of the shared discharge bar SB away from the first sub-electrode portion 211 and is connected to the third shielding electrode 43 and the common electrode. The second light-shielding electrode 52 is located on a side of the shared discharge bar SB away from the second sub-electrode portion 311 and is connected to the fourth shielding electrode 44. In the first direction X, the width of the first light-shielding electrode 51 is greater than the width of the first sub-electrode portion 211, and the width of the second light-shielding electrode 52 is greater than the width of the second sub-electrode portion 311, thereby shielding the shared discharge bar SB from light. It should be noted that when the array substrate 100 is prepared using the 4Msak process, all structures arranged on the same layer as the data line DL include a metal layer and a semiconductor portion located below the metal layer. For example, the shared discharge rod SB includes a metal layer and a semiconductor portion located below the metal layer. Therefore, by shielding the shared discharge rod SB through the first light-shielding electrode 51 and the second light-shielding electrode 52, light leakage in the semiconductor portion of the shared discharge rod SB can be avoided.

[0068] In one embodiment, referring to Figure 3 The array substrate 100 further includes a third light-shielding electrode 53. The third light-shielding electrode 53 is located on a side of the data line DL away from the substrate 10. In the first direction X, the width of the third light-shielding electrode 53 is greater than the width of the data line DL, thereby shielding the data line DL from light. The third light-shielding layer is provided on the same layer as the first pixel electrode 20 and the second pixel electrode 30.

[0069] The following describes the film layer structure of the array substrate 100 by taking the first transistor T1 and the second transistor T2 as examples.

[0070] Reference Figure 5 The array substrate 100 further includes a first conductive layer 1, a gate insulating layer 12, a semiconductor layer 2, a second conductive layer 3, a planar layer 13, and a third conductive layer 4 disposed on the substrate 10. The first conductive layer 1 is disposed on the substrate 10 and is formed with the scan line SL, the first gate G1 of the first transistor T1, and the second gate G2 of the second transistor T2. Optionally, the first conductive layer 1 is further formed with the third gate G3 of the third transistor T3, the common electrode line CL, the first shielding electrode 41, the second shielding electrode 42, the third shielding electrode 43, the fourth shielding electrode 44, the first light-shielding electrode 51, and the second light-shielding electrode 52. The first conductive layer 1 can be formed as multiple layers or a single layer including a low-resistance material such as Al, Ti, Mo, Cu, Ni, or alloys thereof, or a material with high corrosion resistance.

[0071] Optionally, the substrate 10 may be a rigid substrate or a flexible substrate; when the substrate 10 is a rigid substrate, it may include a hard substrate such as a glass substrate; when the substrate 10 is a flexible substrate, it may include a flexible substrate such as a polyimide (PI) film or an ultra-thin glass film.

[0072] Optionally, a buffer layer 11 may be provided between the substrate 10 and the first conductive layer 1. The buffer layer 11 can prevent unwanted impurities or contaminants (e.g., moisture, oxygen, etc.) from diffusing from the substrate 10 into devices that may be damaged by these impurities or contaminants, while also providing a flat top surface. For example, the buffer layer 11 may be made of inorganic materials such as silicon oxide and silicon nitride.

[0073] The gate insulating layer 12 is disposed on a side of the first metal layer away from the substrate 10. The gate insulating layer 12 may be a single layer or multiple layers including at least one of tetraethyl orthosilicate, silicon nitride, and silicon oxide.

[0074] The semiconductor layer 2 and the second conductive layer 3 are disposed on a side of the first conductive layer 1 away from the substrate 10. The second conductive layer 3 is formed with the data line DL, the first drain S1 and first source D1 of the first transistor T1, the second drain S2 and second source D2 of the second transistor T2, the third drain S3 and third source D3 of the third transistor T3, and the shared discharge bar SB. The semiconductor layer 2 is formed with the first active portion AS1 of the first transistor T1 and the second active portion AS2 of the second transistor T2. Alternatively, the semiconductor layer 2 may be formed of polycrystalline silicon. The second conductive layer 3 may be formed as multiple layers or a single layer of a low-resistance material such as Al, Ti, Mo, Cu, Ni, or alloys thereof, or a material with high corrosion resistance. For example, the second conductive layer 3 may be a triple layer of Ti / Cu / Ti, Ti / Ag / Ti, Ti / Al / Ti, or Mo / Al / Mo, among others.

[0075] The planar layer 13 is disposed on a side of the second conductive layer 3 away from the substrate 10. The planar layer 13 is provided with a first via hole H1 at a position corresponding to the first source electrode D1 and a second via hole H2 at a position corresponding to the second source electrode D2. The planar layer 13 can be formed of a resin, such as polyacrylate, polyimide, or a silica-based organic material.

[0076] The third conductive layer 4 is disposed on a side of the planar layer 13 away from the substrate 10. The first pixel electrode 20, the second pixel electrode 30, and the third light-shielding electrode 53 are formed on the third conductive layer 4. The third conductive layer 4 can be formed of a material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3).

[0077] The first overlapping portion 24 is located in the first via hole H1, and the second overlapping portion 34 is located in the second via hole H2. The orthographic projection of the first overlapping portion 24 on the substrate 10 is separated from the orthographic projection of the first conductive layer 1 on the substrate 10, and the orthographic projection of the second overlapping portion 34 on the substrate 10 is separated from the orthographic projection of the first conductive layer 1 on the substrate 10, that is, the orthographic projection of the first overlapping portion 24 on the substrate 10 does not overlap with the orthographic projection of the first conductive layer 1 on the substrate 10, and the orthographic projection of the second overlapping portion 34 on the substrate 10 does not overlap with the orthographic projection of the first conductive layer 1 on the substrate 10, so that the connection position of the first transistor T1 and the first pixel electrode 20 will not form a storage capacitor, and the connection position of the second transistor T2 and the second pixel electrode 30 will not form a storage capacitor. Compared with Figure 1In the sub-pixel structure shown, the first storage capacitor and the second storage capacitor are removed from the non-opening area of ​​the sub-pixel structure of this embodiment, thereby further reducing the area of ​​the non-opening area and improving the pixel aperture ratio; moreover, it can also improve the interference caused by setting the storage capacitor.

[0078] It should be noted that Figure 1 In the sub-pixel structure shown, the storage capacitors (such as the first storage capacitor C1' and the second storage capacitor C2') are composed of a common electrode line CL', an insulating layer, a semiconductor layer and a pixel electrode (such as the first pixel electrode 20' and the second pixel electrode 30'). When the panel driving mode is positive and negative frame driving, the voltage value of the common electrode line CL' under the positive and negative frames remains unchanged, and the voltage value of the pixel electrode is different in the positive and negative frames, resulting in the electric field direction in the storage capacitor in the positive frame being different from that in the negative frame. Due to the presence of the semiconductor layer, the size of the storage capacitor on the common electrode line CL' will be affected by the direction of the electric field. The size of the storage capacitor under the positive frame is different from that in the negative frame, resulting in different brightness in the positive and negative frames, and then causing a series of problems such as crosstalk. In this embodiment, by removing the storage capacitor in the non-opening area, not only can the pixel aperture ratio be further improved, but also the interference caused by the setting of the storage capacitor can be avoided.

[0079] Based on the same inventive concept, the present application also provides a display panel. Figures 1 to 6 , Figure 6 A schematic diagram of a cross-sectional structure of a display panel in an embodiment of the present application is shown. The display panel includes an array substrate 100 of one of the aforementioned embodiments. The display panel is a liquid crystal display panel, etc. This embodiment is described by taking the liquid crystal display panel as an example. Specifically, refer to Figure 6 The display panel 1000 includes a first substrate and a second substrate disposed opposite each other. One of the first substrate and the second substrate is the array substrate 100 of one of the aforementioned embodiments. This embodiment uses the array substrate 100 as the first substrate for illustration, and the second substrate 200 is a color filter substrate. The display panel 1000 also includes liquid crystal molecules 300 sandwiched between the array substrate 100 and the second substrate 200.

[0080] According to the above embodiments, it can be seen that:

[0081] The present application provides an array substrate and a display panel, wherein the array substrate includes a plurality of sub-pixels arranged in an array, a data line located between two adjacent columns of sub-pixels and connected to at least one column of sub-pixels, a scan line located between a first pixel electrode and a second pixel electrode of each row of sub-pixels and connected to a first gate of a first transistor and a second gate of a second transistor, the first gate and the second gate located on the same side of the scan line, the first pixel electrode connected to the first transistor through a first via hole, and the second pixel electrode connected to the second transistor through a second via hole, within each sub-pixel, the first via hole located on a side of the first gate close to the data line connected to the sub-pixel, and the second via hole located on a side of the second gate away from the first gate; thus, by arranging the first and second gates on the same side of the scan line and arranging the first and second via holes on opposite sides of the first gate, the distances between the first and second gates and the opening area can be reduced, thereby reducing the area of ​​the non-opening area, improving the aperture ratio, and improving the technical problem of low aperture ratio existing in existing liquid crystal display panels using multi-domain display technology.

[0082] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0083] The above is a detailed introduction to the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, characterized in that: include: substrate; a plurality of sub-pixels arranged in an array on the substrate, each sub-pixel comprising a first pixel electrode, a second pixel electrode, and a plurality of transistors located between the first pixel electrode and the second pixel electrode, the plurality of transistors comprising a first transistor and a second transistor, the first pixel electrode being connected to the first transistor through a first via hole, and the second pixel electrode being connected to the second transistor through a second via hole; a plurality of data lines arranged on the substrate at intervals along a first direction, each of the data lines being located on one side of the sub-pixel and connected to the corresponding sub-pixel, and the first pixel electrode and the second pixel electrode of each sub-pixel being arranged in sequence in a second direction; a plurality of scan lines arranged on the substrate at intervals along the second direction, each of the scan lines being located between the first pixel electrode and the second pixel electrode of each row of the sub-pixels and connected to the first gate of the first transistor and the second gate of the second transistor of each sub-pixel, the first gate and the second gate being arranged sequentially in the first direction, and being located on the same side of the scan line to which they are connected; In each of the sub-pixels, the first via hole is located on a side of the first gate close to the data line connected to the sub-pixel, the second via hole is located on a side of the second gate away from the first gate, and the first via hole and the second via hole are located on the same side of the scan line.

2. The array substrate according to claim 1, wherein: The first pixel electrode includes a first overlapping portion connected to the first source of the first transistor, and the first overlapping portion is located in the first via hole; the second pixel electrode includes a second overlapping portion connected to the second source of the second transistor, and the second overlapping portion is located in the second via hole; In the first direction, the first overlapping portion at least partially overlaps with the first gate, and the second overlapping portion at least partially overlaps with the second gate.

3. The array substrate according to claim 2, wherein: The first gate and the second gate are integrally provided; a line connecting a center point of the first overlapping portion and a center point of the second overlapping portion is parallel to the first direction.

4. The array substrate according to claim 2, wherein: The array substrate also includes a common electrode line extending in the same direction as the scan line, one of the common electrode line and the scan line is close to the first pixel electrode, and the other is close to the second pixel electrode, and the first overlapping portion, the second overlapping portion, the first gate, and the second gate are all located between the common electrode line and the scan line.

5. The array substrate according to claim 4, wherein: The array substrate further includes a first shielding electrode connected to the common electrode line. The first shielding electrode includes a first shielding portion. The first shielding portion is located between the first overlapping portion and the adjacent data line.

6. The array substrate according to claim 5, wherein: The first shielding electrode further includes a second shielding portion connected to the first shielding portion, and the second shielding portion is located between the first overlapping portion and the adjacent scanning line.

7. The array substrate according to claim 4, wherein: The array substrate further includes a second shielding electrode connected to the common electrode line, and the second shielding electrode is located on a side of the second overlapping portion away from the first overlapping portion.

8. The array substrate according to claim 4, wherein: The first pixel electrode includes a first trunk electrode, a first frame electrode, and a first branch electrode connected to the first trunk electrode and the first frame electrode; the second pixel electrode includes a second trunk electrode, a second frame electrode, and a second branch electrode connected to the second trunk electrode and the second frame electrode; The array substrate further includes a third shielding electrode extending in the same direction as the data line, the third shielding electrode is arranged corresponding to the first frame electrode, and the third shielding electrode is connected to the common electrode; And / or, the array substrate further includes a fourth shielding electrode extending in the same direction as the data line, the fourth shielding electrode is arranged corresponding to the second frame electrode, and a gap is provided between the fourth shielding electrode and the common electrode.

9. The array substrate according to claim 8, wherein: The first trunk electrode includes a first sub-electrode portion in the same direction as the data line extends, and the second trunk electrode includes a second sub-electrode portion in the same direction as the data line extends; The plurality of transistors further include a third transistor, a third drain of the third transistor being connected to the second source of the second transistor, a third gate of the third transistor being connected to the scan line, and the third gate and the first gate being located on the same side of the scan line; The array substrate further includes a shared discharge rod, which is located between two adjacent data lines and corresponding to the first sub-electrode portion and the second sub-electrode portion. The shared discharge rod is connected to the third source of the third transistor.

10. The array substrate according to claim 9, wherein: The array substrate also includes a first light-shielding electrode arranged corresponding to the first sub-electrode portion and a second light-shielding electrode arranged corresponding to the second sub-electrode portion, the first light-shielding electrode is located on a side of the shared discharge rod away from the first sub-electrode portion, the first light-shielding electrode is connected to the third shielding electrode and the common electrode, the second light-shielding electrode is located on a side of the shared discharge rod away from the second sub-electrode portion, and the second light-shielding electrode is connected to the fourth shielding electrode.

11. The array substrate according to any one of claims 4 to 10, characterized in that: The array substrate further includes: a first conductive layer, disposed on the substrate, wherein the scan line, the common electrode line, the first gate and the second gate are formed on the first conductive layer; a second conductive layer, disposed on a side of the first conductive layer away from the substrate, the second conductive layer being formed with the data line, the first source electrode, and the second source electrode; a planar layer, disposed on a side of the second conductive layer away from the substrate, the planar layer being provided with a first via hole at a position corresponding to the first source electrode and a second via hole at a position corresponding to the second source electrode; a third conductive layer, disposed on a side of the planar layer away from the substrate, the first pixel electrode and the second pixel electrode being formed on the third conductive layer; The first overlapping portion is located in the first via hole, the second overlapping portion is located in the second via hole, the orthographic projection of the first overlapping portion on the substrate is separated from the orthographic projection of the first conductive layer on the substrate, and the orthographic projection of the second overlapping portion on the substrate is separated from the orthographic projection of the first conductive layer on the substrate.

12. The array substrate according to any one of claims 1 to 10, characterized in that: The first drain of the first transistor and the second drain of the second transistor are both connected to the same data line. The first drain and the second drain are both U-shaped, and the U-shaped openings are the same.

13. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 12.

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