A fully reconfigurable JESD204B interface ADC test device and test method

Abstract

The invention relates to the fields of high-speed data acquisition, chip testing technology, and the like, and discloses a fully reconfigurable JESD204B interface ADC testing device and a testing method. The testing device can cooperate with a host computer and a signal source to perform JESD204B interface ADC testing, and comprises an FPGA motherboard, an FMC daughter card with a chip testing fixture, a switch matrix circuit, and a JESD204B clock generating circuit integrated into the FPGA motherboard or the FMC daughter card or existing independently; the FPGA motherboard is provided with a Xilinx FPGA, a DDR4 memory connected to the Xilinx FPGA, an Ethernet PHY and a network interface, and a GPIO and a power supply interface A; the FPGA motherboard and the FMC daughter card are detachably connected through the FMC interface; the GPIO and the power supply interface on the switch matrix circuit and the GPIO and the power supply interface A on the FPGA motherboard are connected through a cable; and in view of the defects of the existing scheme, the design of the JESD204B interface ADC device configuration, the data acquisition FPGA test driver, and the back-end application layer data mapping are universalized to the greatest extent.

Description

Technical Field

[0001] The present invention relates to the fields of high-speed data acquisition, chip testing technology, and more specifically, to a fully reconfigurable JESD204B interface ADC testing device and testing method. Background Art

[0002] Compared with traditional CMOS or LVDS interfaces, the JESD204 converter interface has greater advantages in communication speed, size and cost. When using the JESD204 interface in high-speed converters, the reduction in the number of pins can reduce the device package size and the number of wiring, bringing many benefits to circuit board design. Currently, the most commonly used version in high-speed converters is the B version, i.e. JESD204B, which has a channel data rate of up to 12.5Gbps (in fact, many converter manufacturers have extended support to 16Gbps), and has been adopted by many converter suppliers, FPGA manufacturers and users. Generally speaking, ADCs using the JESD204B interface receive ADC sampling data through FPGA.

[0003] At present, ADCs using the JESD204B interface on the market often have a series of functions such as digital down-conversion, extraction, and filtering in addition to high-speed analog-to-digital conversion. Its function and performance testing is a challenge. Currently, there are mainly two types of JESD204B interface ADC data acquisition or testing solutions:

[0004] The first one (Wang Yuan, Deng Fangke, et al. A high-speed ADC acquisition system with dynamically configurable sampling rate (CN211239830 U)) is to send the sampling rate parameters through the host computer, and the FPGA calculates the N, R and other parameters related to the clock division in the JESD204B data acquisition system according to the sampling rate parameters, so as to configure the clock chip, and then configure the ADC model AD9680 and the FPGA data receiving module, and finally realize data acquisition at different sampling rates.

[0005] The second method (Zhang Hongze. JESD interface co-packet design method based on multiple sampling rates in FPGA (CN 111831055B)) is to set the reference clock and data receiving clock of JESD204 PHY to be unshared in the design, store the clock ratio parameters of JESD204 PHY in FPGA in advance according to different sampling rates, and use the configuration module designed in FPGA to configure JESD204 PHY, external clock chip AD9528 and ADC one by one according to the stored relevant parameters, so as to realize one FPGA project supporting multiple sampling rates.

[0006] In the prior art, the host computer in the first solution only acts as the sender of the sampling rate parameters and the receiver of the final data, and the clock parameter calculation and the storage of the device configuration data associated with different sampling rates are implemented in the FPGA. The same version of the FPGA program supports limited sampling rates. When adding a new sampling rate to the same chip, the FPGA design must be modified, which is not flexible enough.

[0007] In the second solution, the JESD204 PHY reference clock and the data receiving clock are not shared. The design requires an external clock chip to send an additional clock to the FPGA, which increases the complexity of the clock design. The same FPGA project supports multiple sampling rates depending on the number of stored clock ratio parameters, which has the same defects as the first solution.

[0008] Both of the above solutions have the problem of poor design flexibility, which is mainly manifested in: 1) It is unable to cope with the changes in the JESD204B application layer data mapping relationship under different L / M / F / NP parameter combinations of the same model device; 2) It is unable to well support other functional tests of the JESD204B interface ADC except the high-speed digital-to-analog conversion function; 3) It is unable to adapt to different models of JESD204B interface ADC devices through simple modifications or replace the clock chip in the system without modifying the FPGA design. Therefore, the above solutions are generally used in functional devices with only a few fixed sampling rates and a single ADC model.

[0009] For the chip test scenario of JESD204B interface ADC, the number of sampling rates and parameter combinations required to traverse the chip functions and evaluate the ADC indicators is very large, and the configuration differences between different ADCs are also large. A more flexible FPGA test driver architecture and supporting devices must be used to support different parameter combinations of the same model ADC and related tests of different models of ADC. Summary of the invention

[0010] The purpose of the present invention is to provide a fully reconfigurable JESD204B interface ADC test device and test method, which aims to improve the design of JESD204B interface ADC device configuration, data acquisition FPGA test driver and back-end application layer data mapping to the greatest extent possible.

[0011] The present invention is achieved through the following technical scheme: a fully reconfigurable JESD204B interface ADC test device, which cooperates with a host computer and a signal source to perform JESD204B interface ADC test, comprises an FPGA motherboard, an FMC daughter card with a chip test fixture, a switch matrix circuit, and a JESD204B clock generation circuit integrated into the FPGA motherboard or the FMC daughter card or existing independently; the FPGA motherboard is provided with a Xilinx FPGA, a DDR4 memory connected to the Xilinx FPGA, an Ethernet PHY and a network interface, and a GPIO and a power supply interface A; the FPGA motherboard and the FMC daughter card are detachably connected through the FMC interface; the chip test fixture is fixed to the FMC daughter card with the chip test fixture through bolts; the GPIO and the power supply interface on the switch matrix circuit and the GPIO and the power supply interface A on the FPGA motherboard are connected through cables.

[0012] In order to better realize the fully reconfigurable JESD204B interface ADC test device described in the present invention, the following setting structure is particularly adopted: the JESD204B clock generation circuit on the FPGA motherboard is controlled by XilinxFPGA, receives an external low-frequency reference clock, and generates multiple clocks required for system data acquisition, wherein the multiple clocks include: a common reference clock and SYSREF clock or SYSREF pulse of JESD204 PHY and MMCM to XilinxFPGA, a SYSREF clock or SYSREF pulse to JESD204B interface ADC, and a sampling reference clock of JESD204B interface ADC; wherein the sampling reference clock to JESD204B interface ADC can be generated by an external signal source having the same source as the external low-frequency reference clock; the JESD204B clock generation circuit can also be integrated into an FMC daughter card with a chip test fixture or exist independently, but are all controlled by XilinxFPGA in a certain form.

[0013] In order to better realize the fully reconfigurable JESD204B interface ADC test device described in the present invention, the following setting structure is particularly adopted: the DDR4 memory on the FPGA motherboard is controlled by Xilinx FPGA, used to cache the JESD204B interface ADC sampling data and can be sent to the Ethernet PHY and network interface in a controllable manner for transmission to the host computer.

[0014] In order to better realize the fully reconfigurable JESD204B interface ADC test device described in the present invention, the following setting structure is particularly adopted: the Ethernet PHY and network interface on the FPGA motherboard are used to communicate with the host computer through an ordinary network cable, and the ARP, IP, UDP and other protocols that must be used in two-way communication are implemented by XilinxFPGA; in addition to using RJ45 sockets and ordinary network cables to communicate with the host computer, the Ethernet PHY and network interface can also be replaced with various forms of optical fiber interfaces and matching optical fibers to realize communication. In addition to using the UDP protocol, the upper-layer communication can also use the more reliable TCP protocol.

[0015] In order to better realize the fully reconfigurable JESD204B interface ADC test device described in the present invention, the following setting structure is particularly adopted: the GPIO and power supply interface A on the FPGA motherboard, on the basis of providing necessary power supply, the remaining I / O interfaces of the GPIO and power supply interface A are controlled by Xilinx FPGA and are used to communicate with external low-speed peripherals such as switch matrix circuits.

[0016] In order to better realize the fully reconfigurable JESD204B interface ADC test device described in the present invention, the following setting structure is particularly adopted: the FMC daughter card with chip test fixture can be replaced as a whole according to different JESD204B interface ADC chip models. It includes a JESD204B interface ADC supporting chip test fixture, 1 to multiple signal input interfaces B, an external ADC sampling reference clock input interface, an external SYSREF clock or SYSREF pulse input interface, and a power management circuit corresponding to the chip to be tested; wherein the chip test fixture is used to load the chip to be tested; the signal input interface B is used to access the external analog signal that needs to be quantized by the JESD204B interface ADC; the external ADC sampling reference clock input interface is used to access the externally generated JESD204B interface ADC sampling reference clock; the external SYSREF clock or SYSREF pulse input interface is used to access the external SYSREF clock or SYSREF pulse; the JESD204B interface ADC sampling reference clock and the SYSREF clock or SYSREF pulse can be selectively accessed through the corresponding external input interface on the FMC daughter card with the chip test fixture, or can be selectively accessed through the relevant signal pins in the FMC interface, wherein the external input interface includes the external ADC sampling reference clock input interface, the external SYSREF clock or SYSREF pulse input interface.

[0017] In order to better realize the fully reconfigurable JESD204B interface ADC test device described in the present invention, the following setting structure is particularly adopted: the switch matrix circuit includes one to multiple signal input interfaces A, multiple signal output interfaces and GPIO and power supply interfaces, and the signal output interface is connected to the signal input interface B on the FMC daughter card with a chip test fixture through a radio frequency cable; the switch matrix circuit is controlled by the Xilinx FPGA on the FPGA motherboard, and the signal input interface A on the switch matrix circuit is connected to one of the signal output interfaces, which is used for switching the input signal channels on the FMC daughter card with the chip test fixture.

[0018] In order to better realize the fully reconfigurable JESD204B interface ADC test device described in the present invention, the following setting structure is particularly adopted: the Xilinx FPGA includes the following FPGA design modules: communication interface module, peripheral unified interface module, system clock management module, FPGA internal management module, ADC data cache control module, ADC driver module; when the Xilinx FPGA is powered on, one or more free-running clock sources are used to provide reference clocks for each FPGA design module, which is not affected by the JESD204B clock generation circuit;

[0019] Among them, the communication interface module is mainly used to drive Ethernet PHY, implement the upper layer protocol required for communication, implement the internal application communication protocol and provide two types of sub-interfaces; one type of sub-interface is a bidirectional instruction / address bus interface used by the host computer to manage various FPGA peripherals, and the other type of sub-interface is an ADC data interface used by the host computer to receive ADC sampling data of the JESD204B interface; the bidirectional instruction / address bus interface design supports a unified address space with an address width of 16 bits and a data width of 32 bits. Different peripherals are managed through different base addresses, and the peripheral access function registers corresponding to the offset addresses under the base addresses of different peripherals are completely unified. The definitions are shown in Table 1. The 16-bit unified address space can support the management of a large number of peripherals and has abundant expansion space.

[0020] Table 1

[0021]

[0022] The peripheral unified interface module (including peripheral unified interface module_1~peripheral unified interface module_N) is used to connect and convert the instruction / address bus of the communication interface module, transfer the related control of the peripheral access function register under the peripheral base address flexibly specified in the FPGA program to the peripheral driver, and convert the read-back data into the clock domain and store it in the read-back data register in the peripheral access function register. This module is designed as a parameterized general module. When instantiating, the peripheral base address, the address width (including read and write control bits) during actual access, and the read and write data width are specified, supporting a maximum of 32-bit address width and 32-bit data width;

[0023] The system clock management module is used to configure the clock chip in the JESD204B clock generation circuit, such as LMK04828 or HMC7044, so that it can generate the JESD204 PHY reference clock, SYSREF clock or SYSREF pulse, JESD204B interface ADC sampling reference clock, etc. required in the system, and optionally provide the clock chip initialization configuration. It must provide an external access interface to connect to the peripheral unified interface module;

[0024] The FPGA internal management module is used to define a series of internal registers to store a large number of control and status signals used inside the FPGA and controlled by the host computer through the communication interface module. Among them, a large number of control and status signals include request signals for controlling the clock chip to send SYSREF clocks or SYSREF pulses, etc.

[0025] The ADC data cache control module includes DDR4 memory driver and cache control logic, which is used to control and cache the raw data sampled by the JESD204B interface ADC. It relies on the FPGA internal management module to control its cache data volume and cache start control, and provides a cache data reading interface to supply the ADC data interface in the communication interface module.

[0026] The ADC driver module consists of two parts: the ADC configuration interface driver and the data interface driver. The ADC configuration interface driver can optionally provide the initialization configuration data of the JESD204B interface ADC, and must provide an external access interface to connect to the peripheral unified interface module, providing a signal path for the host computer to directly access the JESD204B interface ADC register.

[0027] To further better realize the fully reconfigurable JESD204B interface ADC test device described in the present invention, the following setting structure is particularly adopted: the data interface driver includes JESD204 PHY, JESD204, AXI interface conversion module (including AXI interface conversion module A, AXI interface conversion module B) and on-chip clock management module;

[0028] Among them, the JESD204 PHY configuration has Lane 8, and the communication rate and reference clock can be given a set of matching configurations as initial values, but the AXI configuration interface of the JESD204 PHY (602) must be enabled in the IP core configuration interface;

[0029] JESD204 specifies Lane 8, and the rest, such as whether to scramble, F parameter, K parameter, etc., can specify a set of matching configurations as initial values. The AXI configuration interface of JESD204 must also be enabled in the IP core configuration interface. The data output by JESD204 is sent directly to the ADC data cache control module without any mapping, and the upper computer completes the application layer data mapping according to the L / M / F / NP parameters;

[0030] The AXI interface conversion module mainly converts the AXI-Lite interface access timing into the access timing supported by the peripheral unified interface module;

[0031] The data interface driver implements the external input reference clock branching through the IBUFDS_GTE3 primitive, one path is provided to the JESD204 PHY, and the other path is provided to the on-chip clock management module. The on-chip clock management module is mainly based on Xilinx's MMCME3 or PLLE3, and is used to use the same reference clock as the JESD204 PHY to generate the data receiving clock rx_core_clk according to the fixed relationship of 1 / 40 line rate. The on-chip clock management module must enable its DRP management interface in the corresponding IP core configuration interface and mount it on the peripheral unified interface module.

[0032] A test method is implemented based on the fully reconfigurable JESD204B interface ADC test device, comprising the following steps:

[0033] Step S101: Determine the sampling rate, L / M / F parameters, decimation rate and other parameters, and fix the NP parameter to 16 to maintain maximum compatibility. Calculate the line rate and SYSREF frequency based on various parameters. At the same time, determine the K parameter, whether to scramble, and the JESD204 subclass;

[0034] Step S102: According to the line rate calculated in step S101, select a suitable JESD204 PHY reference clock frequency and a reference clock of the on-chip clock management module, and reconfigure the on-chip clock management module;

[0035] Step S103: Change the JESD204B interface ADC sampling reference clock frequency output by the external signal source; if the JESD204B interface ADC sampling reference clock is generated by the JESD204B clock generation circuit in the Xilinx FPGA, this step can be omitted;

[0036] Step S104: reconfigure the clock chip in the JESD204B clock generation circuit according to the JESD204B interface ADC sampling reference clock frequency, SYSREF frequency, and JESD204 PHY reference clock frequency;

[0037] Step S105: reconfigure the JESD204 PHY according to the line rate and the reference clock frequency;

[0038] Step S106: reconfigure JESD204 according to the K parameter, whether to scramble, and the JESD204 subclass;

[0039] Step S107: reconfigure the JESD204B interface ADC according to all parameters, and detect whether the PLL used for JESD204 communication inside the JESD204B interface ADC is locked;

[0040] Step S108: Reset JESD204 on the FPGA RX side, and reset JESD204 PHY in association, but the reset signal does not affect the new configuration data of the two, in preparation for establishing a JESD204 link between Xilinx FPGA and JESD204B interface ADC;

[0041] Step S109: Send a SYSREF clock or SYSREF pulse request signal, the clock chip in the JESD204B clock generation circuit sends the SYSREF clock or SYSREF pulse to the Xilinx FPGA and the JESD204B interface ADC, and the Xilinx FPGA and the JESD204B interface ADC complete the JESD204 link establishment;

[0042] Step S110: controlling the switch matrix circuit to switch its input signal to the expected ADC analog signal input channel as needed;

[0043] Step S111: Sending a data cache quantity and a data cache start control signal as needed to control Xilinx FPGA to cache a section of continuous data;

[0044] Step S112: After the data cache is completed, a control instruction is sent to upload the cached data in packets, and the host computer completes data reception, reorganization and JESD204B interface ADC application layer data mapping;

[0045] Step S113: using the mapped JESD204B interface ADC application layer data to complete the calculation of indicators such as SFDR, ENOB, SNR, SINAD, INL, and DNL;

[0046] Step S114: store the test results, generate a test report, etc.

[0047] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0048] (1) The present invention connects FPGA peripheral control interfaces such as JESD204B interface ADC configuration, JESD204B system clock switching, FPGA clock management module configuration, JESD204 PHY and JESD204 configuration, and signal channel switching control to a host computer communication module through a unified interface based on a base address, and also adds a controllable data cache module, so that the host computer can directly control the above peripherals mounted on the FPGA, and flexibly control the configuration sequence and configuration data of each FPGA peripheral without changing the FPGA design, complete the establishment of the data acquisition link and the caching and uploading of the JESD204B interface ADC sampling data, and dynamically perform application layer data mapping according to the L / M / F / NP parameters, so as to flexibly support chip testing tasks such as data acquisition and indicator evaluation under changes in sampling rate, JESD204 parameters and even chip models.

[0049] (2) Since the JESD204B interface ADC mainly configures the device and reads back the status through the SPI interface, and obtains the JESD204B interface ADC sampling data and some status signals through the JESD204B interface, the test device described in the present invention can completely cover the above two interfaces to support various functions and performance tests of such JESD204B interface ADC. In addition, its strong scalability can support the rapid addition of other auxiliary peripherals that may be required in the JESD204B interface ADC test, such as temperature sensors, programmable potentiometers, etc.

[0050] (3) The universal JESD204 interface ADC driver module used in the present invention reduces the output clock from the clock chip to the FPGA in one JESD204B clock generation circuit, adds a small amount of design to maximize compatibility, and supports ADC operating parameters such as Lane 1, 2, 3, 4, and 8.

[0051] (4) The present invention unifies and generalizes the FPGA peripheral access interface and reasonably sets the peripheral access register. The design of the maximum 32-bit address width and 32-bit data width is compatible with many existing interfaces on the market. It is convenient to mount various entities in the design as FPGA peripherals, and greatly reduces the requirements for FPGA design capabilities when adding FPGA peripherals, and has rich peripheral expansion space.

[0052] (5) The present invention can use a general-purpose PC to replace a dedicated device as the host computer, and with good FPGA design and a general communication interface, the cost is controllable and easy to integrate; all direct or indirect configuration data are stored on the general-purpose PC, there is no storage space bottleneck, and the test cases can be easily expanded as needed.

[0053] (6) The present invention uses the universal JESD204 application layer data mapping function of the host computer and other compatible designs to maximize the flexibility and portability of the test device. For different types of JESD204B interface ADC chips, only the FPGA pin mapping and test cases need to be changed, which greatly reduces the requirements for design capabilities of the transplantation.

[0054] (7) The clock chip in the JESD204B clock generation circuit in the system of the present invention does not need to provide initialization configuration data in the FPGA. When replacing the clock chip with the same configuration interface, there is no need to modify the FPGA design, and the substitutability of components in the system is also improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 This is a hardware layout diagram of a fully reconfigurable JESD204B interface ADC test device described in the present invention.

[0056] Figure 2 This is a design module diagram in the Xilinx FPGA.

[0057] Figure 3 The figure is a flow chart of the testing method of the present invention.

[0058] Among them, 1-FPGA motherboard, 2-FMC daughter card, 3-JESD204B clock generation circuit, 4-switch matrix circuit, 5-XilinxFPGA, 6-DDR4 memory, 7-Ethernet PHY and network interface, 8-GPIO and power supply interface A, 9-FMC interface, 10-chip test fixture, 11-GPIO and power supply interface, 12-signal input interface A, 13-signal output interface, 14-signal input interface B, 15-external ADC sampling reference clock input interface, 16-external SYSREF clock or SYSREF pulse input interface, 100-communication interface module, 300-system clock management module, 400-FPGA internal management module, 500-ADC data cache control module, 600-ADC driver module, 601-ADC configuration interface driver, 602-JESD204 PHY, 605-on-chip clock management module. DETAILED DESCRIPTION

[0059] The present invention is further described in detail below in conjunction with examples, but the embodiments of the present invention are not limited thereto.

[0060] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention.

[0061] It should be noted that similar numbers and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. At the same time, in the description of this application, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the term "and / or" in this application is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone.

[0062] In the description of the present invention, it is necessary to understand that the orientation or positional relationship indicated by terms, etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0063] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, and the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0064] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "connected" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can also be an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0065] Furthermore, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0066] Alternatively, the present invention may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented by software, the present invention may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part.

[0067] In this article, the term "includes", "comprising" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, principle, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, principle, article or device. In the absence of more restrictions, the elements defined by the sentence "comprising..." do not exclude the presence of other identical elements in the process, principle, article or device including the elements.

[0068] Glossary:

[0069] FPGA: Field Programmable Gate Array, field programmable gate array.

[0070] PHY: Physical, short for physical layer or physical layer chip.

[0071] FMC: FPGA Mezzanine Card, FPGA mezzanine card.

[0072] GPIO: General Purpose Input / Output, general input / output.

[0073] MMCM: Mixed-Mode Clock Manager, a module name for clock management inside Xilinx FPGA.

[0074] SYSREF: A generic term for a clock or pulse signal used for synchronization in JESD204B applications.

[0075] ARP: Address Resolution Protocol, a protocol in network communication that obtains the physical address based on the IP address.

[0076] IP protocol: IP, the abbreviation of Internet Protocol, Internet Protocol.

[0077] IP core: IP, the abbreviation of Intellectual Property, intellectual property core.

[0078] UDP: User Datagram Protocol.

[0079] JESD204: A serial interface standard for data converters released by the Joint Electron Device Engineering Council. In this article, it is also the name of the IP core used by Xilinx to implement the JESD204B data link layer on its FPGA.

[0080] JESD204 PHY: JESD204 physical layer interface, which in this article is also the name of the IP core used by Xilinx to implement this interface on its FPGAs.

[0081] AXI-Lite: AXI stands for Advanced Extensible Interface. It is an on-chip bus proposed by ARM for high performance, high bandwidth, and low latency. AXI-Lite is a lightweight version of this bus interface.

[0082] IBUFDS_GTE3: The name of the design primitive used to receive the differential reference clock of the gigabit transceiver in the Xilinx Ultrascale series FPGA.

[0083] MMCME3: Name of the MMCM design primitive in the Xilinx Ultrascale series FPGA.

[0084] PLL: Phase-Locked Loop.

[0085] PLLE3: PLLE3 is the name of the PLL design primitive in the Xilinx Ultrascale series FPGA.

[0086] DRP: Dynamic Reconfiguration Port, dynamic reconfiguration interface.

[0087] SFDR: Spurious Free Dynamic Range, spurious free dynamic range.

[0088] ENOB: Effective Number of Bits, effective number of bits.

[0089] SNR: Signal Noise Ratio, signal-to-noise ratio.

[0090] SINAD: Signal to Noise and Distortion Ratio.

[0091] INL: Integral Non-linearity, integral nonlinearity.

[0092] DNL: Differential Non-linearity, differential nonlinearity.

[0093] Embodiment 1:

[0094] The present invention designs a fully reconfigurable JESD204B interface ADC test device, which cooperates with a host computer (using an ordinary PC) and a signal source to perform JESD204B interface ADC testing. Figure 1 As shown, it includes an FPGA motherboard 1, an FMC daughter card 2 with a chip test fixture 10, a switch matrix circuit 4, and a JESD204B clock generation circuit 3 integrated into the FPGA motherboard 1 or the FMC daughter card 2 or existing independently; the FPGA motherboard 1 is provided with a Xilinx FPGA 5, a DDR4 memory 6 connected to the Xilinx FPGA 5, an Ethernet PHY and network interface 7, and a GPIO and power supply interface A8; the FPGA motherboard 1 and the FMC daughter card 2 are detachably connected through the FMC interface 9; the chip test fixture 10 is fixed to the FMC daughter card 2 with the chip test fixture by bolts; the GPIO and power supply interface 11 on the switch matrix circuit 4 and the GPIO and power supply interface A8 on the FPGA motherboard 1 are connected through cables.

[0095] The Xilinx FPGA 5 on the FPGA motherboard 1 uses Xilinx's Virtex Ultrascale series devices, whose ordinary gigabit transceiver GTH can reach a speed of 16.3 Gbps, and the transceiver GTY can reach a maximum of 32.75 Gbps. The former already supports the maximum speed specified by the JESD204B protocol, and the latter provides upgrade space for subsequent updated versions of the JESD204 design.

[0096] Embodiment 2:

[0097] This embodiment is further optimized on the basis of the above embodiment, and the same points as the above technical solution are not repeated here. Figure 1As shown, in order to better realize the fully reconfigurable JESD204B interface ADC test device described in the present invention, the following setting structure is particularly adopted: the JESD204B clock generation circuit 3 on the FPGA motherboard 1 is controlled by XilinxFPGA5, receives an external low-frequency reference clock, and generates multiple clocks required for system data acquisition, wherein the multiple clocks include: the JESD204 PHY and MMCM common reference clock and SYSREF clock or SYSREF pulse to XilinxFPGA5, the SYSREF clock or SYSREF pulse to the JESD204B interface ADC, and the JESD204B interface ADC sampling reference clock; wherein the sampling reference clock to the JESD204B interface ADC can be generated by an external signal source that is the same as the external low-frequency reference clock; the JESD204B clock generation circuit 3 can also be integrated into the FMC daughter card 2 with a chip test fixture or exist independently, but are all controlled by XilinxFPGA5 in a certain form.

[0098] Embodiment 3:

[0099] This embodiment is further optimized on the basis of any of the above embodiments, and the same points as the above technical solutions are not repeated here. Figure 1 As shown, in order to better realize the fully reconfigurable JESD204B interface ADC test device described in the present invention, the following setting structure is particularly adopted: the DDR4 memory 6 on the FPGA motherboard 1 is controlled by the XilinxFPGA5, and is used to cache the JESD204B interface ADC sampling data and can be controllably sent to the Ethernet PHY and network interface 7 for transmission to the host computer.

[0100] Embodiment 4:

[0101] This embodiment is further optimized on the basis of any of the above embodiments, and the same points as the above technical solutions are not repeated here. Figure 1 As shown, in order to better realize the fully reconfigurable JESD204B interface ADC test device described in the present invention, the following setting structure is particularly adopted: the Ethernet PHY and network interface 7 on the FPGA motherboard 1 are used to communicate with the host computer through an ordinary network cable, and the ARP, IP, UDP and other protocols that must be used in two-way communication are implemented by XilinxFPGA5; the Ethernet PHY and network interface 7 are used in addition to using Figure 1 In addition to the RJ45 socket and ordinary network cable shown in the figure for communicating with the host computer, they can also be replaced with various forms of optical fiber interfaces and matching optical fibers to achieve communication. In addition to using the UDP protocol, the upper layer communication can also use the more reliable TCP protocol.

[0102] Embodiment 5:

[0103] This embodiment is further optimized on the basis of any of the above embodiments, and the same points as the above technical solutions are not repeated here. Figure 1 As shown, in order to better realize the fully reconfigurable JESD204B interface ADC test device described in the present invention, the following setting structure is particularly adopted: the GPIO and power supply interface A8 on the FPGA motherboard 1, on the basis of providing necessary power supply, the remaining I / O interfaces of the GPIO and power supply interface A8 are controlled by XilinxFPGA5 and are used to communicate with external low-speed peripherals such as the switch matrix circuit 4, Figure 1 It just gives a possible form of convenient interconnection.

[0104] Embodiment 6:

[0105] This embodiment is further optimized on the basis of any of the above embodiments, and the same points as the above technical solutions are not repeated here. Figure 1 As shown, in order to better realize the fully reconfigurable JESD204B interface ADC test device described in the present invention, the following setting structure is particularly adopted: the FMC daughter card 2 with the chip test fixture 10 can be replaced as a whole according to the different JESD204B interface ADC chip models. It includes a JESD204B interface ADC supporting chip test fixture 10, 1 to multiple signal input interfaces B14, external ADC sampling reference clock input interface 15, external SYSREF clock or SYSREF pulse input interface 16, and a power management circuit corresponding to the chip to be tested; wherein the chip test fixture 10 is used to load the chip to be tested; the signal input interface B14 is used to access the external analog signal that needs to be quantized by the JESD204B interface ADC; the external ADC sampling reference clock input interface 15 is used to access the externally generated JESD204B interface ADC sampling reference clock; the external SYSREF clock or SYSREF pulse input interface 16 is used to access the external SYSREF clock or SYSREF pulse; the JESD204B interface ADC sampling reference clock and the SYSREF clock or SYSREF pulse can be selectively accessed through the corresponding external input interface on the FMC daughter card 2 with the chip test fixture 10, or can be selectively accessed through the relevant signal pins in the FMC interface 9, wherein the external input interface includes the external ADC sampling reference clock input interface 15 and the external SYSREF clock or SYSREF pulse input interface 16.

[0106] Embodiment 7:

[0107] This embodiment is further optimized on the basis of any of the above embodiments, and the same points as the above technical solutions are not repeated here. Figure 1As shown, in order to better realize the fully reconfigurable JESD204B interface ADC test device described in the present invention, the following setting structure is particularly adopted: the switch matrix circuit 4 includes 1 to multiple signal input interfaces A12, multiple signal output interfaces 13 and GPIO and power supply interface 11, and the signal output interface 13 is connected to the signal input interface B14 on the FMC daughter card 2 with the chip test fixture 10 through a radio frequency cable; the switch matrix circuit 4 is controlled by the XilinxFPGA5 on the FPGA motherboard 1, and the signal input interface A12 on the switch matrix circuit 4 is connected to one of the signal output interfaces 13, which is used for switching the input signal channel on the FMC daughter card 2 with the chip test fixture 10.

[0108] Embodiment 8:

[0109] This embodiment is further optimized on the basis of any of the above embodiments, and the same points as the above technical solutions are not repeated here. Figure 1 , Figure 2 As shown, in order to better realize the fully reconfigurable JESD204B interface ADC test device described in the present invention, the following setting structure is particularly adopted: the Xilinx FPGA5 includes the following FPGA design modules: a communication interface module 100, a peripheral unified interface module, a system clock management module 300, an FPGA internal management module 400, an ADC data cache control module 500, and an ADC driver module 600; when the Xilinx FPGA5 is powered on, one or more free-running clock sources are used to provide a reference clock for each FPGA design module, which is not affected by the JESD204B clock generation circuit 3;

[0110] Among them, the communication interface module 100 is mainly used to drive Ethernet PHY, implement the upper layer protocol required for communication, implement the internal application communication protocol and provide two types of sub-interfaces; one type of sub-interface is a bidirectional instruction / address bus interface for the host computer to manage each FPGA peripheral, and the other type of sub-interface is an ADC data interface for the host computer to receive ADC sampling data of the JESD204B interface; the bidirectional instruction / address bus interface design supports a unified address space, the address bit width is 16 bits, and the data bit width is 32 bits. Different peripherals are managed through different base addresses. The peripheral access function registers corresponding to the offset addresses under the base addresses of different peripherals are completely unified. The definitions are shown in Table 1. The 16-bit unified address space can support the management of a very large number of peripherals and has abundant expansion space.

[0111] Table 1

[0112]

[0113] The peripheral unified interface module (including peripheral unified interface module_1~peripheral unified interface module_N) is used to connect and convert the instruction / address bus of the communication interface module 100, transfer the related control of the peripheral access function register under the peripheral base address flexibly specified in the FPGA program to the peripheral driver, and convert the read-back data into the clock domain and store it in the read-back data register in the peripheral access function register. This module is designed as a parameterized general module. When instantiating, the peripheral base address, the address width (including read and write control bits) during actual access, and the read and write data width are specified. It supports a maximum of 32-bit wide addresses and 32-bit wide data; it supports the following types of access:

[0114] 1) SPI peripherals with 8-bit address and 16-bit data, 16-bit address and 8-bit data, or 8-bit address and 8-bit data;

[0115] 2) IIC peripherals with 16-bit address and 8-bit data, or 8-bit address and 8-bit data;

[0116] 3) AXI-Lite peripherals with 32-bit address and 32-bit data, and 16-bit address and 32-bit data;

[0117] 4) Other peripherals with similar situations and interfaces whose addresses do not exceed 32 bits and whose data does not exceed 32 bits.

[0118] The system clock management module 300 is used to configure the clock chip in the JESD204B clock generation circuit 3, typically LMK04828 or HMC7044, so that it generates the JESD204 PHY reference clock, SYSREF clock or SYSREF pulse, JESD204B interface ADC sampling reference clock, etc. required in the system, and optionally provides the clock chip initialization configuration, and must provide an external access interface to connect with the peripheral unified interface module;

[0119] The FPGA internal management module 400 is used to define a series of internal registers to store a large number of control and status signals used inside the FPGA and controlled by the host computer through the communication interface module 100, wherein a large number of control and status signals include: Figure 2 The GPIO management module described in, or the request signal for the control clock chip to send the SYSREF clock or SYSREF pulse, etc.;

[0120] The ADC data cache control module 500 includes a DDR4 memory driver and cache control logic, and is used to control and cache the JESD204B interface ADC sampling raw data, and relies on the FPGA internal management module 400 to control its cache data volume and cache start control, and provides a cache data reading interface to supply the ADC data interface in the communication interface module 100;

[0121] The ADC driver module 600 includes two parts: an ADC configuration interface driver 601 and a data interface driver. The ADC configuration interface driver 601 can optionally provide initialization configuration data for the JESD204B interface ADC, and must provide an external access interface to connect to the peripheral unified interface module, providing a signal path for the host computer to directly access the JESD204B interface ADC register.

[0122] Embodiment 9:

[0123] This embodiment is further optimized on the basis of any of the above embodiments, and the same points as the above technical solutions are not repeated here. Figure 1 , Figure 2 As shown, in order to better realize the fully reconfigurable JESD204B interface ADC test device described in the present invention, the following setting structure is particularly adopted: the data interface driver includes JESD204PHY602, JESD204, AXI interface conversion module (AXI interface conversion module A, AXI interface conversion module B) and on-chip clock management module 605;

[0124] Among them, JESD204 PHY602 is configured with Lane 8, and the communication rate and reference clock can be given a set of matching configurations as initial values, but the AXI configuration interface of JESD204 PHY (602) must be enabled in the IP core configuration interface;

[0125] JESD204 specifies Lane 8, and the rest, such as whether to scramble, F parameter, K parameter, etc., can specify a set of matching configurations as initial values. The AXI configuration interface of JESD204 must also be enabled in the IP core configuration interface. The data output by JESD204 is sent directly to the ADC data cache control module 500 without any mapping, and the upper computer completes the application layer data mapping according to the L / M / F / NP parameters;

[0126] The AXI interface conversion module mainly converts the AXI-Lite interface access timing into the access timing supported by the peripheral unified interface module;

[0127] The data interface driver implements external input reference clock branching through the IBUFDS_GTE3 primitive, one path is provided to JESD204 PHY602, and the other path is provided to the on-chip clock management module. The on-chip clock management module is mainly based on Xilinx's MMCME3 or PLLE3, and is used to use the same reference clock as JESD204 PHY602, and generate the data receiving clock rx_core_clk according to the fixed relationship of 1 / 40 line rate. The on-chip clock management module must enable its DRP management interface in the corresponding IP core configuration interface and mount it on the peripheral unified interface module.

[0128] In the FPGA design module, each design entity involved in the JESD204B interface ADC data acquisition, data caching, and transmission link can be controlled by the host computer, so the complete reconfiguration operation of each design entity can be realized to support data acquisition and functional testing under different chip sampling rates and L / M / F / NP / scrambling parameter combinations.

[0129] The host computer uses a general-purpose PC, which needs to have an Ethernet card as a medium for communication with the FPGA. Matlab can be selected as a platform for complete system reconfiguration and related indicator analysis and functional testing, and realizes the reconfiguration software interface, signal source control software interface, JESD204 application layer data mapping interface and general ADC indicator analysis interface of all design entities on the link of JESD204B interface ADC data acquisition and transmission. At the same time, the above operations can be integrated into different test cases as needed, which is convenient for testers to call directly.

[0130] Embodiment 10:

[0131] This embodiment is further optimized on the basis of any of the above embodiments, and the same points as the above technical solutions are not repeated here. Figure 1~Figure 3 As shown, a test method is implemented based on the fully reconfigurable JESD204B interface ADC test device, comprising the following steps:

[0132] Step S101 determines the operating parameters and calculates the line rate and SYSREF frequency: determines the sampling rate, L / M / F parameters, decimation rate and other parameters, and fixes the NP parameter to 16 to maintain maximum compatibility. The line rate and SYSREF frequency are calculated based on various parameters. At the same time, it is necessary to determine the K parameter, whether to scramble, and the JESD204 subclass;

[0133] Step S102 reconfigures the on-chip clock management module: according to the line rate calculated in step S101, selects a suitable JESD204 PHY602 reference clock frequency and a reference clock of the on-chip clock management module 605, and reconfigures the on-chip clock management module 605;

[0134] Step S103 changes the ADC sampling reference clock frequency output by the external information source: changes the JESD204B interface ADC sampling reference clock frequency output by the external signal source; if the JESD204B clock generation circuit 3 in the XilinxFPGA5 is used to generate the JESD204B interface ADC sampling reference clock, this step can be omitted;

[0135] Step S104 reconfigures the clock chip in the JESD204B clock generation circuit: reconfigures the clock chip in the JESD204B clock generation circuit 3 according to the JESD204B interface ADC sampling reference clock frequency, SYSREF frequency, and JESD204 PHY reference clock frequency;

[0136] Step S105 reconfigures JESD204 PHY: reconfigures JESD204PHY602 according to the line rate and reference clock frequency;

[0137] Step S106 reconfigures JESD204: reconfigures JED204 according to K parameter, whether to scramble, and JESD204 subclass;

[0138] Step S107 reconfigures the ADC and detects the PLL lock status: reconfigures the JESD204B interface ADC according to all parameters, and detects whether the PLL used for JESD204 communication inside the JESD204B interface ADC is locked;

[0139] Step S108 resets JESD204: resets JESD204 at the FPGA RX end, and resets JESD204 PHY602 in association, but the reset signal does not affect the new configuration data of the two, in preparation for establishing a JESD204 link between Xilinx FPGA5 and the JESD204B interface ADC;

[0140] Step S109 sends a SYSREF request to complete the link establishment: send a SYSREF clock or SYSREF pulse request signal, the clock chip in the JESD204B clock generation circuit 3 sends the SYSREF clock or SYSREF pulse to XilinxFPGA5 and the JESD204B interface ADC, and XilinxFPGA5 and the JESD204B interface ADC complete the JESD204 link establishment;

[0141] Step S110 controls the switch matrix circuit to switch the signal input destination channel: controls the switch matrix circuit 4 to switch its input signal to the expected ADC analog signal input channel as needed;

[0142] Step S111 controls FPGA to cache data: sends data cache quantity and data cache start control signal as needed to control Xilinx FPGA5 to cache a continuous data segment;

[0143] Step S112: Sub-packet uploading of cached data, and the host computer receiving, reorganizing and mapping the data: after the data cache is completed, a control instruction is sent to upload the cached data in packets, and the host computer completes data reception, reorganization and JESD204B interface ADC application layer data mapping;

[0144] Step S113 calculates various indicators: uses the mapped JESD204B interface ADC application layer data to calculate indicators such as SFDR, ENOB, SNR, SINAD, INL, and DNL;

[0145] Step S114: test result processing: storing test results, generating test reports, etc.

[0146] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Any simple modification or equivalent change made to the above embodiment based on the technical essence of the present invention shall fall within the protection scope of the present invention.

Claims

1. A fully reconfigurable JESD204B interface ADC test device, which cooperates with a host computer and a signal source to perform JESD204B interface ADC testing, characterized in that: The invention comprises an FPGA motherboard (1), an FMC daughter card (2) with a chip test fixture (10), a switch matrix circuit (4), and a JESD204B clock generation circuit (3) integrated into the FPGA motherboard (1) or the FMC daughter card (2) or existing independently; the FPGA motherboard (1) is provided with a Xilinx FPGA (5), a DDR4 memory (6) connected to the Xilinx FPGA (5), an Ethernet PHY and network interface (7), and a GPIO and power supply interface A (8); the FPGA motherboard (1) and the FMC daughter card (2) are detachably connected via an FMC interface (9); the switch matrix circuit (4) is connected to the FPGA motherboard (1) and the FMC daughter card (2) via an FMC interface (9); the switch matrix circuit (5 ... The GPIO and power supply interface (11) on the circuit (4) and the GPIO and power supply interface A (8) on the FPGA motherboard (1) are connected via a cable; the Xilinx FPGA (5) comprises the following FPGA design modules: a communication interface module (100), a peripheral unified interface module, a system clock management module (300), an FPGA internal management module (400), an ADC data cache control module (500), and an ADC driver module (600); when the Xilinx FPGA (5) is powered on, one or more free-running clock sources are used to provide reference clocks for each FPGA design module; The communication interface module (100) is mainly used to drive Ethernet PHY, implement the upper layer protocol required for communication, implement the internal application communication protocol and provide two types of sub-interfaces; The peripheral unified interface module is used to connect and convert the instruction / address bus of the communication interface module (100), transfer the relevant control of the peripheral access function register under the peripheral base address flexibly specified in the FPGA program to the peripheral driver, and convert the read-back data into the clock domain and store it in the read-back data register in the peripheral access function register; The system clock management module (300) is used to configure the clock chip in the JESD204B clock generation circuit (3) so that it generates the required JESD204 PHY reference clock, SYSREF clock or SYSREF pulse, and JESD204B interface ADC sampling reference clock, and provides clock chip initialization configuration and an external access interface for connection with the peripheral unified interface module; The FPGA internal management module (400) is used to define a series of internal registers for storing a large number of control and status signals used inside the FPGA and controlled by the host computer through the communication interface module (100), wherein the large number of control and status signals include a request signal for controlling the clock chip to send a SYSREF clock or a SYSREF pulse; The ADC data cache control module (500) comprises a DDR4 memory driver and cache control logic, and is used to control and cache JESD204B interface ADC sampling raw data, and relies on the FPGA internal management module (400) to control its cache data volume and cache start control, while providing a cache data reading interface to supply the ADC data interface in the communication interface module (100); The ADC driver module (600) comprises two parts: an ADC configuration interface driver (601) and a data interface driver. The ADC configuration interface driver (601) provides initialization configuration data for the JESD204B interface ADC, provides an external access interface for connection with a peripheral unified interface module, and provides a signal path for a host computer to directly access a JESD204B interface ADC register.

2. A fully reconfigurable JESD204B interface ADC test device according to claim 1, characterized in that: The JESD204B clock generation circuit (3) on the FPGA motherboard (1) is controlled by the Xilinx FPGA (5), receives an external low-frequency reference clock, and generates multiple clocks required for system data acquisition, wherein the multiple clocks include: a common reference clock and SYSREF clock or SYSREF pulse of the JESD204 PHY and MMCM to the Xilinx FPGA (5), a SYSREF clock or SYSREF pulse to the JESD204B interface ADC, and a sampling reference clock of the JESD204B interface ADC.

3. A fully reconfigurable JESD204B interface ADC test device according to claim 1, characterized in that: The DDR4 memory (6) on the FPGA motherboard (1) is controlled by the Xilinx FPGA (5) and is used to cache the JESD204B interface ADC sampling data and to controllably send the data to the Ethernet PHY and network interface (7) so as to be transmitted to the host computer.

4. The fully reconfigurable JESD204B interface ADC test device according to claim 1, characterized in that: The Ethernet PHY and network interface (7) on the FPGA motherboard (1) are used to communicate with a host computer via a common network cable, and the Xilinx FPGA (5) implements the ARP, IP, and UDP protocols that must be used in bidirectional communication.

5. The fully reconfigurable JESD204B interface ADC test device according to claim 1, characterized in that: The GPIO and power supply interface A (8) on the FPGA motherboard (1) provides necessary power supply, and the remaining I / O interfaces of the GPIO and power supply interface A (8) are controlled by the Xilinx FPGA (5) and are used to communicate with the switch matrix circuit (4).

6. A fully reconfigurable JESD204B interface ADC test device according to claim 1, characterized in that: The FMC daughter card (2) with a chip test fixture (10) comprises a chip test fixture (10), one or more signal input interfaces B (14), an external ADC sampling reference clock input interface (15), an external SYSREF clock or SYSREF pulse input interface (16), and a power management circuit corresponding to the chip to be tested; wherein the chip test fixture (10) is used to load the chip to be tested; the signal input interface B (14) is used to access an external analog signal that needs to be quantized by a JESD204B interface ADC; the external ADC sampling reference clock input interface (15) is used to access an externally generated JESD204B interface ADC sampling reference clock; and the external SYSREF clock or SYSREF pulse input interface (16) is used to access an external SYSREF clock or SYSREF pulse.

7. A fully reconfigurable JESD204B interface ADC test device according to claim 6, characterized in that: The switch matrix circuit (4) comprises one or more signal input interfaces A (12), a plurality of signal output interfaces (13) and a GPIO and power supply interface (11); the signal output interface (13) is connected to a signal input interface B (14) on an FMC daughter card (2) with a chip test fixture (10) via a radio frequency cable; the switch matrix circuit (4) is controlled by a Xilinx FPGA (5) on an FPGA motherboard (1) to connect the signal input interface A (12) on the switch matrix circuit (4) to one of the signal output interfaces (13) for switching input signal channels on the FMC daughter card (2).

8. The fully reconfigurable JESD204B interface ADC test device according to claim 1, characterized in that: The data interface driver includes a JESD204 PHY (602), a JESD204, an AXI interface conversion module and an on-chip clock management module (605); Among them, JESD204 PHY (602) is configured with Lane 8, and a set of matching configurations are given for the communication rate and reference clock as initial values, but the AXI configuration interface of JESD204 PHY (602) must be enabled in the IP core configuration interface; JESD204 specifies Lane 8, and specifies a set of matching configurations for whether to scramble, F parameter, and K parameter as initial values. The AXI configuration interface of JESD204 must also be enabled in the IP core configuration interface. The data output by JESD204 is sent directly to the ADC data cache control module (500) without any mapping, and the upper computer completes the application layer data mapping according to the L / M / F / NP parameters. The AXI interface conversion module mainly converts the AXI-Lite interface access timing into the access timing supported by the peripheral unified interface module; The data interface driver implements external input reference clock branching through the IBUFDS_GTE3 primitive, one path is provided to the JESD204 PHY (602), and the other path is provided to the on-chip clock management module. The on-chip clock management module is mainly based on Xilinx's MMCME3 or PLLE3, and is used to use the same reference clock as the JESD204 PHY (602) to generate a data receiving clock rx_core_clk according to a fixed relationship of 1 / 40 line rate. The on-chip clock management module must enable its DRP management interface in the corresponding IP core configuration interface and be mounted on the peripheral unified interface module.

9. A testing method, characterized in that: A fully reconfigurable JESD204B interface ADC test device according to any one of claims 1 to 8 is implemented, comprising the following steps: Step S101: Determine the sampling rate, L / M / F parameters, and decimation rate parameters, and fix the NP parameter to 16, calculate the line rate and SYSREF frequency based on various parameters, and determine the K parameter, whether to scramble, and the JESD204 subclass; Step S102: According to the line rate calculated in step S101, select a suitable JESD204 PHY (602) reference clock frequency and a reference clock of the on-chip clock management module (605), and reconfigure the on-chip clock management module (605); Step S103: changing the JESD204B interface ADC sampling reference clock frequency output by the external signal source; If the JESD204B clock generation circuit (3) in the Xilinx FPGA (5) is used to generate the JESD204B interface ADC sampling reference clock, this step can be omitted; Step S104: reconfigure the clock chip in the JESD204B clock generation circuit (3) according to the JESD204B interface ADC sampling reference clock frequency, SYSREF frequency, and JESD204 PHY reference clock frequency; Step S105: reconfigure the JESD204 PHY according to the line rate and the reference clock frequency (602); Step S106: reconfigure JESD204 according to the K parameter, whether to scramble, and the JESD204 subclass; Step S107: reconfigure the JESD204B interface ADC according to all parameters, and detect whether the PLL used for JESD204 communication inside the JESD204B interface ADC is locked; Step S108: Reset the JESD204 on the FPGA RX side, and reset the JESD204 PHY (602) in association, but the reset signal does not affect the new configuration data of the two, in preparation for establishing a JESD204 link between the Xilinx FPGA (5) and the JESD204B interface ADC; Step S109: Send a SYSREF clock or SYSREF pulse request signal, the clock chip in the JESD204B clock generation circuit (3) sends the SYSREF clock or SYSREF pulse to the Xilinx FPGA (5) and the JESD204B interface ADC, and the Xilinx FPGA (5) and the JESD204B interface ADC complete the JESD204 link establishment; Step S110: controlling the switch matrix circuit (4) to switch its input signal to the expected ADC analog signal input channel as required; Step S111: sending a data cache quantity and a data cache start control signal as needed to control Xilinx FPGA (5) to cache a section of continuous data; Step S112: After the data cache is completed, a control instruction is sent to upload the cached data in packets, and the host computer completes data reception, reorganization and JESD204B interface ADC application layer data mapping; Step S113: using the mapped JESD204B interface ADC application layer data to complete the calculation of SFDR, ENOB, SNR, SINAD, INL, and DNL indicators; Step S114: store the test results and generate a test report.

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