Display driving circuit and display panel

Abstract

The present application discloses a display driving circuit and a display panel, wherein the display driving circuit comprises: a first light emitting device and a second light emitting device arranged in a stacked manner; a pixel driving circuit connected to the first light emitting device and the second light emitting device; the pixel driving circuit comprises: a driving circuit connected to the anodes of the first light emitting device and the second light emitting device for controlling the voltage applied to the first light emitting device and the second light emitting device; a first switching circuit arranged between the driving circuit and the anode of the first light emitting device for controlling the first light emitting device to emit light; a second switching circuit arranged between the driving circuit and the anode of the second light emitting device for controlling the second light emitting device to emit light; a dimming circuit connected to the control ends of the first switching circuit and the second switching circuit for outputting a frequency modulation signal to control the first light emitting device to emit light and the second light emitting device to emit light. Through the above circuit, the problem of uneven luminous efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of display panels, and in particular to a display driving circuit and a display panel. Background Art

[0002] Tandem OLED (stacked OLED) is a stacked evaporation display technology. It is a device structure that connects multiple light-emitting units in series through a charge generation layer. Tandem OLED is a new type of display technology. Its principle is to use a transparent connecting layer to connect several light-emitting devices in series. Specifically, an OLED pixel consists of an anode, a cathode, and a multilayer organic material sandwiched in the middle. When current passes through, the anode emits holes and the cathode emits electrons. These holes and electrons meet and recombine in the organic layer to generate light. In the tandem OLED, this structure is replicated twice to form two light-emitting layers, which are connected together by a charge generation layer (CGL). When current passes through, some holes and electrons recombine in the first light-emitting layer to emit light, and the remaining holes and electrons pass through the CGL and recombine again in the second light-emitting layer to emit light.

[0003] Compared with traditional single-layer OLED, Tandem OLED has many advantages. First, it can achieve higher brightness, more than twice. Second, Tandem OLED has lower energy consumption. Compared with single-layer OLED, it is more efficient and consumes less energy when displaying images of the same brightness. Third, its device life is extended by more than four times, which can effectively alleviate the common "burn-in" problem of OLED screens. Fourth, while achieving high brightness, Tandem OLED can also reduce some optical components and simplify circuits, thereby reducing weight and thickness.

[0004] Despite this, there are still many problems to be solved in the actual development and application of Tandem OLED. First of all, in order for Tandem OLED to display the correct picture, the two layers of OLED stacked inside must have exactly the same display effect. However, even if the parameters and processes of OLED screens in the same production line are exactly the same, there will still be differences in display effects between different batches, which makes it difficult for the yield rate of Tandem OLED screens to reach a high level. At the same time, since the two layers of Tandem OLED adopt a parallel topological structure, the voltage at both ends of the layer close to the cathode is greatly affected by the voltage drop of the previous layer. Due to the difference in the process of the two evaporation depositions, the difference in display effects between the two layers is almost inevitable. Summary of the invention

[0005] The main technical problem solved by the present application is to provide a display driving circuit and a display panel to improve the problem of uneven luminous efficiency of stacked OLEDs.

[0006] To solve the above-mentioned problem, the present application provides a display driving circuit in the first aspect, wherein the display driving circuit includes: a first light-emitting device and a second light-emitting device stacked together; a pixel driving circuit connected to the first light-emitting device and the second light-emitting device; the pixel driving circuit includes: a driving circuit, the driving circuit is connected to the anodes of the first light-emitting device and the second light-emitting device, and is used to control the voltage applied to the first light-emitting device and the second light-emitting device; a first switching circuit, arranged between the driving circuit and the anode of the first light-emitting device, and is used to control the first light-emitting device to emit light; a second switching circuit, arranged between the driving circuit and the anode of the second light-emitting device, and is used to control the second light-emitting device to emit light; a dimming circuit, connected to the control ends of the first switching circuit and the second switching circuit, and is used to output a frequency modulation signal to control the first light-emitting device and the second light-emitting device to emit light.

[0007] The first switch circuit includes a first switch transistor, the second switch circuit includes a second switch transistor, and the first switch transistor and the second switch transistor are a group of transistors with opposite driving characteristics.

[0008] Wherein, the driving circuit includes: a driving transistor, the gate of the driving transistor is connected to the first signal line, the first electrode is connected to the power line, and the second electrode is connected to the anodes of the first light-emitting device and the second light-emitting device; a first reset transistor is arranged between the first signal line and the gate of the driving transistor, the first electrode of the first reset transistor is connected to the first signal line, and the second electrode is connected to the gate of the driving transistor, and is used to control the driving transistor; a storage capacitor, the first plate of the storage capacitor is connected to the gate of the driving transistor, and the second plate of the storage capacitor is connected to the power line, and is used to maintain the gate voltage of the driving transistor; a third switching transistor is arranged between the first electrode of the driving transistor and the data line; the first electrode of the third switching transistor is connected to the data line, and the third switching transistor The second electrode of the body tube is connected to the first electrode of the driving transistor; a fourth switching transistor is arranged between the second electrode of the driving transistor and the gate of the driving transistor; the first electrode of the fourth switching transistor is connected to the second electrode of the driving transistor, and the second electrode of the fourth switching transistor is connected to the gate of the driving transistor and the first plate of the storage capacitor; a fifth switching transistor is arranged between the power line and the first electrode of the driving transistor; the first electrode of the fifth switching transistor is connected to the power line, and the second electrode is connected to the first electrode of the driving transistor; a second reset transistor, the first electrode of the second reset transistor is connected to the second signal line, and the second electrode is connected to the anodes of the first light-emitting device and the second light-emitting device, for resetting the anodes of the first light-emitting device and the second light-emitting device.

[0009] The gates of the third switch transistor and the fifth switch transistor are connected to the same signal line, and the third switch transistor and the fifth switch transistor are a group of transistors with opposite driving characteristics.

[0010] Wherein, the dimming circuit includes: a low-potential driving transistor, the gate of the low-potential driving transistor is connected to the control circuit, the first electrode is connected to the low-potential signal line, and the second electrode is connected to the gates of the first switching transistor and the second switching transistor; a high-potential driving transistor, the gate of the high-potential driving transistor is connected to the control circuit, the first electrode is connected to the high-potential signal line, and the second electrode is connected to the gates of the first switching transistor and the second switching transistor.

[0011] Wherein, the low potential driving transistor and the high potential driving transistor are a group of transistors with opposite driving characteristics; wherein, the control circuit includes a low potential control circuit, a high potential control circuit and a bootstrap capacitor; the bootstrap capacitor, the first plate of the bootstrap capacitor is connected to the low potential control circuit and the gate of the high potential driving transistor, and the second plate is connected to the high potential control circuit and the gate of the low potential driving transistor; wherein, the low potential control circuit provides a low potential driving signal to the gate of the low potential driving transistor through the bootstrap capacitor to control the conduction of the low potential driving transistor; the high potential control circuit provides a low potential driving signal to the gate of the high potential driving transistor through the bootstrap capacitor The gate provides a high potential drive signal to control the conduction of the high potential drive transistor; the low potential control circuit includes a first transistor, the gate of the first transistor is connected to the first control signal line, the first electrode is connected to the low potential signal line, and the second electrode is connected to the first plate of the bootstrap capacitor; the high potential control circuit includes a second transistor, the gate of the second transistor is connected to the second control signal line, the first electrode is connected to the high potential signal line, and the second electrode is connected to the second plate of the bootstrap capacitor; wherein the first control signal line and the second control signal line are a group of clock signals with opposite phases; the first transistor and the second transistor are a group of transistors with opposite driving characteristics.

[0012] In which, the control circuit also includes: a sixth switching transistor, the gate of the sixth switching transistor is connected to the first control signal line, the first electrode is connected to the second plate of the bootstrap capacitor, the second electrode is connected to the gate of the low-potential driving transistor, and is turned on at the same time as the first transistor, and is used to control the low-potential driving signal output by the low-potential control circuit to be transmitted to the gate of the low-potential driving transistor to control the conduction of the low-potential driving transistor; a seventh switching transistor, the gate of the seventh switching transistor is connected to the second control signal line, the first electrode is connected to the first plate of the bootstrap capacitor, and the second electrode is connected to the gate of the high-potential driving transistor; the seventh switching transistor is turned on at the same time as the second transistor, and is used to control the high-potential driving signal output by the high-potential control circuit to be transmitted to the gate of the high-potential driving transistor to control the conduction of the high-potential driving transistor.

[0013] Among them, the control circuit includes a cascade signal and a pre-charge transistor; the gate of the pre-charge transistor is connected to the second control signal line, the first electrode is connected to the cascade signal, and the second electrode is connected to the first plate of the bootstrap capacitor, which is used to charge the bootstrap capacitor in the pre-charge stage.

[0014] In which, the control circuit also includes: a first isolation transistor, which is arranged between the second transistor and the second plate of the bootstrap capacitor, and is used to isolate the cascade signal from the high-potential signal line during the pre-charging stage to achieve pre-charging of the bootstrap capacitor; a second isolation transistor, which is arranged between the seventh switching transistor and the gate of the high-potential driving transistor, and is used to isolate the cascade signal from the high-potential driving transistor during the pre-charging stage to prevent the high-potential driving transistor from being turned on prematurely.

[0015] Wherein, the control circuit also includes: a second capacitor, a first plate of the second capacitor is connected to the gate of the first isolation transistor, and the second plate is grounded, for controlling the on / off of the first isolation transistor; a third capacitor, a first plate of the third capacitor is connected to the gate of the second isolation transistor, and the second plate is grounded, for controlling the on / off of the second isolation transistor; a first diode, a forward end is connected to the cascade signal, and a reverse end is connected to the first electrode of the pre-charge transistor; a second diode, a forward end is connected to the first plate of the second capacitor and the gate of the first isolation transistor, and a reverse end is connected to the second electrode of the first transistor; a third diode, a forward end is connected to the first plate of the third capacitor and the gate of the second isolation transistor, and a reverse end is connected to the second electrode of the first transistor; wherein, the first isolation transistor and the second isolation transistor are N-type transistors.

[0016] Wherein, the control circuit includes a reset signal line connected to the bootstrap capacitor, the second capacitor and the third capacitor; the reset signal line is respectively connected to the first plate of the bootstrap capacitor, the first plate of the second capacitor and the first plate of the third capacitor, and is used to reset the bootstrap capacitor, the second capacitor and the third capacitor.

[0017] In order to solve the above-mentioned problem, the present application provides a display panel in a second aspect, wherein the display panel includes the display driving circuit described in any embodiment of the first aspect.

[0018] The beneficial effect of the present application is: according to the luminous efficiency of the two stacked layers of OLED, the duty cycle of the frequency modulation signal output to the first switch circuit and the second switch circuit is adjusted by the dimming circuit, thereby changing the luminous frequency of the two stacked layers of OLED, improving the problem of uneven luminous efficiency of the two stacked light-emitting devices OLED, thereby effectively adjusting the panel display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 A schematic diagram of an OLED stacking structure provided in this application;

[0021] Figure 2 A schematic diagram of the structure of an embodiment of a display driving circuit provided by the present application;

[0022] Figure 3 This is a schematic structural diagram of a specific embodiment of the driving circuit of the present application;

[0023] Figure 4 A timing signal diagram of an embodiment of a driving circuit of the present application;

[0024] Figure 5 This is a schematic diagram of the equivalent circuit structure of the driving circuit of the present application in the reset stage;

[0025] Figure 6 This is a schematic diagram of the equivalent circuit structure of the driving circuit of this application in the sampling stage;

[0026] Figure 7 This is a schematic diagram of the equivalent circuit structure of the driving circuit of the present application in the light-emitting stage;

[0027] Figure 8 This is a schematic structural diagram of a first embodiment of a dimming circuit of the present application;

[0028] Fig. 9 This is a schematic diagram of the specific structure of the second embodiment of the dimming circuit of the present application;

[0029] Fig.10 This is a timing signal diagram of the second specific embodiment of the dimming circuit of the present application;

[0030] Fig.11 This is a schematic diagram of the equivalent circuit structure of the dimming circuit of this application in the pre-charging stage;

[0031] Fig.12 This is a schematic diagram of the equivalent circuit structure of the dimming circuit of the present application in the first driving stage;

[0032] Fig.13 This is a schematic diagram of the equivalent circuit structure of the dimming circuit of the present application in the second driving stage;

[0033] Fig.14 This is a schematic diagram of the equivalent circuit structure of the dimming circuit of this application in the blank phase;

[0034] Fig.15 It is a structural schematic diagram of an embodiment of a display panel of the present application.

[0035] first light emitting device OLED1; second light emitting device OLED2; driving circuit 11; dimming circuit 12; first switch transistor T1; second switch transistor T2; driving transistor DT1; first reset transistor T3; storage capacitor Cst; third switch transistor T4; fourth switch transistor T5; fifth switch transistor T6; second reset transistor T7; power line VDD; first signal line Vint; second signal line Vint-Anode; first control line PSCAN (N); second control line PSCAN (N-1); data line data; frequency modulation signal EN (N); low potential drive transistor DT11; high potential drive transistor Body transistor DT12; control circuit 120; low potential signal line VGL; high potential signal line VGH; low potential control circuit 121; high potential control circuit 122; bootstrap capacitor C1; first transistor T11; second transistor T12; sixth switch transistor T13; seventh switch transistor T14; first control signal line XCK; second control signal line CK; pre-charge transistor T15; pre-charge holding transistor T10; cascade signal EN (N-1); first isolation transistor T16; second isolation transistor T17; reset signal line CLR; second capacitor C2; third capacitor C3; first diode D1; second diode D2; third diode D3. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0037] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms of "a", "said", and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless otherwise clearly indicated above, and "multiple" generally includes at least two, but does not exclude the inclusion of at least one.

[0038] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the objects associated with each other are in an "or" relationship. The terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0039] It should be understood that the terms "include", "comprises" or any other variations used herein are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, the elements defined by the sentence "includes..." do not exclude the presence of other identical elements in the process, method, article or device that includes the elements.

[0040] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back...), such directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0041] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The presence of the phrase at each location in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0042] The present application provides a display driving circuit, which includes: a first light emitting device and a second light emitting device stacked together.

[0043] Specifically, see Figure 1 , Figure 1 This is a schematic diagram of an OLED stacking structure provided in this application. Figure 1As shown, it includes a first light-emitting device OLED1 and a second light-emitting device OLED2, which are stacked. Under the premise of keeping the light emission directions coincident, the driving of the light-emitting layer is connected in parallel in the circuit structure. The OLED structure stack includes a hole injection layer (HIL), a hole transport layer (HTL), a light-emitting layer (EM), an electron transport layer (ETL), and an electron injection layer (EIL). Figure 1 As shown in (a) of FIG. 1 , the first light emitting device OLED1 and the second light emitting device OLED2 share a cathode layer. Figure 1 As shown in (b), the cathode layer can be replaced by a transparent thin film metal to form a charge generation layer (CGL), which can play a role in connecting the light-emitting layer. The OLED stacked structure is connected to the display drive circuit through through holes in the PDL (pixel definition layer) and other areas. It should be noted that Figure 1 Among the functional layers shown, such as EM-R / G / B (red / green / blue light-emitting layers), a host light-emitting material and a guest light-emitting material may also be included. For the purpose of adjusting the transmission rate, an electron / hole transport layer may also be added with a related blocking layer. Figure 1 The cases shown are only for explanation of the scheme and are not the only reference for actual application.

[0044] The display driving circuit is arranged at the anode end of the OLED stacked structure, and is used to control the light emission of the first light emitting device and the second light emitting device.

[0045] Please refer to Figure 2 , Figure 2 This is a schematic diagram of the structure of an embodiment of a display driving circuit provided by the present application. Figure 2 As shown, the display driving circuit includes: a first light emitting device OLED1 and a second light emitting device OLED2 and a pixel driving circuit connected to the anodes of the first light emitting device OLED1 and the second light emitting device OLED2. The first light emitting device OLED1 and the second light emitting device OLED2 are stacked and arranged. The specific structure can be as follows Figure 1 as shown in .

[0046] The pixel driving circuit includes: a driving circuit 11 , a first switching circuit, a second switching circuit and a dimming circuit 12 .

[0047] The driving circuit 11 is connected to anodes of the first light emitting device OLED1 and the second light emitting device OLED2 and is used to control the driving voltage applied to the first light emitting device OLED1 and the second light emitting device OLED2.

[0048] The first switch circuit is arranged between the driving circuit 11 and the anode of the first light emitting device OLED1, and is used to control the first light emitting device OLED1 to emit light. When the first switch circuit is turned on, the first light emitting device OLED1 emits light, and when the first switch circuit is turned off, the first light emitting device OLED1 does not emit light.

[0049] The second switch circuit is arranged between the driving circuit 11 and the anode of the second light emitting device OLED2, and is used to control the second light emitting device OLED2 to emit light. The on-off of the second switch circuit controls whether the second light emitting device OLED2 emits light.

[0050] The dimming circuit 12 is connected to the control terminals of the first switch circuit and the second switch circuit, and is used to output a frequency modulation signal to control the duty cycle of the light emission of the first light emitting device OLED1 and the second light emitting device OLED2.

[0051] In this embodiment, the first switch circuit and the second switch circuit are not turned on at the same time, so that the first light emitting device OLED1 and the second light emitting device OLED2 emit light respectively, thereby ensuring that the anode voltages applied to the first light emitting device OLED1 and the second light emitting device OLED2 are the same.

[0052] Specifically, the first switch circuit includes a first switch transistor T1, and the second switch circuit includes a second switch transistor T2. The first switch transistor T1 and the second switch transistor T2 are a group of transistors with opposite driving characteristics. When the first switch transistor T1 is turned on, the second switch transistor T2 is turned off; when the first switch transistor T1 is turned off, the second switch transistor T2 is turned on. The frequency modulation signal includes a low level signal and a high level signal.

[0053] In a specific embodiment, please refer to Figure 3 , Figure 3 FIG. 1 is a schematic diagram of a specific embodiment of the driving circuit of the present application. Figure 3 As shown, the driving circuit 11 includes a driving transistor DT1, a first reset transistor T3, a storage capacitor Cst, a third switch transistor T4, a fourth switch transistor T5, and a fifth switch transistor T6.

[0054] The gate of the driving transistor DT1 is connected to the first signal line Vint, the first electrode of the driving transistor DT1 is connected to the power line VDD, and the second electrode of the driving transistor DT1 is connected to the anodes of the first light-emitting device OLED1 and the second light-emitting device OLED2. The voltage flowing through the anodes of the first light-emitting device OLED1 and the second light-emitting device OLED2 is controlled by controlling the gate voltage of the driving transistor DT1. Among them, one of the first electrode and the second electrode is a source electrode, and the other is a drain electrode.

[0055] The first reset transistor T3 is disposed between the first signal line Vint and the gate of the driving transistor DT1. The first electrode of the first reset transistor T3 is connected to the first signal line Vint, and the second electrode is connected to the gate of the driving transistor DT1, and is used to control the driving transistor DT1, specifically, to control the starting voltage or reset voltage of the driving transistor DT1.

[0056] A first plate of the storage capacitor Cst is connected to the gate of the driving transistor DT1 , and a second plate of the storage capacitor Cst is connected to the power line VDD for maintaining the voltage on the gate of the driving transistor DT1 .

[0057] The third switch transistor T4 is disposed between the first electrode of the driving transistor DT1 and the data line data. The first electrode of the third switch transistor T4 is connected to the data line data, and the second electrode is connected to the first electrode of the driving transistor DT1. The third switch transistor T4 is used to charge a voltage to the gate of the driving transistor DT1 through the driving transistor DT1 during the sampling phase.

[0058] The fourth switch transistor T5 is disposed between the second electrode of the driving transistor DT1 and the gate of the driving transistor DT1. The first electrode of the fourth switch transistor T5 is connected to the second electrode of the driving transistor DT1, and the second electrode is connected to the gate of the driving transistor DT1 and the first electrode plate of the storage capacitor Cst, and is used to connect the gate and drain of the driving transistor DT1 in the sampling phase to charge the gate of the second driving transistor DT1.

[0059] The fifth switch transistor T6 is disposed between the power line VDD and the first electrode of the driving transistor DT1. The first electrode of the fifth switch transistor T6 is connected to the power line VDD, and the second electrode is connected to the first electrode of the driving transistor DT1 and the second electrode of the third switch transistor T4. It is used to control the connection between the power line VDD and the driving transistor DT1.

[0060] The driving circuit 11 further includes a second reset transistor T7, a first electrode of the second reset transistor T7 is connected to the second signal line Vint-Anode, and a second electrode is connected to the anodes of the first light-emitting device OLED1 and the second light-emitting device OLED2, for resetting the anodes of the first light-emitting device OLED1 and the second light-emitting device OLED2 to prevent the first light-emitting device OLED1 and the second light-emitting device OLED2 from being turned on in advance. Specifically, the second electrode of the second reset transistor T7 is connected to the first electrode of the first switch transistor T1 and the first switch transistor T2. In other embodiments, the second reset transistor T7 can be omitted, which is not limited here.

[0061] The gates of the third switch transistor T4 and the fifth switch transistor T6 can be connected to the same signal line, and the third switch transistor T4 and the fifth switch transistor T6 are a group of transistors with opposite driving characteristics, one of which is an N-type transistor and the other is a P-type transistor.

[0062] It should be noted that the first electrode and the second electrode of each transistor in the present application refer to the source terminal and the drain terminal of the transistor respectively, and no specific limitation is made here.

[0063] In this embodiment, the driving circuit includes a reset phase, a sampling phase and a light emitting phase. Figure 4 , Figure 4 This is a timing signal diagram of an embodiment of the driving circuit of the present application.

[0064] The gates of the first reset transistor T3 and the second reset transistor T7 are connected to the same signal line. Specifically, the gates of the third switch transistor T4 and the fifth switch transistor T6 are connected to the first control line PSCAN (N), and the gates of the first reset transistor T3 and the second reset transistor T7 are connected to the second control line PSCAN (N-1).

[0065] In the reset phase, the second control line PSCAN (N-1) controls the first reset transistor T3 and the second reset transistor T7 to turn on, so as to reset the gate of the driving transistor DT1 and the anodes of the first light emitting device OLED1 and the second light emitting device OLED2. Figure 5 , Figure 5 FIG. 1 is a schematic diagram of the equivalent circuit structure of the driving circuit of the present application in the reset stage. Figure 5 As shown, in the reset phase, the first reset transistor T3 and the second reset transistor T7 are turned on, and the second signal line Vint-Anode resets the anode to ensure that the anode potential of the light-emitting device is in the starting phase, while preventing the first switch transistor T1 and the second switch transistor T2 from turning on prematurely. The first signal line Vint charges the gate terminal of the driving transistor DT1 to refresh the data potential stored in the previous frame, and charges the storage capacitor Cst to ensure that the driving transistor DT1 is turned on during the sampling phase. In this embodiment, the fifth switch transistor T6 can also be turned on. Preferably, the fifth switch transistor T6 is not turned on.

[0066] In the sampling phase, the first control line PSCAN (N) controls the third switch transistor T4 and the fourth switch transistor T5 to be turned on at the same time, and the driving transistor DT1 is also turned on to charge the gate of the driving transistor DT1. Figure 6 , Figure 6Schematic diagram of the equivalent circuit structure of the driving circuit of the present application in the sampling stage. The third switch transistor T4, the driving transistor DT1, and the fourth switch transistor T5 form a sampling loop. The data line data enters Cst through the third switch transistor T4, the fourth switch transistor T5, and the driving transistor DT1. At this time, the voltage at one end of the storage capacitor Cst connected to the gate of the driving transistor DT1 is Vdata+Vth, that is, the sampling voltage of the first plate of the storage capacitor Cst is Vdata+Vth.

[0067] In the light-emitting stage, the first control line PSCAN (N) controls the fifth switch transistor T6 to be turned on in the light-emitting stage. Figure 7 , Figure 7 This is a schematic diagram of the equivalent circuit structure of the driving circuit of the present application in the light-emitting stage. In the light-emitting stage, the first switch transistor T1 and the second switch transistor T2 are alternately turned on under the action of the frequency modulation signal EN (N). The driving transistor DT1 generates a data current under the action of the storage capacitor Cst and the power supply voltage VDD to drive the light-emitting device OLED to emit light. Among them, the frequency modulation signal EN (N) is a jump signal including a high-level signal and a low-level signal.

[0068] In this embodiment, the threshold voltage Vth is charged into the gate of the driving transistor DT1 during the sampling phase, thereby eliminating the influence of the threshold voltage Vth drift.

[0069] It should be noted that in other embodiments, the gate of the driving transistor DT1 may be precharged through other circuit structures or data signal lines. In other embodiments, the second reset transistor T7 may be omitted to reset the anode of the light emitting device OLED.

[0070] In one embodiment, the dimming circuit 12 may be composed of two control signal lines with opposite phases.

[0071] In a further embodiment, the dimming circuit 12 includes a low potential driving transistor DT11 and a high potential driving transistor DT12. The low potential driving transistor DT11 is used to output a low level signal to the first switch transistor T1 and the second switch transistor T2, and the high potential driving transistor DT12 is used to output a high potential signal to the first switch transistor T1 and the second switch transistor T2.

[0072] Please refer to Figure 8 , Figure 8 FIG. 1 is a schematic diagram of the structure of the first embodiment of the dimming circuit of the present application. Figure 8As shown, the gate of the low potential driving transistor DT11 is connected to the control circuit 120, the first electrode is connected to the low potential signal line VGL, the second electrode is connected to the gates of the first switch transistor T1 and the second switch transistor T2, and the frequency modulation signal EN (N) is output. The gate of the high potential driving transistor DT12 is connected to the control circuit 120, the first electrode is connected to the high potential signal line VGH, and the second electrode is connected to the gates of the first switch transistor T1 and the second switch transistor T2.

[0073] In this embodiment, the low potential signal and the high potential signal transmitted by the low potential signal line VGL and the high potential signal line VGH are a set of clock signals with opposite phases.

[0074] Further, the control circuit 120 includes a low potential control circuit 121, a high potential control circuit 122 and a bootstrap capacitor C1. The first plate of the bootstrap capacitor C1 is connected to the low potential control circuit 121 and the gate of the high potential driving transistor DT12, and the second plate is connected to the high potential control circuit 122 and the gate of the low potential driving transistor DT11. The low potential control circuit 121 transmits a low potential driving signal to the second plate through the first plate of the bootstrap capacitor C1, and then provides a low potential driving signal to the gate of the low potential driving transistor DT11, so that the low potential driving transistor DT11 is turned on, thereby outputting a low level frequency modulation signal to the gate of the first switch transistor T1 and the second switch transistor T2. The high potential control circuit also provides a high potential driving signal to the gate of the high potential driving transistor DT12 through the bootstrap effect of the bootstrap capacitor C1, so as to control the high potential driving transistor DT12 to be turned on, thereby outputting a high level frequency modulation signal to the gate of the first switch transistor T1 and the second switch transistor T2.

[0075] In this embodiment, the low potential control circuit 121 and the high potential control circuit 122 are used to transmit clock signals with opposite phases to the high potential driving transistor DT12 and the low potential driving transistor DT11, so as to control the high potential driving transistor DT12 and the low potential driving transistor DT11 to be turned on respectively, and form a jumpable frequency modulation signal EN (N). In other embodiments, the control circuit 120 can be directly composed of a group of clock signals with opposite phases, which is not limited here.

[0076] In a specific embodiment, the low potential control circuit 121 includes a first transistor T11, the gate of the first transistor T11 is connected to the first control signal line XCK, the first electrode is connected to the low potential signal line VGL, and the second electrode is connected to the first plate of the bootstrap capacitor C1. The high potential control circuit 122 includes a second transistor T12, the gate of the second transistor T12 is connected to the second control signal line CK, the first electrode is connected to the high potential signal line VGH, and the second electrode is connected to the second plate of the bootstrap capacitor C1. Among them, the first control signal line XCK and the second control signal line CK are a group of clock signals with opposite phases. In other embodiments, the first transistor T11 and the second transistor T12 can also be a group of transistors with opposite driving characteristics, one of which is an N-type transistor and the other is a P-type transistor, and the first control signal line XCK and the second control signal line CK have the same phase.

[0077] In this specific embodiment, when the low potential control circuit 121 is working, the high potential control circuit 122 is not working; when the high potential control circuit 122 is working, the low potential control circuit 121 is not working.

[0078] It should be noted that the working cycle of the dimming circuit 12 includes a first driving stage P2 and a second driving stage P3. In the first driving stage P2, the low potential control circuit 121 controls the low potential driving transistor DT11 to be turned on; in the second driving stage P3, the high potential control circuit 122 controls the high potential driving transistor DT12 to be turned on, thereby outputting a jumping frequency modulation signal EN (N).

[0079] In a further embodiment, the control circuit 120 further includes a sixth switch transistor T13 and a seventh switch transistor T14.

[0080] The gate of the sixth switch transistor T13 is connected to the first control signal line XCK, the first electrode is connected to the second electrode plate of the bootstrap capacitor C1, and the second electrode is connected to the gate of the low potential drive transistor DT11. The sixth switch transistor T13 and the first transistor T11 are turned on at the same time, and the sixth switch transistor T13 is used to control whether the low potential drive signal output by the low potential control circuit 121 can be transmitted to the gate of the low potential drive transistor DT11, thereby controlling the conduction of the low potential drive transistor DT11.

[0081] The gate of the seventh switch transistor T14 is connected to the second control signal line CK, the first electrode is connected to the first plate of the bootstrap capacitor C1, and the second electrode is connected to the gate of the high potential driving transistor DT12. The seventh switch transistor T14 and the second transistor T12 are turned on at the same time, and are used to control the high potential driving signal output by the high potential control circuit 122 to be transmitted to the gate of the high potential driving transistor DT12, thereby controlling the conduction of the high potential driving transistor DT12.

[0082] At the same time, in the first driving stage P2, when the sixth switch transistor T13 is turned on, the seventh switch transistor T14 is turned off, thereby preventing the seventh switch transistor T14 from being turned on, thereby affecting the voltage division on the bootstrap capacitor C1. In the second driving stage P3, when the seventh switch transistor T14 is turned on, the sixth switch transistor T13 is turned off, thereby preventing the sixth switch transistor T13 from being turned on, thereby affecting the voltage division on the bootstrap capacitor C1.

[0083] It should be noted that in other embodiments, the sixth switch transistor T13 and the seventh switch transistor T14 may not be provided. This is because the high potential drive transistor DT12 is a high potential conduction transistor. Even if the low potential voltage on the first transistor T11 is transmitted to the high potential drive transistor DT12, the high potential drive transistor DT12 will not be turned on, but other effects (such as voltage division) will occur. Similarly, the low potential drive transistor DT11 is a low potential conduction transistor. Even if the high potential voltage on the second transistor T12 is transmitted to the low potential drive transistor DT11, the low potential drive transistor DT11 will not be turned on.

[0084] In the above embodiment, the low potential driving transistor DT11 and the high potential driving transistor DT12 are a group of transistors with opposite driving characteristics. Specifically, the low potential driving transistor DT11 is a low potential conduction transistor, and the high potential driving transistor DT12 is a high potential conduction transistor.

[0085] In other embodiments, the low potential driving transistor DT11 and the high potential driving transistor DT12 may also be transistors with the same driving characteristics, and the first electrodes of the first transistor T11 and the second transistor T12 are connected to the same potential signal (such as both are high potential signals VGH or both are low potential signals VGL). In this case, the connection between the first transistor T11 and the high potential driving transistor DT12 can be cut off by the sixth switch transistor T13, and the connection between the second transistor T12 and the low potential driving transistor DT11 can be cut off by the seventh switch transistor T14, thereby controlling the low potential driving transistor DT11 to be turned on or controlling the high potential driving transistor DT12 to be turned on respectively.

[0086] It should be noted that, through the coupling effect of the bootstrap capacitor C1, when the voltage on the first plate decreases, the voltage on the second plate also decreases, thereby reducing the gate voltage of the low-potential driving transistor DT11, thereby driving the low-potential driving transistor DT11 to turn on. When the voltage on the second plate increases, the voltage on the first plate also increases, thereby increasing the gate voltage of the high-potential driving transistor DT12, thereby driving the high-potential driving transistor DT12 to turn on.

[0087] In further embodiments, please refer to Fig. 9 , Fig. 9 Schematic diagram of the specific structure of the second embodiment of the dimming circuit of the present application. Fig. 9 As shown, the control circuit 120 Figure 8 On the basis of , it also includes a cascade signal EN (N-1) and a pre-charge transistor T15. It is used to charge the starting voltage into the bootstrap capacitor C1, so that the bootstrap capacitor C1 has a bootstrap effect, and then in the driving stage, it can control the conduction of the high-potential driving transistor DT12 and the low-potential driving transistor DT11, and make this conduction have a certain stability. Specifically, the gate of the pre-charge transistor T15 is connected to the second control signal line CK, the first electrode is connected to the cascade signal EN (N-1), and the second electrode is connected to the first plate of the bootstrap capacitor C1, which is used to charge the bootstrap capacitor C1 in the pre-charge stage P1, so that the first plate of the bootstrap capacitor C1 is positively charged. Among them, the cascade signal EN (N-1) is the frequency modulation signal of the previous stage. In a specific embodiment, the dimming circuit 12 is a cascaded GOA circuit, and the frequency modulation signal output by the dimming circuit 12 is also connected to the input end of the pre-charge transistor T15 of the next stage.

[0088] In order to ensure that the pre-charging transistor T15 successfully charges the bootstrap capacitor C1, and avoid the charging failure caused by the lower plate of the bootstrap capacitor C1 being in a floating state when the pre-charging transistor T15 charges the bootstrap capacitor C1, the control circuit 120 further includes a pre-charging holding transistor T10, the gate of the pre-charging holding transistor T10 is connected to the cascade signal EN (N-1), the first electrode is grounded, and the second electrode is connected to the second plate of the bootstrap capacitor C1, which is used to make the bootstrap capacitor C1 work in the pre-charging stage P1, so as to charge the first plate of the bootstrap capacitor C1 so that it can store the initial potential.

[0089] Furthermore, the control circuit 120 further includes: a first isolation transistor T16 and a second isolation transistor T17. The first isolation transistor T16 is disposed between the second transistor T12 and the second electrode plate of the bootstrap capacitor C1, and is used to isolate the cascade signal EN (N-1) from the high potential signal line VGH in the pre-charging phase P1, thereby pre-charging the bootstrap capacitor C1 and avoiding the cascade signal EN (N-1) from being directly connected to the high potential signal line VGH, thereby affecting the pre-charging of the bootstrap capacitor C1.

[0090] The second isolation transistor T17 is disposed between the seventh switch transistor T14 and the gate of the high potential driving transistor DT12, and is used to isolate the cascade signal EN (N-1) from the high potential driving transistor DT12 in the pre-charging phase P1, so as to prevent the cascade signal EN (N-1) from being transmitted to the high potential driving transistor DT12, thereby causing the high potential driving transistor DT12 to be turned on in advance.

[0091] The control circuit 120 further includes a second capacitor C2, a third capacitor C3, a first diode D1, a second diode D2, and a third diode D3.

[0092] The first plate of the second capacitor C2 is connected to the gate of the first isolation transistor T16, and the second plate is grounded, for controlling the on / off of the first isolation transistor T16. In other embodiments, the on / off of the first isolation transistor T16 can also be controlled by a low potential signal line.

[0093] The first plate of the third capacitor C3 is connected to the gate of the second isolation transistor T17, and the second plate is grounded, for controlling the on / off of the second isolation transistor T17. In other embodiments, the on / off of the second isolation transistor T17 can also be controlled by a low potential signal line.

[0094] The forward end of the first diode D1 is connected to the cascade signal EN (N-1), and the reverse end is connected to the first electrode of the pre-charge transistor T15 and the gate of the pre-charge holding transistor T10, so that in the pre-charge phase P1, the pre-charge voltage can be charged into the bootstrap capacitor C1 through the pre-charge transistor T15.

[0095] The forward end of the second diode D2 is connected to the first plate of the second capacitor C2 and the gate of the first isolation transistor T16, and the reverse end is connected to the second electrode of the first transistor T11, and is used to release the high potential voltage on the second capacitor C2 in the first driving stage P2, so that the voltage on the second capacitor C2 is a low potential voltage, and then control the first isolation transistor T16 to be in the on state after the first driving stage P2.

[0096] The third diode D3 has a forward end connected to the first electrode of the third capacitor C3 and the gate of the second isolation transistor T17, and a reverse end connected to the second electrode of the first transistor T11, and is used to release the high potential voltage on the third capacitor C3 in the first driving stage P2, so that the voltage on the third capacitor C3 is a low potential voltage, and then control the second isolation transistor T17 to be in a conducting state in the stage after the first driving stage P2.

[0097] Furthermore, the control circuit 120 also includes a reset signal line CLR connected to the bootstrap capacitor C1, the second capacitor C2, and the third capacitor C3. The reset signal line CLR is respectively connected to the first plate of the bootstrap capacitor C1, the first plate of the second capacitor C2, and the first plate of the third capacitor C3, and is used to reset the bootstrap capacitor C1, the second capacitor C2, and the third capacitor C3. Specifically, the reset signal line CLR is a high potential, and before the pre-charge stage P1, the high potential is charged to the second capacitor C2 and the third capacitor C3 and maintained, so that the first isolation transistor T16 and the second isolation transistor T17 are in a cut-off state in the pre-charge stage P1, thereby avoiding the formation of signal crosstalk.

[0098] In other embodiments, the on / off of the first isolation transistor T16 and the second isolation transistor T17 may also be controlled by other low-potential signal lines, thereby playing an isolation role in the pre-charging stage P1.

[0099] In this embodiment, the dimming circuit 12 also includes a Blanking stage. In the Blanking stage, the bootstrap capacitor C1, the second capacitor C2 and the third capacitor C3 are reset, mainly to reset the potential of C1, in preparation for the next frame. At the same time, the second capacitor C2 and the third capacitor C3 are reset, so that the first isolation transistor T16 and the second isolation transistor T17 do not work.

[0100] Please read further Fig.10 , Fig.10 This is a timing signal diagram of the second specific embodiment of the dimming circuit of the present application. Fig.10 As shown, the driving of the dimming circuit includes a pre-charging stage P1, an alternating first driving stage P2 and a second driving stage P3. In this embodiment, the low potential driving transistor DT11, the first isolation transistor T16 and the second isolation transistor T17 are N-type transistors (low potential conduction transistors), and the rest are P-type transistors (high potential conduction transistors).

[0101] In the pre-charge phase P1, the second control signal line CK controls the pre-charge transistor T15 to turn on, and the cascade signal EN (N-1) charges the first plate of the bootstrap capacitor C1 through the pre-charge transistor T15. The cascade signal EN (N-1) controls the pre-charge holding transistor T10 to turn on, so that the bootstrap capacitor C1 has storage capacity, so that the first plate of the bootstrap capacitor C1 can store initial charge. For details, please refer to Fig.11 , Fig.11 This is a schematic diagram of the equivalent circuit structure of the dimming circuit of the present application in the pre-charging stage, wherein the first diode D1 ensures forward charging and avoids power failure on the bootstrap capacitor C1.

[0102] In the first driving stage P2, the first control signal line XCK outputs a high level, controls the first transistor T11 to be turned on and the sixth switch transistor T13 to be turned on; at the same time, a low potential voltage is charged to the gate of the first isolation transistor T16 and the second isolation transistor T17 (discharging process), thereby controlling the first isolation transistor T16 and the second isolation transistor T17 to be turned on. For details, please refer to Fig.12 , Fig.12This is a schematic diagram of the equivalent circuit structure of the dimming circuit of the present application in the first driving stage. Among them, the second diode D2 and the third diode D3 are used to maintain the low potential voltage on the second capacitor C2 and the third capacitor C3. In this stage, the low potential signal on the low potential control signal line VGL is transmitted to the first plate of the bootstrap capacitor C1 through the first transistor T11. According to the coupling effect of the bootstrap capacitor C1, the gate voltage of the low potential driving transistor DT11 is pulled down, so that the low potential driving transistor DT11 is turned on, and then the low potential frequency modulation signal EN (N) is output. At the same time, due to the isolation effect of the second transistor T12 and the seventh switch transistor T14, even if the first isolation transistor T16 and the second isolation transistor T17 are turned on, the charge on the bootstrap capacitor C1 will not be discharged.

[0103] In the second driving stage P3, the second control signal line CK outputs a high potential, controlling the second transistor T12, the seventh switch transistor T14, and the pre-charge transistor T15 to be turned on. Since the gate voltages of the first isolation transistor T16 and the second isolation transistor T17 are kept at a low potential, the first isolation transistor T16 and the second isolation transistor T17 are still in the turned-on state in the second driving stage P3. For details, please refer to Fig.13 , Fig.13 This is a schematic diagram of the equivalent circuit structure of the dimming circuit of the present application in the second driving stage. In this stage, the high-potential signal on the high-potential control signal line VGH is transmitted to the second plate of the bootstrap capacitor C1 through the second transistor T12, and according to the coupling effect of the bootstrap capacitor C1, the gate voltage of the high-potential driving transistor DT12 is pulled up, so that the high-potential driving transistor DT12 is turned on, and then the high-potential frequency modulation signal EN (N) is output.

[0104] It should be noted that since the voltage difference between the first plate and the second plate of the bootstrap capacitor C1 is fixed, under the action of the high potential signal line VGH and the low potential signal line VGL, its pull-up voltage and pull-down voltage also have a certain stability, thereby improving the stability of the output signal of the dimming circuit 12. At the same time, the conduction condition of the high potential driving transistor DT12 and the low potential driving transistor DT11 is that the absolute value of the gate-source voltage Vgs (Vgate-Vsource)>Vth. In the circuit model shown in the example, Vsource is the EM (N) terminal, which is in a floating state. When in the working state, due to the effects of the parasitic capacitance of the output terminal, EM (N) may still retain a potential close to the previous timing in some abnormal states. At the same time, due to the voltage drop of the node voltage of the second transistor T12, the sixth switch transistor T13, the seventh switch transistor T14, and the first isolation transistor T16, the voltage when the high potential signal line VGH and the low potential signal line VGL are directly connected and transmitted to the gate of the high potential transistor D12 and the low potential driving transistor D11 may be slightly lower than VGH, VGL (absolute value). In this case, Vgate-Vsource may be relatively close to or lower than Vth, causing the problem that the high potential transistor D12 and the low potential driving transistor D11 cannot be turned on, affecting the function. The bootstrap capacitor C1 ensures the stability of the voltage drop transmitted from the high potential signal line VGH and the low potential signal line VGL to the gates of the high potential transistor D12 and the low potential drive transistor D11 .

[0105] Furthermore, the driving cycle of the dimming circuit 12 includes a blank phase, which can be specifically referred to in Fig.14 , Fig.14 This is a schematic diagram of the equivalent circuit structure of the dimming circuit of the present application in the blank phase. In this phase, the bootstrap capacitor C1, the second capacitor C2, and the third capacitor C3 are reset through the reset signal line CLR, the first isolation transistor T16 and the second isolation transistor T17 are turned off, and the potential on the bootstrap capacitor C1 is reset to prepare for the next frame.

[0106] In the light-emitting stage, the dimming circuit 12 controls the alternation of the first driving stage P2 and the second driving stage P3 to realize the output of the frequency modulation signal EN (N). The frequency modulation signal EN (N) is a jump signal including a high-level signal and a low-level signal, wherein the duty ratio of the high-level signal and the low-level signal can be adjusted according to the control signal on the first control signal line XCK and the second control signal line CK. For example, when the light-emitting efficiency of the first light-emitting device OLED1 is significantly lower than that of the second light-emitting device OLED2, the duty ratio of the high-potential control signal output by the second control signal line CK can be increased, and the duty ratio of the high-potential control signal output by the first control signal line XCK can be reduced, thereby increasing the duty ratio (light-emitting time) of the first light-emitting device OLED1, and then increasing the brightness of the light-emitting layer corresponding to the first light-emitting device OLED1.

[0107] The beneficial effects of this embodiment are: the anode of the pixel driving circuit is set on both sides of the light-emitting group, and the output end of the driving transistor is set as two parallel anode outputs, which ensures that the voltage applied to the two groups of OLED anode terminals is equal in the working state. By designing the control transistors (the first switching transistor and the second switching transistor) belonging to the two anode outputs as a group of TFTs with opposite channel types, the two light-emitting layers are controlled to emit light in a time-sharing manner. By changing the pulse signal output by the dimming circuit (GOA) to a frequency-modulated signal with positive and negative values, the duty cycle can be adjusted at the same time. According to the luminous efficiency of the two-layer light-emitting device OLED, by adjusting the respective duty cycles of CK and XCK, the PWM (pulse width modulation) frequency of the two layers of OLED is changed, so that the panel display effect can be effectively adjusted.

[0108] The present application also provides a display panel. Fig.15 , Fig.15 FIG. 1 is a schematic diagram of the structure of an embodiment of a display panel of the present application. Fig.15 As shown, the display panel includes a substrate 10, a pixel driving circuit layer 20 is disposed on the substrate 10, and an OLED stacking structure 30 is disposed on the pixel driving circuit layer 20. The OLED stacking structure 30 includes a first light emitting device OLED1 and a second light emitting device OLED2. The first light emitting device OLED1 and the second light emitting device OLED2 are stacked in a manner as shown in FIG. Figure 1 In the parallel stacking shown in (a), specifically, the light-emitting layers of the first light-emitting device OLED1 and the second light-emitting device OLED2 are stacked, the anodes of the first light-emitting device OLED1 and the second light-emitting device OLED2 are arranged on both sides of the stacked light-emitting layer, and the cathodes of the first light-emitting device OLED1 and the second light-emitting device OLED2 are shared. Fig.15The first anode 31 of the first light-emitting device OLED1 and the second anode 32 of the second light-emitting device OLED2 are arranged on the upper and lower sides of the stacked light-emitting layer, wherein the second anode 32 of the second light-emitting device OLED2 can be connected to the pixel driving circuit in the lower pixel driving circuit layer 20 through the via hole on the pixel definition layer.

[0109] The pixel driving circuit layer 20 is provided with a plurality of transistors, and the plurality of transistors are interconnected to form the pixel driving circuit in the above embodiment. The pixel driving circuit is connected to the anodes of the first light emitting device OLED1 and the second light emitting device OLED2 arranged in a stacked manner, and is used to control the light emission of the first light emitting device OLED1 and the second light emitting device OLED2. The first light emitting device OLED1 can be arranged above the second light emitting device OLED2, or the second light emitting device OLED2 can be arranged above the first light emitting device OLED1, which is not limited here. The OLED stacked structure 30 is as shown in FIG. Figure 1 As shown in (a) in .

[0110] The above are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A display driving circuit, characterized in that: The display driving circuit comprises: A first light emitting device and a second light emitting device are stacked; a pixel driving circuit connected to the first light emitting device and the second light emitting device; The pixel driving circuit comprises: a driving circuit connected to anodes of the first light emitting device and the second light emitting device and configured to control a voltage applied to the first light emitting device and the second light emitting device; A first switch circuit is provided between the driving circuit and the anode of the first light emitting device, and is used to control the first light emitting device to emit light; A second switch circuit is provided between the driving circuit and the anode of the second light emitting device, and is used to control the second light emitting device to emit light; a dimming circuit connected to the control ends of the first switch circuit and the second switch circuit, and configured to output a frequency modulation signal to control the first light emitting device and the second light emitting device to emit light; wherein the frequency modulation signal is a transition signal including a high level signal and a low level signal in the light emitting stage; The dimming circuit includes a low potential driving transistor, a high potential driving transistor, a low potential control circuit, a high potential control circuit and a bootstrap capacitor; the first plate of the bootstrap capacitor is connected to the low potential control circuit and the gate of the high potential driving transistor, and the second plate is connected to the high potential control circuit and the gate of the low potential driving transistor; The low potential control circuit provides a low potential drive signal to the gate of the low potential drive transistor through the bootstrap capacitor to control the low potential drive transistor to be turned on, thereby controlling the low potential drive transistor to output the frequency modulation signal including a low level signal; The high potential control circuit provides a high potential driving signal to the gate of the high potential driving transistor through the bootstrap capacitor to control the high potential driving transistor to be turned on, thereby controlling the high potential driving transistor to output the frequency modulation signal including a high level signal.

2. The display driving circuit according to claim 1, characterized in that: The first switch circuit includes a first switch transistor, the second switch circuit includes a second switch transistor, and the first switch transistor and the second switch transistor are a group of transistors with opposite driving characteristics.

3. The display driving circuit according to claim 1, characterized in that: The driving circuit comprises: a driving transistor, wherein a gate of the driving transistor is connected to a first signal line, a first electrode of the driving transistor is connected to a power line, and a second electrode of the driving transistor is connected to anodes of the first light emitting device and the second light emitting device; a first reset transistor, disposed between the first signal line and the gate of the driving transistor, wherein a first electrode of the first reset transistor is connected to the first signal line, and a second electrode of the first reset transistor is connected to the gate of the driving transistor, for controlling the driving transistor; A storage capacitor, wherein a first plate of the storage capacitor is connected to the gate of the driving transistor, and a second plate of the storage capacitor is connected to the power line, for maintaining a gate voltage of the driving transistor; A third switch transistor is disposed between the first electrode of the driving transistor and the data line; the first electrode of the third switch transistor is connected to the data line, and the second electrode of the third switch transistor is connected to the first electrode of the driving transistor; a fourth switch transistor, disposed between the second electrode of the driving transistor and the gate of the driving transistor; a first electrode of the fourth switch transistor is connected to the second electrode of the driving transistor, and a second electrode of the fourth switch transistor is connected to the gate of the driving transistor and the first plate of the storage capacitor; a fifth switch transistor, disposed between the power line and the first electrode of the driving transistor; the first electrode of the fifth switch transistor is connected to the power line, and the second electrode of the fifth switch transistor is connected to the first electrode of the driving transistor; A second reset transistor, wherein a first electrode of the second reset transistor is connected to a second signal line, and a second electrode of the second reset transistor is connected to anodes of the first light emitting device and the second light emitting device, for resetting the anodes of the first light emitting device and the second light emitting device.

4. The display driving circuit according to claim 3, characterized in that: The gate of the third switch transistor and the gate of the fifth switch transistor are connected to the same signal line, and the third switch transistor and the fifth switch transistor are a group of transistors with opposite driving characteristics.

5. The display driving circuit according to claim 1, characterized in that: The low potential driving transistor and the high potential driving transistor are a group of transistors with opposite driving characteristics; The low potential control circuit comprises a first transistor, a gate of the first transistor is connected to a first control signal line, a first electrode of the first transistor is connected to the low potential signal line, and a second electrode of the first transistor is connected to a first plate of the bootstrap capacitor; The high potential control circuit comprises a second transistor, a gate of the second transistor is connected to a second control signal line, a first electrode of the second transistor is connected to the high potential signal line, and a second electrode of the second transistor is connected to a second plate of the bootstrap capacitor; The first control signal line and the second control signal line are a group of clock signals with opposite phases; the first transistor and the second transistor are a group of transistors with opposite driving characteristics.

6. The display driving circuit according to claim 5, characterized in that: The control circuit further comprises: a sixth switch transistor, wherein the gate of the sixth switch transistor is connected to the first control signal line, the first electrode of the sixth switch transistor is connected to the second electrode plate of the bootstrap capacitor, the second electrode of the sixth switch transistor is connected to the gate of the low potential drive transistor, the sixth switch transistor is turned on at the same time as the first transistor, and is used to control the low potential drive signal output by the low potential control circuit to be transmitted to the gate of the low potential drive transistor, so as to control the conduction of the low potential drive transistor; A seventh switching transistor, wherein the gate of the seventh switching transistor is connected to the second control signal line, the first electrode of the seventh switching transistor is connected to the first plate of the bootstrap capacitor, and the second electrode of the seventh switching transistor is connected to the gate of the high-potential driving transistor; the seventh switching transistor and the second transistor are turned on at the same time, and are used to control the high-potential driving signal output by the high-potential control circuit to be transmitted to the gate of the high-potential driving transistor, so as to control the conduction of the high-potential driving transistor.

7. The display driving circuit according to claim 6, characterized in that: The control circuit includes a cascade signal and a pre-charge transistor; The gate of the pre-charge transistor is connected to the second control signal line, the first electrode of the pre-charge transistor is connected to the cascade signal, and the second electrode of the pre-charge transistor is connected to the first plate of the bootstrap capacitor, for charging the bootstrap capacitor in the pre-charge stage.

8. The display driving circuit according to claim 7, characterized in that: The control circuit further comprises: A first isolation transistor is disposed between the second transistor and the second electrode plate of the bootstrap capacitor, and is used to isolate the cascade signal from the high potential signal line in the pre-charging stage to achieve pre-charging of the bootstrap capacitor; The second isolation transistor is arranged between the seventh switch transistor and the gate of the high potential drive transistor, and is used to isolate the cascade signal from the high potential drive transistor in the pre-charge stage to prevent the high potential drive transistor from being turned on in advance.

9. The display driving circuit according to claim 8, characterized in that: The control circuit further comprises: A second capacitor, wherein a first plate of the second capacitor is connected to the gate of the first isolation transistor, and a second plate of the second capacitor is grounded, and is used to control on / off of the first isolation transistor; a third capacitor, wherein a first plate of the third capacitor is connected to the gate of the second isolation transistor, and a second plate of the third capacitor is grounded, and is used to control the on / off of the second isolation transistor; a first diode, wherein a forward end of the first diode is connected to the cascade signal, and a reverse end of the first diode is connected to a first electrode of the pre-charge transistor; a second diode, wherein a forward end of the second diode is connected to the first plate of the second capacitor and the gate of the first isolation transistor, and a reverse end of the second diode is connected to the second electrode of the first transistor; a third diode, wherein a forward end of the third diode is connected to the first plate of the third capacitor and the gate of the second isolation transistor, and a reverse end of the third diode is connected to the second electrode of the first transistor; The first isolation transistor and the second isolation transistor are N-type transistors.

10. The display driving circuit according to claim 9, characterized in that: The control circuit includes a reset signal line connected to the bootstrap capacitor, the second capacitor and the third capacitor; The reset signal line is respectively connected to the first plate of the bootstrap capacitor, the first plate of the second capacitor and the first plate of the third capacitor, and is used to reset the bootstrap capacitor, the second capacitor and the third capacitor.

11. A display panel, characterized in that: The display panel comprises the display driving circuit according to any one of claims 1 to 10.

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