A power chip packaging structure

Abstract

The present invention discloses a power chip packaging structure, which relates to the field of chip packaging technology. It includes a welding seat, which is installed on the surface of a circuit board and is connected to the circuit path in the circuit board; a contact cover, which is installed at the mouth of the top surface of the welding seat; when the welding seat and the contact cover are assembled, the bottom surface of the contact cover presses the chip stacking structure placed in the welding seat, and allows the chip stacking structure to be connected to the circuit path with the help of the welding seat; the top surface of the contact cover is recessed based on the chip arrangement position in the chip stacking structure. The present invention changes the stacking method between chips, and sets a recessed surface corresponding to the top surface of the chip on the top surface of the contact cover, and applies heat dissipation silicone paste on each recessed surface, so that the heat generated by the chip can be quickly transferred to the contact cover, and then the heat is dissipated through other heat dissipation measures (such as heat sinks, fans, etc.), thereby ensuring the normal operation of the chip.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a power chip packaging structure. Background Art

[0002] The power chip packaging structure is used to improve the energy efficiency and stability of electronic equipment. The packaging structure packages the power chip with the external circuit to form a compact and reliable whole. It can not only effectively reduce power loss, but also improve thermal management performance, ensuring that the chip maintains a stable temperature under long-term high-load operation.

[0003] After searching, the Chinese invention patent with publication number "CN115101492A" discloses "a 3D chip packaging heat dissipation structure". The application sets a water leakage detection component. In order to protect water from entering the chip when the structure leaks, since the microchannel tube is an integrated structure, the connection between the microchannel tube and the water distribution pipe or the connection between the microchannel tube and the water collection pipe is most likely to leak. A cable-type water immersion sensor is set here. When a water leak occurs, an alarm is immediately sounded to remind the user, so as to ensure that water does not enter the chip, thereby ensuring the service life of the chip;

[0004] In addition, the Chinese invention patent with publication number "CN115346936A" discloses "3D chip packaging structure and packaging method". The application arranges the second chip on the first surface of the first chip, and forms a first insulating packaging layer on the first surface and wraps the surface of the second chip. In this way, the transmission speed of the chip can be improved, the packaging size can be optimized, and the packaging process of the first chip and the second chip can be simplified, the complexity of the packaging process can be reduced, and the total packaging cost can be reduced;

[0005] However, since the above two disclosed chip packaging structures are constructed based on the principle of 3D chip packaging technology, and the 3D chip packaging technology completely stacks each chip together, in actual use, different chip layers in the 3D chip package have different functions. Therefore, when the power chip runs a single-core project, power and instruction data will not only flow to a specific chip in the power chip, but also need to be transmitted and distributed through other chip layers in the power chip, which increases energy consumption and makes the thermal management of the overall system more complicated. The core of the present invention is to address this problem and propose a power chip packaging structure to optimize the interconnection structure between chips. Summary of the invention

[0006] The object of the present invention is to provide a power chip packaging structure to solve the problems raised in the above background technology.

[0007] To achieve the above object, the present invention provides the following technical solution: a power chip packaging structure, comprising:

[0008] The welding seat is installed on the surface of the circuit board and is connected to the circuit path inside the circuit board;

[0009] The contact cover is installed at the mouth of the top surface of the welding seat;

[0010] When the welding seat and the contact cover are assembled, the bottom surface of the contact cover presses the chip stacking structure placed in the welding seat, and the chip stacking structure is connected to the circuit path by means of the welding seat;

[0011] There is a position difference between adjacent chips in the chip stacking structure, and the stacking contact areas between two adjacent chips do not completely overlap. The top surface of the contact cover is recessed based on the chip arrangement position in the chip stacking structure, and multiple recessed surfaces are formed. The top surface of each chip in the chip stacking structure corresponds to a recessed surface on the top surface of the contact cover, and the surface of each recessed surface is used for applying silicone paste for heat dissipation.

[0012] As a further preferred embodiment of the present technical solution, the chip stacking structure includes:

[0013] Several chips with different functions are stacked from bottom to top and installed inside the welding seat. A first angle which is not an acute angle is formed between the chip at the bottom of the welding seat and the chip at the top of the welding seat together with the bottom of the welding seat.

[0014] As a further preferred embodiment of the present technical solution, the stacked contact regions between two adjacent chips are connected in circuit, and a plurality of buffer pads are pressed and installed between the chip and the bottom end of the inside of the welding seat, and the buffer pad bonding is used to connect the chip circuit and the circuit path in the circuit board;

[0015] A first distance is left between each chip and the chip at the bottom of the welding seat, and the first distance gradually increases. The volume of the buffer pad bonding increases with the increase of the first distance.

[0016] As a further preferred embodiment of the present technical solution, the chip stacking structure includes:

[0017] A plurality of chips with different functions are evenly fitted and installed on the side wall of the welding seat based on the number of corners of the welding seat, a second angle is formed between each chip and the welding seat, and two adjacent chips are stacked and form a third angle;

[0018] The sum of the third angle and the second angle does not exceed 90 degrees.

[0019] As a further preferred embodiment of the present technical solution, a Zhongyuan chip is arranged at the center position inside the welding seat, and the Zhongyuan chip is stacked and installed at the center position of the chip stacking structure. Each edge of the outer surface of the Zhongyuan chip corresponds to one of the chips, and leads for interconnection are fixed between the chip and the outer surface of the Zhongyuan chip.

[0020] As a further preferred embodiment of the technical solution, a wafer pad is fixed inside the welding seat, and a plurality of guide pins are provided at the bottom of the welding seat, and the guide pins are used to connect with the circuit path;

[0021] The wafer pad is provided with transmission channels corresponding to the number of guide pins, and the aperture of the transmission channels in the wafer pad and the overall thickness of the wafer pad gradually decrease from both sides of the welding seat to the central area of ​​the welding seat.

[0022] As a further preferred embodiment of the present technical solution, a plurality of buffer pads are filled between the chip and the wafer pad, and each buffer pad bonding corresponds to one of the transmission channels;

[0023] Several of the buffer pads are bonded to form an inclined base for supporting the chip, and an inclination angle is formed between the inclined base and the welding seat. The chip is attached and fixed on the top surface of the inclined base, and based on the inclination angle, the heat dissipation surface of the chip is inclined to the plane of the wafer pad.

[0024] As a further preferred embodiment of the present technical solution, a through hole is opened from top to bottom in the contact area of ​​two adjacent stacked chips, and the through hole is filled with a through column bonding, which is used to connect all circuit combinations in the chip stacking structure.

[0025] As a further preferred embodiment of the present technical solution, a plurality of heat sink fins are arranged on the top surface of the contact protection cover, the heat sink fins are evenly distributed based on the chip arrangement position in the chip stacking structure, and the heat sink fins correspond to the top surface of the chip one by one;

[0026] The bottom surface of the heat sink fin is attached to the concave surface of the top surface of the contact cover, the top surface of the heat sink fin protrudes from the top surface of the contact cover, and the top surface of the heat sink fin is an inclined surface, and the inclination angle of the inclined surface matches the inclination angle of the chip in the chip stacking structure.

[0027] As a further preferred embodiment of the present technical solution, a plurality of heat dissipation holes for dissipating heat generated during operation of the chip stacking structure are provided on each side wall of the welding seat, and the heat dissipation holes on each side wall correspond to the position of the chip in the chip stacking structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is an isometric view of the present invention;

[0029] Figure 2It is a main cross-sectional view of the second embodiment of the present invention;

[0030] Figure 3 This is a first structural diagram of Embodiment 3 of the present invention;

[0031] Figure 4 This is a second structural diagram of Embodiment 3 of the present invention;

[0032] Figure 5 It is a cross-sectional view of the packaging structure of a stacked power chip in the prior art;

[0033] Figure 6 A structural diagram of the chip packaging structure of the present invention;

[0034] Figure 7 It is an assembly diagram of the tilting base of the present invention;

[0035] Figure 8 A schematic diagram of a circuit of a stacked power chip in a circuit board in the prior art;

[0036] Fig. 9 This is a circuit diagram of the second embodiment of the chip of the present invention;

[0037] Fig.10 This is a circuit diagram of the third embodiment of the chip of the present invention.

[0038] In the figure: 1. Contact cover; 2. Chip stacking structure; 201. Central source chip; 202. Side chip; 203. Tilted base; 204. Lead; 205. Tilted sensing wafer; 206. Buffer pad bonding; 207. Through-column bonding; 208. Flat sensing wafer; 3. Welding seat; 4. Guide pin; 5. Wafer pad. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] Before understanding the technical solution proposed in the present invention, it should be clear that the 3D chip packaging technology in the prior art refers to stacking multiple chips and using micro-bumps and micro-through hole structures to achieve inter-layer interconnection, thereby constructing an integrated circuit with a three-dimensional structure. Specifically in the present invention, the micro-bumps are the buffer pad bonding 206, and the micro-through holes are the through holes.

[0041] Embodiment 1: Since 3D chip packaging completely stacks each chip together, but since different chip layers have different functions, when the power chip runs a single-core project, electricity and instruction data will not only flow to a specific chip in the power chip, but also need to be transmitted and distributed through other chip layers in the power chip, which increases energy consumption and makes the thermal management of the overall system more complicated. The core of the present invention is to address this problem and propose a power chip packaging structure to optimize the interconnection structure between chips.

[0042] It should be clear that reference Figure 1-Figure 7 It can be seen that in this embodiment, the power chip packaging structure includes: a welding seat 3, a contact cover 1 and a chip stacking structure 2.

[0043] Specifically, in this embodiment, the welding seat 3 is installed on the surface of the circuit board and is connected to the circuit path in the circuit board. The contact cover 1 is installed at the plate mouth on the top surface of the welding seat 3 and is used to seal the welding seat 3, so that when the welding seat 3 and the contact cover 1 are assembled, the bottom surface of the contact cover 1 will press the chip stacking structure 2 placed in the welding seat 3, and allow the chip stacking structure 2 to be connected to the circuit path with the help of the welding seat 3.

[0044] It should be added that, in the present embodiment, each layer of chips in the chip stacking structure 2 needs to transmit electrical signals with the external circuit or other chip layers, wherein the welding seat 3 serves as a bridge between the chip stacking structure 2 and the circuit board, providing the necessary electrical connection points, so that the chip stacking structure 2 can be smoothly connected to the circuit path in the circuit board to realize signal transmission and processing. In addition, during actual operation, the welding seat 3 not only provides electrical connection, but also plays a role in supporting and fixing the chip stacking structure 2. By installing the chip stacking structure 2 on the welding seat 3, the relative position between the chip layers can be ensured to be stable, thereby preventing chip displacement or damage caused by factors such as vibration or temperature changes during operation.

[0045] It should be further explained that the reference Figure 1-Figure 4 It can be seen that in the present embodiment, there is a position difference between adjacent chips in the chip stacking structure 2, and the stacking contact areas between two adjacent chips do not completely overlap, and the top surface of the contact cover 1 is recessed based on the chip arrangement position in the chip stacking structure 2, and a plurality of recessed surfaces are formed, and the top surface of each chip in the chip stacking structure 2 corresponds to a recessed surface attached to the top surface of the contact cover 1, and the surface of each recessed surface is used to apply silicone paste for heat dissipation. It should be clear that in the present embodiment, the setting of the recessed surface is used to improve the heat conduction efficiency between the chip stacking structure 2 and the contact cover 1, reduce the accumulation of heat on the chip surface, and thereby improve the heat dissipation performance of the overall packaging structure.

[0046] Specifically, since the chips in the chip stacking structure 2 generate a lot of heat during operation, the conventional 3D chip packaging technology makes the chips in the chip stacking structure 2 Figure 5 As shown in the stacking, so when executing single-core or multi-core tasks, Figure 8 It can be seen that the heat transfer path is long because each layer of chips in the chip stacking structure 2 needs to pass through, resulting in low heat dissipation efficiency, which in turn affects the heat dissipation of the chip stacking structure 2. However, in this embodiment, due to the position difference between adjacent chips in the chip stacking structure 2, the chips in the chip stacking structure 2 are not completely stacked together as in the traditional 3D chip packaging technology, but there is a certain space interval, such as Fig. 9 and Fig.10 It can be seen that when such a design performs single-core or multi-core tasks, the combination of each chip is independent of the chip combination in the 3D chip packaging technology, so the heat can be transferred from the heat-generating chip to the surrounding environment faster without passing through each layer of chips, thereby greatly improving the heat dissipation efficiency. It should be added that in the present invention, Figure 8 , Fig. 9 and Fig.10 The "Vo" and "Vi" represent the output voltage and input voltage respectively.

[0047] In addition, it should be further explained that the reference Figure 2-Figure 4 By setting a concave surface corresponding to the top surface of the chip on the top surface of the contact cover 1 and applying heat dissipation silicone paste on each concave surface, the heat generated by the chip can be quickly transferred to the contact cover 1, and then the heat can be dissipated through other heat dissipation measures (such as heat sinks, fans, etc.), thereby ensuring the normal operation of the chip.

[0048] It should also be added that the design of the recessed surface also increases the contact area between the chip stacking structure 2 and the contact cover 1, thereby improving the connection strength between the two, making the chip stacking structure 2 more stable when subjected to external impact or vibration, and less prone to displacement or damage.

[0049] Embodiment 2: Since 3D chip packaging technology realizes data transmission by completely stacking different chip layers together, during actual operation, a certain amount of magnetic field will be generated between each layer of chips when they are powered on, and the magnetic fields will affect each other, thereby causing signal interference during data transmission, affecting the stability and speed of data transmission. Figure 2 It can be seen that this embodiment proposes a chip stacking structure 2, specifically a stepped stacking power chip package.

[0050] It should be noted that in this embodiment, the chip stacking structure 2 includes: a plurality of chips with different functions, which are stacked from bottom to top and installed inside the welding seat 3, and a first angle which is not an acute angle is formed between the chip located at the bottom of the welding seat 3 and the chip located at the top of the welding seat 3 and the bottom of the welding seat 3.

[0051] It should be clear that in this embodiment, the limitation of the first angle is used to reduce the magnetic field interference between adjacent chip layers, and the first angle is not set as an acute angle, which ensures that the chip located at the bottom of the welding seat 3 and the chip located at the top of the welding seat 3 are not at different heights in the same position, and further limits the chip stacking structure 2 to present a stepped stacking effect.

[0052] It should be added that, in the present embodiment, by setting the first angle, a certain space interval is formed between adjacent chip layers, thereby reducing the direct effect between magnetic fields, thereby reducing the possibility of signal interference and improving the reliability and speed of data transmission. In addition, the stepped stacking design also helps to optimize the heat dissipation performance. Since the chip generates heat during operation, the traditional 3D chip packaging technology's tight stacking method easily causes heat to accumulate between chips, which is difficult to dissipate effectively. The stepped stacking structure increases the space interval between chip layers, allowing the heat to be dissipated to the surrounding environment more quickly, thereby improving the heat dissipation efficiency of the overall packaging structure and ensuring the stable operation of the chip.

[0053] In addition, it should be further explained that the reference Figure 2 It can be seen that in this embodiment, the overlapping contact area circuits between two adjacent chips are connected, and a number of buffer pad bonds 206 are pressed and installed between the chip and the bottom end inside the welding seat 3. The buffer pad bonds 206 are used to connect the chip circuit and the circuit path inside the circuit board. A first distance is left between each chip and the chip located at the bottom of the welding seat 3. The first distance gradually increases, and the volume of the buffer pad bonds 206 increases with the increase of the first distance.

[0054] It should be clear that in the present embodiment, the first spacing is used to ensure that there is sufficient space between two adjacent chips to prevent physical contact or electromagnetic interference between each other. In addition, as the first spacing gradually increases, the buffer pad bonding 206 is set to increase in volume as the first spacing increases, so that when thermal expansion or pressure changes, the buffer pad bonding 206 can better adapt to and disperse the stress caused by these changes, thereby protecting the connection between the chips from being destroyed. At the same time, the first spacing and its corresponding volume of the buffer pad bonding 206 optimize the packaging density and performance while meeting the requirements of physical isolation and electromagnetic protection.

[0055] Embodiment 3: Due to the 3D chip packaging technology, in the actual assembly process, the power chip prepared by the 3D chip packaging technology will be limited by the application scenario due to its thickness. For example, in some thin and light devices, due to space limitations, it is not necessary to directly connect the chip layers with Figure 5 Stacking in the form of will make the thin and light device too large and reduce portability. Figure 3 , a chip stacking structure 2 is proposed, specifically a spliced ​​power chip package.

[0056] It should be noted that in this embodiment, the chip stacking structure 2 includes: a number of chips with different functions, which are evenly fitted on the side wall of the welding seat 3 based on the number of corners of the welding seat 3, and a second angle is formed between each chip and the welding seat 3. Two adjacent chips are stacked and form a third angle, and the sum of the third angle and the second angle does not exceed 90 degrees.

[0057] In addition, in the present embodiment, a central source chip 201 is arranged at the center position inside the welding seat 3, and the central source chip 201 is stacked and installed at the center position of the chip stacking structure 2. Each edge of the outer surface of the central source chip 201 corresponds to a chip, and leads 204 for interconnection are fixed between the chip and the outer surface of the central source chip 201.

[0058] It should be clear that in this embodiment, reference Figure 1 and Figure 6 It can be seen that several chips with different functions are divided into multiple side chips 202 and a central source chip 201 based on their positions in the welding seat 3, wherein the side chips 202 are evenly fitted and installed on the side wall position inside the welding seat 3, and a second angle is formed between each side chip 202 and the welding seat 3, which is specifically manifested as a first structure and a second structure in this embodiment.

[0059] Among them reference Figure 3 It can be seen that in the first structure, the central source chip 201 is placed in the middle due to the plurality of wing chips 202 , and the position of the central source chip 201 is lower than that of all the wing chips 202 .

[0060] It should be clear that the characteristics of the first structure make it possible for the chip stacking structure 2 proposed in this embodiment to be in actual operation. Since the central source chip 201 is in a lower position, it is conducive to the dissipation of heat and the formation of a heat dissipation duct on the central recessed surface of the contact cover 1, thereby optimizing the heat dissipation performance of the entire chip.

[0061] It should be added that reference Figure 4It can be seen that the second structure places the central source chip 201 in the middle by a plurality of side wing chips 202 , and makes the position of the central source chip 201 lower than all the side wing chips 202 , but at this time, the heat dissipation surface of the side wing chip 202 is away from the central source chip 201 and faces the outside of the welding seat 3 .

[0062] It should be clear that the characteristics of the second structure make it possible for the chip stacking structure 2 proposed in this embodiment to have the heat dissipation surface of the wing chip 202 directly face the external environment during actual operation, relative to the first structure, thereby reducing the accumulation of heat inside the chip and further improving the heat dissipation efficiency. In addition, the design of the second structure also allows a larger space to be formed between the wing chip 202 and the central source chip 201, which is conducive to air circulation and thus accelerates heat dissipation.

[0063] It is worth noting that, regardless of the first structure or the second structure, the chip stacking structure 2 in this embodiment achieves an optimized layout in a limited space by cleverly adjusting the angles and positions between the chips, which not only meets the volume requirements of thin and light devices, but also ensures efficient operation and good heat dissipation of the power chips.

[0064] Embodiment 4: As a supplement to the contents of Embodiment 1 and Embodiment 3, it should be clear that in this embodiment, a wafer pad 5 is fixed inside the welding seat 3, and a plurality of guide pins 4 are provided at the bottom of the welding seat 3. The guide pins 4 are used to connect to the circuit path. Transmission channels corresponding to the number of guide pins 4 are opened in the wafer pad 5. The transmission channel aperture in the wafer pad 5 and the overall thickness of the wafer pad 5 gradually decrease from both sides of the welding seat 3 to the central area of ​​the welding seat 3. A plurality of buffer pad bonds 206 are filled between the chip and the wafer pad 5. Each buffer pad bond 206 corresponds to a transmission channel. A plurality of buffer pad bonds 206 form a support for the chip. The inclined base 203 has an inclination angle formed between the inclined base 203 and the welding base 3, the chip is fixed on the top surface of the inclined base 203, and based on the inclination angle, the heat dissipation surface of the chip is inclined to the plane of the wafer pad 5. In addition, in the present application, a wafer is fixed on the top of the chip, and the wafer is a building material of the chip. In the present application, the wafer provides a stable base for the circuits in the chip. Specifically, in the present application, the wafer on the top of the chip is divided into an inclined sensing wafer 205 and a flat sensing wafer 208 due to its position, wherein the inclined sensing wafer 205 is installed on the top of the side wing chip 202, and the flat sensing wafer 208 is installed on the top of the central source chip 201.

[0065] It should be noted that, in the present embodiment, the wafer pad 5 is not only used to fix the guide pin 4, but also enables the buffer pad bonding 206 to transmit the data in the chip to the guide pin 4 through the transmission channel. In addition, during the actual assembly, the transmission channel aperture in the wafer pad 5 and the overall thickness of the wafer pad 5 are gradually reduced from the two sides of the welding seat 3 to the central area of ​​the welding seat 3, so that the welding seat 3 can be assembled with reference to the actual assembly. Figure 7 It can be seen that the chip stacking structure 2 assembled in the welding base 3 can realize that the bottommost chip in the chip stacking structure 2 is tilted because of the contact between the bottom and the tilted base 203.

[0066] Therefore, when this embodiment is applied to the structure proposed in Example 3, since the bottom chip in the chip stacking structure 2 is tilted, it not only optimizes the compactness of the overall packaging structure, but also further improves the heat dissipation efficiency of the chip. In addition, the tilted bottom chip can more effectively direct the heat to the edge of the welding seat 3, and directly dissipate it to the external environment through the heat dissipation surface of the side chip 202, thereby avoiding the accumulation of heat inside the chip. In addition, this tilted design also helps to reduce the thermal stress between chips and improve the stability and reliability of the packaging structure. At the same time, the transmission channel design of the wafer pad 5 ensures the efficient transmission of data inside the chip, so that the entire packaging structure has good data transmission capabilities while maintaining high performance.

[0067] Embodiment 5 is a supplement to the contents of Embodiment 1, Embodiment 2 and Embodiment 3. It should be noted that in the prior art, 3D chip packaging technology refers to stacking multiple chips and using micro-bumps and micro-through-hole structures to achieve inter-layer interconnection, thereby constructing an integrated circuit with a three-dimensional structure. Specifically, in this embodiment, through holes (micro-through holes) are opened from top to bottom in the contact area of ​​two adjacent stacked chips, and the through holes are filled with through-pillar bonding 207 (micro-bumps). The through-pillar bonding 207 (micro-bumps) is used to connect all circuit combinations in the chip stacking structure 2.

[0068] Embodiment 6: To improve the actual heat dissipation effect of the first embodiment, the second embodiment and the third embodiment, this embodiment proposes the following features: Figure 1It can be seen that the features proposed in this embodiment include: a plurality of heat sink fins are arranged on the top surface of the contact cover 1, the heat sink fins are evenly distributed based on the chip arrangement position in the chip stacking structure 2, and the heat sink fins 101 correspond to the top surface of the chip one by one, the bottom surface of the heat sink fin 101 is attached to the recessed surface of the top surface of the contact cover 1, the top surface of the heat sink fin 101 protrudes from the top surface of the contact cover 1, and the top surface of the heat sink fin 101 is an inclined surface, and the inclination angle of the inclined surface matches the inclination angle of the chip in the chip stacking structure 2. In addition, in this embodiment, each side wall of the welding seat 3 is provided with a plurality of heat sink holes for dissipating heat during the operation of the chip stacking structure 2, and the heat sink holes at each side wall correspond to the chip position in the chip stacking structure 2.

[0069] It should be noted that this embodiment not only increases the heat dissipation area by adding heat dissipation fins 101 to the contact cover 1, but also further improves the air flow efficiency by utilizing the inclined surface design, so that the heat can be dissipated to the surrounding environment more quickly. At the same time, the one-to-one correspondence between the heat dissipation fins and the top surface of the chip ensures that the heat can be directly guided from the chip source to the heat dissipation system, thereby improving the targetedness and efficiency of heat dissipation. In addition, the heat dissipation holes opened on the side wall of the welding seat 3 correspond to the chip position, further optimizing the heat discharge path, reducing the heat retention inside the packaging structure, and further improving the overall heat dissipation performance. This comprehensive heat dissipation design solves the heat dissipation problem faced by power chips in thin and light devices due to limited volume, and also achieves a good balance between heat dissipation efficiency and packaging compactness.

[0070] Embodiment 7: To further improve the technical solution proposed in Embodiment 1, this embodiment proposes a method for constructing a chip stacking structure 2, which includes S100-S600.

[0071] S100: Prepare various components required for the chip stacking structure 2, including the central source chip 201, the wing chip 202, the wafer pad 5, the guide pin 4, and the buffer pad bonding 206, and ensure that the specifications and quantities of these components meet the design requirements.

[0072] Specifically, the design requirements include: the central source chip 201 needs to have high integration and low power consumption characteristics to meet the needs of complex circuit systems; the wing chip 202 needs to be compatible with the central source chip 201 and complement each other in function to jointly improve the overall performance; the wafer pad 5 needs to have excellent conductivity and stability to ensure the accuracy and reliability of signal transmission between chips; the selection of the guide pin 4 needs to consider its material, diameter and elasticity to ensure that the chip can be stabilized and damaged during the connection process; during the assembly process, parameters such as temperature and pressure need to be strictly controlled to avoid thermal stress or mechanical damage to the chip.

[0073] S200: Preliminarily position the Zhongyuan chip 201 and place it on a preset workbench or fixture to ensure that the position and angle of the chip are accurate.

[0074] Specifically, the preliminary positioning method is to use the high-precision computer visual recognition system in the existing technology to scan the chip, identify the edge and mark points of the chip through image processing technology, and then calculate the deviation of the chip from the ideal position based on the chip model preset in the computer. Next, the chip is moved and rotated slightly through a fine-tuning robotic arm or fixture until the edge and mark points of the chip completely coincide with the preset position. During this process, the computer needs to continuously repeat the scanning, calculation and adjustment process until the predetermined positioning accuracy is achieved, thereby completing the preliminary positioning of the Zhongyuan chip 201.

[0075] S300: stacking the wing chip 202 with the central source chip 201 at a predetermined angle and position.

[0076] S400: Fix the wafer pad 5 inside the welding base 3, and ensure that the guide pin 4 is correctly connected with the transmission channel inside the wafer pad 5, so as to prepare for subsequent data transmission.

[0077] S500: Fill the buffer pad bonding 206 between the wafer pad 5 and the chip to construct an inclined base 203 for supporting the chip, and adjust the inclination angle of the inclined base 203 as needed to ensure that the heat dissipation surface of the chip can be inclined to the plane of the wafer pad 5.

[0078] S600: Perform a comprehensive inspection and test on the constructed chip stacking structure 2, including but not limited to electrical performance test and heat dissipation performance test, to ensure that it meets the design requirements and has stable and reliable performance.

[0079] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is limited by the attached embodiments and their equivalents.

Claims

1. A power chip packaging structure, characterized in that: include: A welding seat (3) is mounted on the surface of the circuit board and is connected to the circuit path in the circuit board; A contact protection cover (1) is mounted on the top surface of the welding seat plate (3) at the plate mouth; When the welding seat (3) and the contact cover (1) are assembled, the bottom surface of the contact cover (1) presses the chip stacking structure (2) placed in the welding seat (3), and the chip stacking structure (2) is connected to the circuit path by means of the welding seat (3); There is a position difference between adjacent chips in the chip stacking structure (2), and the stacking contact areas between two adjacent chips do not completely overlap. The top surface of the contact cover (1) is recessed based on the chip arrangement position in the chip stacking structure (2), and forms a plurality of recessed surfaces. The top surface of each chip in the chip stacking structure (2) corresponds to a recessed surface on the top surface of the contact cover (1), and the surface of each recessed surface is used for applying silicone paste for heat dissipation.

2. A power chip packaging structure according to claim 1, characterized in that: The chip stacking structure (2) comprises: A plurality of chips with different functions are stacked and installed from bottom to top inside the welding seat (3), and a first angle which is not an acute angle is formed between the chip located at the bottom of the welding seat (3) and the chip located at the top of the welding seat (3) together with the bottom of the welding seat (3).

3. A power chip packaging structure according to claim 2, characterized in that: The stacked contact regions between two adjacent chips are electrically connected, and a plurality of buffer pad bonds (206) are pressed and installed between the chip and the bottom end of the inside of the welding seat (3), and the buffer pad bonds (206) are used to connect the chip circuit and the circuit path in the circuit board; A first spacing is left between each chip and the chip at the bottom of the welding seat (3), and the first spacing gradually increases, and the volume of the buffer pad bonding (206) increases as the first spacing increases.

4. The power chip packaging structure according to claim 1, characterized in that: The chip stacking structure (2) comprises: A plurality of chips with different functions, the plurality of chips being evenly fitted and mounted on the side wall of the welding seat (3) based on the number of corners of the welding seat (3), a second angle being formed between each chip and the welding seat (3), and a third angle being formed between two adjacent chips stacked together; The sum of the third angle and the second angle does not exceed 90 degrees.

5. The power chip packaging structure according to claim 4, characterized in that: A central source chip (201) is arranged at the center position inside the welding base (3); the central source chip (201) is stacked and installed at the center position of the chip stacking structure (2); each edge of the outer surface of the central source chip (201) corresponds to one of the chips; and leads (204) for interconnection are fixed between the chips and the outer surface of the central source chip (201).

6. The power chip packaging structure according to claim 1, characterized in that: A wafer pad (5) is fixed inside the welding seat (3), and a plurality of guide pins (4) are provided at the bottom of the welding seat (3), and the guide pins (4) are used to connect to the circuit path; The wafer pad (5) is provided with transmission channels corresponding to the number of the guide pins (4), and the aperture of the transmission channels in the wafer pad (5) and the overall thickness of the wafer pad (5) gradually decrease from both sides of the welding seat (3) to the central area of ​​the welding seat (3).

7. A power chip packaging structure according to claim 6, characterized in that: A plurality of buffer pad bonds (206) are filled between the chip and the wafer pad (5), and each buffer pad bond (206) corresponds to one of the transmission channels; A plurality of the buffer pads are bonded (206) to form an inclined base for supporting a chip, an inclination angle is formed between the inclined base and the welding base (3), the chip is bonded and fixed on the top surface of the inclined base, and based on the inclination angle, the heat dissipation surface of the chip is inclined to the plane of the wafer pad (5).

8. The power chip packaging structure according to claim 1, characterized in that: A through hole is opened from top to bottom in the contact area of ​​two adjacent stacked chips, and the through hole is filled with a through column bonding (207). The through column bonding (207) is used to connect all circuit combinations in the chip stacking structure (2).

9. The power chip packaging structure according to claim 1, characterized in that: The top surface of the contact protection cover (1) is provided with a plurality of heat dissipation fins, the heat dissipation fins are evenly distributed based on the chip arrangement positions in the chip stacking structure (2), and the heat dissipation fins (101) correspond one-to-one to the top surface of the chip; The bottom surface of the heat dissipation fin (101) is attached to the concave surface of the top surface of the contact protection cover (1), the top surface of the heat dissipation fin (101) protrudes from the top surface of the contact protection cover (1), and the top surface of the heat dissipation fin (101) is an inclined surface, and the inclination angle of the inclined surface matches the inclination angle of the chip in the chip stacking structure (2).

10. The power chip packaging structure according to claim 1, characterized in that: Each side wall of the welding seat (3) is provided with a plurality of heat dissipation holes for dissipating heat generated when the chip stacking structure (2) is in operation, and each heat dissipation hole on the side wall corresponds to the position of the chip in the chip stacking structure (2).

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