Device interconnection system, method, device, medium and program product

Abstract

This application discloses a device interconnection system, method, device, medium, and program product in the field of computer technology. This application incorporates different hardware resource devices, such as memory devices, hardware acceleration devices, or computing devices, into different resource pools. Furthermore, at least one upstream port of at least one switch chip in each resource pool is connected to an upstream port of at least one switch chip in another resource pool, thereby achieving interconnection between different resource pools. At least one downstream port of at least one switch chip in each resource pool is connected to a hardware resource device, thereby achieving interconnection of devices within the system with as few ports as possible. Downstream devices do not need to be connected in pairs, reducing the number of connection lines and the complexity of wiring layout. Communication delay can be reduced accordingly, thus meeting the communication needs of services with low latency requirements.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a device interconnection system, method, device, medium and program product. Background Art

[0002] Current bus topologies are mostly tree-like structures based on the PCIe bus and PCIe switch chips (PCIe-enabled switching chips). In this structure, the number of PCIe switch ports is limited. As system scale increases, the number of layers increases, and the number of PCIe switches increases, leading to complex wiring and configuration. Furthermore, the increased number of hops in a multi-layer topology increases communication latency, making it impossible to meet the stringent low-latency requirements of businesses.

[0003] Therefore, how to simplify the complexity of device interconnection and wiring layout is a problem that technical personnel in this field need to solve. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a device interconnection system, method, device, medium and program product to simplify the complexity and wiring layout of device interconnection. The specific solution is as follows:

[0005] In a first aspect, the present application provides a device interconnection system, comprising:

[0006] At least two resource pools, each resource pool including at least one switching chip;

[0007] At least one downstream port of the at least one switching chip is used to connect to a hardware resource device; the hardware resource device in the same resource pool is: a memory device, a hardware acceleration device or a computing device, and the hardware resource devices in different resource pools are different;

[0008] The at least one upstream port of the at least one switching chip is used to connect to the upstream port of at least one switching chip in another resource pool; the at least one upstream port of the at least one switching chip is used to connect to the upstream ports of other switching chips in the resource pool where the current switching chip is located;

[0009] The at least one switching chip is used to: forward the upstream data to the corresponding downstream port according to the destination address of the upstream data sent by any upstream port; and / or forward the downstream data to the corresponding upstream port according to the destination address of the downstream data sent by any downstream port.

[0010] Optionally, the at least one switching chip includes: a routing and forwarding engine module;

[0011] The routing forwarding engine module is used to determine the destination address of upstream data sent by any upstream port in the current switching chip according to the routing table; and / or the destination address of downstream data sent by any downstream port in the current switching chip.

[0012] Optionally, the at least one switching chip includes: a storage module;

[0013] The storage module is used for storing a routing table, upstream data sent by any upstream port in the current switching chip, and downstream data sent by any downstream port in the current switching chip.

[0014] Optionally, the at least one switching chip includes: a direct memory access engine module;

[0015] The direct memory access engine module is used to realize communication between other resource pools connected to any upstream port of the current switching chip and hardware resource devices connected to any downstream port of the current switching chip using direct memory access technology.

[0016] Optionally, the at least one switching chip includes: a control logic module;

[0017] The control logic module includes: a data packet conversion unit, a register unit and a resource sensing unit;

[0018] The data packet conversion unit is used to: perform data format conversion on upstream data sent by any upstream port in the current switching chip and / or downstream data sent by any downstream port in the current switching chip;

[0019] The register unit is used to configure the port information of any upstream port and / or any downstream port in the current switching chip; the port information includes: port parameters, port attributes and port status;

[0020] The resource sensing unit is used to monitor whether each downstream port in the current switching chip is connected to a hardware resource device, and / or monitor resource usage information of the hardware resource device connected to the downstream port in the current switching chip, and generate a corresponding resource sensing table.

[0021] Optionally, each downstream port of the at least one switching chip supports a first protocol, and each upstream port of the at least one switching chip supports a second protocol;

[0022] Accordingly, the data packet conversion unit is used to: convert the upstream data sent by any upstream port in the current switching chip from the second protocol format to the first protocol format; and / or convert the upstream data sent by any downstream port in the current switching chip from the first protocol format to the second protocol format.

[0023] Optionally, the register unit is used to configure a routing table and a resource awareness table.

[0024] Optionally, the resource sensing unit is configured to update the resource sensing table in real time based on whether each downstream port is connected to a hardware resource device and / or resource usage information of the hardware resource device obtained through real-time monitoring.

[0025] Optionally, any hardware resource device is configured to: send idle resource information in itself to the resource sensing unit according to a preset period;

[0026] Correspondingly, the resource awareness unit updates the resource awareness table according to the information sent by the hardware resource device.

[0027] Optionally, the resource sensing unit is used to: regularly detect whether the communication links between the upstream ports of the current switching chip and the connected resource pool are connected; regularly detect whether the communication links between the downstream ports of the current switching chip and the connected hardware resource devices are connected.

[0028] Optionally, each upstream port of the at least one switching chip is provided with a decoder;

[0029] The decoder is used to determine the address mapping relationship between the memory of the computing device connected to the upstream port where the current decoder is located and the hardware resource device connected to the downstream port in the current switching chip.

[0030] Optionally, the decoder is used to store memory capacity information of a computing device connected to the upstream port where the current decoder is located.

[0031] Optionally, the at least one switching chip includes: a cache coherence interface module;

[0032] The cache consistency interface module is used to provide a cache consistency transmission channel between hardware resource devices connected to each downstream port in the current switching chip.

[0033] Optionally, the at least one switching chip includes: a clock and reset module;

[0034] The clock and reset module is used to maintain clock synchronization between devices in the system.

[0035] Optionally, the at least one switching chip further includes: a switching function module.

[0036] Optionally, the at least one switching chip includes: a power management module;

[0037] The power management module is used to provide power to the switching function module and the switching chips in each resource pool, and manage the power consumption of the switching function module and the switching chips in each resource pool.

[0038] Optionally, each hardware resource device in each resource pool supports a CLOS topology and / or a fully interconnected topology.

[0039] In a second aspect, the present application provides a device interconnection method, which is applied to any of the aforementioned device interconnection systems, comprising:

[0040] For any resource pool in the device interconnection system, connect at least one upstream port of at least one switch chip in the current resource pool to the upstream port of at least one switch chip in another resource pool; connect at least one downstream port of at least one switch chip in the current resource pool to a hardware resource device; and connect at least one upstream port of at least one switch chip in the current resource pool to the upstream ports of another switch chip in the current resource pool;

[0041] The device interconnection system includes at least two resource pools, each resource pool includes at least one switching chip; the hardware resource devices in the same resource pool are: memory devices, hardware acceleration devices or computing devices, and the hardware resource devices in different resource pools are different;

[0042] Among them, the at least one switching chip is used to: forward the upstream data to the corresponding downstream port according to the destination address of the upstream data sent by any upstream port; and / or forward the downstream data to the corresponding upstream port according to the destination address of the downstream data sent by any downstream port.

[0043] In a third aspect, the present application provides an electronic device, comprising:

[0044] memory for storing computer programs;

[0045] The processor is used to execute the computer program to implement the device interconnection method disclosed above.

[0046] In a fourth aspect, the present application provides a non-volatile storage medium for storing a computer program, wherein the computer program implements the aforementioned disclosed device interconnection method when executed by a processor.

[0047] In a fifth aspect, the present application provides a computer program product, comprising a computer program / instruction, which, when executed by a processor, implements the steps of the aforementioned disclosed device interconnection method.

[0048] From the above scheme, it can be seen that the present application provides a device interconnection system, including: at least two resource pools, each resource pool including at least one switching chip; at least one downstream port of the at least one switching chip is used to connect to a hardware resource device; the hardware resource device in the same resource pool is: a memory device, a hardware acceleration device or a computing device, and the hardware resource devices in different resource pools are different; at least one upstream port of the at least one switching chip is used to connect to the upstream port of at least one switching chip in other resource pools; the at least one switching chip is used to: forward the upstream data to the corresponding downstream port according to the destination address of the upstream data sent by any upstream port; and / or forward the downstream data to the corresponding upstream port according to the destination address of the downstream data sent by any downstream port.

[0049] It can be seen that the beneficial effects of the present application are: different hardware resource devices, such as memory devices, hardware acceleration devices or computing devices, are included in different resource pools; and at least one upstream port of at least one switching chip in each resource pool is connected to the upstream port of at least one switching chip in other resource pools, thereby realizing the interconnection between different resource pools; at least one downstream port of at least one switching chip in each resource pool is connected to the hardware resource device, so that the switching chip forwards the upstream data to the corresponding downstream port according to the destination address of the upstream data sent by any upstream port; and / or forwards the downstream data to the corresponding upstream port according to the destination address of the downstream data sent by any downstream port, thereby realizing intra-system communication. This solution realizes the interconnection of devices within the system with the least possible number of ports. Downstream devices do not need to be connected in pairs, which reduces the number of connection lines and the complexity of wiring layout. The communication delay can be reduced accordingly, meeting the communication needs of services with low latency requirements.

[0050] Correspondingly, the device interconnection method, device, medium and program product provided by this application also have the above-mentioned technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0052] Figure 1 A schematic diagram of a device interconnection system disclosed in this application;

[0053] Figure 2 This is a schematic diagram of the second device interconnection system disclosed in this application;

[0054] Figure 3 This is a schematic diagram of the third device interconnection system disclosed in this application;

[0055] Figure 4 A schematic diagram of a switch chip disclosed in this application;

[0056] Figure 5 A schematic diagram of an electronic device disclosed in this application;

[0057] Figure 6 A server structure diagram provided for this application;

[0058] Figure 7 This is a terminal structure diagram provided for this application. DETAILED DESCRIPTION

[0059] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments of this application, all other examples obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0060] Currently, most bus topologies are tree-like structures based on the PCIe bus and PCIe switch chips. In this structure, the number of PCIe switch ports is limited. As the system scale expands, the number of layers increases, and the number of PCIe switches becomes large, leading to complex wiring and configuration. Furthermore, the increase in hop count in a multi-level topology also increases communication latency, making it impossible to meet the stringent low-latency requirements of businesses. Therefore, this application provides a device interconnection solution that simplifies the complexity of device interconnection and the wiring layout.

[0061] See also Figure 1 As shown, an embodiment of the present application discloses a device interconnection system, including: at least two resource pools, each resource pool including at least one switch chip; at least one downstream port of at least one switch chip is used to connect to a hardware resource device; the hardware resource device in the same resource pool is: a memory device, a hardware acceleration device, or a computing device, and the hardware resource devices in different resource pools are different; at least one upstream port of at least one switch chip is used to connect to the upstream port of at least one switch chip in another resource pool. The at least one upstream port of the at least one switch chip is used to connect to the upstream port of another switch chip in the resource pool where the current switch chip is located.

[0062] exist Figure 1 In the example, each switch chip has ports P1 to PN, where P1 to P5 are upstream ports and P6 to PN are downstream ports. Of course, the number of upstream ports can be expanded according to actual needs.

[0063] It should be noted that memory devices may include DRAM (Dynamic Random Access Memory), hardware acceleration devices may include GPUs (Graphics Processing Units), FPGAs (Field-Programmable Gate Arrays), and computing devices may include CPUs (Central Processing Units), NICs (Network Interface Controllers), DRAM, and the like. In one embodiment, each hardware resource device in each resource pool supports a CLOS topology and / or a fully interconnected topology.

[0064] Among them, at least one switching chip is used to: forward upstream data to the corresponding downstream port according to the destination address of the upstream data sent by any upstream port; and / or forward downstream data to the corresponding upstream port according to the destination address of the downstream data sent by any downstream port.

[0065] In one embodiment, at least one switching chip includes: a routing and forwarding engine module; the routing and forwarding engine module is used to: determine the destination address of upstream data sent by any upstream port in the current switching chip according to the routing table; and / or the destination address of downstream data sent by any downstream port in the current switching chip.

[0066] In one embodiment, at least one switching chip includes a storage module configured to store a routing table, upstream data sent by any upstream port in the current switching chip, and downstream data sent by any downstream port in the current switching chip.

[0067] In one embodiment, at least one switching chip includes: a direct memory access engine module; the direct memory access engine module is used to: use direct memory access (Data Memory Access, also known as direct memory access) technology to achieve communication between other resource pools connected to any upstream port in the current switching chip and hardware resource devices connected to any downstream port in the current switching chip.

[0068] In one example, at least one switching chip includes: a control logic module; the control logic module includes: a data packet conversion unit, a register unit, and a resource sensing unit.

[0069] The data packet conversion unit is used to perform data format conversion on upstream data sent by any upstream port in the current switching chip and / or downstream data sent by any downstream port in the current switching chip.

[0070] The register unit is used to configure the port information of any upstream port and / or any downstream port in the current switching chip; the port information includes: port parameters, port attributes and port status.

[0071] The resource sensing unit is used to monitor whether each downstream port in the current switching chip is connected to a hardware resource device, and / or monitor resource usage information of the hardware resource device connected to the downstream port in the current switching chip, and generate a corresponding resource sensing table.

[0072] Accordingly, each downstream port of the at least one switching chip supports a first protocol, and each upstream port of the at least one switching chip supports a second protocol; accordingly, the data packet conversion unit is used to: convert upstream data sent by any upstream port in the current switching chip from the second protocol format to the first protocol format; and / or convert upstream data sent by any downstream port in the current switching chip from the first protocol format to the second protocol format. For example: each downstream port of the at least one switching chip supports the CCIX protocol (a cache coherent interconnect protocol for accelerators), and each upstream port of the at least one switching chip supports the CXL protocol (Compute Express Link, an open interconnect technology standard); accordingly, the data packet conversion unit is used to: convert upstream data sent by any upstream port in the current switching chip from the CXL protocol format to the CCIX protocol format; and / or convert upstream data sent by any downstream port in the current switching chip from the CCIX protocol format to the CXL protocol format.

[0073] Accordingly, the register unit is used to configure the routing table and the resource awareness table. The resource awareness table records parameters such as the remaining memory, maximum bandwidth, and remaining computing power of the hardware resource device.

[0074] Accordingly, the resource sensing unit is configured to update the resource sensing table in real time according to whether each downstream port is connected to a hardware resource device and / or resource usage information of the hardware resource device obtained through real-time monitoring.

[0075] In one embodiment, any hardware resource device is configured to send idle resource information thereof to the resource sensing unit according to a preset period; accordingly, the resource sensing unit updates the resource sensing table according to the information sent by the hardware resource device.

[0076] Moreover, the resource sensing unit is used to: regularly detect whether the communication links between the upstream ports of the current switching chip and the connected resource pool are connected; regularly detect whether the communication links between the downstream ports of the current switching chip and the connected hardware resource devices are connected.

[0077] In one embodiment, each upstream port of at least one switching chip is provided with a decoder; the decoder is configured to determine an address mapping relationship between the memory of a computing device connected to the upstream port where the decoder is currently located and the hardware resource device connected to the downstream port of the current switching chip. In one example, the decoder is configured to store memory capacity information of the computing device connected to the upstream port where the decoder is currently located.

[0078] In one embodiment, at least one switching chip includes a cache consistency interface module; the cache consistency interface module is used to provide a cache consistency transmission channel between hardware resource devices connected to each downstream port in the current switching chip.

[0079] In one embodiment, at least one switching chip includes a clock and reset module. The clock and reset module is used to maintain clock synchronization between devices in the system.

[0080] In one embodiment, at least one switching chip further includes a switching function module. The at least one switching chip further includes a power management module configured to provide power to the switching function module and the switching chips in each resource pool, and to manage power consumption of the switching function module and the switching chips in each resource pool.

[0081] It can be seen that this embodiment incorporates different hardware resource devices, such as memory devices, hardware acceleration devices, or computing devices, into different resource pools; and at least one upstream port of at least one switching chip in each resource pool is connected to the upstream port of at least one switching chip in other resource pools, thereby realizing the interconnection between different resource pools; at least one downstream port of at least one switching chip in each resource pool is connected to the hardware resource device, so that the switching chip forwards the upstream data to the corresponding downstream port according to the destination address of the upstream data sent by any upstream port; and / or forwards the downstream data to the corresponding upstream port according to the destination address of the downstream data sent by any downstream port, thereby realizing intra-system communication. This solution realizes the interconnection of devices within the system with the least possible number of ports. Downstream devices do not need to be connected to each other, which reduces the number of connection lines and the complexity of the wiring layout. The communication delay can be reduced accordingly, meeting the communication needs of services with low latency requirements.

[0082] It should be noted that the switch chip in this application is a CXL switch chip (hereinafter referred to as a switch) at the bus level within the rack. In addition to switching and forwarding functions, it also performs CXL cache coherence maintenance. In addition, the connection between any two CXL switch chips is the CXL bus.

[0083] See Figure 2 This embodiment adopts a direct connection mode with reference to the Dragonfly network (a network topology structure), and divides the entire system into three layers: system layer, group layer (resource pool layer), and switch layer. The system layer includes 4 resource pools, which are fully connected to each other, which can improve network interconnectivity and redundancy, and ensure that data is transmitted efficiently and reliably throughout the system. In addition, the entire system supports resource scalability and is suitable for the construction of pooled systems. The switch forwarding hop count is at most 3 hops, and the transmission path and number of nodes are better than the CLOS topology, with superior latency performance. Compared with the fully interconnected device topology or the fully interconnected switch topology, Figure 3 The number of connecting wires in the example is greatly reduced, and the wiring difficulty, deployment difficulty and cost are significantly reduced.

[0084] Figure 2 The demonstration showcased heterogeneous acceleration resource pools for GPUs and FPGAs, as well as CXL extended memory resource pools based on DRAM and NVMe SSDs. In practice, the number and types of resource pools can be appropriately increased based on the application acceleration scenario, such as adding an NPU accelerated computing resource pool.

[0085] Figure 2 The system shown achieves full interconnection of pooled resources with a limited number of links, greatly reducing the consumption of multiple devices, improving energy efficiency, and reducing transmission delay; secondly, deploying different types of resource pools facilitates resource management and scheduling, and can rationally allocate application computing power based on the characteristics of different resources, improve acceleration efficiency, and at the same time improve resource utilization.

[0086] Specifically, this embodiment configures three CXL 3.1 switch chips for each resource pool, supporting switch-to-switch connectivity. One upstream port on each switch chip is used to interconnect different resource pools, resulting in a total of six PCIe links with bidirectional bandwidths of 192 GB / s for PCIE 4.0 and 384 GB / s for PCIE 5.0. Within a resource pool, two upstream ports on each switch are used to interconnect resource devices connected to different switch chips within the same resource pool. Three PCIe links enable full connectivity within the resource pool. Figure 2 Each CXL switch has 10 interfaces, and can actually have more interfaces.

[0087] In this embodiment, the number XYZ indicates: the Xth resource pool, the Zth port on the Yth switch, then the corresponding Figure 2 , X ranges from 1 to 4, Y ranges from 1 to 3, and Z ranges from 1 to 10. Port 1 of each switch is used for interconnection between resource pools. The specific port interconnection table is shown in Table 1, enabling pairwise interconnection between the four pools. Ports 3 and 4 of each switch are used for pairwise interconnection between the three switches within a resource pool.

[0088] Table 1 Interconnection table between resource pools

[0089]

[0090] X represents the link within the resource pool, and the interconnection within the resource pool is shown in Table 2.

[0091] Table 2 Interconnection table within the resource pool

[0092]

[0093] In this example, fully connecting the 12 CXL switch chips requires a total of 6 + 3 × 4 = 18 connection lines, with each switch chip occupying 3 interfaces. If a fully interconnected topology were used for these 12 CXL switch chips, 12 × 11 / 2 = 66 connection lines would be required to directly interconnect the 12 switch chips, with each CXL switch occupying 11 interfaces. According to this embodiment, the number of occupied interfaces is relatively small, which also means that larger-scale system interconnection can be achieved when the switch expansion capability is limited. Therefore, this solution, based on the interconnection of all devices, greatly reduces the use of connection lines and the occupation of switch port resources, reducing the difficulty of wiring.

[0094] Furthermore, the number of hardware devices connected to the switch, the number of switches in each resource pool, and the number of resource pools can all be scaled based on actual computing needs, with the cost of expansion increasing sequentially across the three levels. Within the memory resource pool, the CXL protocol's memory expansion capabilities allow devices with various storage media, such as DRAM and NVMe SSDs, to be expanded into system memory via the CXL bus. This access latency is significantly lower than the latency required by RDMA technology for network access in traditional, separate memory pools.

[0095] On the switch in the FPGA and GPU accelerated computing resource pool, corresponding interfaces are reserved for connecting to NIC network cards, which can achieve connection with Ethernet for cross-rack communication and support further expansion of the system scale.

[0096] In addition, the resource pool also supports a variety of hardware device resource topologies and is compatible with the CLOS topology and the fully interconnected topology of the DPU (Data Processing Unit), providing more possibilities for system performance improvement and innovative applications.

[0097] If one link between two resource pools cannot meet the bandwidth requirements, ports 2 and 3 on each switch can be used to further interconnect to obtain greater parallel bandwidth. Ensure that each switch has a direct link to the other three resource pools, such as Figure 3 As shown in Table 3, the maximum number of hops in the system is reduced to 2. While bandwidth increases, the average system latency is further reduced. The corresponding port connections are shown in Table 3, requiring a total of 18 links.

[0098] Table 3 Interconnection between resource pools in bandwidth expansion mode

[0099]

[0100] In one example, the switch can be implemented based on a reconfigurable FPAG and can support both the CXL protocol and the PCIe protocol. Figure 4 As shown, the switch includes the following functional modules:

[0101] Routing and Forwarding Engine: This module is responsible for routing and forwarding packets, controlling traffic distribution and arbitrating bus and interface resources to ensure efficient and stable data transmission. The ternary content addressable memory (TCAM) is used to store and quickly search routing table entries (for fast route lookups, storing entries whenever a port is connected). This highly efficient search function allows for rapid matching of a packet's destination address and determination of its next-hop path.

[0102] HDM decoder (Host-managed Device Memory Decoder): exists on each upstream port of the Switch. It stores the volatile and persistent memory capacity of the extended memory and determines the mapping relationship between the host physical address and the device physical address. The HDM decoder in the upstream port determines which downstream port is the target of the memory access. It resolves the address mapping relationship between the host address and the downstream device address.

[0103] On-chip storage module: On-chip SRAM memory can be used, which has fast read and write speeds and low access latency, and can be used as storage space for important information such as cached data packets, forwarding tables, and transit buffers.

[0104] Direct Memory Access (DMA) engine module: used to support DMA high-speed data transmission function, reducing the CPU load by directly accessing memory.

[0105] Control logic module: responsible for controlling, managing, and configuring switch resources and functions, including:

[0106] 1) The packet conversion unit is responsible for converting the format of received packets, such as converting packets from the CXL protocol to the CCIX protocol, editing and modifying packet header information, and implementing cache coherence maintenance. CCIX is used between accelerated computing devices within the group.

[0107] 2) Register unit, responsible for implementing the configuration space of the switch device, used to configure the parameters, attributes and status of the port, and configure the parameters of the routing table and resource awareness table.

[0108] 3) Resource Awareness Table, used to monitor system resource usage. This resource utilization table can be stored in the module's SDRAM cache, enabling rapid data read, write, and update, ensuring rapid access to resource utilization information when needed. For example, the memory / computing device periodically sends information about free memory capacity and the number of free computing units to the control logic module. Upon receiving this port resource information, the control logic module configures the resource awareness table to dynamically monitor resource utilization. The control logic module can also periodically send signals to the port module to detect whether the link between the port and the external device is functioning properly. It also controls the physical connection of the port, enabling dynamic transformation of the system connection topology and fault monitoring and isolation.

[0109] Cache Coherence Interface Module: This module connects to the motherboard's PCIe interface and provides a data transmission channel with devices such as accelerators. It includes the protocol transport layer, link layer, and physical layer. The physical layer is responsible for physical link initialization and control-related functions, the link layer is responsible for data link status control and management, and the transport layer is responsible for message encapsulation and decapsulation.

[0110] The switch device also needs other supporting modules, such as the clock and reset module, which provides clock synchronization and reset functions between devices to ensure the accuracy of data transmission; the power management module is responsible for supplying power to each module of the switch and managing the power consumption of the switch device.

[0111] It should be noted that the resource perception unit and idle port design within the switch support dynamic expansion of resources within the pool and efficient pooled resource management. At the same time, similar resources within the pool are redundant devices. Even if one or more devices fail, their tasks can be taken over by devices of the same type through internal scheduling within the system, thereby improving the reliability of the pooled platform.

[0112] In summary, this embodiment proposes a hierarchical pooled server system interconnection topology based on the CXL 3.1 protocol specification. The first layer consists of pooled servers; the second layer consists of multiple resource pools, interconnected between each other; and the third layer consists of a single switch layer, connecting multiple heterogeneous acceleration and storage devices. Multiple interconnection methods are also supported between devices, such as through protocols such as CCIX. This interconnection topology not only reduces system connectivity complexity but also enables interconnection between devices within all resource pools with only a small number of hops. This interconnection architecture enables low-latency, consistent access to host memory and extended memory resources from heterogeneous CPU and accelerator computing resources across the entire server system, supporting large-scale expansion of pooled resources and resource pool management and maintenance. This solution also supports bandwidth expansion mode, enabling interconnection with more links and higher bandwidth between resource pools. This system offers excellent flexibility, allowing for flexible link configuration and adjustment based on specific needs. Furthermore, each switch has direct links to other resource pools, providing redundant paths for interconnection between resource pools and improving the reliability and fault tolerance of the server system. In addition, the switch device is designed with a resource perception unit and related control logic to support dynamic perception of pooled resource utilization; and the control logic module supports dynamic configuration of port links, which can realize dynamic adjustment of system topology, increase the flexibility of system topology and support fault isolation.

[0113] The pooled server interconnection topology provided in this embodiment enables high-bandwidth, low-latency interconnection within a high-computing-power server system. Furthermore, it can be connected to the network through devices such as network cards, supporting wider-scale, higher-level interconnection. This topology not only simplifies system deployment but also reduces costs and power consumption, making it suitable for use in data centers.

[0114] The following introduces a device interconnection method provided in an embodiment of the present application. The device interconnection method described below can be referenced with other embodiments described in this document.

[0115] An embodiment of the present application discloses a device interconnection method, which is applied to the device interconnection system described in any of the aforementioned embodiments. The method includes: for any resource pool in the device interconnection system, connecting at least one upstream port of at least one switching chip in the current resource pool to the upstream port of at least one switching chip in other resource pools; connecting at least one downstream port of at least one switching chip in the current resource pool to a hardware resource device; and connecting at least one upstream port of at least one switching chip in the current resource pool to the upstream ports of other switching chips in the current resource pool.

[0116] The device interconnection system includes at least two resource pools, each resource pool includes at least one switching chip; the hardware resource devices in the same resource pool are: memory devices, hardware acceleration devices or computing devices, and the hardware resource devices in different resource pools are different;

[0117] Among them, at least one switching chip is used to: forward upstream data to the corresponding downstream port according to the destination address of the upstream data sent by any upstream port; and / or forward downstream data to the corresponding upstream port according to the destination address of the downstream data sent by any downstream port.

[0118] In one embodiment, at least one switching chip includes: a routing and forwarding engine module; the routing and forwarding engine module is used to: determine the destination address of upstream data sent by any upstream port in the current switching chip according to the routing table; and / or the destination address of downstream data sent by any downstream port in the current switching chip.

[0119] In one embodiment, at least one switching chip includes a storage module configured to store a routing table, upstream data sent by any upstream port in the current switching chip, and downstream data sent by any downstream port in the current switching chip.

[0120] In one embodiment, at least one switching chip includes: a direct memory access engine module; the direct memory access engine module is used to: use direct memory access technology to realize communication between other resource pools connected to any upstream port in the current switching chip and hardware resource devices connected to any downstream port in the current switching chip.

[0121] In one embodiment, at least one switching chip includes: a control logic module; the control logic module includes: a data packet conversion unit, a register unit, and a resource sensing unit.

[0122] The data packet conversion unit is used to perform data format conversion on upstream data sent by any upstream port in the current switching chip and / or downstream data sent by any downstream port in the current switching chip.

[0123] The register unit is used to configure the port information of any upstream port and / or any downstream port in the current switching chip; the port information includes: port parameters, port attributes and port status.

[0124] The resource sensing unit is used to monitor whether each downstream port in the current switching chip is connected to a hardware resource device, and / or monitor resource usage information of the hardware resource device connected to the downstream port in the current switching chip, and generate a corresponding resource sensing table.

[0125] In one embodiment, each downstream port of at least one switching chip supports the CCIX protocol, and each upstream port of at least one switching chip supports the CXL protocol; accordingly, the data packet conversion unit is used to: convert upstream data sent by any upstream port in the current switching chip from the CXL protocol format to the CCIX protocol format; and / or convert upstream data sent by any downstream port in the current switching chip from the CCIX protocol format to the CXL protocol format.

[0126] In one embodiment, the register unit is used to configure a routing table and a resource awareness table.

[0127] In one embodiment, the resource sensing unit is configured to update the resource sensing table in real time based on whether each downstream port is connected to a hardware resource device and / or resource usage information of the hardware resource device obtained through real-time monitoring.

[0128] In one embodiment, any hardware resource device is configured to send idle resource information thereof to the resource sensing unit according to a preset period; accordingly, the resource sensing unit updates the resource sensing table according to the information sent by the hardware resource device.

[0129] In one embodiment, the resource sensing unit is used to: regularly detect whether the communication links between the upstream ports of the current switching chip and the connected resource pool are connected; regularly detect whether the communication links between the downstream ports of the current switching chip and the connected hardware resource devices are connected.

[0130] In one embodiment, each upstream port of at least one switching chip is provided with a decoder; the decoder is used to determine the address mapping relationship between the memory of the computing device connected to the upstream port where the current decoder is located and the hardware resource device connected to the downstream port in the current switching chip.

[0131] In one embodiment, the decoder is configured to store memory capacity information of a computing device connected to an upstream port where the current decoder is located.

[0132] In one embodiment, at least one switching chip includes a cache consistency interface module; the cache consistency interface module is used to provide a cache consistency transmission channel between hardware resource devices connected to each downstream port in the current switching chip.

[0133] In one embodiment, at least one switching chip includes a clock and reset module. The clock and reset module is used to maintain clock synchronization between devices in the system.

[0134] In one embodiment, at least one switching chip further includes: a switching function module.

[0135] In one embodiment, at least one switching chip includes a power management module; the power management module is used to provide power to the switch and the switching chips in each resource pool, and manage the power consumption of the switch and the switching chips in each resource pool.

[0136] In one embodiment, each hardware resource device in each resource pool supports a CLOS topology and / or a fully interconnected topology.

[0137] Among them, for more specific working processes of each module and unit in this embodiment, reference can be made to the corresponding contents disclosed in the aforementioned embodiments, which will not be repeated here.

[0138] It can be seen that this embodiment provides a device interconnection method, which realizes the interconnection of devices in the system with the smallest possible number of ports. Downstream devices do not need to be connected to each other, which reduces the number of connection lines and the complexity of wiring layout. The communication delay can be reduced accordingly, meeting the communication needs of services with low latency requirements.

[0139] The following describes an electronic device provided by an embodiment of the present application, and the electronic device described below can be referenced with other embodiments described herein. The electronic device can be any functional module of the aforementioned system.

[0140] See also Figure 5 As shown, the embodiment of the present application discloses an electronic device, including:

[0141] Memory 501, used for storing computer programs;

[0142] The processor 502 is configured to execute the computer program to implement the method disclosed in any of the above embodiments.

[0143] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: forwarding the upstream data to the corresponding downstream port according to the destination address of the upstream data sent by any upstream port; and / or forwarding the downstream data to the corresponding upstream port according to the destination address of the downstream data sent by any downstream port.

[0144] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: determine the destination address of the upstream data sent by any upstream port in the current switching chip according to the routing table; and / or the destination address of the downstream data sent by any downstream port in the current switching chip.

[0145] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: storing a routing table, upstream data sent by any upstream port in the current switching chip, and downstream data sent by any downstream port in the current switching chip.

[0146] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: using direct memory access technology to realize communication between other resource pools connected to any upstream port in the current switching chip and hardware resource devices connected to any downstream port in the current switching chip.

[0147] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: convert the data format of the upstream data sent by any upstream port in the current switching chip and / or the downstream data sent by any downstream port in the current switching chip.

[0148] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: configure the port information of any upstream port and / or any downstream port in the current switching chip; the port information includes: port parameters, port attributes and port status.

[0149] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: monitor whether each downstream port in the current switching chip is connected to a hardware resource device, and / or monitor the resource usage information of the hardware resource device connected to the downstream port in the current switching chip, and generate a corresponding resource perception table.

[0150] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: converting upstream data sent by any upstream port in the current switching chip from the CXL protocol format to the CCIX protocol format; and / or converting upstream data sent by any downstream port in the current switching chip from the CCIX protocol format to the CXL protocol format.

[0151] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: configuring a routing table and a resource awareness table.

[0152] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: based on whether each downstream port is connected to a hardware resource device and / or resource usage information of the hardware resource device obtained through real-time monitoring, update the resource perception table in real time.

[0153] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: sending the idle resource information in itself to the resource perception unit according to a preset period; accordingly, it can also specifically implement the following steps: updating the resource perception table according to the information sent by the hardware resource device.

[0154] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: regularly detect whether the communication link between each upstream port of the current switching chip and the connected resource pool is connected; regularly detect whether the communication link between each downstream port of the current switching chip and the connected hardware resource device is connected.

[0155] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: determine the address mapping relationship between the memory of the computing device connected to the upstream port where the current decoder is located, and the hardware resource device connected to the downstream port in the current switching chip.

[0156] In this embodiment, when the processor executes the computer program stored in the memory, it may specifically implement the following steps: storing the memory capacity information of the computing device connected to the upstream port where the current decoder is located.

[0157] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: providing a cache consistency transmission channel between hardware resource devices connected to each downstream port in the current switching chip.

[0158] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: maintaining clock synchronization between devices in the system.

[0159] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: providing power to the switch and the switching chips in each resource pool, and managing the power consumption of the switch and the switching chips in each resource pool.

[0160] Furthermore, the embodiment of the present application also provides an electronic device. The electronic device can be Figure 6 The server shown can also be Figure 7The terminal shown. Figure 6 and Figure 7 Each of the diagrams is a structural diagram of an electronic device according to an exemplary embodiment, and the contents in the diagrams cannot be considered as any limitation on the scope of use of the present application.

[0161] Figure 6 This is a schematic diagram of the structure of a server provided in an embodiment of the present application. The server may specifically include: at least one processor, at least one memory, a power supply, a communication interface, an input / output interface, and a communication bus. The memory is used to store a computer program, which is loaded and executed by the processor to implement the relevant steps of the device interconnection disclosed in any of the aforementioned embodiments.

[0162] In this embodiment, the power supply is used to provide operating voltage for each hardware device on the server; the communication interface can create a data transmission channel between the server and external devices. The communication protocol it follows is any communication protocol that can be applied to the technical solution of this application and is not specifically limited here; the input and output interface is used to obtain external input data or output data to the outside world. The specific interface type can be selected according to specific application needs and is not specifically limited here.

[0163] In addition, the memory as a carrier for resource storage can be a read-only memory, random access memory, disk or CD, etc. The resources stored thereon include operating system, computer programs and data, etc. The storage method can be temporary storage or permanent storage.

[0164] The operating system is used to manage and control the hardware devices and computer programs on the server, enabling the processor to operate and process data in the memory. It can be Windows Server, NetWare, Unix, Linux, etc. In addition to computer programs capable of implementing the device interconnection method disclosed in any of the aforementioned embodiments, computer programs can also include computer programs capable of performing other specific tasks. Data can include data such as application update information and information about the application developer.

[0165] Figure 7 This is a schematic diagram of the structure of a terminal provided in an embodiment of the present application. The terminal may specifically include but is not limited to a smartphone, tablet computer, laptop computer or desktop computer.

[0166] Generally, the terminal in this embodiment includes: a processor and a memory.

[0167] The processor may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor may be implemented in at least one of the following hardware forms: a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), or a PLA (Programmable Logic Array). The processor may also include a main processor and a coprocessor. The main processor is used to process data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing content required to be displayed on the display. In some embodiments, the processor may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0168] The memory may include one or more computer non-volatile storage media, which may be non-transitory. The memory may also include high-speed random access memory, and non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory is used to store at least the following computer program, wherein, after the computer program is loaded and executed by the processor, it can implement the relevant steps in the device interconnection method performed by the terminal side disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory may also include operating systems and data, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system may include Windows, Unix, Linux, etc. The data may include but is not limited to update information of the application.

[0169] In some embodiments, the terminal may further include a display screen, an input and output interface, a communication interface, a sensor, a power supply, and a communication bus.

[0170] Those skilled in the art will understand that Figure 7 The structure shown in the figure does not constitute a limitation to the terminal, and may include more or fewer components than shown in the figure.

[0171] A non-volatile storage medium provided in an embodiment of the present application is introduced below. The non-volatile storage medium described below can be referenced with other embodiments described herein.

[0172] A non-volatile storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the device interconnection method disclosed in the aforementioned embodiment. The non-volatile storage medium is a computer-readable non-volatile storage medium that, as a carrier for resource storage, may be a read-only memory, random access memory, magnetic disk, or optical disk. The resources stored thereon include an operating system, computer programs, and data, and the storage method may be either temporary or permanent.

[0173] A computer program product provided in an embodiment of the present application is introduced below. The computer program product described below can be referenced with other embodiments described herein.

[0174] A computer program product includes a computer program / instruction, which implements the steps of the device interconnection method disclosed above when the computer program / instruction is executed by a processor.

[0175] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0176] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, a hard disk, a removable disk, a CD-ROM, or any other form of non-volatile storage medium known in the art.

[0177] This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A device interconnection system, characterized in that: include: At least two resource pools, each resource pool including at least one switching chip; At least one downstream port of the at least one switching chip is used to connect to a hardware resource device; the hardware resource device in the same resource pool is: a memory device, a hardware acceleration device or a computing device, and the hardware resource devices in different resource pools are different; The at least one upstream port of the at least one switching chip is used to connect to the upstream port of at least one switching chip in another resource pool; the at least one upstream port of the at least one switching chip is used to connect to the upstream ports of other switching chips in the resource pool where the current switching chip is located; The at least one switching chip is configured to: forward the upstream data to the corresponding downstream port according to the destination address of the upstream data sent by any upstream port; and / or forwarding the downstream data to the corresponding upstream port according to the destination address of the downstream data sent by any downstream port; Wherein, the at least one switching chip includes: a control logic module; The control logic module includes: a data packet conversion unit, a register unit and a resource sensing unit; The data packet conversion unit is used to: perform data format conversion on upstream data sent by any upstream port in the current switching chip and / or downstream data sent by any downstream port in the current switching chip; The register unit is used to configure the port information of any upstream port and / or any downstream port in the current switching chip; the port information includes: port parameters, port attributes and port status; The resource sensing unit is used to monitor whether each downstream port in the current switching chip is connected to a hardware resource device, and / or monitor resource usage information of the hardware resource device connected to the downstream port in the current switching chip, and generate a corresponding resource sensing table.

2. The device interconnection system according to claim 1, characterized in that: The at least one switching chip includes: a routing and forwarding engine module; The routing forwarding engine module is used to determine the destination address of upstream data sent by any upstream port in the current switching chip according to the routing table; and / or the destination address of downstream data sent by any downstream port in the current switching chip.

3. The device interconnection system according to claim 1, characterized in that: The at least one switching chip includes: a storage module; The storage module is used for storing a routing table, upstream data sent by any upstream port in the current switching chip, and downstream data sent by any downstream port in the current switching chip.

4. The device interconnection system according to claim 1, characterized in that: The at least one switching chip includes: a direct memory access engine module; The direct memory access engine module is used to realize communication between other resource pools connected to any upstream port of the current switching chip and hardware resource devices connected to any downstream port of the current switching chip using direct memory access technology.

5. The device interconnection system according to claim 1, characterized in that: Each downstream port of the at least one switching chip supports a first protocol, and each upstream port of the at least one switching chip supports a second protocol; Accordingly, the data packet conversion unit is used to: convert the upstream data sent by any upstream port in the current switching chip from the second protocol format to the first protocol format; and / or convert the upstream data sent by any downstream port in the current switching chip from the first protocol format to the second protocol format.

6. The device interconnection system according to claim 1, characterized in that: The register unit is used to configure a routing table and a resource awareness table.

7. The device interconnection system according to claim 1, characterized in that: The resource sensing unit is configured to update the resource sensing table in real time based on whether each downstream port is connected to a hardware resource device and / or resource usage information of the hardware resource device obtained through real-time monitoring.

8. The device interconnection system according to claim 1, characterized in that: Any hardware resource device is used to: send idle resource information in itself to the resource sensing unit according to a preset period; Correspondingly, the resource awareness unit updates the resource awareness table according to the information sent by the hardware resource device.

9. The device interconnection system according to claim 1, characterized in that: The resource sensing unit is used to: regularly detect whether the communication links between the upstream ports of the current switching chip and the connected resource pool are connected; regularly detect whether the communication links between the downstream ports of the current switching chip and the connected hardware resource devices are connected.

10. The device interconnection system according to claim 1, characterized in that: Each upstream port of the at least one switching chip is provided with a decoder; The decoder is used to determine the address mapping relationship between the memory of the computing device connected to the upstream port where the current decoder is located and the hardware resource device connected to the downstream port in the current switching chip.

11. The device interconnection system according to claim 10, characterized in that: The decoder is used to store memory capacity information of a computing device connected to the upstream port where the current decoder is located.

12. The device interconnection system according to claim 1, characterized in that: The at least one switching chip includes: a cache coherence interface module; The cache consistency interface module is used to provide a cache consistency transmission channel between hardware resource devices connected to each downstream port in the current switching chip.

13. The device interconnection system according to claim 1, characterized in that: The at least one switching chip includes: a clock and reset module; The clock and reset module is used to maintain clock synchronization between devices in the system.

14. The device interconnection system according to any one of claims 1 to 13, characterized in that: The device interconnection system further includes: a switching function module.

15. The device interconnection system according to claim 14, characterized in that: The at least one switching chip includes: a power management module; The power management module is used to provide power to the switching function module and the switching chips in each resource pool, and manage the power consumption of the switching function module and the switching chips in each resource pool.

16. The device interconnection system according to any one of claims 1 to 13, characterized in that: Each hardware resource device in each resource pool supports a CLOS topology and / or a fully interconnected topology.

17. A device interconnection method, characterized in that: The device interconnection system according to any one of claims 1 to 16 comprises: For any resource pool in the device interconnection system, connect at least one upstream port of at least one switch chip in the current resource pool to the upstream port of at least one switch chip in another resource pool; connect at least one downstream port of at least one switch chip in the current resource pool to a hardware resource device; and connect at least one upstream port of at least one switch chip in the current resource pool to the upstream ports of another switch chip in the current resource pool; The device interconnection system includes at least two resource pools, each resource pool includes at least one switching chip; the hardware resource devices in the same resource pool are: memory devices, hardware acceleration devices or computing devices, and the hardware resource devices in different resource pools are different; The at least one switching chip is configured to: forward the upstream data to the corresponding downstream port according to the destination address of the upstream data sent by any upstream port; and / or forward the downstream data to the corresponding upstream port according to the destination address of the downstream data sent by any downstream port; Wherein, the at least one switching chip includes: a control logic module; The control logic module includes: a data packet conversion unit, a register unit and a resource sensing unit; The data packet conversion unit is used to: perform data format conversion on upstream data sent by any upstream port in the current switching chip and / or downstream data sent by any downstream port in the current switching chip; The register unit is used to configure the port information of any upstream port and / or any downstream port in the current switching chip; the port information includes: port parameters, port attributes and port status; The resource sensing unit is used to monitor whether each downstream port in the current switching chip is connected to a hardware resource device, and / or monitor resource usage information of the hardware resource device connected to the downstream port in the current switching chip, and generate a corresponding resource sensing table.

18. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to execute the computer program to implement the method according to claim 17.

19. A non-volatile storage medium, characterized in that: Used to store a computer program, wherein when the computer program is executed by a processor, the method according to claim 17 is implemented.

20. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the method according to claim 17 is implemented.

Images