Array substrate, display panel and display device

Abstract

Embodiments of the present disclosure provide an array substrate, a display panel and a display device, and relate to the technical field of display, and are used for improving display effect. The array substrate comprises a substrate, a plurality of pixel driving circuits and a plurality of first scan signal lines. The plurality of pixel driving circuits are located on one side of the substrate. One pixel driving circuit comprises a compensation transistor, a driving transistor and a first conductive connection part, wherein the control electrode of the driving transistor and the second electrode of the compensation transistor are electrically connected to the first conductive connection part. The plurality of first scan signal lines are located on one side of the substrate, the plurality of first scan signal lines all extend along a row direction, and are arranged in sequence along a column direction, the row direction and the column direction are both parallel to the substrate, and are cross arranged; one first scan signal line is electrically connected to the control electrode of the compensation transistor of one row of pixel driving circuits. Wherein, the first conductive connection part and the first scan signal line do not overlap in the direction perpendicular to the substrate. The array substrate is used for the display panel.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to an array substrate, a display panel and a display device. BACKGROUND

[0002] At present, OLED (Organic Light-Emitting Diode) display devices are widely used due to their self-luminous, fast response, wide viewing angle and flexible substrate, etc. The OLED display device includes a plurality of sub-pixels, each of which includes a pixel driving circuit and a light emitting device. The light emitting device is driven by the pixel driving circuit to emit light, thereby realizing display. SUMMARY

[0003] Embodiments of the present disclosure aim to provide an array substrate, a display panel and a display device to improve the display effect of the display panel.

[0004] To achieve the above-mentioned purpose, embodiments of the present disclosure provide the following technical solutions.

[0005] In one aspect, an array substrate is provided. The array substrate includes a substrate, a plurality of pixel driving circuits and a plurality of first scan signal lines. The plurality of pixel driving circuits are located on one side of the substrate and arranged in multiple rows and multiple columns. One pixel driving circuit includes a compensation transistor, a driving transistor and a first conductive connection part, wherein the control electrode of the driving transistor and the second electrode of the compensation transistor are electrically connected to the first conductive connection part. The plurality of first scan signal lines are located on one side of the substrate. The plurality of first scan signal lines each extend along a row direction and are arranged in sequence along a column direction. The row direction and the column direction are both parallel to the substrate and are arranged in a cross manner. One first scan signal line is electrically connected to the control electrode of the compensation transistor of one row of pixel driving circuits. The first conductive connection part and the first scan signal line do not overlap in a direction perpendicular to the substrate.

[0006] In the above array substrate, by making the first conductive connection part and the first scan signal line not overlapping, the capacitance value between the first conductive connection part and the first scan signal line can be reduced. Therefore, when the voltage of the first scan signal line changes, the voltage change value of the first conductive connection part can be reduced, and the voltage of the first conductive connection part in the pixel driving circuit adjacent to the above-mentioned pixel driving circuit in the row direction is less affected by the first scan signal line. In this way, the light emitting brightness of the light emitting device driven by the adjacent pixel driving circuit is less affected, thereby improving the problem of horizontal crosstalk. When the above-mentioned array substrate 300 is applied to a display panel, the display effect of the display panel can be improved.

[0007] In some embodiments, the pixel driving circuit further comprises a data writing transistor and a first light emitting control transistor, a second electrode of the data writing transistor is electrically connected to a first electrode of the driving transistor and a second electrode of the first light emitting control transistor. The array substrate further comprises a plurality of second scan signal lines and a plurality of light emitting control signal lines located on one side of the substrate; the plurality of second scan signal lines each extend along the row direction and are arranged in sequence along the column direction, and one second scan signal line is electrically connected to the control electrode of the data writing transistor of one row of pixel driving circuits; the plurality of light emitting control signal lines each extend along the row direction and are arranged in sequence along the column direction, and one light emitting control signal line is electrically connected to the control electrode of the first light emitting control transistor of one row of pixel driving circuits. The array substrate further comprises a plurality of row pixel regions, the plurality of row pixel regions extend along the row direction and are arranged in sequence along the column direction; one row of pixel driving circuits is arranged in one row pixel region, and the first scan signal line, the second scan signal line and the light emitting control signal line electrically connected to the row of pixel driving circuits are located in the row pixel region where the row of pixel driving circuits is located. In one row pixel region, the orthographic projection of the first scan signal on the substrate is located on the side of the orthographic projection of the second scan signal line on the substrate away from the orthographic projection of the light emitting control signal line on the substrate, and the orthographic projection of the driving transistor on the substrate is located between the orthographic projection of the second scan signal line on the substrate and the orthographic projection of the light emitting control signal line on the substrate.

[0008] In some embodiments, in one row pixel region, the compensation transistor and the first conductive connection part are arranged in sequence along the column direction; wherein the compensation transistor passes through the first scan signal line, and the orthographic projection of the second electrode of the compensation transistor on the substrate is located on the side of the orthographic projection of the first scan signal line on the substrate close to the orthographic projection of the light emitting control signal line on the substrate, and the first conductive connection part is located on the side of the first scan signal line close to the light emitting control signal line.

[0009] In some embodiments, in one row pixel region, a part of the orthographic projection of the data writing transistor on the substrate is arranged opposite to the orthographic projection of the compensation transistor on the substrate along the row direction, and another part of the orthographic projection of the data writing transistor on the substrate is arranged opposite to the orthographic projection of the first conductive connection part on the substrate along the row direction.

[0010] In some embodiments, the data write transistor passes through the second scan signal line, and the data write transistor is located at a side of the first scan signal line close to the light emission control signal line. The array substrate further comprises a plurality of data transfer portions, the plurality of data transfer portions being located at a side of the plurality of pixel driving circuits away from the substrate. The array substrate further comprises a plurality of data lines, the plurality of data lines being located at a side of the plurality of data transfer portions away from the substrate, the plurality of data lines each extending along the column direction and arranged along the row direction in sequence, and one data line being electrically connected to the first electrode of the data write transistor of one row of pixel driving circuits through one data transfer portion. In one row pixel region, the orthogonal projection of the data transfer portion on the substrate is located between the orthogonal projection of the first scan signal line on the substrate and the orthogonal projection of the second scan signal line on the substrate.

[0011] In some embodiments, in one row pixel region, a part of the orthogonal projection of the first conductive connection portion on the substrate overlaps with a part of the orthogonal projection of the compensation transistor on the substrate, and another part of the orthogonal projection of the first conductive connection portion on the substrate overlaps with a part of the orthogonal projection of the driving transistor on the substrate.

[0012] In some embodiments, the pixel driving circuit further comprises a second conductive connection portion, the second conductive connection portion being electrically connected to the first electrode of the driving transistor, the second electrode of the first light emission control transistor and the second electrode of the data write transistor. The orthogonal projection of the second conductive connection portion on the substrate does not overlap with the orthogonal projection of the first scan signal line on the substrate.

[0013] In some embodiments, the pixel driving circuit further comprises a third reset transistor, the second electrode of the third reset transistor being electrically connected to the second conductive connection portion. The array substrate further comprises a plurality of second reset signal lines, the plurality of second reset signal lines being located at a side of the plurality of pixel driving circuits away from the substrate, the plurality of second reset signal lines each extending along the row direction and arranged along the column direction in sequence, and one second reset signal line being electrically connected to the control electrode of the third reset transistor of one row of pixel driving circuits; the second reset signal line electrically connected to the row of pixel driving circuits is located in the row pixel region in which the row of pixel driving circuits is located. In one row pixel region, the second reset signal line is located at a side of the light emission control signal line away from the first scan signal line.

[0014] In some embodiments, the array substrate further comprises a plurality of third initialization signal lines, the plurality of third initialization signal lines being located at a side of the substrate; the plurality of third initialization signal lines each extending along the row direction and arranged along the column direction in sequence, and one third initialization signal line being electrically connected to the first electrode of the third reset transistor of one row of pixel driving circuits. In one row pixel region, the orthogonal projection of the third initialization signal line on the substrate at least partially overlaps with the orthogonal projection of the light emission control signal line on the substrate.

[0015] In some embodiments, in a row pixel region: the third reset transistor passes the second reset signal line and is located on the side of the third initialization signal line away from the light emitting control signal line; wherein the orthogonal projection of the first electrode of the third reset transistor on the substrate is between the orthogonal projection of the third initialization signal line on the substrate and the orthogonal projection of the second reset signal line on the substrate, and the orthogonal projection of the second electrode of the third reset transistor on the substrate is on the side of the orthogonal projection of the second reset signal line on the substrate away from the orthogonal projection of the third initialization signal line on the substrate. The second conductive connection part crosses the third initialization signal line, the light emitting control signal line and the second reset signal line, and is electrically connected to the second electrode of the third reset transistor.

[0016] In some embodiments, the part of the orthogonal projection of the substrate on which the second conductive connection part overlaps the orthogonal projections on the substrate of the second electrode, the control electrode and part of the first electrode of the third reset transistor.

[0017] In some embodiments, the pixel driving circuit further comprises a second light emitting control transistor and a second reset transistor; the first electrode of the second light emitting control transistor is electrically connected to the second electrode of the driving transistor and the first electrode of the compensation transistor, and the second electrode of the second light emitting control transistor is electrically connected to the light emitting device and the second electrode of the second reset transistor; wherein the control electrode of the second light emitting control transistor of a row of pixel driving circuits is electrically connected to a light emitting control signal line, and the control electrode of the second reset transistor of a row of pixel driving circuits is electrically connected to a second reset signal line. The array substrate further comprises: a plurality of second initialization signal lines, the plurality of second initialization signal lines are located on the side of the plurality of pixel driving circuits away from the substrate, the plurality of second initialization signal lines extend along the row direction and are arranged along the column direction in sequence; and a second initialization signal line is electrically connected to the first electrode of the second reset transistor of a row of pixel driving circuits. In a row pixel region: the orthogonal projection of the second initialization signal line on the substrate is on the side of the orthogonal projection of the second reset signal line on the substrate away from the orthogonal projection of the first scan signal line on the substrate.

[0018] In some embodiments, the pixel driving circuit further comprises: a first reset transistor and a third conductive connection part, the third conductive connection part is electrically connected to the second electrode of the first reset transistor, the second electrode of the driving transistor and the first electrode of the compensation transistor. The array substrate further comprises: a plurality of first reset signal lines, the plurality of first reset signal lines are located on the side of the plurality of pixel driving circuits away from the substrate; the plurality of first reset signal lines all extend along the row direction and are arranged along the column direction in sequence, and a first reset signal line is electrically connected to the control electrode of the first reset transistor of a row of pixel driving circuits. In a row pixel region, the orthogonal projection of the first reset signal line on the substrate is on the side of the orthogonal projection of the light emitting control signal line on the substrate away from the orthogonal projection of the first scan signal line on the substrate.

[0019] In some embodiments, the array substrate further comprises: a plurality of first initialization signal lines, the plurality of first initialization signal lines are located on a side of the plurality of pixel driving circuits away from the substrate, the plurality of first initialization signal lines each extend along the row direction and are arranged in sequence along the column direction, and one first initialization signal line is electrically connected to the first electrode of the first reset transistor of one row of pixel driving circuits. In the row pixel region, the first initialization signal line is located on a side of the first reset signal line away from the first scan signal line.

[0020] In some embodiments, the first reset transistor passes the first reset signal line, the first electrode of the first reset transistor has a projection on the substrate located between the projection of the first reset signal line on the substrate and the projection of the first initialization signal line on the substrate, and the second electrode of the first reset transistor has a projection on the substrate located between the projection of the first reset signal line on the substrate and the projection of the second reset signal line on the substrate.

[0021] In some embodiments, the projection of the first reset signal line on the substrate overlaps the projection of the second initialization signal line on the substrate.

[0022] In some embodiments, the array substrate further comprises: a plurality of auxiliary signal lines, the plurality of auxiliary signal lines are located on a side of the substrate, the plurality of auxiliary signal lines each extend along the column direction and are arranged in sequence along the row direction. One auxiliary signal line is electrically connected to any one of the first initialization signal line, the second initialization signal line, and the third initialization signal line.

[0023] In some embodiments, one row of pixel driving circuits is divided into a plurality of repeating units arranged in sequence along the row direction, and one repeating unit includes at least one pixel driving circuit. The auxiliary signal line is located between two adjacent repeating units in the row direction.

[0024] In some embodiments, the repeating unit includes two pixel driving circuits, and the two pixel driving circuits in one repeating unit are symmetrically arranged in the row direction.

[0025] In some embodiments, the plurality of auxiliary signal lines include a first auxiliary signal line, a second auxiliary signal line, and a third auxiliary signal line, the first auxiliary signal line is electrically connected to the first initialization signal line, the second auxiliary signal line is electrically connected to the second initialization signal line, and the third auxiliary signal line is electrically connected to the third initialization signal line.

[0026] In some embodiments, the array substrate further comprises: a light shielding layer located between the substrate and the pixel driving circuit, and the projection of the light shielding layer on the substrate covers the projection of the driving transistor on the substrate.

[0027] In some embodiments, the light shielding layer comprises a plurality of light shielding portions and a plurality of connecting portions, a normal projection of the light shielding portion on the substrate covers a normal projection of the driving transistor on the substrate. Wherein, two light shielding portions adjacent in the row direction are connected by the connecting portion; and / or, two light shielding portions adjacent in the column direction are connected by the connecting portion; the light shielding layer is configured to receive the first voltage signal.

[0028] In another aspect, a display panel is provided. The display panel comprises the array substrate according to any one of the above embodiments, a light emitting device layer, and an encapsulation layer. Wherein, the light emitting device layer is located on a side of the array substrate away from the substrate; and the encapsulation layer is located on a side of the light emitting device layer away from the array substrate.

[0029] The display panel has the same structure and beneficial technical effects as the array substrate provided in some embodiments described above, and will not be repeated here.

[0030] In yet another aspect, a display device is provided. The display device comprises the display panel according to any one of the above embodiments and a driving chip, the driving chip is electrically connected to the display panel.

[0031] The display device has the same structure and beneficial technical effects as the display panel provided in some embodiments described above, and will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings needed to be used in some embodiments of the present disclosure will be briefly introduced below. Obviously, the drawings described below are only the drawings of some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0033] Figure 1 Structure diagram of the display device according to some embodiments;

[0034] Figure 2 Structure diagram of the display panel according to some embodiments;

[0035] Figure 3 Structure diagram of the display panel according to some embodiments;

[0036] Figure 4 Structure diagram of the display panel according to some embodiments;

[0037] Figure 5 Equivalent circuit diagram of the "8T1C" pixel driving circuit according to some embodiments;

[0038] Figure 6A timing diagram of an "8T1C" pixel driving circuit according to some embodiments;

[0039] Figure 7 This is a schematic diagram of the “8T1C” pixel driving circuit according to some embodiments during the first stage t1;

[0040] Figure 8 This is a schematic diagram of the “8T1C” pixel driving circuit according to some embodiments during the second stage t2;

[0041] Figure 9 This is a schematic diagram of the “8T1C” pixel driving circuit according to some embodiments at the third stage t3;

[0042] Figure 10 This is a schematic diagram of the “8T1C” pixel driving circuit according to some embodiments at the fourth stage t4;

[0043] Figure 11 The measured timing diagram of the "8T1C" pixel driving circuit is shown below.

[0044] Figure 12 This is a structural diagram of an array substrate according to some embodiments;

[0045] Figure 13 This is a diagram of the film structure of an array substrate according to some embodiments;

[0046] Figure 14A This is another film layer structure diagram of an array substrate according to some embodiments;

[0047] Figure 14B This is another film layer structure diagram of an array substrate according to some embodiments;

[0048] Figure 15 This is another structural schematic diagram of an array substrate according to some embodiments;

[0049] Figure 16 This is a structural diagram of an array substrate according to some embodiments;

[0050] Figure 17 This is a structural diagram of the first active film layer of an array substrate according to some embodiments;

[0051] Figure 18A This is a structural diagram of the first active film layer of an array substrate according to some embodiments;

[0052] Figure 18B Based on Figure 18A A diagram showing the film stacking of the array substrate with the first active film layer in the image.

[0053] Figure 19 This is a structural diagram of the first gate metal layer of an array substrate according to some embodiments;

[0054] Figure 20 Structure diagram for a first active film layer and a first gate metal layer stack according to some embodiments;

[0055] Figure 21 Structure diagram for a second gate metal layer of an array substrate according to some embodiments;

[0056] Figure 22 Structure diagram for a first active film layer, a first gate metal layer, and a second gate metal layer stack according to some embodiments;

[0057] Figure 23 Structure diagram for a second active film layer of an array substrate according to some embodiments;

[0058] Figure 24 Structure diagram for a first active film layer, a first gate metal layer, a second gate metal layer, and a second active film layer stack according to some embodiments;

[0059] Figure 25 Structure diagram for a third gate metal layer of an array substrate according to some embodiments;

[0060] Figure 26 Structure diagram for a first active film layer, a first gate metal layer, a second gate metal layer, a second active film layer, and a third gate metal layer stack according to some embodiments;

[0061] Figure 27 Structure diagram for an insulating layer of an array substrate according to some embodiments;

[0062] Figure 28 Structure diagram for a first active film layer, a first gate metal layer, a second gate metal layer, a second active film layer, a third gate metal layer, and an insulating layer stack according to some embodiments;

[0063] Figure 29 Structure diagram for a first source-drain metal layer of an array substrate according to some embodiments;

[0064] Figure 30 Structure diagram for a first active film layer, a first gate metal layer, a second gate metal layer, a second active film layer, a third gate metal layer, an insulating layer, and a first source-drain metal layer stack according to some embodiments;

[0065] Figure 31 Structure diagram for a second source-drain metal layer of an array substrate according to some embodiments;

[0066] Figure 32A structural diagram of a first active film layer, a first gate metal layer, a second gate metal layer, a second active film layer, a third gate metal layer, an insulating layer, a first source-drain metal layer, and a second source-drain metal layer stacked according to some embodiments. DETAILED DESCRIPTION

[0067] The technical solutions in the some embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0068] Unless otherwise required by context, the term "comprise" and other forms of the term "comprise", such as "comprises" and "comprising", and other forms of the term "comprise", such as "comprises" and "comprising", are to be construed in an open, inclusive, and non-exhaustive way, that is, in the sense of "including, but not limited to". In the description of the specification, the terms "some embodiments", "example", or "some examples" are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example includes in at least one embodiment or example of the present disclosure. The illustrative representation of the above terms does not necessarily mean the same embodiment or example. In addition, the specific features, structures, materials, or characteristics described can be included in any one or more embodiments or examples in any appropriate manner.

[0069] Hereinafter, the terms "first" and "second" are used only for descriptive purposes, and cannot be understood to indicate or imply relative importance or implicitly indicate the number of the indicated technical features. Therefore, the features defined with "first" and "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise stated.

[0070] In describing some embodiments, "coupled" and "connected" and their derivatives can be used. The term "connected" should be interpreted broadly, for example, "connected" can be fixedly connected, or detachably connected, or integrated; can be directly connected, or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" can also mean that two or more components do not have direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0071] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0072] As used herein, "about" or "approximately" includes the recited value and the average value within an acceptable range of deviation from the recited value, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system).

[0073] As used herein, "parallel," "perpendicular" includes the recited condition and conditions that approximate the recited condition, the approximation being within an acceptable range of deviation, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and near parallel, where the acceptable range of deviation for near parallel can be, for example, within 5°; "perpendicular" includes absolute perpendicular and near perpendicular, where the acceptable range of deviation for near perpendicular can also be, for example, within 5°.

[0074] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0075] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized examples of exemplary embodiments. In the interest of clarity, not all of the individual features of actual implementations are necessarily shown in a particular figure. Additionally, the order in which some or all of the features appear in the figures is intended to be an example and not an absolute. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated in the figures, which are schematically represented. For example, in reality, the regions illustrated in the figures can have irregular and / or roughly formed shapes. In addition, the exemplary embodiments are not limited to the specific examples of shapes and dimensions of the regions shown in the figures. Thus, the exemplary embodiments should not be construed as limited to the shapes of the regions illustrated in the figures, which are schematically represented, and are not intended to limit the scope of the exemplary embodiments.

[0076] Some embodiments of the present disclosure provide a display device.

[0077] Figure 1 A structural diagram of a display device according to some embodiments.

[0078] See Figure 1The display device 100 is a product with an image (including a still image or a dynamic image, where the dynamic image can be a video) display function. For example, the display device 100 can be any one of a display, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a personal digital assistant (PDA), a digital camera, a camcorder, a viewfinder, a navigator, a vehicle, a large-area wall, a household appliance, an information inquiry device (such as a business inquiry device of an electronic government, a bank, a hospital, and a power department), a monitor, and the like.

[0079] The display device 100 includes a display panel 200 and a driving chip electrically connected to the display panel 200, which can provide the display panel 200 with a data signal required for light emission of the display panel 200.

[0080] Figure 2 A structural diagram of the display panel 200 according to some embodiments.

[0081] Referring to Figure 2 The display panel 200 can include a display area AA and a peripheral area BB located at least on one side of the display area AA. The peripheral area BB can be arranged around the display area AA.

[0082] The display panel 200 can include a plurality of sub-pixels 210 arranged in the display area AA. The plurality of sub-pixels 210 can be arranged in an array.

[0083] The sub-pixel 210 is the smallest unit for picture display of the display panel 200. The plurality of sub-pixels 210 can include a red sub-pixel, a blue sub-pixel, and a green sub-pixel. By adjusting the brightness (gray scale) of different color sub-pixels, a variety of color displays can be realized through color combination and superposition, thereby realizing full-color display of the display panel 200.

[0084] In some other examples, the display panel 200 can further include a white sub-pixel.

[0085] Figure 3 A structural diagram of the display panel 200 according to some embodiments.

[0086] Referring to Figure 3 Each sub-pixel 210 can include a light emitting device 212 and a pixel driving circuit 211 for driving the light emitting device 212 to emit light.

[0087] In addition, the display panel 200 can further include a plurality of signal lines. For example, the signal lines can include a data line Dt, a first power signal line Vdd, a first scan signal line G-N, a second scan signal line G-P, a light-emitting control signal line Em, a first reset signal line Rst-P, a second reset signal line Rst-H, a first initialization signal line (not shown in the figure), a second initialization signal line, and a third initialization signal line, etc. The plurality of signal lines described above can be electrically connected to the pixel driving circuit 211 to provide the pixel driving circuit 211 with the signals required by the pixel driving circuit 211.

[0088] Figure 4 A structural diagram of the display panel 200 according to some embodiments.

[0089] Referring to Figure 4 , the display panel 200 includes an array substrate 300, a light-emitting device layer 400, and an encapsulation layer 500 which are sequentially stacked.

[0090] The array substrate 300 includes a plurality of pixel driving circuits 211 (as shown in Figure 3 , and the light-emitting device layer 400 includes a plurality of light-emitting devices 212 (as shown in Figure 3 .

[0091] The light-emitting device layer 400 includes an anode layer, a light-emitting layer, and a cathode layer which are sequentially stacked. In some examples, an electron transport layer is further provided between the cathode layer and the light-emitting layer, and a hole transport layer is further provided between the anode layer and the light-emitting layer.

[0092] The encapsulation layer 500 can cover the plurality of light-emitting devices 212 in the light-emitting device layer 400, encapsulate the light-emitting devices 212, prevent water vapor and oxygen in the external environment from entering the display panel 200, damage the organic material in the light-emitting device 212, and shorten the service life of the display panel 200.

[0093] In some embodiments, the pixel driving circuit 211 includes a plurality of transistors. In some embodiments, the structure of the pixel driving circuit 211 in the present disclosure includes a plurality of structures, which can be selected and arranged according to actual needs. For example, the structure of the pixel driving circuit can include “2T1C”, “6T1C”, “7T1C”, “6T2C”, “7T2C”, or “8T1C”, etc. Here, “T” represents a thin-film transistor, and the number before “T” represents the number of thin-film transistors; “C” represents a storage capacitor C, and the number before “C” represents the number of storage capacitors C. The following will be described by taking the “8T1C” pixel driving circuit as an example.

[0094] Figure 5 An equivalent circuit diagram of the “8T1C” pixel driving circuit 211 according to some embodiments.

[0095] Referring to Figure 5 The pixel driving circuit 211 includes a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light emitting control transistor T5, a second light emitting control transistor T6, a second reset transistor T7, a third reset transistor T8, and a capacitor Cst.

[0096] The gate g1 of the first reset transistor T1 is electrically connected to a first reset signal line Rst-P, the first pole s1 of the first reset transistor T1 is electrically connected to a first initialization signal line Vt1, and the second pole d1 of the first reset transistor T1 is electrically connected to a third node N3.

[0097] The gate g2 of the compensation transistor T2 is electrically connected to a first scan signal line G-N, the first pole s2 of the compensation transistor T2 is electrically connected to the third node N3, and the second pole d2 of the compensation transistor T2 is electrically connected to a first node N1.

[0098] The gate g3 of the driving transistor T3 is electrically connected to the first scan signal line G-N, the first pole s3 of the driving transistor T3 is electrically connected to a second node N2, and the second pole d3 of the driving transistor T3 is electrically connected to the third node N3.

[0099] The gate g4 of the data writing transistor T4 is electrically connected to a second scan signal line G-P, the first pole s4 of the data writing transistor T4 is electrically connected to a data signal line Dt, and the second pole d4 of the data writing transistor T4 is electrically connected to the second node N2.

[0100] The gate g5 of the first light emitting control transistor T5 is electrically connected to a light emitting control signal line Em, the first pole s5 of the first light emitting control transistor T5 is electrically connected to a first power supply signal line Vdd, and the second pole d5 of the first light emitting control transistor T5 is electrically connected to the second node N2.

[0101] The gate g6 of the second light emitting control transistor T6 is electrically connected to the light emitting control signal line Em, the first pole s6 of the second light emitting control transistor T6 is electrically connected to the third node N3, and the second pole d6 of the second light emitting control transistor T6 is electrically connected to an anode of the light emitting device 212.

[0102] The gate g7 of the second reset transistor T7 is electrically connected to a second reset signal line Rst-H, the first pole s7 of the second reset transistor T7 is electrically connected to a second initialization signal line Vt2, and the second pole d7 of the second reset transistor T7 is electrically connected to the anode of the light emitting device 212 and the second pole d6 of the second light emitting control transistor T6.

[0103] The gate g8 of the third reset transistor T8 is electrically connected to the second reset signal line Rst-H, the first pole s8 of the third reset transistor T8 is electrically connected to the third initialization signal line Vt3, and the second pole d8 of the third reset transistor T8 is electrically connected to the second node N2.

[0104] The first pole of the capacitor Cst is electrically connected to the first node N1, and the second pole is electrically connected to the first power supply signal line Vdd.

[0105] The cathode of the light emitting device 212 is electrically connected to the second power supply signal line.

[0106] In some examples, the voltage of the power supply signal provided by the first power supply signal line Vdd is higher than the voltage of the power supply signal provided by the second power supply signal line.

[0107] In some examples, the compensation transistor T2 can be an N-type transistor, and the first reset transistor T1, the driving transistor T3, the data write transistor T4, the first light emitting control transistor T5, the second light emitting control transistor T6, the second reset transistor T7, and the third reset transistor T8 can be P-type transistors.

[0108] In some examples, the compensation transistor T2 can be an oxide transistor, and the oxide transistor can be an N-type transistor, and the other transistors can be LTPS (Low Temperature Poly Silicon) transistors, and the LTPS transistors can be P-type transistors.

[0109] In some examples, the compensation transistor T2 can be an N-type transistor, and the first reset transistor T1, the driving transistor T3, the data write transistor T4, the first light emitting control transistor T5, the second light emitting control transistor T6, the second reset transistor T7, and the third reset transistor T8 can be P-type transistors.

[0110] In some examples, the compensation transistor T2 can be an N-type transistor, and the first reset transistor T1, the driving transistor T3, the data write transistor T4, the first light emitting control transistor T5, the second light emitting control transistor T6, the second reset transistor T7, and the third reset transistor T8 can be P-type transistors.

[0111] The driving process of the pixel driving circuit 211 provided by some embodiments of the present disclosure is described below with the compensation transistor T2 being an N-type transistor and the other transistors being P-type transistors as an example.

[0112] Figure 6 Timing diagram of the “8T1C” pixel driving circuit 211 according to some embodiments.

[0113] Please refer to Figure 6 , the first scan signal line G-N is used for transmitting the first scan signal Gt-N, the second scan signal line G-P is used for transmitting the second scan signal Gt-P, the light emitting control signal line Em is used for transmitting the light emitting control signal EM, the first reset signal line Rst-P is used for transmitting the first reset signal RST-P, and the second reset signal line Rst-H is used for transmitting the second reset signal RST-H.

[0114] The driving process of the pixel driving circuit 211 is as follows: one frame period includes a first stage t1, a second stage t2, a third stage t3, and a fourth stage.

[0115] Figure 7 The schematic diagram of the “8T1C” pixel driving circuit 211 in the first stage t1 according to some embodiments. It should be noted that in Figure 7 , the transistors covered with “X” represent that the transistors are in the off state, at this time, the first electrode and the second electrode of the transistor are not opened, and the transistors not covered with “X” represent that the transistors are in the on state, at this time, the first electrode and the second electrode of the transistor are in conduction.

[0116] Please refer to Figure 7 at the same time, and in combination with Figure 6 , in the first stage t1, the second reset signal RST-H is at a low level, under the control of the second reset signal RST-H, the second reset transistor T7 and the third reset transistor T8 are opened, therefore, the second initialization signal provided by the second initialization signal line Vt2 can reset the anode of the light emitting device 212 through the second reset transistor T7, and the third initialization signal provided by the third initialization signal line Vt3 can reset the second node N2 through the third reset transistor T8.

[0117] The light emitting control signal EM is at a high level, under the control of the light emitting control signal EM, the first light emitting control transistor T5 and the second light emitting control transistor are in the off state.

[0118] The second scan signal Gt-P is at a high level, under the control of the second scan signal Gt-P, the data writing transistor T4 is in the off state.

[0119] The first scan signal Gt-N is high, and under the control of the first scan signal Gt-N, the compensation transistor T2 is in an open state.

[0120] The first reset signal RST-P is high, and under the control of the first reset signal RST-P, the first reset transistor T1 is in a closed state.

[0121] The driving transistor T3 is in a closed state.

[0122] Figure 8 A schematic diagram of the "8T1C" pixel driving circuit 211 in the second stage t2 according to some embodiments.

[0123] Please refer to Figure 8 at the same time, and in combination with Figure 6 The second reset signal RST-H changes to high, and under the control of the second reset signal RST-H, the second reset transistor T7 and the third reset transistor T8 are closed.

[0124] The first reset signal RST-P changes to low, and under the control of the first reset signal RST-P, the first reset transistor T1 is opened. At this time, the first initialization signal provided by the first initialization signal line Vt1 can be written to the third node N3 through the first reset transistor T1, so as to reset the third node N3.

[0125] At the same time, the first scan signal Gt-N is high, and under the control of the first scan signal Gt-N, the compensation transistor T2 is in an open state. At this time, the first initialization signal provided by the first initialization signal line Vt1 can be written to the first node N1 through the first reset transistor T1 and the compensation transistor T2, so as to reset the first node N1. At this time, the first node N1 can make the driving transistor T3 open.

[0126] Under the condition that the driving transistor T3 is opened, the first initialization signal provided by the first initialization signal line Vt1 can be written to the second node N2 through the first reset transistor T1 and the driving transistor T3, so as to reset the second node N2.

[0127] After that, the first reset signal RST-P changes to high, so that the first reset transistor T1 is closed, and the second scan signal Gt-P changes to low, and under the control of the second scan signal Gt-P, the data writing transistor T4 is opened. Therefore, the data signal provided by the data signal line Dt can be written to the first node N1 in turn through the data writing transistor T4, the second node N2, the driving transistor T3, the third node N3 and the compensation transistor T2. At this time, the first node N1 to which the data signal is written can make the driving transistor T3 closed.

[0128] The light emitting control signal EM is at high level, under the control of the light emitting control signal EM, the first light emitting control transistor T5 and the second light emitting control transistor are in the off state.

[0129] Figure 9 A schematic diagram of the "8T1C" pixel driving circuit 211 at the third stage t3 according to some embodiments.

[0130] Please refer to Figure 9 at the same time, and in combination with Figure 6 The second scan signal Gt-P changes to high level, under the control of the second scan signal Gt-P, the data writing transistor T4 is closed.

[0131] The first scan signal Gt-N changes to low level, under the control of the first scan signal Gt-N, the compensation transistor T2 is closed.

[0132] The second reset signal RST-H changes to low level, under the control of the second reset signal RST-H, the second reset transistor T7 and the third reset transistor T8 are opened. Therefore, the second initialization signal provided by the second initialization signal line Vt2 can reset the anode of the light emitting device 212 through the second reset transistor T7, and the third initialization signal provided by the third initialization signal line Vt3 can reset the second node N2 through the third reset transistor T8.

[0133] Subsequently, the second reset signal RST-H changes to high level, so that the second reset transistor T7 and the third reset transistor T8 are closed.

[0134] The first reset signal RST-P remains at high level, under the control of the first reset signal RST-P, the first reset transistor T1 is in the off state.

[0135] The light emitting control signal EM continues to remain at high level, under the control of the light emitting control signal EM, the first light emitting control transistor T5 and the second light emitting control transistor are in the off state.

[0136] The driving transistor T3 is in the off state.

[0137] Figure 10 A schematic diagram of the "8T1C" pixel driving circuit 211 at the fourth stage t4 according to some embodiments.

[0138] Please refer to Figure 10 at the same time, and in combination with Figure 6, the light emitting control signal EM changes to low level, under the control of the light emitting control signal EM, the first light emitting control transistor T5 and the second light emitting control transistor T6 are turned on, and then the first power signal provided by the first power signal line Vdd can be written into the second node N2 through the first light emitting control transistor T5, at this time, a voltage difference is formed between the second node N2 and the first node N1, so that the driving transistor T3 is turned on, and the second light emitting control transistor T6 is turned on, therefore, the first power signal provided by the first power signal line Vdd can be written into the anode of the light emitting device 212 through the first light emitting control transistor T5, the second node N2, the driving transistor T3, the third node N3 and the second light emitting control transistor T6 in turn, so that the light emitting device 212 emits light.

[0139] The second scan signal Gt-P continues to maintain high level, and under the control of the second scan signal Gt-P, the data writing transistor T4 is turned off.

[0140] The first scan signal Gt-N continues to maintain low level, and under the control of the first scan signal Gt-N, the compensation transistor T2 is turned off.

[0141] The second reset signal RST-H changes to high level, and under the control of the second reset signal RST-H, the second reset transistor T7 and the third reset transistor T8 are turned off.

[0142] The first reset signal RST-P continues to maintain high level, and under the control of the first reset signal RST-P, the first reset transistor T1 is in the off state.

[0143] Figure 11 The actual measurement timing diagram of the "8T1C" pixel driving circuit 211.

[0144] Please refer to Figure 11 In the first scan signal Gt-N waveform test of the actual product, the inventors found that the potential of the first scan signal Gt-N will jump at the moment when the transistor controlled by the second reset signal RST-H is turned on, at this time, a glitch will be generated in the waveform of the first scan signal Gt-N. Among them, Figure 11 In the dashed box CC in the waveform of the first scan signal Gt-N.

[0145] Through analysis, it can be known that the potential jump of the first scan signal Gt-N is mainly caused by the voltage mutation of the second node N2 and the third node N3.

[0146] For example, please refer to Figure 6 and Figure 7In the driving process of the pixel driving circuit 211, in the first stage t1, the second reset signal RST-H transmitted by the second reset signal line Rst-H is low, and the third reset transistor T8 controlled thereby is turned on. At this time, the third initialization signal transmitted by the third initialization signal line Vt3 can be written into the second node N2 through the third reset transistor T8, so that the voltage of the second node N2 changes.

[0147] In the related art, the second node N2 overlaps with the first scan signal line G-N, and thus a capacitor can be formed between the second node N2 and the first scan signal line G-N. When the third initialization signal is written into the second node N2, the voltage of the second node N2 changes, and due to the capacitive coupling between the second node N2 and the first scan signal line G-N, the voltage of the first scan signal line G-N also changes.

[0148] For another example, please refer to Figure 6 and Figure 8 In the second stage t2, the first reset signal RST-P changes to low, the first reset transistor T1 is turned on, and the first initialization signal provided by the first initialization signal line Vt1 can be written into the third node N3 through the first reset transistor T1, so as to reset the third node N3, and thus the voltage of the third node N3 changes abruptly. At the same time, the first scan signal Gt-N is high, and the compensation transistor T2 is in the open state. At this time, the first initialization signal provided by the first initialization signal line Vt1 can be written into the first node N1 through the first reset transistor T1 and the compensation transistor T2, so as to reset the first node N1. At this time, the first node N1 can turn on the driving transistor T3. In the case where the driving transistor T3 is turned on, the first initialization signal provided by the first initialization signal line Vt1 can be written into the second node N2 through the first reset transistor T1 and the driving transistor T3, so as to reset the second node N2, and thus the voltage of the second node N2 changes abruptly. In summary, in the second stage t2, the voltages of the second node N2 and the third node N3 change abruptly.

[0149] In the related art, the second node N2 and the third node N3 are both arranged to overlap with the first scan signal line G-N. Therefore, the second node N2 and the third node N3 can form a capacitance with the first scan signal line G-N. Further, when the voltage of the second node N2 and the third node N3 changes, the voltage of the first scan signal line G-N can change due to the capacitive coupling between the second node N2 and the first scan signal line G-N and the capacitive coupling between the third node N3 and the first scan signal line G-N. In the related art, the capacitance between the second node N2 and the first scan signal line G-N is 1.829 fF. The capacitance between the third node N3 and the first scan signal line G-N is 3.340 fF. At this time, the capacitance between the second node N2 and the first scan signal line G-N is large, and the capacitance between the third node N3 and the first scan signal line G-N is large.

[0150] In addition, in the related art, a first scan signal line G-N can be arranged to overlap with the first node N1 of a row of pixel driving circuits 211. Therefore, the first scan signal line G-N can form a capacitance with the first node N1 of a row of pixel driving circuits 211. When the voltage of the second node N2 and / or the third node N3 of a pixel driving circuit 211 changes, the voltage of the first scan signal line G-N electrically connected to the pixel driving circuit 211 can change. Due to the capacitive coupling between the first scan signal line G-N and the first node N1, the voltage of the first node N1 of the pixel driving circuit 211 can fluctuate, which can cause a voltage fluctuation of about 0.1 mv at the N1 point.

[0151] At the same time, the first scan signal line G-N can also affect the voltage of the first node N1 in the pixel driving circuit 211 adjacent to the pixel driving circuit 211 in the row direction. The voltage of the first node N1 can affect the opening degree of the driving transistor T3, and further affect the brightness of the light emitting device 212. This phenomenon can be referred to as lateral crosstalk deterioration.

[0152] Based on this, the present disclosure provides an array substrate 300.

[0153] Figure 12 A structural diagram of the array substrate 300 according to some embodiments.

[0154] Please refer to Figure 12 The array substrate 300 includes a substrate 310, a plurality of first scan signal lines Gate-N, and a plurality of pixel driving circuits 211. The plurality of pixel driving circuits 211 and the plurality of first scan signal lines G-N are located on one side of the substrate 310.

[0155] The substrate 310 can include a display area AA and a peripheral area BB, where the display area AA of the substrate 310 is the same area as the display area AA of the display panel 200 provided in some of the above embodiments, and the peripheral area BB of the substrate 310 is the same area as the peripheral area BB of the display panel 200 provided in some of the above embodiments. The plurality of row pixel regions 301 can be located in the display area AA.

[0156] The substrate 310 can be a single-layer structure or a stacked structure, and can be rigid or flexible.

[0157] In addition to the substrate 310, the array substrate 300 can further include a first active layer, a first gate metal layer, a second gate metal layer, a second active layer, a third gate metal layer, a first source-drain metal layer, and a second source-drain metal layer, which are sequentially stacked on the substrate 310. For example, the first active layer and the first gate metal layer are used to form part of the transistors in the pixel driving circuit 211, such as the first reset transistor T1, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second reset transistor T7, and the third reset transistor T8. The second gate metal layer, the second active layer, and the third gate metal layer can be used to form another part of the transistors in the pixel driving circuit 211, such as the compensation transistor T2. In addition, the first gate metal layer, the second gate metal layer, and the third gate metal layer can be used to form part of the signal lines for providing signals to the pixel driving circuit 211. The first source-drain metal layer and the second source-drain metal layer can be used to form the remaining part of the signal lines for providing signals to the pixel driving circuit 211.

[0158] For example, the plurality of first scan signal lines G-N can be located on the side of the plurality of pixel driving circuits 211 away from the substrate 310. The plurality of pixel driving circuits 211 are arranged in multiple rows and multiple columns. A row of pixel driving circuits 211 extends along a row direction X, and a column of pixel driving circuits 211 extends along a column direction Y, where the row direction X and the column direction Y are both parallel to the substrate 310 and cross each other.

[0159] In some examples, the row direction X and the column direction Y can be approximately perpendicular, and the included angle between the row direction X and the column direction Y is approximately equal to 90°. For example, the included angle between the row direction X and the column direction Y can be 85°, 90°, or 95°.

[0160] The plurality of first scan signal lines G-N all extend along the row direction X and are sequentially arranged along the column direction Y. For example, a first scan signal line G-N passes through a row of pixel driving circuits 211. Here, “passes through” can be understood as the orthogonal projection of the first scan signal line G-N on the substrate 310 and the orthogonal projection of the pixel driving circuit 211 on the substrate 310 have an overlap.

[0161] The array substrate 300 can include a plurality of row pixel regions 301 extending along a row direction X and arranged in sequence along a column direction Y, and one row pixel driving circuit 211 arranged in one row pixel region 301, and the first scan signal line G-N, the second scan signal line G-P, the light-emitting control signal line Em, the first reset signal line Rst-P and the second reset signal line Rst-H electrically connected to the row pixel driving circuit 211 are all located in the row pixel region 301 where the row pixel driving circuit 211 is located.

[0162] Figure 13 A film layer structure diagram of the array substrate 300 according to some embodiments.

[0163] Referring to Figure 13 , one pixel driving circuit 211 includes a compensation transistor T2 and a driving transistor T3. The compensation transistor T2 includes a control electrode g2, a first electrode s2 and a second electrode d2, and the driving transistor T3 includes a control electrode g3, a first electrode s3 and a second electrode d3.

[0164] One first scan signal line G-N is electrically connected to the control electrode g2 of the compensation transistor T2 of one row pixel driving circuit 211, so that the first scan signal line G-N can provide the first scan signal Gt-N for the control electrode g2 of the compensation transistor T2 in the row pixel driving circuit 211.

[0165] Figure 14A Another film layer structure diagram of the array substrate 300 according to some embodiments.

[0166] Referring to Figure 14A , one pixel driving circuit 211 further includes a first conductive connection part N11, wherein the control electrode g3 of the driving transistor T3 (as shown in Figure 13 ) and the second electrode d2 of the compensation transistor T2 (as shown in Figure 13 ) are both electrically connected to the first conductive connection part N11. The first conductive connection part N11 does not overlap with the first scan signal line G-N in a direction perpendicular to the substrate 310.

[0167] The first conductive connection part N11 can be a first node N1 (as shown in Figure 5 ) in an equivalent circuit diagram of the pixel driving circuit 211.

[0168] The first conductive connection part N11 does not overlap with the first scan signal line G-N in a direction perpendicular to the substrate 310, which can be understood as that the orthogonal projection of the first conductive connection part N11 on the substrate 310 does not overlap with the orthogonal projection of the first scan signal line G-N on the substrate 310. In this way, the capacitance between the first conductive connection part N11 and the first scan signal line G-N can be reduced.

[0169] As can be seen from the above, in the driving process of the pixel driving circuit 211, in the first stage t1, the third initialization signal transmitted by the third initialization signal line Vt3 can be written into the second node N2 through the third reset transistor T8, so that the voltage of the second node N2 changes abruptly. In the second stage t2, the first initialization signal provided by the first initialization signal line Vt1 can be written into the third node N3 through the first reset transistor T1, so that the voltage of the third node N3 changes abruptly. Then, in the case that the driving transistor T3 is turned on, the first initialization signal provided by the first initialization signal line Vt1 can be written into the second node N2 through the first reset transistor T1 and the driving transistor T3, so that the voltage of the second node N2 changes abruptly. In the case that the voltage of the second node N2 changes abruptly and / or the voltage of the third node N3 changes abruptly, the voltage of the first scan signal line G-N changes. In some embodiments of the present disclosure, by making the first conductive connection N11 not overlap with the first scan signal line G-N, the capacitance value between the first conductive connection N11 and the first scan signal line G-N can be reduced, and thus, when the voltage of the first scan signal line G-N changes, the voltage change value of the first conductive connection N11 can be reduced, and the voltage of the first scan signal line G-N has less influence on the voltage of the first conductive connection N11 in the pixel driving circuit 211 adjacent to the pixel driving circuit 211 in the row direction X, so as to have less influence on the luminance of the light emitting device 212 driven by the adjacent pixel driving circuit 211, thereby improving the problem of lateral crosstalk, and improving the display effect of the display panel 200 when the array substrate 300 is applied to the display panel 200.

[0170] Please continue to refer to Figure 14A In some embodiments, the pixel driving circuit 211 further includes a data writing transistor T4 and a first light emitting control transistor T5. The second electrode d4 (as shown in FIG. 12) of the data writing transistor T4 is electrically connected to the first electrode s3 of the driving transistor T3 and the second electrode d5 (as shown in FIG. 12) of the first light emitting control transistor T5. Figure 13 Figure 13 The second electrode d5 (as shown in FIG. 12) of the first light emitting control transistor T5 is electrically connected to the first electrode s2 of the second reset transistor T2.

[0171] The array substrate 300 further includes a plurality of second scan signal lines G-P and a plurality of light emitting control signal lines Em, and the plurality of second scan signal lines G-P and the plurality of light emitting control signal lines Em are located on one side of the substrate 310. For example, the plurality of second scan signal lines G-P and the plurality of light emitting control signal lines Em can be located on the side of the plurality of pixel driving circuits 211 away from the substrate 310.

[0172] ​The plurality of second scan signal lines G-P extend along the row direction X and are arranged in sequence along the column direction Y. One second scan signal line G-P is electrically connected to the control electrode g4 of the data writing transistor T4 of one row of pixel driving circuits 211 (as shown in Figure 13 Thus, one second scan signal line G-P can provide the second scan signal Gt-P for the control electrode g4 of the data writing transistor T4 of one row of pixel driving circuits 211.

[0173] The plurality of light emitting control signal lines Em extend along the row direction X and are arranged in sequence along the column direction Y. One light emitting control signal line Em is electrically connected to the control electrode g5 of the first light emitting control transistor T5 of one row of pixel driving circuits 211. Thus, one light emitting control signal line Em can provide the light emitting control signal EM for the first light emitting control transistor T5 of one row of pixel driving circuits 211.

[0174] The first scan signal line G-N, the second scan signal line G-P and the light emitting control signal line Em electrically connected to one row of pixel driving circuits 211 are located in the row pixel region 301 where the row of pixel driving circuits 211 is located (as shown in Figure 12 ).

[0175] In one row pixel region 301 (as shown in Figure 12 ), the orthogonal projection of the first scan signal G-N on the substrate 310 is located on the side of the orthogonal projection of the second scan signal line G-P on the substrate 310 away from the orthogonal projection of the light emitting control signal line Em on the substrate 310, and the orthogonal projection of the driving transistor T3 on the substrate 310 is located between the orthogonal projection of the second scan signal line G-P on the substrate 310 and the orthogonal projection of the light emitting control signal line Em on the substrate 310.

[0176] Please refer to Figure 13 In the pixel driving circuit 211, the first electrode and the second electrode of the transistor are located on the two sides of the control electrode, and the gate line is electrically connected to the control electrode of the transistor, and thus the position of the gate line electrically connected to the transistor can determine the position of the transistor in the pixel driving circuit 211. The above-mentioned transistor can include the first reset transistor T1, the compensation transistor T2, …, and the third reset transistor T8. The gate line can include the first scan signal line G-N, the second scan signal line G-P, the light emitting control signal line Em, the first reset signal line Rst-P and the second reset signal line Rst-H.

[0177] In one row pixel region 301 (as Figure 12As shown: the orthographic projection of the first scan signal GN on the substrate 310 is located on the side of the orthographic projection of the second scan signal line GP on the substrate 310 that is away from the orthographic projection of the light emission control signal line Em on the substrate 310, and the orthographic projection of the driving transistor T3 on the substrate 310 is located between the orthographic projections of the second scan signal line GP and the light emission control signal line Em on the substrate 310. The first conductive connection N11 is electrically connected to the control electrode g3 of the driving transistor T3 and the second electrode d2 of the compensation transistor T2. Therefore, the orthographic projection of the end of the first conductive connection N11 electrically connected to the driving transistor T3 on the substrate 310 is located on the side of the second scan signal line GP that is away from the orthographic projection of the first scan signal line GN on the substrate 310. Furthermore, the first conductive connection N11 does not overlap with the first scan signal GN. Therefore, the orthographic projection of the first conductive connection N11 on the substrate 310 can be located on the side of the orthographic projection of the second scan signal line GP on the substrate 310 that is far away from the orthographic projection on the substrate 310, thereby ensuring that the first conductive connection N11 does not overlap with the first scan signal GN.

[0178] Please continue reading. Figure 14A In some embodiments, in a row pixel region 301 (e.g. Figure 12 As shown, within the array, compensation transistor T2 and the first conductive connection portion N11 are sequentially arranged along the column direction Y. The compensation transistor T2 passes through the first scan signal line GN.

[0179] Among them, the first electrode s2 and the second electrode d2 of the compensation transistor T2 are located on both sides of the first scan signal line GN in the column direction Y.

[0180] The orthogonal projection of the first electrode s2 of the compensation transistor T2 onto the substrate 310 is located on the side opposite to the orthogonal projection of the first scan signal line GN onto the substrate 310.

[0181] The orthographic projection of the second electrode d2 of the compensation transistor T2 onto the substrate 310 is located on the side of the orthographic projection of the first scan signal line GN onto the substrate 310 that is close to the orthographic projection of the light emission control signal line EM onto the substrate 310. The first conductive connection N11 is located on the side of the first scan signal line GN that is close to the light emission control signal line EM.

[0182] The phrase "compensation transistor T2 passes through the first scan signal line GN" can be understood as follows: the orthographic projection of compensation transistor T2 on substrate 310 overlaps with the orthographic projection of the first scan signal line GN on substrate 310. The overlapping portion of the first scan signal line GN and compensation transistor T2 can be reused as the control electrode g2 of compensation transistor T2.

[0183] The first conductive connection N11 is electrically connected to the second electrode d2 of the compensation transistor T2. Therefore, the orthographic projection of the first conductive connection N11 on the substrate 310 overlaps with the orthographic projection of the second electrode d2 of the compensation transistor T2 on the substrate 310.

[0184] One end of the first conductive connection part N11 is electrically connected to the control electrode g3 of the driving transistor T3 (e.g., ...). Figure 13 (as shown) and the second electrode d2 of the compensation transistor T2 (as shown) Figure 13 As shown in the diagram, the orthographic projection of the second electrode d2 of the compensation transistor T2 onto the substrate 310 is located on the side where the orthographic projection of the first scan signal line GN onto the substrate 310 is close to the orthographic projection of the light emission control signal line EM onto the substrate 310. Therefore, the orthographic projection of the end of the first conductive connection N11 electrically connected to the second electrode d2 of the compensation transistor T2 onto the substrate 310 can be located on the side where the orthographic projection of the first scan signal line GN onto the substrate 310 is close to the orthographic projection of the light emission control signal line EM onto the substrate 310. From the above embodiments, it can be seen that the orthographic projection of the end of the first conductive connection N11 electrically connected to the driving transistor T3 onto the substrate 310 is located on the side of the second scan signal line GP away from the orthographic projection of the first scan signal line GN onto the substrate 310. Therefore, the orthographic projection of the first conductive connection N11 as a whole onto the substrate 310 is located on the side where the orthographic projection of the first scan signal line GN onto the substrate 310 is close to the orthographic projection of the light emission control signal line EM onto the substrate 310, thereby ensuring that the first conductive connection N11 and the first scan signal line GN do not overlap.

[0185] Please continue reading. Figure 14A In a row pixel region 301 (e.g.) Figure 12 As shown, a portion of the orthogonal projection of the data writing transistor T4 onto the substrate 310 is positioned opposite to the orthogonal projection of the compensation transistor T2 onto the substrate 310 in the row direction X. Another portion of the orthogonal projection of the data writing transistor T4 onto the substrate 310 is positioned opposite to the orthogonal projection of the first conductive connection portion N11 onto the substrate 310 in the row direction X. This arrangement reduces the size of the pixel driving circuit 211 in the column direction Y.

[0186] Among them, the data writing transistor T4 is located on the side of the compensation transistor T2 in the row direction X, and the data writing transistor T4 is also located on the side of the first conductive connection part N11 in the row direction X.

[0187] Please continue reading. Figure 14AThe data write transistor T4 is connected to the second scan signal line G-P, and the data write transistor T4 is located on the side of the first scan signal line G-N close to the light-emitting control signal line EM. One second scan signal line G-P overlaps the data write transistor T4 in one row of pixel driving circuits 211.

[0188] The array substrate 300 further comprises a plurality of data transfer portions 394, and the plurality of data transfer portions 394 are located on the side of the plurality of pixel driving circuits 211 away from the substrate 310.

[0189] Figure 14B A further film layer structure diagram of the array substrate 300 according to some embodiments.

[0190] Please refer to Figure 14B and combine with Figure 14A The array substrate 300 further comprises a plurality of data lines Dt. The plurality of data lines Dt are located on the side of the plurality of data transfer portions 394 away from the substrate 310, the plurality of data lines Dt all extend along the column direction Y and are arranged along the row direction Y in sequence, and one data line Dt is electrically connected to the first electrode s4 of the data write transistor T4 in one row of pixel driving circuits 211 through one data transfer portion 394.

[0191] In one row of pixel regions 301, the orthogonal projection of the data transfer portion 394 on the substrate 310 is located between the orthogonal projection of the first scan signal line G-N on the substrate 310 and the orthogonal projection of the second scan signal line G-P on the substrate 310.

[0192] The data line Dt can be electrically connected to the first electrode s4 of the data write transistor T4 through the data transfer portion 394, so that the data transfer portion 394 can receive the data signal transmitted by the data line Dt, and thus the voltage of the data transfer portion 394 can change with the data signal. When the voltage of the data transfer portion 394 changes, it may interfere with the transistors around it. By arranging the data transfer portion 394 between the first scan signal line G-N and the second scan signal line G-P, the first scan signal line G-N and the second scan signal line G-P can shield the interference of the data transfer portion 394 on other transistors.

[0193] In some examples, the first scan signal line G-N and the second scan signal line G-P have at least two different intervals in the column direction Y. For example, the first scan signal line G-N can include a main body portion G1 and an isolation portion G2, wherein a projection of the main body portion G1 on the substrate 310 can be disposed opposite a projection of the data writing transistor T4 on the substrate 310 in the column direction Y, and a projection of the isolation portion G2 on the substrate 310 can be disposed opposite a projection of the data relay portion 394 on the substrate 310 in the column direction Y. The distance between the isolation portion G2 and the second scan signal line G-P in the column direction Y is greater than the distance between the main body portion G1 and the second scan signal line G-P in the column direction Y. In this way, a larger space can be provided for the data relay portion 394.

[0194] In some examples, the isolation portion G2 and the second scan signal line G-P have at least two different intervals in the column direction Y. For example, the isolation portion G2 can include a first isolation portion connected to the main body portion G1 and a second isolation portion connected to the first isolation portion, wherein the distance between the second isolation portion and the second scan signal line G-P in the column direction Y is greater than the distance between the first isolation portion and the second scan signal line G-P in the column direction Y. The first isolation portion can extend away from the second scan signal line G-P.

[0195] Please continue to refer to Figure 14A In one row pixel region 301 (as shown in Figure 12 A portion of the projection of the first conductive connection portion N11 on the substrate 310 overlaps a portion of the projection of the compensation transistor T2 on the substrate 310. For example, a portion of the projection of the first conductive connection portion N11 on the substrate 310 can overlap the projection of the second electrode d2 of the compensation transistor T2 on the substrate 310.

[0196] Another portion of the projection of the first conductive connection portion N11 on the substrate 310 overlaps a portion of the projection of the drive transistor T3 on the substrate 310.

[0197] The projection of the second electrode d2 of the compensation transistor T2 on the substrate 310 and the projection of the drive transistor T3 on the substrate 310 are both located on the side of the first scan signal line G-N close to the light emission control signal line EM, and in this case, the second scan signal line G-P, the light emission control signal line EM, the second electrode d2 of the compensation transistor T2, and the drive transistor T3 are all located on the same side of the first scan signal line G-N in the column direction Y. In this way, the projection of the first conductive connection portion N11 on the substrate 310 does not overlap the projection of the first scan signal line G-N on the substrate 310.

[0198] Please continue to refer toFigure 14A In some embodiments, the pixel driving circuit 211 further includes a second conductive connection N22, which is electrically connected to the first electrode s3 of the driving transistor T3, the second electrode d5 of the first light-emitting control transistor T5, and the second electrode d4 of the data writing transistor T4.

[0199] The orthogonal projection of the second conductive connection N22 on the substrate 310 does not overlap with the orthogonal projection of the first scan signal line G-N on the substrate 310.

[0200] In the equivalent circuit diagram of the pixel driving circuit 211, the second conductive connection N22 can be a second node N2 (as shown in Figure 5 ).

[0201] The orthogonal projection of the second conductive connection N22 on the substrate 310 does not overlap with the orthogonal projection of the first scan signal line G-N on the substrate 310, which can be understood as that the second conductive connection N22 does not overlap with the first scan signal line G-N in the direction perpendicular to the substrate 310, thereby reducing the capacitance between the second conductive connection N22 and the first scan signal line G-N.

[0202] Please refer to Figure 14A again, and combine with Figure 7 and Figure 8During the driving process of the pixel driving circuit 211, the voltage of the second conductive connection N22 undergoes abrupt changes in both the first stage t1 and the second stage t2. By ensuring that the orthographic projections of the second conductive connection N22 and the first scan signal line GN on the substrate 310 do not overlap, the capacitance formed between the second conductive connection N22 and the first scan signal line GN can be reduced. This reduces the impact of the voltage change of the second conductive connection N22 on the voltage of the first scan signal line GN, thereby reducing the voltage change value of the first scan signal line GN. Furthermore, it reduces the impact of the first scan signal line GN on the voltage of the first conductive connection N11, i.e., reduces the voltage change value of the first conductive connection N11. In summary, in some embodiments of this disclosure, by ensuring that the orthographic projections of the second conductive connection N22 and the first scan signal line GN on the substrate 310 do not overlap, the voltage change of the first scan signal line GN has a smaller impact on the luminous brightness of the light-emitting device 212. Furthermore, when the voltage change value of the first scan signal line GN is small, the first scan signal line GN has a smaller impact on the voltage of the first conductive connection portion N11 in the pixel driving circuit 211 adjacent to the pixel driving circuit 211 in the row direction X. As a result, the impact on the light emission brightness of the light-emitting device 212 driven by the adjacent pixel driving circuit 211 is smaller, thereby improving the problem of lateral crosstalk. When the array substrate 300 is applied to the display panel 200, the display effect of the display panel 200 can be improved.

[0203] The second scan signal line GP is electrically connected to the control electrode g4 of the data writing transistor T4, and the light control signal line Em is electrically connected to the control electrode g5 of the first light-emitting control transistor T5. Therefore, the position of the second scan signal line GP determines the position of the control electrode g4 of the data writing transistor T4, and the position of the light control signal line Em determines the position of the control electrode g5 of the first light-emitting control transistor T5.

[0204] In some of the embodiments above, in a row pixel region 301 (e.g. Figure 12 As shown: the orthographic projection of the first scan signal GN on the substrate 310 is located on the side of the orthographic projection of the second scan signal line GP on the substrate 310 that is far from the orthographic projection of the light-emitting control signal line Em on the substrate 310, and the driving transistor T3 is located between the second scan signal line GP and the light-emitting control signal line Em. This arrangement allows the driving transistor T3, the data writing transistor T4, and the first light-emitting control transistor T5 to be located on the same side of the first scan signal line GN.

[0205] The second conductive connection N22 is electrically connected to the second electrode d4 of the data writing transistor T4, the second electrode d5 of the first light emitting control transistor T5, and the control electrode g3 of the driving transistor T3. Therefore, the second conductive connection N22 can be located on the same side of the first scan signal G-N as the data writing transistor T4, the first light emitting control transistor T5, and the driving transistor T3. In this way, the second conductive connection N22 can not overlap the first scan signal G-N, and the capacitance value of the formed capacitance between the second conductive connection N22 and the first scan signal line G-N can be reduced.

[0206] In some embodiments, the data writing transistor T4 and the first light emitting control transistor T5 are sequentially arranged along the column direction Y, and the first light emitting control transistor T5 is located on the side of the data writing transistor T4 away from the first scan signal line G-N.

[0207] In some embodiments, the pixel driving circuit 211 further includes a third reset transistor T8, and the second electrode d8 of the third reset transistor T8 is electrically connected to the second conductive connection N22.

[0208] The array substrate 300 further includes a plurality of second reset signal lines Rst-H, the plurality of second reset signal lines Rst-H are located on the side of the plurality of pixel driving circuits 211 away from the substrate 310, the plurality of second reset signal lines Rst-H each extend along the row direction X and are sequentially arranged along the column direction Y.

[0209] One second reset signal line Rst-H is electrically connected to the control electrode g8 of the third reset transistor T8 of one row of pixel driving circuits 211, and thus the one second reset signal line Rst-H can provide the second reset signal RST-H to the control electrode g8 of the third reset transistor T8 of the one row of pixel driving circuits 211.

[0210] The second reset signal line Rst-H electrically connected to one row of pixel driving circuits 211 is located in the row pixel region 301 (as shown in Figure 12 ) in which the one row of pixel driving circuits 211 is located.

[0211] In one row pixel region (as shown in Figure 12 ), the second reset signal line Rst-H is located on the side of the light emitting control signal line Em away from the first scan signal line G-N.

[0212] By locating the second reset signal line Rst-H on the side of the light emitting control signal line Em away from the first scan signal line G-N, the third reset transistor T8 and the first light emitting control transistor T5 can be located on the same side of the first scan signal line G-N. As known from the above embodiments, the data writing transistor T4, the driving transistor T3 and the first light emitting control transistor T5 can be located on the same side of the first scan signal line G-N. The second conductive connection N22 can be electrically connected to the second electrode d8 of the third reset transistor T8, the second electrode d4 of the data writing transistor T4, the first electrode s3 of the driving transistor T3 and the second electrode d5 of the first light emitting control transistor T5. Since the third reset transistor T8, the data writing transistor T4, the driving transistor T3 and the first light emitting control transistor T5 are located on the same side of the first scan signal line G-N, the second conductive connection N22 can be avoided from overlapping the first scan signal line G-N, and thus the capacitance between the second conductive connection N22 and the first scan signal line G-N can be reduced.

[0213] In some embodiments, the array substrate 300 further comprises a plurality of third initialization signal lines Vt3 located on one side of the substrate 310. For example, the plurality of third initialization signal lines Vt3 can be located on the side of the plurality of pixel driving circuits 211 away from the substrate 310.

[0214] The plurality of third initialization signal lines Vt3 all extend along the row direction X and are arranged along the column direction Y in sequence. One third initialization signal line Vt3 is electrically connected to the first electrode s3 of the third reset transistor T8 of one row of pixel driving circuits 211.

[0215] The third initialization signal line Vt3 electrically connected to one row of pixel driving circuits 211 is located within the row of pixel regions 301 (as shown in Figure 12 ) in which the row of pixel driving circuits 211 is located.

[0216] In one row of pixel regions 301 (as shown in Figure 12 ), the orthogonal projection of the third initialization signal line Vt3 on the substrate 310 at least partially overlaps the orthogonal projection of the light emitting control signal line Em on the substrate 310. At this time, the orthogonal projection of the third initialization signal line Vt3 on the substrate 310 is located between the orthogonal projection of the second reset signal line Rst-H on the substrate 310 and the orthogonal projection of the second scan signal line G-P on the substrate 310.

[0217] The orthogonal projection of the third initialization signal line Vt3 on the substrate 310 at least partially overlaps the orthogonal projection of the light emitting control signal line Em on the substrate 310, so as to reduce the size of the pixel driving circuit 211 in the column direction Y.

[0218] Please continue to refer to Figure 14Aand in combination Figure 13 In one row pixel region 301 (as shown): the third reset transistor T8 passes the second reset signal line Rst-H, and is located on the side of the third initialization signal line Vt3 away from the light emission control signal line Em. Figure 12

[0219] The first pole s8 and the second pole d8 of the third reset transistor T8 are respectively located on two sides of the second reset signal line Rst-H in the column direction Y. For example, the orthographic projection of the first pole s8 of the third reset transistor T8 on the substrate 310 is located between the orthographic projection of the third initialization signal line Vt3 on the substrate 310 and the orthographic projection of the second reset signal line Rst-H on the substrate 310, and thus the first pole s8 of the third reset transistor T8 is arranged adjacent to the third initialization signal line Vt3 in the column direction Y.

[0220] The orthographic projection of the second pole d8 of the third reset transistor T8 on the substrate 310 is located on the side of the orthographic projection of the second reset signal line Rst-H on the substrate 310 away from the orthographic projection of the third initialization signal line Vt3 on the substrate 310.

[0221] The first pole s8 of the third reset transistor T8 is electrically connected to the third initialization signal line Vt3, and the first pole s8 of the third reset transistor T8 is arranged adjacent to the third initialization signal line Vt3 in the column direction Y, so that the first pole s8 of the third reset transistor T8 can be electrically connected to the third initialization signal line Vt3.

[0222] In some examples, the array substrate 300 can further include a second adapter 392, wherein the second adapter 392 can be electrically connected to the third initialization signal line Vt3 and the first pole s8 of the third reset transistor T8, respectively. For example, the orthographic projection of the second adapter 392 on the substrate 310 can overlap the orthographic projection of the third initialization signal line Vt3 on the substrate 310 and the orthographic projection of the first pole s8 of the third reset transistor T8 on the substrate 310 at both ends of the orthographic projection of the second adapter 392 on the substrate 310.

[0223] The second conductive connection N22 crosses the third initialization signal line Vt3, the light emission control signal line Em, and the second reset signal line Rst-H, and is electrically connected to the second pole d8 of the third reset transistor T8.

[0224] The second conductive connection N22 crosses the third initialization signal line Vt3, the light emission control signal line Em, and the second reset signal line Rst-H, which can be understood as that the orthographic projection of the second conductive connection N22 on the substrate 310 can partially overlap the orthographic projection of the third initialization signal line Vt3, the light emission control signal line Em, and the second reset signal line Rst-H on the substrate 310. ​

[0225] The second conductive connection N22 can extend in the column direction Y, for example.

[0226] In some embodiments, a part of the second conductive connection N22 in the orthographic projection of the substrate 310 overlaps with the second electrode d8, the control electrode g8 and a part of the first electrode s8 of the third reset transistor T8 in the orthographic projection of the substrate 310. The second electrode d8, the control electrode g8 and the first electrode s8 of the third reset transistor T8 can be arranged in sequence in the column direction Y. By making a part of the second conductive connection N22 in the orthographic projection of the substrate 310 overlap with the second electrode d8, the control electrode g8 and a part of the first electrode s8 of the third reset transistor T8 in the orthographic projection of the substrate 310, the width of the pixel driving circuit 211 in the row direction X can be reduced.

[0227] In some examples, a part of the orthographic projection of the third reset transistor T8 on the substrate 310 is arranged opposite to a part of the orthographic projection of the first light emitting control transistor T5 on the substrate 310 in the row direction X, which can reduce the width of the pixel driving circuit 211 in the row direction X.

[0228] In some embodiments, the driving transistor T3, the data writing transistor T4, the first light emitting control transistor T5 and the third reset transistor T8 are all located on the side of the first scan signal line G-N where the second scan signal line G-P is arranged. At this time, the driving transistor T3, the data writing transistor T4, the first light emitting control transistor T5 and the third reset transistor T8 all do not overlap with the first scan signal line G-N. Therefore, the first electrode s3 of the driving transistor T3, the second electrode d4 of the data writing transistor T4, the second electrode d5 of the first light emitting control transistor T5 and the second electrode d8 of the third reset transistor T8 electrically connected by the second conductive connection N22 all do not overlap with the first scan signal line G-N.

[0229] The voltage of the first electrode s3 of the driving transistor T3, the second electrode d4 of the data writing transistor T4, the second electrode d5 of the first light emitting control transistor T5, and the second electrode d8 of the third reset transistor T8 can change with the second conductive connection N22, so when the voltage of the above four changes, the voltage fluctuation of the first scan signal line G-N will also occur. By making the first electrode s3 of the driving transistor T3, the second electrode d4 of the data writing transistor T4, the second electrode d5 of the first light emitting control transistor T5, and the second electrode d8 of the third reset transistor T8 all electrically connected to the second conductive connection N22 without overlapping with the first scan signal line G-N, the capacitance between the above four and the first scan signal line G-N can be reduced, so when the voltage of the second conductive connection N22 changes, the voltage fluctuation of the first scan signal line G-N can be reduced, thereby reducing the influence of the first scan signal line G-N on the voltage of the first conductive connection N11, and further improving the display effect of the display panel.

[0230] Please continue to refer to Figure 14A , and in combination with Figure 13 In some embodiments, the pixel driving circuit 211 further includes a second light emitting control transistor T6 and a second reset transistor T7.

[0231] The first electrode s6 of the second light emitting control transistor T6 is electrically connected to the second electrode d3 of the driving transistor T3 and the first electrode s2 of the compensation transistor T2, and the second electrode d6 of the second light emitting control transistor T6 is electrically connected to the light emitting device 212 and the second electrode d7 of the second reset transistor T7.

[0232] The control electrode g6 of the second light emitting control transistor T6 of a row of pixel driving circuits 211 is electrically connected to a light emitting control signal line Em, and thus a light emitting control signal line Em can provide a light emitting control signal EM for the control electrode g6 of the second light emitting control transistor T6 of a row of pixel driving circuits 211.

[0233] The control electrode g7 of the second reset transistor T7 of a row of pixel driving circuits 211 is electrically connected to a second reset signal line Rst-H, and thus a second reset signal line Rst-H can provide a second reset signal RST-H for the control electrode g7 of the second reset transistor T7 of a row of pixel driving circuits 211.

[0234] The array substrate 300 further includes a plurality of second initialization signal lines Vt2, the plurality of second initialization signal lines Vt2 are located on the side of the plurality of pixel driving circuits 211 away from the substrate 310, the plurality of second initialization signal lines Vt2 extend along the row direction X and are arranged in sequence along the column direction Y.

[0235] A second initialization signal line Vt2 is electrically connected to the first electrode s7 of the second reset transistor T7 of a row of pixel driving circuits 211, and thus a second initialization signal provided by the second initialization signal line Vt2 can reset the first electrode s7 of the second reset transistor T7 of the row of pixel driving circuits 211.

[0236] The second reset signal line Rst-H and the second initialization signal line Vt2 electrically connected to the row of pixel driving circuits 211 are both located in the row of pixel regions 301 (as shown in Figure 12 ).

[0237] In one row of pixel regions 301 (as shown in Figure 12 ), the orthographic projection of the second initialization signal line Vt2 on the substrate 310 is located on the side of the orthographic projection of the second reset signal line Rst-H on the substrate 310 away from the orthographic projection of the first scan signal line G-N on the substrate 310.

[0238] The first electrode s7 and the second electrode d7 of the second reset transistor T7 can be located on two sides of the second reset signal line Rst-H in the column direction Y, respectively. For example, the orthographic projection of the first electrode s7 of the second reset transistor T7 on the substrate 310 can be located between the orthographic projection of the second reset signal line Rst-H on the substrate 310 and the orthographic projection of the second initialization signal line Vt2 on the substrate 310. In this way, the first electrode s7 of the second reset transistor T7 and the second initialization signal line Vt2 can be arranged adjacent to each other in the column direction Y, so that the first electrode s7 of the second reset transistor T7 and the second initialization signal line Vt2 can be electrically connected.

[0239] In some examples, the array substrate 300 can further include a fifth adapter 395, which can be electrically connected to the first electrode s7 of the second reset transistor T7 and the second initialization signal line Vt2, and thus the second initialization signal line Vt2 can be electrically connected to the first electrode s7 of the second reset transistor T7 through the fifth adapter 395. The two ends of the orthographic projection of the fifth adapter 395 on the substrate 310 can overlap with the orthographic projection of the first electrode s7 of the second reset transistor T7 on the substrate 310 and the orthographic projection of the second initialization signal line Vt2 on the substrate 310, respectively.

[0240] In some examples, the orthographic projection of the second reset transistor T7 on the substrate 310 and the orthographic projection of the third reset transistor T8 on the substrate 310 are arranged opposite to each other in the row direction X. In this way, the size of the pixel driving circuit 211 in the column direction Y can be reduced.

[0241] Please continue to refer to Figure 14A , and in combination with Figure 13In some embodiments, the pixel driving circuit 211 further comprises a first reset transistor T1 and a third conductive connection N33. The third conductive connection N33 is electrically connected to the second electrode d1 of the first reset transistor T1, the second electrode d3 of the driving transistor T3, the first electrode s2 of the compensation transistor T2, and the first electrode s6 of the second light-emitting control transistor T6.

[0242] The array substrate 300 further comprises a plurality of first reset signal lines Rst-P. The plurality of first reset signal lines Rst-P are located on the side of the plurality of pixel driving circuits 211 away from the substrate 310; the plurality of first reset signal lines Rst-P are all extended along the row direction X and arranged along the column direction Y in sequence, and one first reset signal line Rst-P is electrically connected to the control electrode g1 of the first reset transistor T1 of one row of pixel driving circuits 211, so that the one first reset signal line Rst-P can provide the first reset signal RST-P for the control electrode g1 of the first reset transistor T1 of the one row of pixel driving circuits 211.

[0243] The first reset signal line Rst-P electrically connected to one row of pixel driving circuits 211 is located on the row of pixel regions 301 (as shown in Figure 12 ) in which the one row of pixel driving circuits 211 is located.

[0244] In the row of pixel regions 301 (as shown in Figure 12 ), the orthogonal projection of the first reset signal line Rst-P on the substrate 310 is located on the side of the orthogonal projection of the light-emitting control signal line Em on the substrate 310 away from the orthogonal projection of the first scan signal line G-N on the substrate 310.

[0245] For example, in the row of pixel regions 301 (as shown in Figure 12 ), the orthogonal projection of the first reset signal line Rst-P on the substrate 310 is located on the side of the orthogonal projection of the second reset signal line Rst-H on the substrate 310 away from the orthogonal projection of the first light-emitting control signal line EM on the substrate 310.

[0246] The position of the first reset signal line Rst-P determines the position of the first reset transistor T1 in the pixel driving circuit 211, and by locating the first reset signal line Rst-P on the side of the light-emitting control signal line Em away from the first scan signal line Em, the first reset transistor T1 and the compensation transistor T2 can be respectively located on the two sides of the first scan signal line Em.

[0247] The normal projection of the first electrode s2 of the compensation transistor T2 on the substrate 310 is located on the side of the normal projection of the first scan signal line G-N on the substrate 310 which is away from the normal projection of the light emitting control signal line EM on the substrate 310. The third conductive connection N33 can be electrically connected to the first electrode s2 of the compensation transistor T2 and the second electrode d2 of the first reset transistor T1. Therefore, the third conductive connection N33 can extend from one side of the first scan signal line G-N in the column direction Y to the other side of the first scan signal line G-N in the column direction Y, and at this time, the third conductive connection N33 overlaps the first scan signal line G-N in the direction perpendicular to the substrate 310.

[0248] In addition, since the third conductive connection N33 is also electrically connected to the second electrode d3 of the driving transistor T3 and the first electrode s6 of the second light emitting control transistor T6, the voltage of the second electrode d3 of the driving transistor T3 and the voltage of the first electrode s6 of the second light emitting control transistor T6 are equal to the voltage of the third conductive connection N33.

[0249] As can be seen from the above embodiments, the normal projection of the driving transistor T3 on the substrate 310 and the normal projection of the second light emitting control transistor T6 on the substrate 310 are both located on the side of the normal projection of the first scan signal line G-N on the substrate 310 which is close to the normal projection of the light emitting control signal line EM on the substrate 310. Therefore, the normal projection of the second electrode d3 of the driving transistor T3 on the substrate 310 and the normal projection of the first electrode s6 of the second light emitting control transistor T6 on the substrate 310 are located on the side of the normal projection of the first scan signal line G-N on the substrate 310 which is close to the normal projection of the light emitting control signal line EM on the substrate 310. In this way, the second electrode d3 of the driving transistor T3 and the first electrode s6 of the second light emitting control transistor T6 do not overlap the first scan signal line G-N, and therefore, when the voltage of the third conductive connection N33 changes abruptly, the influence on the voltage of the first scan signal line G-N can be reduced.

[0250] In summary, among the third conductive connection N33, the second electrode d1 of the first reset transistor T1, the second electrode d3 of the driving transistor T3, the first electrode s2 of the compensation transistor T2 and the first electrode s6 of the second light emitting control transistor T6, the third conductive connection N33 overlaps the first scan signal line G-N, while the second electrode d1 of the first reset transistor T1, the second electrode d3 of the driving transistor T3, the first electrode s2 of the compensation transistor T2 and the first electrode s6 of the second light emitting control transistor T6 do not overlap the first scan signal line G-N. Therefore, when the voltage of the third conductive connection N33 changes abruptly, the influence on the voltage of the first scan signal line G-N can be reduced.

[0251] In some examples, the third conductive connection N33 can pass, in the column direction Y, the connection of the first electrode s2 of the compensation transistor T2, the second electrode d3 of the drive transistor T3, and the first electrode s6 of the second light emission control transistor T6 in this order, and the second electrode d1 of the first reset transistor T1.

[0252] In some examples, the orthogonal projection of the second initialization signal line Vt2 on the substrate 310 overlaps the orthogonal projection of the first reset signal line Rst-P on the substrate 310. At this time, the orthogonal projection of the second initialization signal line Vt2 on the substrate 310 can partially overlap the orthogonal projection of the first reset signal line Rst-P on the substrate 310, or can fully overlap the orthogonal projection of the first reset signal line Rst-P on the substrate 310. In this way, the size of the pixel driving circuit 211 in the column direction Y is reduced.

[0253] Please continue to refer to Figure 13 and Figure 14A In some examples, the array substrate 300 further includes a plurality of first initialization signal lines Vt1, which can be located on the side of the plurality of pixel driving circuits 211 away from the substrate 310. The plurality of first initialization signal lines Vt1 each extend in the row direction X and are arranged in the column direction Y in this order. One first initialization signal line Vt1 is electrically connected to the first electrode s1 of the first reset transistor T1 of one row of pixel driving circuits 211, and thus can provide the first initialization signal to the first electrode s1 of the first reset transistor T1 of the one row of pixel driving circuits 211.

[0254] The first initialization signal line Vt1 electrically connected to one row of pixel driving circuits 211 is located in the row of pixel regions 301 in which the one row of pixel driving circuits 211 is located (as shown in FIG. 3B). Figure 12

[0255] In the row of pixel regions 301 (as shown in FIG. 3B), the first initialization signal line Vt1 is located on the side of the first reset signal line Rst-P away from the first scan signal line G-N. Figure 12

[0256] In some examples, the first reset transistor T1 passes the first reset signal line Rst-P. At this time, the orthogonal projection of the first reset transistor T1 on the substrate 310 overlaps the orthogonal projection of the first reset signal line Rst-P on the substrate 310.

[0257] The first electrode s1 and the second electrode d1 of the first reset transistor T1 are respectively located on the two sides of the first reset signal line Rst-P in the column direction Y.

[0258] ​​The first electrode s1 of the first reset transistor T1 is located between the orthogonal projection of the first reset signal line Rst-P on the substrate 310 and the orthogonal projection of the first initialization signal line Vt1 on the substrate 310. In this way, the first electrode s1 of the first reset transistor T1 is arranged adjacent to the first initialization signal line Vt1, and the first electrode s1 of the first reset transistor T1 can be electrically connected to the first initialization signal line Vt1.

[0259] In some examples, the array substrate 300 further includes a first adapter 391. The first adapter 391 can be electrically connected to the first electrode s1 of the first reset transistor T1 and the first initialization signal line Vt1, and the first initialization signal line Vt1 can be electrically connected to the first electrode s1 of the first reset transistor T1 through the first adapter 391. The orthogonal projection of the first adapter 391 on the substrate 310 can overlap with the orthogonal projection of the first electrode s1 of the first reset transistor T1 and the orthogonal projection of the first initialization signal line Vt1 on the substrate 310.

[0260] The orthogonal projection of the second electrode d1 of the first reset transistor T1 on the substrate 310 is located between the orthogonal projection of the first reset signal line Rst-P on the substrate 310 and the orthogonal projection of the second reset signal line Rst-H on the substrate 310. The third conductive connection N33 can be electrically connected to the second electrode d1 of the first reset transistor T1, and thus the length of the third conductive connection N33 can be reduced.

[0261] In some examples, a part of the orthogonal projection of the first reset transistor T1 on the substrate 310 is arranged opposite to a part of the orthogonal projection of the second reset transistor T7 on the substrate 310 in the row direction Y. In this way, the size of the pixel driving circuit 211 in the column direction Y can be reduced.

[0262] Figure 15 Another structural schematic diagram of the array substrate 300 according to some embodiments.

[0263] Please refer to Figure 15 The array substrate 300 further includes a plurality of auxiliary signal lines Vt40. The plurality of auxiliary signal lines Vt40 are located on one side of the substrate 310. For example, the plurality of auxiliary signal lines Vt40 can be located on the side of the pixel driving circuit 211 away from the substrate 310.

[0264] The plurality of auxiliary signal lines Vt40 extend along the column direction Y and are arranged in sequence along the row direction X.

[0265] Any one of the first initialization signal line Vt1, the second initialization signal line Vt2, and the third initialization signal line Vt3 is electrically connected to one of the plurality of auxiliary signal lines Vt40.

[0266] For example, among the plurality of auxiliary signal lines Vt40, the auxiliary signal line Vt40 electrically connected with the first initialization signal line Vt1 is the first auxiliary signal line Vt41.

[0267] Among the plurality of auxiliary signal lines Vt40, the auxiliary signal line Vt40 electrically connected with the second initialization signal line Vt2 is the second auxiliary signal line Vt42.

[0268] Among the plurality of auxiliary signal lines Vt40, the auxiliary signal line Vt40 electrically connected with the third initialization signal line Vt3 is the third auxiliary signal line Vt43.

[0269] In some embodiments, the plurality of auxiliary signal lines Vt40 can include any one or more of the first auxiliary signal line Vt41, the second auxiliary signal line Vt42, and the third auxiliary signal line Vt43.

[0270] By setting the first auxiliary signal line Vt41 electrically connected with the first initialization signal line Vt1, the first initialization signal line Vt1 and the first auxiliary signal line Vt41 can be interwoven into a mesh shape, and thus the impedance of the first initialization signal line Vt1 can be reduced.

[0271] By setting the second auxiliary signal line Vt42 electrically connected with the second initialization signal line Vt2, the second initialization signal line Vt2 and the second auxiliary signal line Vt42 can be interwoven into a mesh shape, and thus the impedance of the second initialization signal line Vt2 can be reduced.

[0272] By setting the third auxiliary signal line Vt43 electrically connected with the third initialization signal line Vt3, the third initialization signal line Vt3 and the third auxiliary signal line Vt43 can be interwoven into a mesh shape, and thus the impedance of the third initialization signal line Vt3 can be reduced.

[0273] In some embodiments, the first auxiliary signal line Vt41, the second auxiliary signal line Vt42, and the third auxiliary signal line Vt43 can be arranged in a loop along the row direction X. For example, along the row direction X, the first auxiliary signal line Vt41, the second auxiliary signal line Vt42, the third auxiliary signal line Vt43, the first auxiliary signal line Vt41, the second auxiliary signal line Vt42, and the third auxiliary signal line Vt43, and so on, the first auxiliary signal line Vt41, the second auxiliary signal line Vt42, and the third auxiliary signal line Vt43 are sequentially arranged.

[0274] The first auxiliary signal line Vt41, the second auxiliary signal line Vt42 and the third auxiliary signal line Vt43 can be arranged in a cyclic manner along the row direction X, so that the auxiliary signal line Vt41, the second auxiliary signal line Vt42 and the third auxiliary signal line Vt43 can be designed more regularly, thereby facilitating the manufacturing of the array substrate 300.

[0275] Please continue to refer to Figure 15 In some embodiments, one row of pixel driving circuits 211 is divided into a plurality of repeating units 201 arranged in sequence along the row direction X, and one repeating unit 201 includes at least one pixel driving circuit 211.

[0276] The auxiliary signal line Vt40 is located between two adjacent repeating units 201 along the row direction X.

[0277] In some embodiments, one row of repeating units 201 is located in the array substrate 300 (as shown in FIG. 3). Figure 12

[0278] One or more pixel driving circuits 211 can be arranged in one repeating unit 201. For example, the repeating unit 201 includes two pixel driving circuits 211, and the two pixel driving circuits 211 in the repeating unit 201 are symmetrically arranged along the row direction X.

[0279] Figure 16 A structural diagram of the array substrate 300 according to some embodiments.

[0280] Please refer to Figure 16 In some embodiments, the array substrate 300 can further include a light shielding layer 320, and the light shielding layer 320 is located between the substrate 310 and the pixel driving circuit 211. The orthogonal projection of the light shielding layer 320 on the substrate 310 can cover the orthogonal projection of the driving transistor T3 on the substrate 310 (as shown in FIG. 3). Figure 14A

[0281] For example, the orthogonal projection of the light shielding layer 320 on the substrate 310 can completely cover the orthogonal projection of the driving transistor T3 on the substrate 310, and the orthogonal projection of the driving transistor T3 on the substrate 310 can be located in the area covered by the orthogonal projection of the light shielding layer 320 on the substrate 310.

[0282] In some embodiments, the light shielding layer 320 includes a plurality of light shielding portions 321 and a plurality of connecting portions 322, and the orthogonal projection of the light shielding portion 321 on the substrate 310 covers the orthogonal projection of the driving transistor T3 on the substrate 310.

[0283] In some embodiments, the light shielding layer 320 includes a plurality of light shielding portions 321 and a plurality of connecting portions 322, and the orthogonal projection of the light shielding portion 321 on the substrate 310 covers the orthogonal projection of the driving transistor T3 on the substrate 310.​​

[0284] The light shielding layer 320 is configured to receive a first voltage signal.

[0285] By causing the light shielding layer 320 to receive the first voltage signal, the static electricity accumulation of the light shielding layer 320 can be reduced. The two adjacent light shielding portions 321 are connected by the connecting portion 322, so that the impedance of the light shielding layer 320 can be reduced.

[0286] Next, the film layers of the array substrate 300 will be introduced.

[0287] Figure 17 A structural diagram of the first active film layer 330 of the array substrate 300 according to some embodiments.

[0288] Referring to Figure 17 The array substrate 300 includes the first active film layer 330. The first active film layer 330 can be used to form the active layers of the plurality of transistors in the pixel driving circuit 211, wherein the active layer of a transistor can include the channel region of the transistor and the first and second poles on both sides of the channel region.

[0289] In some examples, the first active film layer 330 can be made of polysilicon material.

[0290] For example, the first active film layer 330 includes the active layer of the first reset transistor T1, the active layer of the driving transistor T3, the active layer of the data writing transistor T4, the active layer of the first light emitting control transistor T5, the active layer of the second light emitting control transistor T6, the active layer of the second reset transistor T7, and the active layer of the third reset transistor T8.

[0291] The active layer of the driving transistor T3 can be in the shape of a “U”. One end of the active layer of the driving transistor T3 is connected to the active layer of the second light emitting control transistor T6, and the other end is connected to the active layer of the data writing transistor T4 and the active layer of the first light emitting control transistor T5.

[0292] Part of the active layer of the data writing transistor T4 can extend along the column direction Y, and part of the active layer of the first light emitting control transistor T5 can extend along the column direction Y.

[0293] The active layer of the second light emitting control transistor T6 is connected to the active layer of the second reset transistor T7 away from one end of the active layer of the driving transistor T3.

[0294] Part of the active layer of the third reset transistor T8 can be located between the active layer of the second reset transistor T7 and the active layer of the first light emitting control transistor T5. The opening of the “U” shape formed by the active layer of the driving transistor T3 can be away from the active layer of the third reset transistor T8.

[0295] The active layer of the second reset transistor T7, which is away from one end of the active layer of the second light emitting control transistor T6, can be located between the active layer of the first reset transistor T1 and the active layer of the third reset transistor T8.

[0296] In some examples, the first active film layer 330 can further include an active connection part 331, where the active connection part 331 is connected to the active layer of the data writing transistor T4, the active layer of the first light emitting control transistor T5, and the active layer of the driving transistor T3.

[0297] Figure 18A A structural diagram of the first active film layer 330 of the array substrate 300 according to some embodiments. In the diagram, only the partial structure of the repeat unit 201 on the left side is shown. Figure 18A

[0298] Please refer to Figure 18A In some other embodiments, the two first reset transistors T1 in one repeat unit 201 are respectively located at the two ends of the repeat unit 201 in the row direction X, that is, in one repeat unit 201, the first reset transistor T1 in one pixel driving circuit 211 is located away from another pixel driving circuit 211. At this time, the first reset transistors T1 in two adjacent repeat units 201 in the row direction X are arranged adjacently.

[0299] The first poles s1 of the two first reset transistors T1 adjacent in the row direction X can be electrically connected. At this time, the two first reset transistors T1 adjacent in the row direction X share the first pole s1. By such arrangement, the width of the pixel driving circuit 211 in the row direction X can be reduced, which is conducive to the high PPI (Pixels Per inch) design of the display panel.

[0300] The first poles s5 of the two first light emitting control transistors T5 adjacent in the row direction X can be electrically connected.

[0301] Figure 18B A film layer stacking diagram of the array substrate 300 based on the first active film layer 330 in Figure 18A In the diagram, only the partial structure of the repeat unit 201 on the left side is shown. Figure 18B

[0302] Please refer to Figure 18B The first pole s1 of the first reset transistor T1 is electrically connected to the first initialization signal line Vt1. The array substrate 300 can further include a seventh switching part 397. The seventh switching part 397 is electrically connected to the first poles s1 of the two first reset transistors T1 through vias.

[0303] ​​In some of the above embodiments, the first electrodes s1 of two first reset transistors T1 adjacent in the row direction X can be electrically connected. In this way, the first initialization signal line Vt1 can be electrically connected to the first electrodes s1 of the two first reset transistors T1 through a seventh switch 397.

[0304] Figure 19 A structural diagram of the first gate metal layer of the array substrate 300 according to some embodiments.

[0305] Referring to Figure 19 The array substrate 300 further includes a first gate metal layer 340, which can be located on the side of the first active film layer 330 away from the substrate 310.

[0306] For example, the first gate metal layer 340 can include a second scan signal line G-P, an emission control signal line Em, a first reset signal line Rst-P, a second reset signal line Rst-H, and a first electrode of a capacitor Cst.

[0307] For example, the second scan signal line G-P, the emission control signal line Em, the first reset signal line Rst-P, and the second reset signal line Rst-H can be arranged in sequence along the column direction Y, and the first electrode of the capacitor Cst can be located between the second scan signal line G-P and the emission control signal line Em.

[0308] Figure 20 A structural diagram of the first active film layer 330 and the first gate metal layer 340 arranged in a stack according to some embodiments.

[0309] Referring to Figure 20 The portion of the first gate metal layer 340 overlapping the first active film layer 330 can serve as a control electrode of a transistor.

[0310] For example, the portion of the second scan signal line G-P overlapping the channel region of the data writing transistor T4 can be reused as the control electrode g4 of the data writing transistor T4.

[0311] The first electrode of the capacitor Cst is arranged to overlap the channel region of the driving transistor T3, and thus the first electrode of the capacitor Cst can be reused as the control electrode g3 of the driving transistor T3.

[0312] The portion of the emission control signal line Em overlapping the channel region of the first emission control transistor T5 can be reused as the control electrode g5 of the first emission control transistor T5, and the portion of the emission control signal line Em overlapping the channel region of the second emission control transistor T6 can be reused as the control electrode g6 of the second emission control transistor T6.

[0313] The part of the second reset signal line Rst-H overlapping with the channel region of the second reset transistor T7 can be reused as the control electrode g7 of the second reset transistor T7, and the part of the second reset signal line Rst-H overlapping with the channel region of the third reset transistor T8 can be reused as the control electrode g8 of the third reset transistor T8.

[0314] Figure 21 A structural diagram of the second gate metal layer of the array substrate 300 according to some embodiments.

[0315] Referring to Figure 21 The second gate metal layer 350 is located on the side of the first gate metal layer 340 away from the substrate 310, and the first gate metal layer 340 can include the first scan signal line G-N, the second electrode of the capacitor Cst, and the first initialization signal line Vt1.

[0316] Figure 22 A structural diagram of the first active film layer 330, the first gate metal layer 340, and the second gate metal layer 350 arranged in a stack according to some embodiments.

[0317] Referring to Figure 22 The second electrode of the capacitor Cst can be arranged in a stack with the first electrode of the capacitor Cst, and a via hole can be arranged on the second electrode of the capacitor Cst.

[0318] In some examples, the second gate metal layer 350 can further include an electrode connection part 351, and the second electrodes of the capacitors Cst in two adjacent pixel driving circuits 211 in the row direction X can be electrically connected through the electrode connection part 351, so as to reduce the impedance of the second electrodes of the capacitors Cst.

[0319] Figure 23 A structural diagram of the second active film layer of the array substrate 300 according to some embodiments.

[0320] Referring to Figure 23 The second active film layer 360 can be located on the side of the second gate metal layer 350 away from the substrate 310. The second active film layer 330 can include the active layer of the compensation transistor T2. The active layer of the compensation transistor T2 can include the first electrode, the channel region, and the second electrode of the compensation transistor T2.

[0321] For example, the second active film layer 360 can be made of an oxide, for example, the second active film layer 330 can be made of IGZO (Indium Gallium Zinc Oxide).

[0322] Figure 24 A structural diagram of the first active film layer 330, the first gate metal layer 340, the second gate metal layer 350, and the second active film layer 360 arranged in a stack according to some embodiments.

[0323] Referring to Figure 24 , the channel region of the compensation transistor T2 can be arranged to overlap the second scan signal line G-P, and the portion of the second scan signal line G-P overlapping the channel region of the compensation transistor T2 can be reused as the control electrode g2 of the compensation transistor T2.

[0324] Figure 25 A structural diagram of the third gate metal layer of the array substrate 300 according to some embodiments.

[0325] Referring to Figure 25 , the third gate metal layer 370 is arranged on the side of the second active film layer 360 facing away from the substrate 310, and the third gate metal layer 370 can include the first scan signal line G-N, the second initialization signal line Vt2, and the third initialization signal line Vt3.

[0326] Figure 26 A structural diagram of the first active film layer 330, the first gate metal layer 340, the second gate metal layer 350, the second active film layer 360, and the third gate metal layer 370 arranged in a stack according to some embodiments.

[0327] Referring to Figure 26 , the portion of the first scan signal line G-N in the third gate metal layer 370 overlapping the active layer of the compensation transistor T2 can be used as the control electrode of the compensation transistor T2, and in this case, the compensation transistor T2 can be a double-gate transistor.

[0328] The first scan signal line G-N in the third gate metal layer 370 can be arranged to overlap the first scan signal line G-N in the first gate metal layer 340.

[0329] The second initialization signal line Vt2 can be arranged to overlap the second reset signal line Rst-H, and the third initialization signal line Vt3 can be arranged to overlap the light-emitting control signal line Em.

[0330] Figure 27 A structural diagram of the insulating layer of the array substrate 300 according to some embodiments. Figure 28 A structural diagram of the first active film layer 330, the first gate metal layer 340, the second gate metal layer 350, the second active film layer 360, the third gate metal layer 370, and the insulating layer 380 arranged in a stack according to some embodiments.

[0331] Referring to Figure 27 and Figure 28 , the insulating layer 380 is arranged on the side of the third gate metal layer 370 facing away from the substrate 310, and the insulating layer 380 includes a plurality of vias 381.

[0332] Figure 29A structural diagram of the first source-drain metal layer of the array substrate 300 according to some embodiments.

[0333] Referring to Figure 29 , the first source-drain metal layer 390 is located on the side of the insulating layer 380 facing away from the substrate 310. The first source-drain metal layer 390 includes a first conductive connection N11, a second conductive connection N22, and a third conductive connection N33.

[0334] Figure 30 A structural diagram of the first active film layer 330, the first gate metal layer 340, the second gate metal layer 350, the second active film layer 360, the third gate metal layer 370, the insulating layer 380, and the first source-drain metal layer 390 stacked according to some embodiments.

[0335] Referring to Figure 30 , the first conductive connection N11 can be electrically connected to the control electrode g3 of the driving transistor T3 (as shown in Figure 13 ) and the second electrode d2 of the compensation transistor T2 (as shown in Figure 13 ) through the via 381 in the insulating layer 380.

[0336] The second conductive connection N22 can be electrically connected to the second electrode d5 of the first light-emitting control transistor T5 and the second electrode d8 of the third reset transistor T8 through the via 381 in the insulating layer 380, and the second electrode d5 of the first light-emitting control transistor T5 can be electrically connected to the second electrode d4 of the data writing transistor T4 and the first electrode s3 of the driving transistor T3 through the active connection 331, so that the second conductive connection N22 can be electrically connected to the second electrode d4 of the data writing transistor T4, the second electrode d5 of the first light-emitting control transistor T5, the first electrode s3 of the driving transistor T3, and the second electrode d8 of the third reset transistor T8.

[0337] The third conductive connection N33 can be electrically connected to the second electrode d1 of the first reset transistor T1, the second electrode d3 of the driving transistor T3, the first electrode s2 of the compensation transistor T2, and the first electrode s6 of the second light-emitting control transistor T6 through the via 381 in the insulating layer 380.

[0338] In addition, the first source-drain metal layer 390 can include a first transfer portion 391, a second transfer portion 392, a third transfer portion 393, a data transfer portion 394, a fifth transfer portion 395, and a sixth transfer portion 396.

[0339] The first transfer portion 391 can be electrically connected to the first initialization signal line Vt1 and the first electrode s1 of the first reset transistor T1 through the via.

[0340] The second adapter 392 can be electrically connected to the first electrode s8 of the third reset transistor T8 and the third initialization signal line Vt3 through a via hole, so that the third initialization signal line Vt3 can be electrically connected to the first electrode s8 of the third reset transistor T8.

[0341] The third adapter 393 can be electrically connected to the second gate metal layer 350 and can further include an electrode adapter 351 and the first electrode s5 of the first light emitting control transistor T5, and the electrode adapter 351 is electrically connected to the second electrode of the capacitor Cst, so that the third adapter 393 can be coupled to the second electrode of the capacitor Cst.

[0342] In some examples, the third adapter 393 can include a first sub-adapter 3931 and a second sub-adapter 3932, wherein the first sub-adapter 3931 can extend substantially along a first specified direction, wherein the first specified direction is parallel to the substrate 310 and intersects the row direction X and the column direction Y. The second sub-adapter 3932 is connected to one end of the first sub-adapter 3931. The orthogonal projection of the first sub-adapter 3931 on the substrate 310 is closer to the orthogonal projection of the first scan signal line G-N on the substrate 310 than the orthogonal projection of the second sub-adapter 3932 on the substrate 310. The orthogonal projection of the first sub-adapter 3931 on the substrate 310 is closer to the orthogonal projection of the third conductive adapter N33 on the substrate 310 than the orthogonal projection of the second sub-adapter 3932 on the substrate 310.

[0343] In examples, the second sub-adapter 3932 away from the first sub-adapter 3931 can be connected to the first electrode s5 of the first light emitting control transistor T5 through a via hole.

[0344] Please see Figure 16 In some examples, within one repeating unit, the data write transistor T4 in the two pixel driving circuits 211 are adjacent in the row direction X, and the first light emitting control transistor T5 in the two pixel driving circuits 211 are adjacent in the row direction X. The third adapter 393 electrically connected to the first electrode s5 of the first light emitting control transistor T5 in the two pixel driving circuits 211 shares the second sub-adapter 3932, at this time, the first sub-adapter 3931 electrically connected to the first electrode s5 of the first light emitting control transistor T5 in the two pixel driving circuits 211 is electrically connected to the same second sub-adapter 3932. One second sub-adapter 3932 can be electrically connected to the first electrode s5 of the first light emitting control transistor T5 in the two pixel driving circuits 211 within one repeating unit.

[0345] Please continue to see Figure 30 The data adapter 394 can be electrically connected to the first electrode s4 of the data write transistor T4 through a via hole.

[0346] The fifth adapter 395 can be electrically connected to the first electrode s7 of the second reset transistor T7 and the second initialization signal line Vt2 through a via hole, so that the second initialization signal line Vt2 can be electrically connected to the first electrode s7 of the second reset transistor T7.

[0347] The sixth adapter 396 can be electrically connected to the second electrode d6 of the second light-emitting control transistor T6 and the second electrode d7 of the second reset transistor T7 through a via hole. The sixth adapter 396 can also be electrically connected to the light-emitting device 212, so that the light-emitting device 212 can be electrically connected to the second electrode d6 of the second light-emitting control transistor T6 and the second electrode d7 of the second reset transistor T7 through the sixth adapter 396.

[0348] Please refer again to Figure 15 In some embodiments, the first source-drain metal layer 390 can further include a plurality of auxiliary signal lines Vt40. For example, the plurality of auxiliary signal lines Vt40 can include any one or more of a first auxiliary signal line Vt41, a second auxiliary signal line Vt42, and a third auxiliary signal line Vt43.

[0349] Figure 31 A structural diagram of the second source-drain metal layer of the array substrate 300 according to some embodiments. Figure 32 A structural diagram of the first active film layer 330, the first gate metal layer 340, the second gate metal layer 350, the second active film layer 360, the third gate metal layer 370, the insulating layer 380, the first source-drain metal layer 390, and the second source-drain metal layer stacked according to some embodiments.

[0350] Please refer to Figure 31 The second source-drain metal layer 410 is located on the side of the first source-drain metal layer 390 away from the substrate 310. The second source-drain metal layer 410 can include a first power signal line VDD and a data line DT. The first power signal line VDD can be electrically connected to the third adapter 393, which is electrically connected to the first electrode s5 of the first light-emitting control transistor T5 and the second electrode of the capacitor Cst. Thus, the first power signal line VDD can provide a first power signal to the second electrode of the capacitor Cst and the first electrode s5 of the first light-emitting control transistor T5 through the third adapter 393.

[0351] For example, the first power signal line VDD can be connected to one end of the first sub-adapter 3931 away from the second sub-adapter 3932 through a via hole.

[0352] The data line DT can be electrically connected to the data adapter 394, so that the data line DT can provide a data signal to the first electrode s4 of the data writing transistor T4 through the data adapter 394.

[0353] In the present disclosure, the array substrate 300 provided is tested. Figure 31 The display panel of the provided array substrate 300 is tested. It is tested that the capacitance value between the second conductive connection N22 and the first scan signal line G-N is 0, and the capacitance value between the third conductive connection N33 and the first scan signal line is 2.859 fF.

[0354] In the related art, the capacitance value between the second conductive connection N22 and the first scan signal line G-N is 1.829 fF, and the capacitance value between the third conductive connection N33 and the first scan signal line is 3.340 fF.

[0355] It can be known through comparison that the present disclosure can effectively reduce the capacitance value between the second conductive connection N22 and the first scan signal line G-N, and the capacitance value between the third conductive connection N33 and the first scan signal line, compared with the related art.

[0356] In some embodiments above, the film layer structure of the “8T1C” pixel driving circuit is introduced, and in some other embodiments, the “8T1C” pixel driving circuit can also have different film layer structures, which are not introduced one by one here.

[0357] The above is merely a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, any person skilled in the art can think of changes or replacements within the technical range disclosed by the present disclosure, which shall be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. An array substrate, characterized in that, include: Substrate; Multiple pixel driving circuits are located on one side of the substrate and arranged in multiple rows and columns; one pixel driving circuit includes a compensation transistor, a driving transistor, and a first conductive connection portion, wherein the control electrode of the driving transistor and the second electrode of the compensation transistor are both electrically connected to the first conductive connection portion; the pixel driving circuit further includes a data writing transistor and a first light-emitting control transistor, wherein the second electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor and the second electrode of the first light-emitting control transistor; Multiple first scan signal lines are located on one side of the substrate. The multiple first scan signal lines extend along the row direction and are arranged sequentially along the column direction. The row direction and the column direction are both parallel to the substrate and are intersected. One first scan signal line is electrically connected to the control electrode of the compensation transistor of a row pixel driving circuit. Multiple light-emitting control signal lines are located on one side of the substrate; the multiple light-emitting control signal lines all extend along the row direction and are arranged sequentially along the column direction, and one light-emitting control signal line is electrically connected to the control electrode of the first light-emitting control transistor of the row pixel driving circuit; The first conductive connection portion is located on the side of the first scanning signal line close to the light emission control signal line, and the first conductive connection portion and the first scanning signal line do not overlap in the direction perpendicular to the substrate.

2. The array substrate according to claim 1, characterized in that, The array substrate further includes: multiple second scan signal lines located on one side of the substrate; the multiple second scan signal lines all extend along the row direction and are arranged sequentially along the column direction, and one second scan signal line is electrically connected to the control electrode of the data write transistor of a row pixel driving circuit; The array substrate further includes: a plurality of row pixel regions, the plurality of row pixel regions extending along the row direction and arranged sequentially along the column direction; a row pixel driving circuit is disposed in a row pixel region, and the first scan signal line, the second scan signal line and the light emission control signal line electrically connected to the row pixel driving circuit are located in the row pixel region where the row pixel driving circuit is located; Within one of the row pixel regions: the orthographic projection of the first scan signal line on the substrate is located on the side away from the orthographic projection of the second scan signal line on the substrate, and the orthographic projection of the driving transistor on the substrate is located between the orthographic projection of the second scan signal line on the substrate and the orthographic projection of the light emission control signal line on the substrate.

3. The array substrate according to claim 2, characterized in that, Within one row pixel region, the compensation transistor and the first conductive connection are sequentially arranged along the column direction; wherein, the compensation transistor passes through the first scan signal line, and the orthographic projection of the second electrode of the compensation transistor on the substrate is located on the side of the orthographic projection of the first scan signal line on the substrate that is close to the orthographic projection of the light emission control signal line on the substrate.

4. The array substrate according to claim 3, characterized in that, Within one row pixel region, a portion of the orthogonal projection of the data writing transistor on the substrate is disposed opposite to the orthogonal projection of the compensation transistor on the substrate in the row direction, and another portion of the orthogonal projection of the data writing transistor on the substrate is disposed opposite to the orthogonal projection of the first conductive connection portion on the substrate in the row direction.

5. The array substrate according to claim 4, characterized in that, The data writing transistor passes through the second scan signal line, and the data writing transistor is located on the side of the first scan signal line closer to the light emission control signal line; The array substrate further includes: Multiple data transfer units are located on the side of the multiple pixel driving circuits away from the substrate; Multiple data lines are located on the side of the multiple data adapters away from the substrate. The multiple data lines extend along the column direction and are arranged sequentially along the row direction. Each data line is electrically connected to the first pole of the data writing transistor of a row pixel driving circuit through a data adapter. Within one of the row pixel regions, the orthographic projection of the data transfer unit on the substrate is located between the orthographic projections of the first scan signal line on the substrate and the orthographic projections of the second scan signal line on the substrate.

6. The array substrate according to claim 3, characterized in that, Within one row pixel region, a portion of the orthogonal projection of the first conductive connection on the substrate overlaps with a portion of the orthogonal projection of the compensation transistor on the substrate, and another portion of the orthogonal projection of the first conductive connection on the substrate overlaps with a portion of the orthogonal projection of the driving transistor on the substrate.

7. The array substrate according to any one of claims 2 to 6, characterized in that, The pixel driving circuit further includes a second conductive connection portion, which is electrically connected to the first electrode of the driving transistor, the second electrode of the first light-emitting control transistor, and the second electrode of the data writing transistor. The orthographic projection of the second conductive connection portion on the substrate does not overlap with the orthographic projection of the first scanning signal line on the substrate.

8. The array substrate according to claim 7, characterized in that, The pixel driving circuit further includes: a third reset transistor, wherein the second electrode of the third reset transistor is electrically connected to the second conductive connection portion; The array substrate further includes: multiple second reset signal lines, which are located on the side of the multiple pixel driving circuits away from the substrate. The multiple second reset signal lines extend along the row direction and are arranged sequentially along the column direction. One second reset signal line is electrically connected to the control electrode of the third reset transistor of a row pixel driving circuit. The second reset signal line electrically connected to the row pixel driving circuit is located within the row pixel area where the row pixel driving circuit is located. Within one of the row pixel regions: the second reset signal line is located on the side of the light emission control signal line away from the first scan signal line.

9. The array substrate according to claim 8, characterized in that, Also includes: Multiple third initialization signal lines are located on one side of the substrate; the multiple third initialization signal lines all extend along the row direction and are arranged sequentially along the column direction, and one third initialization signal line is electrically connected to the first terminal of the third reset transistor of a row pixel driving circuit; Within one of the row pixel regions: the orthographic projection of the third initialization signal line on the substrate at least partially overlaps with the orthographic projection of the light emission control signal line on the substrate.

10. The array substrate according to claim 9, characterized in that, Within one row pixel region: the third reset transistor passes through the second reset signal line and is located on the side of the third initialization signal line away from the light emission control signal line; wherein, the orthographic projection of the first electrode of the third reset transistor on the substrate is located between the orthographic projection of the third initialization signal line on the substrate and the orthographic projection of the second reset signal line on the substrate, and the orthographic projection of the second electrode of the third reset transistor on the substrate is located on the side of the orthographic projection of the second reset signal line on the substrate away from the orthographic projection of the third initialization signal line on the substrate; The second conductive connection portion spans the third initialization signal line, the light emission control signal line, and the second reset signal line, and is electrically connected to the second pole of the third reset transistor.

11. The array substrate according to claim 10, characterized in that, The portion of the second conductive connection portion projected onto the substrate overlaps with the projected portions of the second electrode, control electrode, and part of the first electrode of the third reset transistor onto the substrate.

12. The array substrate according to claim 9, characterized in that, The pixel driving circuit further includes a second light-emitting control transistor and a second reset transistor; the first electrode of the second light-emitting control transistor is electrically connected to the second electrode of the driving transistor and the first electrode of the compensation transistor, and the second electrode of the second light-emitting control transistor is electrically connected to the light-emitting device and the second electrode of the second reset transistor; wherein, the control electrode of the second light-emitting control transistor of a row pixel driving circuit is electrically connected to one of the light-emitting control signal lines, and the control electrode of the second reset transistor of a row pixel driving circuit is electrically connected to one of the second reset signal lines. The array substrate further includes: a plurality of second initialization signal lines, the plurality of second initialization signal lines being located on the side of the plurality of pixel driving circuits away from the substrate, the plurality of second initialization signal lines extending along the row direction and arranged sequentially along the column direction; one second initialization signal line being electrically connected to the first terminal of the second reset transistor of a row pixel driving circuit; Within one of the row pixel regions: the orthographic projection of the second initialization signal line on the substrate is located on the side where the orthographic projection of the second reset signal line on the substrate is far from the orthographic projection of the first scan signal line on the substrate.

13. The array substrate according to claim 12, characterized in that, The pixel driving circuit further includes: a first reset transistor and a third conductive connection portion, wherein the third conductive connection portion is electrically connected to the second terminal of the first reset transistor, the second terminal of the driving transistor, and the first terminal of the compensation transistor; The array substrate further includes: a plurality of first reset signal lines, the plurality of first reset signal lines being located on the side of the plurality of pixel driving circuits away from the substrate; the plurality of first reset signal lines all extend along the row direction and are arranged sequentially along the column direction, and one first reset signal line is electrically connected to the control electrode of the first reset transistor of a row pixel driving circuit; Within the row pixel region, the orthographic projection of the first reset signal line on the substrate is located on the side where the orthographic projection of the light emission control signal line on the substrate is far from the orthographic projection of the first scan signal line on the substrate.

14. The array substrate according to claim 13, characterized in that, Also includes: Multiple first initialization signal lines are located on the side of the multiple pixel driving circuits away from the substrate. The multiple first initialization signal lines extend along the row direction and are arranged sequentially along the column direction. One first initialization signal line is electrically connected to the first terminal of the first reset transistor of the row pixel driving circuit. Within the row pixel region, the first initialization signal line is located on the side of the first reset signal line that is away from the first scan signal line.

15. The array substrate according to claim 14, characterized in that, The first reset transistor passes through the first reset signal line. The orthographic projection of the first electrode of the first reset transistor on the substrate is located between the orthographic projection of the first reset signal line on the substrate and the orthographic projection of the first initialization signal line on the substrate. The orthographic projection of the second electrode of the first reset transistor on the substrate is located between the orthographic projection of the first reset signal line on the substrate and the orthographic projection of the second reset signal line on the substrate.

16. The array substrate according to claim 14, characterized in that, The orthographic projection of the first reset signal line on the substrate overlaps with the orthographic projection of the second initialization signal line on the substrate.

17. The array substrate according to claim 14, characterized in that, Also includes: Multiple auxiliary signal lines are located on one side of the substrate, and the multiple auxiliary signal lines extend along the column direction and are arranged sequentially along the row direction; One of the auxiliary signal lines is electrically connected to any one of the first initialization signal line, the second initialization signal line, and the third initialization signal line.

18. The array substrate according to claim 17, characterized in that, A row of pixel driving circuits is divided into multiple repeating units arranged sequentially along the row direction, and each repeating unit includes at least one of the pixel driving circuits. The auxiliary signal line is located between two adjacent repeating units in the row direction.

19. The array substrate according to claim 18, characterized in that, The repeating unit includes two pixel driving circuits, and the two pixel driving circuits in one repeating unit are symmetrically arranged in the row direction.

20. The array substrate according to claim 17, characterized in that, The multiple auxiliary signal lines include a first auxiliary signal line, a second auxiliary signal line, and a third auxiliary signal line. The first auxiliary signal line is electrically connected to the first initialization signal line, the second auxiliary signal line is electrically connected to the second initialization signal line, and the third auxiliary signal line is electrically connected to the third initialization signal line.

21. A display panel, characterized in that, include: The array substrate as described in any one of claims 1 to 20; The light-emitting device layer is located on the side of the array substrate away from the substrate; An encapsulation layer is located on the side of the light-emitting device layer away from the array substrate.

22. A display device, characterized in that, include: The display panel as described in claim 21; The driver chip is electrically connected to the display panel.

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