Calibration of pulse width modulated amplifier systems

Abstract

A switched mode amplifier system can include a switched mode amplifier having an amplifier input coupled to an output of an analog integrator and an amplifier output and include a calibration system. The calibration system can be configured to force an input of the analog integrator to be a fixed known input value, force the amplifier output to be a fixed known duty cycle, measure an analog signal generated at the output of the analog integrator in response to forcing the input of the analog integrator to be the fixed value, determine an offset of the switched mode amplifier system based on the analog signal, and correct the offset.

Description

Technical Field

[0001] This disclosure generally relates to circuitry for audio devices, including but not limited to personal audio devices such as cordless phones and media players, and more specifically to systems and methods for calibrating pulse width modulation amplifier systems. Background Technology

[0002] Personal audio devices (including cordless phones, such as mobile / cellular phones, MP3 players, and other consumer audio devices) are widely used. These personal audio devices may include circuitry for driving a pair of headphones or one or more speakers. This circuitry typically includes a power amplifier for driving the audio output signal to the headphones or speakers. Generally, a power amplifier amplifies the audio signal by drawing power from a power source and controlling the audio output signal to match the shape of the input signal but with a larger amplitude.

[0003] An example of an audio amplifier is a Class D amplifier. Class D amplifiers (also known as “switching amplifiers”) can include electronic amplifiers in which the amplifying device (e.g., a transistor, typically a metal-oxide-semiconductor field-effect transistor) operates as an electronic switch. In a Class D amplifier, the signal to be amplified is converted into a series of pulses using pulse width modulation (PWM), pulse density modulation (PDM), or another modulation method, thus converting the signal into a modulated signal, where the pulse characteristics of the modulated signal (e.g., pulse width, pulse density, etc.) are a function of the signal amplitude. After amplification using a Class D amplifier, the output pulse train can be converted back into an unmodulated analog signal by passing it through a passive low-pass filter, where such a low-pass filter can be inherent in the Class D amplifier or in a load driven by a Class D amplifier. Class D amplifiers are frequently used because they can be more energy-efficient than linear analog amplifiers, as they dissipate less power (e.g., heat) in active devices compared to linear analog amplifiers.

[0004] In amplifier systems, including those with Class D amplifiers, identifying and correcting any signal offsets that may exist in the amplifier path can be critical. Examples of signal offsets might be inherent offsets in the integrator stage of the preamplifier stage of the amplifier system, or mismatches in resistors used to set the gain of the amplifier system. Without correcting these types of signal offsets, signal distortion, inaccuracies, and / or other undesirable conditions may persist. Summary of the Invention

[0005] Based on the teachings of this disclosure, one or more disadvantages and problems associated with existing methods for minimizing offset in pulse width modulation amplifier systems can be reduced or eliminated.

[0006] According to embodiments of this disclosure, a switch-mode amplifier system may include a switch-mode amplifier having an amplifier input and an amplifier output coupled to the output of an analog integrator, including a feedback network coupled between the amplifier output and the input of the analog integrator, including a loop filter configured to generate a digital loop filter output, including a quantizer configured to generate a pulse-width modulation representation of the digital loop filter output, and including a calibration system. The calibration system may be configured to force the input of the analog integrator to a fixed, known input value, low-pass filter the pulse-width modulation representation of the digital loop filter output generated by the quantizer to generate a filtered quantizer output signal, determine an offset of the switch-mode amplifier system based on the filtered quantizer output signal, and correct the offset.

[0007] According to these and other embodiments of this disclosure, a method for a switch-mode amplifier system can be provided, the switch-mode amplifier system having a switch-mode amplifier including an amplifier input and an amplifier output coupled to the output of an analog integrator, a feedback network coupled between the amplifier output and the input of the analog integrator, a loop filter configured to generate a digital loop filter output, and a quantizer configured to generate a pulse width modulation representation of the digital loop filter output. The method may include forcing the input of the analog integrator to a fixed, known input value, low-pass filtering the pulse width modulation representation of the digital loop filter output generated by the quantizer to generate a filtered quantizer output signal, and determining and correcting an offset of the switch-mode amplifier system based on the filtered quantizer output signal.

[0008] According to these and other embodiments of this disclosure, a calibration system for use with a switch-mode amplifier system can be provided, the switch-mode amplifier system having a switch-mode amplifier including an amplifier input and an amplifier output coupled to the output of an analog integrator, a feedback network coupled between the amplifier output and the input of the analog integrator, a loop filter configured to generate a digital loop filter output, and a quantizer configured to generate a pulse-width modulation representation of the digital loop filter output. The calibration system can be configured to force the input of the analog integrator to a fixed, known input value, low-pass filter the pulse-width modulation representation of the digital loop filter output generated by the quantizer to generate a filtered quantizer output signal, determine the offset of the switch-mode amplifier system based on the filtered quantizer output signal, and correct the offset.

[0009] According to these and other embodiments of this disclosure, a switch-mode amplifier system may include a switch-mode amplifier having an amplifier input and an amplifier output coupled to the output of an analog integrator, and includes a calibration system. The calibration system may be configured to force the input of the analog integrator to a fixed, known input value, force the amplifier output to a fixed, known duty cycle, and, in response to forcing the input of the analog integrator to a fixed value, measure an analog signal generated at the output of the analog integrator, determine an offset of the switch-mode amplifier system based on the analog signal, and correct the offset.

[0010] According to these and other embodiments of this disclosure, a method for a switch-mode amplifier system can be provided, the switch-mode amplifier system having a switch-mode amplifier including an amplifier input and an amplifier output coupled to the output of an analog integrator. The method may include forcing the input of the analog integrator to a fixed, known input value, forcing the amplifier output to a fixed, known duty cycle, and, in response to forcing the input of the analog integrator to a fixed value, measuring an analog signal generated at the output of the analog integrator, determining an offset of the switch-mode amplifier system based on the analog signal, and correcting the offset.

[0011] According to these and other embodiments of this disclosure, a calibration system for use with a switch-mode amplifier system having a switch-mode amplifier including an amplifier input and an amplifier output coupled to the output of an analog integrator can be provided. The calibration system can force the input of the analog integrator to a fixed, known input value, force the amplifier output to a fixed, known duty cycle, and, in response to forcing the input of the analog integrator to a fixed value, measure an analog signal generated at the output of the analog integrator, determine the offset of the switch-mode amplifier system based on the analog signal, and correct the offset.

[0012] According to these and other embodiments of the present disclosure, a switch-mode amplifier system may include a switch-mode amplifier having an amplifier input and an amplifier output having an output coupled to an analog integrator, and includes a calibration system configured to force the input of the analog integrator to a fixed, known input value, determine the slew rate of the analog signal generated at the output of the analog integrator in response to forcing the input of the analog integrator to a fixed value, and determine the integrator gain of the switch-mode amplifier system based on the slew rate.

[0013] According to these and other embodiments of this disclosure, a method for a switch-mode amplifier system can be provided, the switch-mode amplifier system having a switch-mode amplifier including an amplifier input and an amplifier output coupled to the output of an analog integrator. The method may include forcing the input of the analog integrator to a fixed, known input value, determining, in response to forcing the input of the analog integrator to a fixed value, a slew rate of the analog signal generated at the output of the analog integrator, and determining the integrator gain of the switch-mode amplifier system based on the slew rate.

[0014] According to these and other embodiments of this disclosure, a calibration system for use with a switch-mode amplifier system having a switch-mode amplifier including an amplifier input and an amplifier output coupled to the output of an analog integrator can be provided. The calibration system can be configured to force the input of the analog integrator to a fixed, known input value, determine the slew rate of the analog signal generated at the output of the analog integrator in response to forcing the input of the analog integrator to a fixed value, and determine the integrator gain of the switch-mode amplifier system based on the slew rate.

[0015] The technical advantages of this disclosure will be apparent to those skilled in the art from the accompanying drawings, description, and claims included herein. The objects and advantages of the embodiments will be accomplished and realized, at least by means of the elements, features, and combinations particularly pointed out in the claims.

[0016] It should be understood that the foregoing general description and the following detailed description are illustrative and explanatory, and are not intended to limit the claims set forth in this disclosure. Attached Figure Description

[0017] A more complete understanding of this embodiment and its advantages can be obtained by referring to the following description in conjunction with the accompanying drawings, wherein like reference numerals denote like features, in which:

[0018] Figure 1 This is an illustration of an example personal audio device according to an embodiment of the present disclosure;

[0019] Figure 2 A block diagram of selected components of an example audio integrated circuit in a personal audio device according to an embodiment of the present disclosure is shown;

[0020] Figure 3 An embodiment of the present disclosure is shown for use with Figure 2 The flowchart depicts an example method for open-loop calibration of an audio integrated circuit.

[0021] Figure 4 An embodiment of the present disclosure is shown for determining Figure 2A flowchart illustrating an example method for gaining an audio integrated circuit is shown in the figure; and

[0022] Figure 5 An embodiment of the present disclosure is shown for use with Figure 2 The flowchart illustrates an example method for closed-loop calibration of an audio integrated circuit. Detailed Implementation

[0023] Figure 1 This is an illustration of an example personal audio device 1 according to an embodiment of the present disclosure. Figure 1 A personal audio device 1 is depicted, which is coupled to a headset 3 in the form of a pair of earbud speakers 8A and 8B. Figure 1 The headset 3 depicted is merely an example, and it should be understood that the personal audio device 1 can be used with various audio transducers, including but not limited to headphones, earbuds, in-ear headphones, and external speakers. The plug 4 provides electrical connection between the headset 3 and the personal audio device 1. The personal audio device 1 can use a touchscreen 2 to provide a display to the user and receive user input, or alternatively, a standard liquid crystal display (LCD) can be combined with various buttons, sliders, and / or dials located on the front and / or sides of the personal audio device 1. Similarly, as... Figure 1 As shown, the personal audio device 1 may include an audio integrated circuit (IC) 9 for generating analog audio signals to be transmitted to a headset 3 and / or another audio transducer.

[0024] Figure 2 A block diagram of selected components of an example audio IC 9 for a personal audio device according to an embodiment of the present disclosure is shown. In some embodiments, the example audio IC 9 may be used to implement... Figure 1 The audio IC 9. (e.g.) Figure 2 As shown, the microcontroller core 18 can provide a digital audio input signal DIG_IN to the digital-to-analog converter (DAC) 14, which can convert the digital audio input signal into an analog input signal V. IN DAC 14 can provide an analog input signal V to amplifier 16. IN Amplifier 16 can amplify or attenuate the analog input signal V. IN To provide audio output signal V OUT The audio output signal can operate a speaker, a headphone transducer, a line-level signal output, and / or other suitable output.

[0025] Similarly, Figure 2As shown, amplifier 16 may include a signal input network 24, a first stage 22 (e.g., an analog front end), a quantizer 34, a final output stage including a Class D audio output stage 42, a signal feedback network 26, and a control system 28. The first stage 22 is configured to receive an analog input signal V at the amplifier input of amplifier 16. IN And generate as analog input signal V IN The intermediate signal V of the function INT The Class D audio output stage 42 is configured to output according to the quantized intermediate signal V. IN An audio output signal V is generated at the amplifier output of amplifier 16. OUT The signal feedback network 26 is coupled between the amplifier output and the amplifier input, and the control system 28 is used to control the operation of certain components of the amplifier 16, as described in more detail below.

[0026] The signal input network 24 may include any suitable input network that receives the amplifier input of the amplifier 16. For example, such as Figure 2 As shown, the signal input network 24 may include a variable input resistor 46, wherein the resistance of the variable input resistor may be controlled by a control signal received from the control system 28, as described in more detail below.

[0027] The first stage 22 can include any suitable analog front-end circuitry for regulating the analog input signal V. IN For use by Class D audio output stage 42. For example, the first stage 22 may include one or more analog integrators 30 and 32 cascaded in series, such as Figure 2 As shown.

[0028] Quantizer 34 may include an intermediate signal V configured to be quantized. INT To generate an equivalent digital PWM signal V QUANT Any system, device, or apparatus. Therefore, quantizer 34 can be referred to as a digital pulse width modulator. For example... Figure 2 As shown, the quantizer 34 can receive one or more control signals from the control system 28, which can control the operation of the quantizer 34 during the calibration phase of the audio IC 9, as described in more detail below.

[0029] Class D audio output stage 42 can include any system, device, or apparatus configured to receive the output of quantizer 34 and drive the output signal V. OUT The output signal is the analog input signal V. IN An amplified version. Therefore, the Class D audio output stage 42 may include multiple output switches configured to receive the modulated signal V generated by the quantizer 34. QUANT Generate output signal V OUTAfter being amplified by the Class D audio output stage 42, its output pulse train can be converted back into an unmodulated analog signal by passing it through a passive low-pass filter, which can be either the output circuit of the Class D audio output stage 42 or inherent in the load driven by the Class D audio output stage 42.

[0030] Signal feedback network 26 may include a method for indicative audio output signal V OUT The signal is fed back to any suitable feedback network at the amplifier input of amplifier 16. For example, such as... Figure 2 As shown, the signal feedback network 26 may include a variable feedback resistor 48, wherein the resistance of the variable feedback resistor 48 is controlled by a control signal received from the control system 28, as described in more detail below. Those skilled in the art will recognize that the closed-loop gain of the amplifier 16 can be set by the ratio of the resistance of the variable feedback resistor 48 to the resistance of the variable input resistor 46.

[0031] Similarly, Figure 2 As shown, the example audio IC 9 may also include a control system 28. The control system 28 may include any suitable system, device, or apparatus configured to receive signals within the signal path of the indicator amplifier 16 (e.g., the voltage V output by the integrator 30). INT ′ and / or modulated signal V QUANT The control system 28 receives information from the combiner 20 and performs calibration of the audio IC 9 based on that information. For example, in some embodiments, the control system 28 may generate a digital trim signal, which is combined by the combiner 20 with the digital audio input signal DIG_IN, to effectively modify the digital audio input signal DIG_IN to correct for a detected offset within the amplifier system of the audio IC 9. As another example, in these and other embodiments, the control system 28 may generate one or more analog trim signals to modify the resistance of one or more input resistors 46, one or more feedback resistors 48, and / or the parameters of the integrator 30 (e.g., modifying the current source of the operational amplifier of the integrator 30, modifying the external current source or resistor that applies an external offset to the integrator 30, etc.).

[0032] Figure 3 A flowchart of an example method 300 for open-loop calibration of an amplifier system for an audio IC 9 according to an embodiment of the present disclosure is shown. According to some embodiments, method 300 may begin at step 302. As described above, the teachings of this disclosure can be implemented in various configurations of the audio IC 9. Therefore, the preferred initialization point of method 300 and the order of the steps comprising method 300 may depend on the chosen implementation.

[0033] At step 302, the control system 28 can initialize the digital and analog fine-tuning values ​​to default values. For example, the digital fine-tuning value can be set to zero, while the analog fine-tuning value can be set according to the desired nominal gain of amplifier 16. At step 304, the control system 28 can transmit a control signal to the microcontroller core 18, causing the microcontroller core 18 to output the zero value of the digital audio input signal DIG_IN. At step 306, the control system 28 can transmit a control signal to the vectorizer 34 to cause the quantizer 34 to generate a differential modulation signal V from zero to the Class D audio output stage 42. QUANT (For example, by outputting the same square wave signal on each of its differential outputs), regardless of the intermediate voltage V generated by the first stage 22. INT How. By doing so, during this type of open-loop calibration mode, the control system 28 effectively interrupts / disconnects the signal feedback loop present during normal operation of the audio IC 9.

[0034] At step 308, the control system 28 can determine the voltage V. INT Is the amplitude of ′ lower than a first predetermined threshold? Voltage V INT The fundamental non-zero value of ′ can indicate the presence of an offset within the signal path of amplifier 16, including but not limited to the inherent offset of integrator 30, the offset due to mismatch between input resistors 46, and / or the offset due to mismatch between feedback resistors 48. Therefore, control system 28 can attempt to minimize voltage V during open-loop calibration mode by changing the digital trim and / or one or more analog trims. INT ′, so that the voltage V INT The amplitude of ′ decreases below a first predetermined threshold. Therefore, if the voltage V INT If the amplitude of ′ is lower than the first predetermined threshold, then method 300 can continue to step 312. Otherwise, method 300 can continue to step 310.

[0035] At step 310, the control system 28 may change the digital trim and / or one or more analog trims in an attempt to reduce the voltage V. INT The magnitude of ′. After completing step 310, method 300 can proceed to step 308 again.

[0036] At step 312, the control system 28 may store digital and / or analog fine-tuning settings so that these fine-tuning settings can be recalled and applied during normal operation of the amplifier system.

[0037] While the steps described above can detect and correct the overall offset of the amplifier system, they may not isolate any specific source of offset. However, the following steps can isolate offset caused by mismatches between input resistors 46 and / or between feedback resistors 48.

[0038] At step 314 (while keeping the digital audio input signal DIG_IN at zero), the control system 28 can transmit a control signal to the vectorizer 34 so that the quantizer 34 generates a differential PWM output at a first duty cycle (e.g., 25% duty cycle), while simultaneously converting the differential modulation signal V of the quantizer 34... QUANT Keep it at zero, and determine the resulting voltage V. INT At step 316 (while keeping the digital audio input signal DIG_IN at zero), the control system 28 can transmit a control signal to the vectorizer 34 so that the quantizer 34 generates a differential PWM output at a second duty cycle (e.g., 75% duty cycle), while simultaneously converting the differential modulation signal V of the quantizer 34... QUANT Keep it at zero, and determine the resulting voltage V. INT ′.

[0039] Operating at different duty cycles, while simultaneously converting the differentially modulated signal V from quantizer 34... QUANT Keeping it at zero allows for a change in the output voltage V. OUT The effect of common-mode voltage. Therefore, in steps 314 and 316, instead of changing the duty cycle of the differential output of quantizer 34, in some embodiments, control system 28 can generate a change in output voltage V between two different levels. OUT The control signal for the common-mode voltage (e.g., by changing the power supply voltage of Class D audio output stage 42). The voltage V at the first duty cycle / first output common-mode voltage. INT The value of ′ is related to the voltage V at the second duty cycle / second output common mode voltage. INT The difference between the values ​​can indicate the mismatch resistance between the input resistors 46 and / or between the feedback resistors 48.

[0040] In some embodiments, instead of operating at two different duty cycles as described above, the control system 28 can generate a control signal that varies the output voltage V between at least three different levels (e.g., at least three different duty cycles). OUT The common-mode voltage; determining the voltage V at various duty cycles. INT The difference between the input resistor 46 and the feedback resistor 48 is corrected, including the linear and nonlinear mismatches of the input resistor 46 and / or the linear and nonlinear mismatches of the feedback resistor 48.

[0041] At step 318, the control system 28 can determine the voltage V between the first duty cycle / first output common-mode voltage and the second duty cycle / second output common-mode voltage. INTThe method checks whether the magnitude of the difference is lower than a second predetermined threshold. If the magnitude of the difference is lower than the second predetermined threshold, method 300 can proceed to step 322. Otherwise, method 300 can proceed to step 320.

[0042] At step 320, the control system 28 may change the digital trim and / or one or more analog trims in an attempt to reduce the voltage V. INT The magnitude of ′. After completing step 320, method 300 can proceed to step 314 again.

[0043] At step 322, the control system 28 may store digital and / or analog fine-tuning settings for recall and application during normal operation of the amplifier system. After completing step 322, method 300 may end.

[0044] The steps of method 300 can be applied to each gain setting of the amplifier system to determine the offset and perform calibration for each gain setting.

[0045] although Figure 3 The specific number of steps to be taken in method 300 is disclosed, but can be compared to... Figure 3 The steps described herein may be performed with more or fewer steps. Furthermore, although... Figure 3 A specific order of steps to be taken in method 300 is disclosed, but the steps of method 300 can be performed in any suitable order. For example, in some embodiments, steps 314-322 for isolating and calibrating resistor mismatch can be performed before steps 302-312 for determining and calibrating overall offset.

[0046] Method 300 may be implemented using control system 28, its components or components coupled thereto, or any other system operable to implement method 300. In some embodiments, method 300 may be implemented partly or entirely in software and / or firmware embodied in a computer-readable medium.

[0047] Figure 4 A flowchart of an example method 400 for determining the gain of an amplifier system for an audio IC 9 according to an embodiment of the present disclosure is shown. According to some embodiments, method 400 may begin at step 402. As described above, the teachings of this disclosure can be implemented in various configurations of the audio IC 9. Therefore, the preferred initialization point of method 400 and the order of the steps comprising method 400 may depend on the chosen implementation.

[0048] At step 402, the control system 28 may transmit a control signal to the vectorizer 34 so that the quantizer 34 generates a differential modulation signal V from zero to Class D audio output stage 42. QUANT(For example, by outputting the same square wave signal on each of its differential outputs), regardless of the intermediate voltage V generated by the first stage 22. INT How. By doing so, during this open-loop calibration mode, the control system 28 effectively interrupts / disconnects the signal feedback loop present during the normal operation of the audio IC 9.

[0049] At step 404, the control system 28 can transmit a control signal to the microcontroller core 18, causing the microcontroller core 18 to output the value of the digital audio input signal DIG_IN, so that the DAC 14 generates a square wave signal with a small duty cycle at its output (e.g., the DAC 14's possible minimum duty cycle or minimum non-zero value). Because this square wave signal is applied to the input of the amplifier 16 in this open-loop configuration, the integrator 30 generates an output voltage V... INT A periodic signal can be generated at a finite transition rate between its minimum and maximum values ​​as it increases from its minimum to its maximum, and vice versa. In some embodiments, a square wave signal may result in a voltage V generated by integrator 30. INT The output saturates. In these and other embodiments, the input voltage can be slowly ramped up.

[0050] At step 406, the control system 28 can determine the output voltage V. INT The slew rate. At step 408, the control system 28 can estimate the integrator gain of the amplifier system based on the slew rate, because the input from the integrator 30 (e.g., the analog input signal V) IN ) and the output of integrator 30 (e.g., voltage V) INT The integrator gain of (′) can be the voltage V INT A function of slope.

[0051] After completing step 408, method 400 can end.

[0052] although Figure 4 The specific number of steps to be taken in method 400 is disclosed, but can be compared to... Figure 4 The steps described herein may be performed with more or fewer steps. Furthermore, although... Figure 4 A specific order of steps to be taken in method 400 is disclosed, but the steps of method 400 can be performed in any suitable order.

[0053] Method 400 may be implemented using control system 28, its components or components coupled thereto, or any other system operable to implement method 400. In some embodiments, method 400 may be implemented partly or entirely in software and / or firmware embodied in a computer-readable medium.

[0054] When method 300 interrupts or disconnects the amplifier feedback loop to perform calibration, in addition to or as an alternative to the open-loop calibration of method 300, control system 28 may also perform calibration while keeping the amplifier system in a closed-loop configuration, as described below with reference to method 500.

[0055] Figure 5 A flowchart of an example method 500 for closed-loop calibration of an amplifier system for an audio IC 9 according to an embodiment of the present disclosure is shown. According to some embodiments, method 500 may begin at step 502. As described above, the teachings of this disclosure can be implemented in various configurations of the audio IC 9. Therefore, the preferred initialization point of method 500 and the order of the steps comprising method 500 may depend on the chosen implementation.

[0056] At step 502, the control system 28 can initialize the digital and analog trim values ​​to default values. For example, the digital trim value can be set to zero, while the analog trim value can be set according to the desired nominal gain of the amplifier 16. At step 504, the control system 28 can transmit a control signal to the microcontroller core 18, causing the microcontroller core 18 to output a zero value for the digital audio input signal DIG_IN.

[0057] At step 506, the control system 28 can modulate the modulation signal V generated by the quantizer 34. QUANT Perform low-pass filtering (e.g., using an averaging filter). At step 508, the control system 28 can determine the low-pass filtered modulation signal V. QUANT Whether the amplitude is lower than the first predetermined threshold. The modulated signal V after low-pass filtering. QUANT The fundamental non-zero value can indicate an offset within the signal path of amplifier 16, including but not limited to the inherent offset of integrator 30, offset due to mismatch between input resistors 46, and / or offset due to mismatch between feedback resistors 48. Therefore, control system 28 can attempt to minimize the low-pass filtered modulation signal V during closed-loop calibration mode by changing the digital trim and / or one or more analog trims. QUANT In order to convert the low-pass filtered modulated signal V QUANT The amplitude decreases below a first predetermined threshold. Therefore, if the low-pass filtered modulation signal V... QUANT If the magnitude is lower than the first predetermined threshold, then method 500 can continue to step 512. Otherwise, method 500 can continue to step 510.

[0058] At step 510, the control system 28 may change the digital trim and / or one or more analog trims in an attempt to reduce the modulation signal V after low-pass filtering. QUANT The magnitude. After completing step 510, method 500 can proceed to step 506 again.

[0059] At step 512, the control system 28 may store digital and / or analog fine-tuning settings so that these settings can be recalled and applied during normal operation of the amplifier system.

[0060] While the steps described above can detect and correct the overall offset of the amplifier system, they may not isolate any specific source of offset. However, the following steps can isolate offset caused by mismatches between input resistors 46 and / or between feedback resistors 48.

[0061] At step 514, the control system 28 may transmit a control signal to the vectorizer 34 to cause the quantizer 34 to generate a differential PWM output at a first duty cycle (e.g., 25% duty cycle) and determine the resulting low-pass filtered modulation signal V. QUANT At step 516, the control system 28 may transmit a control signal to the vectorizer 34 to cause the quantizer 34 to generate a differential PWM output at a second duty cycle (e.g., 75% duty cycle) and determine the resulting low-pass filtered modulation signal V. QUANT .

[0062] Operating at different duty cycles, while simultaneously converting the differentially modulated signal V from quantizer 34... QUANT Keeping it close to zero allows for changes in the output voltage V. OUT The effect of common-mode voltage. Therefore, in steps 514 and 516, instead of changing the duty cycle of the differential output of quantizer 34, in some embodiments, control system 28 can generate a change in output voltage V between two different levels. OUT The control signal for the common-mode voltage (e.g., by changing the power supply voltage of the Class D audio output stage 42). The differential modulation signal V at the first duty cycle / first output common-mode voltage. QUANT The value of the differential modulation signal V at the second duty cycle / second output common-mode voltage is compared with that of the second duty cycle / second output common-mode voltage. QUANT The difference between the values ​​can indicate the mismatch resistance between the input resistors 46 and / or between the feedback resistors 48.

[0063] In some embodiments, instead of operating at two different duty cycles as described above, the control system 28 can generate a control signal that varies the output voltage V between at least three different levels (e.g., at least three different duty cycles). OUT The common-mode voltage; determining the voltage V at various duty cycles. INT The difference between the input resistor 46 and the feedback resistor 48 is corrected, including the linear and nonlinear mismatches of the input resistor 46 and / or the linear and nonlinear mismatches of the feedback resistor 48.

[0064] At step 518, the control system 28 can determine the low-pass filtered modulation signal V between the first duty cycle / first output common-mode voltage and the second duty cycle / second output common-mode voltage. QUANT The method checks whether the magnitude of the difference is lower than a second predetermined threshold. If the magnitude of the difference is lower than the second predetermined threshold, then method 500 can proceed to step 522. Otherwise, method 500 can proceed to step 520.

[0065] At step 520, the control system 28 may change the digital trim and / or one or more analog trims in an attempt to reduce the differential modulation signal V. QUANT The magnitude. After completing step 520, method 500 can proceed to step 514 again.

[0066] At step 522, the control system 28 may store digital and / or analog fine-tuning settings for recall and application during normal operation of the amplifier system. After completing step 522, method 500 may end.

[0067] The steps of method 500 can be applied to each gain setting of the amplifier system to determine the offset and perform calibration for each gain setting.

[0068] although Figure 5 The specific number of steps to be taken in method 500 is disclosed, but can be compared to... Figure 5 The steps shown can be performed with more or fewer steps. Furthermore, although... Figure 5 A specific order of steps to be taken in method 500 is disclosed, but the steps of method 500 can be performed in any suitable order. For example, in some embodiments, steps 514-522 for isolating and calibrating resistor mismatch can be performed before steps 502-512 for determining and calibrating overall offset.

[0069] Method 500 may be implemented using control system 28, its components or components coupled thereto, or any other system operable to implement method 500. In some embodiments, method 500 may be implemented partly or entirely in software and / or firmware embodied in a computer-readable medium.

[0070] The calibration operation performed by the control system 28 as described above can be performed at any suitable time, including but not limited to the calibration phase that occurs when the audio IC 9 is powered on, the calibration phase that occurs after the audio IC 9 is assembled, the calibration phase that occurs when the amplifier system is not using the audio IC 9 (e.g., not generating audio content), and / or the calibration phase that occurs in response to temperature changes near the audio IC 9.

[0071] As used herein, when two or more elements are referred to as being “coupled” to each other, this terminology indicates that the two or more elements are in electronic or mechanical communication, whether or not they are indirectly or directly connected, and whether or not there is an intermediary element, as the case may be.

[0072] This disclosure covers all changes, substitutions, variations, alterations, and modifications to the exemplary embodiments described herein that will be understood by those skilled in the art. Similarly, where appropriate, the appended claims cover all changes, substitutions, variations, alterations, and modifications to the exemplary embodiments described herein that will be understood by those skilled in the art. Furthermore, the means or systems or components of means or systems adapted, arranged, enabled, configured, activated, operable, or operated to perform a particular function as mentioned in the appended claims cover means or systems or components, whether or not they or those particular functions are activated, turned on, or unlocked, provided that those means or systems or components are so adapted, arranged, enabled, configured, activated, operable, or operated. Therefore, modifications, additions, or omissions may be made to the systems, means, or methods described herein without departing from the scope of this disclosure. For example, components of systems and means may be integrated or separate. Furthermore, the operation of the systems and means disclosed herein may be performed by more, fewer, or other components, and the described methods may include more, fewer, or other steps. Furthermore, steps may be performed in any suitable order. As used in this document, “each” means each member of a set or each member of a subset of a set.

[0073] Although exemplary embodiments are shown in the accompanying drawings and described below, the principles of this disclosure can be implemented using any number of techniques, whether or not such techniques are currently known. This disclosure should in no way be limited to the exemplary embodiments and techniques shown in the drawings and described above.

[0074] Unless otherwise specified, the items depicted in the accompanying drawings are not necessarily drawn to scale.

[0075] All examples and conditional statements described herein are intended for educational purposes to assist the reader in understanding the present disclosure and concepts contributed by the inventors to advance the art, and are to be construed as not being limited to these specific examples and conditions. Although embodiments of the present disclosure have been described in detail, it should be understood that various changes, substitutions, and modifications can be made thereto without departing from the spirit and scope of the present disclosure.

[0076] While specific advantages have been listed above, various embodiments may include some, none, or all of the listed advantages. Furthermore, other technical advantages will become apparent to those skilled in the art after reading the foregoing figures and description.

[0077] In order to assist the Patent Office and any reader of any patent published in this application in understanding the appended claims, the applicants wish to indicate that they do not intend any appended claim or claim element to refer to 35 U.S.SC §112(f) unless the terms “means for…” or “steps for…” are expressly used in a particular claim.

Claims

1. A switched mode amplifier system comprising: a switched mode amplifier comprising: an amplifier input coupled to an output of an analog integrator; and an amplifier output; and a calibration system configured to: force an input of the analog integrator to be a fixed known input value; force the amplifier output to be a fixed known duty cycle; measure an analog signal generated at an output of the analog integrator in response to forcing the input of the analog integrator to be the fixed value; determine an offset of the switched mode amplifier system based on the analog signal; and correct the offset.

2. The switched mode amplifier system of claim 1, wherein: the offset comprises an input offset of the analog integrator; and correcting the offset comprises modifying the input offset of the analog integrator.

3. The switched mode amplifier system of claim 1, wherein, correcting the offset comprises adding a digital correction to the input of the analog integrator.

4. The switched mode amplifier system of claim 1, further comprising a digital-to-analog converter coupled at its output to the input of the analog integrator.

5. The switched mode amplifier system of claim 4, wherein, correcting the offset comprises adding a digital correction to an input of the digital-to-analog converter.

6. The switched mode amplifier system of claim 5, wherein, the digital correction is a function of a common mode component of an output signal at the amplifier output.

7. The switched mode amplifier system of claim 1, wherein, the amplifier output comprises a differential output comprising a positive polarity terminal and a negative polarity terminal.

8. The switched mode amplifier system of claim 1, further comprising a feedback network coupled between the amplifier output and the input of the analog integrator.

9. The switched mode amplifier system of claim 8, wherein: the offset comprises a resistor mismatch of a feedback resistor integrated to the feedback network and / or an input resistor coupled to the input of the analog integrator; and correcting the offset comprises modifying at least one resistance of the feedback resistor and / or the input resistor.

10. The switched mode amplifier system of claim 9, wherein, the fixed known duty cycle is substantially the same on the positive polarity terminal and the negative polarity terminal of the amplifier output.

11. The switched mode amplifier system of claim 10, the calibration system configured to: change the fixed known duty cycle from a first fixed duty cycle to a second fixed duty cycle; determine a difference in an output signal at the output of the analog integrator in response to changing the fixed known duty cycle from the first fixed duty cycle to the second fixed duty cycle; and correct the difference. correcting the difference comprises modifying at least one resistance of a feedback resistor integrated to a feedback network coupled between the amplifier output and the input of the analog integrator and / or an input resistor coupled to the input of the analog integrator.

12. The switched mode amplifier system of claim 11, wherein, correcting the difference comprises adding a digital correction to an input of the digital-to-analog converter.

13. The switched mode amplifier system of claim 11, further comprising a digital to analog converter coupled at its output to an input of the analog integrator; and wherein, 14. The switched mode amplifier system of claim 9, the calibration system configured to: change the fixed known duty cycle between at least three duty cycles; determine a difference in an output signal at the output of the analog integrator in response to changing the fixed known duty cycle between at least three duty cycles; and ​ correcting the offset includes adding a digital correction to an input of the analog integrator.

15. The switched mode amplifier system of claim 1, wherein, The calibration system is capable of performing the forcing, measuring, determining, and correcting steps during a calibration phase that occurs when an integrated circuit including the switched mode amplifier system is powered on, that occurs after the switched mode amplifier system is assembled, that occurs when the amplifier system is not in use, and / or that occurs in response to a change in temperature in a vicinity of the switched mode amplifier system.

16. The switched mode amplifier system of claim 1, wherein, The calibration system is further configured to: store a calibration value for correcting the offset; and reinvoke the stored calibration value and apply the calibration value to correct the offset.

17. A method in a switched mode amplifier system having a switched mode amplifier, the switched mode amplifier including an amplifier input coupled to an output of an analog integrator and an amplifier output, the method comprising: forcing an input of the analog integrator to be a fixed known input value; forcing the amplifier output to be a fixed known duty cycle; measuring an analog signal generated at the output of the analog integrator in response to forcing the input of the analog integrator to be the fixed value; determining an offset of the switched mode amplifier system based on the analog signal; and correcting the offset.

18. The method of claim 17, wherein: the offset includes an input offset of the analog integrator; and correcting the offset includes modifying the input offset of the analog integrator.

19. The method of claim 17, wherein, correcting the offset includes adding a digital correction to an input of the analog integrator.

20. The method of claim 17, the switched mode amplifier system further having a digital-to-analog converter, the digital-to-analog converter coupled at its output to an input of the analog integrator.

21. The method of claim 20, wherein, correcting the offset includes adding a digital correction to an input of the digital-to-analog converter.

22. The method of claim 21, wherein, the digital correction is a function of a common mode component of an output signal at the amplifier output.

23. The method of claim 17, wherein, the amplifier output includes a differential output, the differential output including a positive polarity terminal and a negative polarity terminal.

24. The method of claim 17, the switched mode amplifier system further having a feedback network coupled between the amplifier output and the input of the analog integrator.

25. The method of claim 24, wherein: the offset includes a resistor mismatch of a feedback resistor integrated into the feedback network and / or an input resistor coupled to the input of the analog integrator; and correcting the offset includes modifying at least one of the feedback resistor and / or the input resistor. the fixed known duty cycle is substantially the same on the positive polarity terminal and the negative polarity terminal of the amplifier output.

26. The method of claim 25, wherein, 27. The method of claim 26, further comprising: changing the fixed known duty cycle from a first fixed duty cycle to a second fixed duty cycle; determining a difference in an output signal at the output of the analog integrator in response to changing the fixed known duty cycle from the first fixed duty cycle to the second fixed duty cycle; and correcting the difference. ​ ​ 28. The method of claim 27, wherein, Correcting the difference includes modifying at least one of a feedback resistor integrated into a feedback network coupled between the amplifier output and an input of the analog integrator and / or an input resistor coupled to the input of the analog integrator.

29. The method of claim 27, the switched mode amplifier system further having a digital-to-analog converter coupled at its output to an input of the analog integrator; and wherein, Correcting the difference includes adding a digital correction to an input of the digital-to-analog converter.

30. The method of claim 25, further comprising: varying the fixed known duty cycle between at least three duty cycles; determining a difference in output signals at an output of the analog integrator in response to varying the fixed known duty cycle between at least three duty cycles; and correcting the difference includes correcting a non-linear difference between a feedback resistor integrated into the feedback network and / or an input resistor coupled to the input of the analog integrator.

31. The method of claim 17, further comprising performing the forcing, measuring, determining, and correcting steps during a calibration phase, the calibration phase occurring when an integrated circuit including the switch mode amplifier system is powered on, occurring after the switch mode amplifier system is assembled, occurring when the amplifier system is not in use, and / or occurring in response to a change in temperature proximate the switch mode amplifier system.

32. The method of claim 17, further comprising: storing a calibration value used to correct the offset; and retrieving the stored calibration value and applying the calibration value to correct the offset.

33. A calibration system for use with a switch mode amplifier system having a switch mode amplifier, the switch mode amplifier including an amplifier input coupled to an output of an analog integrator and an amplifier output, the calibration system configured to: force an input of the analog integrator to a fixed known input value; force the amplifier output to a fixed known duty cycle; measure an analog signal generated at the output of the analog integrator in response to forcing the input of the analog integrator to the fixed value; determine an offset of the switch mode amplifier system based on the analog signal; and correct the offset.

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