Gate drive circuit and display device

Abstract

The present invention relates to the field of display technology and provides a gate drive circuit and a display device. The gate drive circuit includes multiple gate drive units. In each gate drive unit, a drive signal generation module outputs a gate drive signal for that stage based on multiple clock signals, multiple gate drive signals, and a voltage signal at a control node. A transfer signal generation module outputs a transfer signal for that stage based on the voltage signal at the control node. An output stabilization module clamps the voltage signal at the control node based on a first timing signal or a second timing signal to stabilize the gate drive signal and transfer signal for that stage. A pull-down control module maintains the voltage at the control node at a high potential during the pull-down phase of the gate drive signal for that stage, thereby shortening the pull-down time of the gate drive signal for that stage. This effectively improves the output capability of the GIA circuit and reduces the gate pull-down time without increasing the size of the TFT, thereby reducing circuit noise and power consumption.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a gate drive circuit and a display device. Background Art

[0002] Liquid crystal displays (LCDs) offer numerous advantages, including thinness, energy efficiency, and radiation-free performance. Consequently, they have gradually replaced traditional cathode ray tube (CRT) displays. Currently, LCDs are widely used in a variety of electronic devices, including high-definition digital televisions, desktop computers, personal digital assistants (PDAs), laptop computers, mobile phones, and digital cameras.

[0003] Taking a thin film transistor (TFT) liquid crystal display device as an example, it includes: a liquid crystal display panel and a driving circuit, wherein the liquid crystal display panel includes a plurality of gate lines and a plurality of data lines, and two adjacent gate lines and two adjacent data lines intersect to form a pixel unit, and each pixel unit includes at least one thin film transistor. The driving circuit includes: a gate drive circuit and a source drive circuit. With the pursuit of low cost of liquid crystal display devices by manufacturers and the improvement of manufacturing technology, it has become possible to set the driving circuit integrated chip originally set outside the liquid crystal display panel on the glass substrate of the liquid crystal display panel. For example, the gate drive integrated circuit is set on the array substrate (Gate IC in Array, GIA) to simplify the manufacturing process of the liquid crystal display device and reduce production costs.

[0004] The basic working principle of the liquid crystal display panel and the driving circuit is as follows: the gate driving circuit sends a gate driving signal to the gate line through a pull-up transistor electrically connected to the gate line, turning on the TFT of each row in sequence, and then the source driving circuit simultaneously charges the pixel units of an entire row to the required voltage to display different grayscales. That is, first the gate driving circuit of the first row turns on the thin film transistors of the first row through its pull-up transistor, and then the source driving circuit charges the pixel units of the first row. When the pixel units of the first row are charged, the gate driving circuit turns off the thin film transistors of that row, and then the gate driving circuit of the second row turns on the thin film transistors of the second row through its pull-up transistor, and then the source driving circuit charges and discharges the pixel units of the second row. This sequence continues, and when the pixel units of the last row are charged, charging starts again from the first row.

[0005] In the existing gate drive circuit, the output end of the gate drive signal of each stage of the gate drive unit is connected to the gate drive unit of the previous stage and / or the next stage, so that the gate drive signal output by it is used as the transmission signal of the previous stage and / or the next stage gate drive unit. This is equivalent to increasing the load of each stage of the gate drive unit, thereby causing the driving capability of each stage of the gate drive unit to decrease, and the transmission signal is easily attenuated due to a short circuit or a decrease in the driving capability of a stage of the gate drive unit, which can easily cause the failure of the entire gate drive circuit and poor reliability. At the same time, as product resolution increases and the number of GIA stages increases, the charging time of each row of gates is getting shorter and shorter. In addition, the dual-gate structure design (dual gate structure refers to a dual gate structure with two gates, each of which can control the degree of current flowing through the transistor, thereby achieving precise current control) further shortens the charging time. This requires the output capability of the GIA circuit to be continuously improved. To ensure that the gate drive circuit can output a sufficiently large voltage, the output capability of the GIA circuit is generally improved by increasing the size of the TFT, such as increasing the channel width-to-length ratio of the pull-up transistor. However, due to the large channel width-to-length ratio of the pull-up transistor, its own parasitic capacitance between the gate and source is large. Therefore, when multiple AC signals switch between positive and negative voltages, the parasitic capacitance between the gate and source of the transistor will produce a large coupling effect (especially at high temperatures). This will cause the gate drive signal and the transmission signal output by the gate drive unit to be unstable. In addition, as the number of GIA stages increases, the noise and power consumption increase, which in turn requires effective suppression of noise and power loss.

[0006] Therefore, it is necessary to provide an improved technical solution to overcome the above technical problems existing in the prior art. Summary of the Invention

[0007] In order to solve the above technical problems, the present invention provides a gate drive circuit and a display device, which can effectively improve the output capability of the GIA circuit and reduce the gate pull-down time without increasing the TFT size, thereby reducing circuit noise and power consumption.

[0008] In one aspect, the present invention provides a gate driving circuit, comprising a plurality of gate driving units, each of which is configured to drive a corresponding gate line on a display panel, wherein each of the gate driving units comprises:

[0009] A drive signal generating module, the drive signal generating module including a plurality of signal input terminals, outputting a current-stage gate drive signal according to a clock signal, a previous-stage gate drive signal, a subsequent-stage gate drive signal, and a voltage signal of a control node inputted by the plurality of signal input terminals;

[0010] a transfer signal generating module, the transfer signal generating module being connected to the drive signal generating module and outputting a transfer signal of this stage according to the voltage signal of the control node;

[0011] an output stabilization module, the output stabilization module being connected between the first timing signal terminal, the second timing signal terminal, and the control node, and clamping and controlling the voltage signal of the control node according to the first timing signal or the second timing signal to stabilize the gate drive signal of the current stage and the transfer signal of the current stage;

[0012] A pull-down control module is connected between the control node and the output stabilization module, and maintains the voltage of the control node at a high potential during the pull-down phase of the current-stage gate drive signal to shorten the pull-down time of the current-stage gate drive signal.

[0013] In some embodiments, the plurality of signal input terminals include:

[0014] A first signal input terminal, the first signal input terminal receiving the gate drive signal of the first three stages;

[0015] A second signal input terminal, the second signal input terminal receiving the transmission signal of the first three stages;

[0016] A third signal input terminal, the third signal input terminal receiving the gate drive signal of the last three stages;

[0017] a fourth signal input terminal, the fourth signal input terminal receiving the first clock signal;

[0018] A fifth signal input terminal is connected to the second clock signal.

[0019] In some embodiments, the driving signal generating module includes:

[0020] A first switching element, a second switching element and a third switching element, wherein the first switching element and the third switching element are connected in series between the first signal input terminal and the fourth signal input terminal, the connection node between the first switching element and the third switching element is connected to the control terminal of the second switching element as the control node, the control terminal of the first switching element is connected to the second signal input terminal, the control terminal of the third switching element is connected to the third signal input terminal, the first terminal of the second switching element is connected to the fifth signal input terminal, and the second terminal of the second switching element provides the gate drive signal of this stage.

[0021] In some embodiments, the transfer signal generating module includes:

[0022] A fourth switch element, wherein the control end of the fourth switch element is connected to the control node, the first end of the fourth switch element is connected to the fifth signal input end, and the second end of the fourth switch element provides the current stage transmission signal.

[0023] In some embodiments, the output stabilization module includes:

[0024] a first output stabilization unit, connected between the first timing signal terminal and the control node, and clamping and controlling the voltage signal of the control node according to the first timing signal to stabilize the gate drive signal of the current stage and the transfer signal of the current stage;

[0025] The second output stabilization unit is connected between the second timing signal terminal and the control node, and clamps and controls the voltage signal of the control node according to the second timing signal to stabilize the gate drive signal of this stage and the transfer signal of this stage.

[0026] In some embodiments, the first output stabilization unit includes:

[0027] The fifth switching element, the sixth switching element, the seventh switching element, the eighth switching element, the ninth switching element and the tenth switching element, the first end and the control end of the fifth switching element, and the control end of the seventh switching element are commonly connected to the first timing signal end, the second end of the fifth switching element is connected to the control ends of the eighth switching element, the ninth switching element and the tenth switching element as the first connection node, the control end of the sixth switching element is connected to the control node, the second end of the sixth switching element is connected to the first connection node, the first end of the eighth switching element is connected to the control node, the first end of the ninth switching element is connected to the second end of the second switching element, and the first end of the tenth switching element is connected to the second end of the fourth switching element.

[0028] In some embodiments, the second output stabilization unit includes:

[0029] The eleventh switching element, the twelfth switching element, the thirteenth switching element, the fourteenth switching element, the fifteenth switching element and the sixteenth switching element, the second end and the control end of the eleventh switching element and the control end of the thirteenth switching element are commonly connected to the second timing signal end, the first end of the eleventh switching element is connected to the control ends of the fourteenth switching element, the fifteenth switching element and the sixteenth switching element as the second connection node, the control end of the twelfth switching element is connected to the control node, the second end of the twelfth switching element and the second end of the seventh switching element are commonly connected to the second connection node, the first end of the twelfth switching element and the first end of the seventh switching element are commonly connected to the first end of the sixth switching element, the first end of the fourteenth switching element is connected to the The second end of the eighth switching element, and the connection node of the fourteenth switching element and the eighth switching element, the first end of the seventh switching element and the second end of the thirteenth switching element are commonly connected to the first low voltage signal end, the second end of the fourteenth switching element is connected to the control node, the first end of the fifteenth switching element is connected to the second end of the ninth switching element, the second end of the fifteenth switching element is connected to the second end of the second switching element, the first end of the sixteenth switching element is connected to the second end of the tenth switching element, the second end of the sixteenth switching element is connected to the second end of the fourth switching element, the connection node of the fifteenth switching element and the ninth switching element and the connection node of the sixteenth switching element and the tenth switching element are commonly connected to the first low voltage signal end.

[0030] In some embodiments, the pull-down control module includes:

[0031] a first capacitor, a seventeenth switching element, an eighteenth switching element, a nineteenth switching element, and a twenty-first switching element; wherein the first end of the first capacitor is connected to the control node; the second end of the first capacitor is connected to the first end of the seventeenth switching element and the first end of the eighteenth switching element, respectively; the control end of the seventeenth switching element serves as a sixth signal input end, receiving the current stage transmission signal; the second end of the seventeenth switching element is connected to the first high voltage signal end; the control end of the eighteenth switching element serves as a seventh signal input end, receiving the gate drive signals of the first three stages; the second end of the eighteenth switching element is connected to the second low voltage signal end, receiving the first low voltage signal or a low-level signal less than the first low voltage signal; the control end of the nineteenth switching element is connected to the control end of the eighth switching element; the first end of the nineteenth switching element and the second end of the twentieth switching element are commonly connected to the second end of the first capacitor; the second end of the nineteenth switching element is connected to the first end of the twentieth switching element, and the control end of the twentieth switching element is connected to the control end of the fourteenth switching element.

[0032] In some embodiments, the first clock signal and the second clock signal have the same period, and the duty cycle of the first clock signal and the second clock signal are both fifty percent.

[0033] In another aspect, the present invention provides a display device comprising:

[0034] A panel including a two-dimensional pixel array consisting of a plurality of pixels, and a plurality of gate lines in a first direction and a plurality of data lines in a second direction connected to each pixel array;

[0035] A data driving circuit, used for providing image signals to the data lines;

[0036] The gate driving circuit is used to provide gate scanning signals to the gate lines.

[0037] The beneficial effects of the present invention are as follows: the present invention provides a gate drive circuit and a display device, wherein the gate drive circuit includes multiple stages of gate drive units, a drive signal generation module in each stage of the gate drive unit outputs a gate drive signal of the current stage based on a clock signal, a previous stage gate drive signal, a next stage gate drive signal, and a voltage signal of a control node connected to multiple signal input terminals, a transfer signal generation module outputs a transfer signal of the current stage based on the voltage signal of the control node, an output stabilization module is used to clamp and control the voltage signal of the control node based on a first timing signal or a second timing signal to stabilize the gate drive signal of the current stage and the transfer signal of the current stage, and a pull-down control module is used to maintain the voltage of the control node at a high potential during the pull-down phase of the gate drive signal of the current stage to shorten the pull-down time of the gate drive signal of the current stage, thereby effectively improving the output capability of the GIA circuit and reducing the gate pull-down time without increasing the size of the TFT, thereby reducing circuit noise and power consumption.

[0038] At the same time, the technical solution of the present invention can be applied to high-resolution display devices to improve their data transmission rate and response speed, as well as the design solution for dual-gate structure thin-film transistors, which can achieve precise control of current while improving product stability and reliability.

[0039] In addition, as the number of stages of the GIA circuit increases and the charging time of the gate drive signal of each row of transistors becomes shorter and shorter, the charging efficiency is guaranteed. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.

[0041] Figure 1 A schematic diagram showing the circuit structure of a gate driving unit in a gate driving circuit in the prior art is shown;

[0042] Figure 2 Show Figure 1 Schematic diagram of the potential change of the control node Q in the gate driving unit and the waveform of the gate driving signal Gn at this stage;

[0043] Figure 3 A schematic diagram showing the circuit structure of a gate driving unit in a gate driving circuit provided by an embodiment of the present disclosure is shown;

[0044] Figure 4a Show Figure 3 A timing diagram of the clock signals required in the gate drive unit is shown;

[0045] Figure 4b Shown separately Figure 1 and Figure 3 Schematic diagram of the potential change of the control node Q in the gate driving unit and the waveform of the gate driving signal Gn at this stage;

[0046] Figure 5 A schematic diagram showing the circuit structure of a gate driving unit in a gate driving circuit provided by another embodiment of the present disclosure is shown;

[0047] Figure 6 A schematic diagram of the circuit structure of a gate driving unit in a gate driving circuit provided in yet another embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0048] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The accompanying drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure may be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the disclosure.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0050] The gate drive circuit (also referred to as a shift register) disclosed herein includes multiple stages of gate drive units (also referred to as shift register units). The gate drive units of each stage are electrically connected to each row of gate lines on the display panel, thereby applying the gate drive signal sequentially to each row of gate lines. The connection relationship between the gate drive units will be described in detail below.

[0051] Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings.

[0052] Figure 1A schematic diagram showing the circuit structure of each gate driving unit in a gate driving circuit in the prior art is shown. Figure 2 Show Figure 1 Schematic diagram of the potential change of the control node Q in the gate driving unit and the waveform of the gate driving signal Gn of this stage.

[0053] The gate drive circuit includes multiple stages such as Figure 1 In the gate driving unit 100 shown, each stage of the gate driving unit 100 includes a driving signal generating module, a transfer signal generating module, a first stabilizing module, and a second stabilizing module. The driving signal generating module is used to output the gate driving signal Gn of the current stage, and the transfer signal generating module is used to output the transfer signal Zn. The first stabilizing module and the second stabilizing module work alternately to stabilize the gate driving signal Gn of the current stage output by the driving signal generating module and the transfer signal Zn output by the transfer unit.

[0054] Among them, the driving signal generating module includes a first switching element M1, a second switching element M2, and a third switching element M3. The transfer signal generating module includes a fourth switching element M4, and the fourth switching element M4 includes a seventh path end, an eighth path end, and a fourth control end. The seventh path end receives the first clock signal CLK3, the fourth control end is connected to the second path end of the first switching element M1, and the eighth path end outputs the current stage transfer signal Zn. The first stabilizing module includes a fifth switching element M5, a sixth switching element M6, a seventh switching element M7, an eighth switching element M8, a ninth switching element M9, and a tenth switching element M10. The second stabilizing module includes an eleventh switching element M11, a twelfth switching element M12, a thirteenth switching element M13, a fourteenth switching element M14, a fifteenth switching element M15, and a sixteenth switching element M16. The circuit connection relationship between each module and its modules is as shown in FIG. Figure 1 As shown, no detailed description is given here.

[0055] The working process of each gate drive unit is divided into four stages: pre-charging stage, pull-up stage, pull-down stage, and stabilization stage:

[0056] Pre-charging stage: the upper three-level transfer signal Zn-3 output by the gate driving unit with a difference of three levels upward changes from a low level to a high level, and the first switching element M1 is turned on. When the upper three-level gate driving signal Gn-3 changes from a low level to a high level, the node Q is pre-charged through the turned-on first switching element M1. Due to the jump (from a low level to a high level) of the upper three-level gate driving signal Gn-3 output by the gate driving unit with a difference of three levels upward, the parasitic capacitance between the first channel end and the first control end of the first switching element M1 is coupled, so that the voltage of the first control end of the first switching element M1 is further pulled up, and the first switching element M1 is more fully turned on. Moreover, since the node Q is pre-charged, the second switch element M2, the fourth switch element M4, the sixth switch element M6 and the twelfth switch element M12 are all turned on, and the voltages at the node QB1 and the node QB2 are respectively pulled down to the first reference low voltage provided by the first reference low voltage source VSQ through the turned-on sixth switch element M6 and the twelfth switch element M12. Therefore, the eighth switch element M8, the ninth switch element M9, the tenth switch element M10, the fourteenth switch element M14, the fifteenth switch element M15 and the sixteenth switch element M16 are all turned off.

[0057] Pull-up phase: When the level of the first clock signal CLK3 changes from low to high, since the node Q has already been precharged during the pre-charge phase, the second switch element M2 and the fourth switch element M4 are both turned on. Due to the conduction of the second switch element M2 and the bootstrap effect of the first capacitor C1, the voltage at the node Q is further pulled up. The further increase in the voltage at the node Q makes the second switch element M2 more fully conductive, so that the current-stage gate drive signal Gn output by the current-stage gate driver unit is pulled up by the first clock signal CLK3 through the conductive second switch element M2. Similarly, the further increase in the voltage at the node Q makes the fourth switch element M4 more fully conductive, so that the current-stage transfer signal Zn output by the current-stage gate driver unit is pulled up by the first clock signal CLK3 through the conductive fourth switch element M4.

[0058] Pull-down Phase: When the level of the first clock signal CLK3 changes from high to low, since the second switching element M2 and the fourth switching element M4 are both turned on during the pull-up phase and the second clock signal CLK5 and the three lower gate drive signals output by the gate driving unit three levels below are at a high level, the first clock signal CLK3 pulls down the current-stage gate drive signal Gn and the current-stage transfer signal Zn output by the current-stage gate driving unit through the turned-on second switching element M2 and the turned-on fourth switching element M4, respectively. This causes the current-stage gate drive signal Gn and the current-stage transfer signal Zn output by the current-stage gate driving unit to be quickly pulled down. Furthermore, since the three lower gate drive signals Gn+3 output by the gate driving unit three levels below change from a low level to a high level, the third switching element M3 turns on. Therefore, when the second clock signal CLK5 changes from a high level to a low level, the node Q is pulled down by the second clock signal CLK5 through the turned-on third switching element M3.

[0059] Stable Phase: During the pull-down phase, the gate drive signal Gn and the transfer signal Zn output by the gate drive unit are pulled low by the first clock signal CLK3 via the conductive second switch element M2 and the conductive fourth switch element M4, respectively. Furthermore, the voltage at node Q is also pulled low via the conductive third switch element M3. Therefore, during the subsequent period, i.e., the stable phase, it is necessary to maintain node Q, the transfer signal Zn of the gate drive unit, and the gate drive signal Gn output by the gate drive unit at a low level to achieve an ideal waveform.

[0060] Because of the existence of C, the voltage at point Q is coupled and raised when the gate drive signal Gn of this stage starts to charge, such as Figure 2 As shown, when the pull-up phase A is followed by the pull-down phase B, Q is coupled and pulled down when the gate drive signal Gn of the current stage is pulled down. Due to the existence of phase B, the voltage at point Q decreases correspondingly when the gate drive signal Gn of the current stage is pulled down, thereby causing the gate drive signal Gn of the current stage to pull down slowly, resulting in a lower output capability of the GIA. To improve the output capability of the GIA, the prior art generally achieves this by increasing the size of the switch tube T2 or even other TFTs in the GIA circuit, but this will increase circuit noise and power consumption.

[0061] Based on this, the present disclosure proposes a new circuit structure of a gate drive unit, which can improve the output capacity of GIA while reducing circuit noise and power consumption without increasing the size of TFT or even reducing the size of TFT.

[0062] Figure 3 FIG. 1 is a schematic diagram showing a circuit structure of a gate driving unit in a gate driving circuit provided by an embodiment of the present disclosure, Figure 4a Show Figure 3The timing diagram of the clock signal required in the gate drive unit is shown in FIG. Figure 4b Shown separately Figure 1 and Figure 3 Schematic diagram of the potential change of the control node Q in the gate driving unit and the waveform of the gate driving signal Gn of this stage.

[0063] On the one hand, the embodiment of the present disclosure provides a gate driving circuit, which includes a multi-stage gate driving unit 200, each stage of the gate driving unit 200 is used to drive a corresponding gate line on the display panel, wherein, with reference to Figure 3 Each gate driving unit 200 may include: a driving signal generating module 210 , a transfer signal generating module 220 , an output stabilizing module 230 and a pull-down control module 240 .

[0064] The drive signal generating module 210 includes multiple signal input terminals and is configured to output a current-stage gate drive signal Gn based on clock signals (e.g., CLK5 and CLK3), a previous-stage gate drive signal (in this embodiment, the first three stages, such as Gn-3), a subsequent-stage gate drive signal (in this embodiment, the subsequent three stages, such as Gn+3), and a voltage signal at the control node Q. The transfer signal generating module 220 is connected to the drive signal generating module 210 and is configured to output a current-stage transfer signal Zn based on the voltage signal at the control node Q. The output stabilization module 230 is connected between the first timing signal terminal, the second timing signal terminal, and the control node Q and clamps and controls the voltage signal at the control node Q based on the first timing signal V1 or the second timing signal V2 to stabilize the current-stage gate drive signal Gn and the current-stage transfer signal Zn. The pull-down control module 240 is connected between the control node Q and the output stabilization module 230 and is used to maintain the voltage of the control node Q at a high potential during the pull-down phase of the current-stage gate drive signal Gn, so as to shorten the pull-down time of the current-stage gate drive signal Gn.

[0065] In this embodiment, the clock signal required by each gate driving unit 200 can be obtained by performing phase shifting on the initial clock signal CLK1, such as Figure 4aAs shown in CLK2-CLK6, the phase shift step unit between adjacent clock signals is, for example, T / 4. Of course, in the structure of the gate driving unit 200 of this embodiment, only the clock signals CLK5 and CLK3 are applied, and the application circuit structure of other clock signals is not fully shown. It should also be noted that the aforementioned phase shift step unit can be adjusted according to actual needs. For example, to meet the display effect of a high-resolution display device, the phase shift step unit can be adjusted to T / 6, T / 8, etc., or in a low-resolution display device, the phase shift step unit can be adjusted to T / 3, T / 2, etc., or in other alternative implementations, the clock signal selected by each gate driving unit 200 can be selected from other timing signals other than those in this embodiment of CLK2-CLK6 according to waveform parameters, which is not limited here.

[0066] In this embodiment, it is assumed that the gate driving circuit includes N-level gate driving units 200 (e.g., N≥7), the gate driving unit 200 of this level is the n-th level gate driving unit 200, wherein N-3≥n≥4, the transfer signal output by the gate driving unit 200 of this level is Zn, and the gate driving signal output is Gn. Then, the previous level gate driving signal output by the drive signal generating module 210 of the gate driving unit 200 that is one level above is Gn-1, the previous level gate driving signal output by the drive signal generating module 210 of the gate driving unit 200 that is two levels above is Gn-2, and the previous level gate driving signal output by the drive signal generating module 210 of the gate driving unit 200 that is three levels above is Gn-3; the previous level gate driving signal output by the transfer signal generating module 220 of the gate driving unit 200 that is one level above is Gn-1. The transfer signal is Zn-1, the upper two-level transfer signals output by the transfer signal generating module 220 of the gate driving unit 200 that differs by two levels upward are Zn-2, and the upper three-level transfer signals output by the transfer signal generating module 220 of the gate driving unit 200 that differs by three levels upward are Zn-3; the next-level gate driving signal output by the drive signal generating module 210 of the gate driving unit 200 that differs by one level downward is Gn+1, the next-level gate driving signals output by the drive signal generating module 210 of the gate driving unit 200 that differs by two levels downward are Gn+2, and the next-level gate driving signals output by the drive signal generating module 210 of the gate driving unit 200 that differs by three levels downward are Gn+3, and so on. In the following text, the upper level is also referred to as the previous level, and the next level is referred to as the next level. Other names are similar and have the same meanings.

[0067] In some embodiments, the plurality of signal input terminals include:

[0068] A first signal input terminal, the first signal input terminal is connected to the gate drive signal Gn-3 of the first three stages;

[0069] A second signal input terminal, the second signal input terminal is connected to the transmission signal Zn-3 of the first three stages;

[0070] A third signal input terminal, the third signal input terminal is connected to the gate drive signal Gn+3 of the last three stages;

[0071] a fourth signal input terminal, the fourth signal input terminal receiving the first clock signal CLK5;

[0072] A fifth signal input terminal is connected to the second clock signal CLK3.

[0073] In some embodiments, the drive signal generating module 210 includes: a first switch element M1, a second switch element M2, and a third switch element M3. The first switch element M1 and the third switch element M3 are connected in series between the first signal input terminal and the fourth signal input terminal. The connection node between the first switch element M1 and the third switch element M3 serves as the control node Q and is connected to the control terminal of the second switch element M2. The control terminal of the first switch element M1 is connected to the second signal input terminal, the control terminal of the third switch element M3 is connected to the third signal input terminal, a first terminal of the second switch element M2 is connected to the fifth signal input terminal, and a second terminal of the second switch element M2 provides the current-stage gate drive signal Gn.

[0074] In some embodiments, the transfer signal generating module 220 includes: a fourth switch element M4, the control end of the fourth switch element M4 is connected to the control node Q, the first end of the fourth switch element M4 is connected to the fifth signal input end, and the second end of the fourth switch element M4 provides the current stage transfer signal Zn.

[0075] In some embodiments, the output stabilization module 230 may include: a first output stabilization unit and a second output stabilization unit. The first output stabilization unit is connected between the first timing signal terminal and the control node Q, and clamps and controls the voltage signal of the control node Q according to the first timing signal V1 to stabilize the current-stage gate drive signal Gn and the current-stage transfer signal Zn. The second output stabilization unit is connected between the second timing signal terminal and the control node Q, and clamps and controls the voltage signal of the control node Q according to the second timing signal V2 to stabilize the current-stage gate drive signal Gn and the current-stage transfer signal Zn.

[0076] The first and second timing signals V1 and V2 are both low-frequency signals. Their periods and duty cycles are equal. When the first timing signal V1 is high, the second timing signal V2 is low, and when the first timing signal V1 is low, the second timing signal V2 is high. This allows the first and second output stabilization units to operate alternately. The first clock signal CLK5 and the second clock signal CLK3 have the same period, and both have a duty cycle of 50%. However, the first clock signal CLK5 and the second clock signal CLK3 differ by one-third of a period. Therefore, when the first clock signal CLK5 transitions from high to low, i.e., is on a falling edge, the second clock signal CLK3 is high.

[0077] In some embodiments, the first output stabilization unit includes: a fifth switching element M5 , a sixth switching element M6 , a seventh switching element M7 , an eighth switching element M8 , a ninth switching element M9 and a tenth switching element M10 .

[0078] Among them, the first end and the control end of the fifth switch element M5 and the control end of the seventh switch element M7 are commonly connected to the first timing signal end and are connected to the first timing signal V1. The second end of the fifth switch element M5 serves as the first connection node QB1 and is respectively connected to the control ends of the eighth switch element M8, the ninth switch element M9 and the tenth switch element M10. The control end of the sixth switch element M6 is connected to the control node Q, the second end of the sixth switch element M6 is connected to the first connection node QB1, the first end of the eighth switch element M8 is connected to the control node Q, the first end of the ninth switch element M9 is connected to the second end of the second switch element M2, and the first end of the tenth switch element M10 is connected to the second end of the fourth switch element M4.

[0079] In some embodiments, the second output stabilization unit includes an eleventh switching element M11 , a twelfth switching element M12 , a thirteenth switching element M13 , a fourteenth switching element M14 , a fifteenth switching element M15 , and a sixteenth switching element M16 .

[0080] The second end and the control end of the eleventh switch element M11 and the control end of the thirteenth switch element M13 are commonly connected to the second timing signal end and are connected to the second timing signal V2. The first end of the eleventh switch element M11 is connected as the second connection node QB2 to the control ends of the fourteenth switch element M14, the fifteenth switch element M15 and the sixteenth switch element M16, respectively. The control end of the twelfth switch element M12 is connected to the control node Q. The second end of the twelfth switch element M12 and the second end of the seventh switch element M7 are commonly connected to the second connection node QB2. The first end of the twelfth switch element M12 and the first end of the seventh switch element M7 are commonly connected to the first end of the sixth switch element M6. The first end of the fourteenth switch element M14 is connected to the second end of the eighth switch element M8, and the fourteenth switch element M14 is connected to the eighth switch element M8. The connection node of the switch element M8, the first end of the seventh switch element M7 and the second end of the thirteenth switch element M13 are commonly connected to the first low voltage signal end and are connected to the first low voltage signal VGL. The second end of the fourteenth switch element M14 is connected to the control node Q. The first end of the fifteenth switch element M15 is connected to the second end of the ninth switch element M9, and the second end of the fifteenth switch element M15 is connected to the second end of the second switch element M2. The first end of the sixteenth switch element M16 is connected to the second end of the tenth switch element M10, and the second end of the sixteenth switch element M16 is connected to the second end of the fourth switch element M4. The connection node of the fifteenth switch element M15 and the ninth switch element M9 and the connection node of the sixteenth switch element M16 and the tenth switch element M10 are commonly connected to the first low voltage signal end and are connected to the first low voltage signal VGL.

[0081] In some embodiments, the pull-down control module 240 includes: a first capacitor C1 , a seventeenth switching element M17 , an eighteenth switching element M18 , a nineteenth switching element M19 , and a twentieth switching element M20 .

[0082] The first end of the first capacitor C1 is connected to the control node Q, the second end of the first capacitor C1 is connected to the first ends of the seventeenth switching element M17 and the eighteenth switching element M18, respectively. The control end of the seventeenth switching element M17 serves as a sixth signal input end, receiving the current-stage transfer signal Zn. The second end of the seventeenth switching element M17 is connected to the first high-voltage signal end. The control end of the eighteenth switching element M18 serves as a seventh signal input end, receiving the gate drive signal Gn-3 of the first three stages. The second end of the eighteenth switching element M18 is connected to the second low-voltage signal end, receiving a first low-voltage signal or a low-level signal less than the first low-voltage signal. The control end of the nineteenth switching element M19 is connected to the control end of the eighth switching element M8. The first end of the nineteenth switching element M19 and the second end of the twentieth switching element M20 are commonly connected to the second end of the first capacitor C1. The second end of the nineteenth switching element M19 is connected to the first end of the twentieth switching element M20, and the control end of the twentieth switching element M20 is connected to the control end of the fourteenth switching element M14.

[0083] In this embodiment, preferably, the first to twentieth switching elements M1 - M20 are N-type transistors.

[0084] In other embodiments, the first to twentieth switching elements M1 to M20 may also be implemented using other switching elements, such as P-type transistors. The following uses the first to twentieth switching elements M1 to M20 as N-type transistors as an example to specifically describe the specific implementation and working principle of the embodiment of the present disclosure.

[0085] In some embodiments, the first clock signal CLK5 and the second clock signal CLK3 have the same period, and the duty cycle of the first clock signal CLK5 and the second clock signal CLK3 are both 50%.

[0086] In this embodiment, the working process of each gate driving unit 200 is also divided into four stages: pre-charging stage, pull-up stage, pull-down stage, and stable stage. Figure 1 The circuits shown have similar structures and similar working principles, which can be understood in conjunction with the above description. Similarly, since the first clock signal CLK5 is a clock signal, it will continue to generate pulses in the subsequent period (i.e., after the stabilization phase), which will affect the transfer signal Zn output by the current-stage gate driving unit 200 and the current-stage gate driving signal Gn output by the current-stage gate driving unit 200. In order to eliminate these effects, the embodiment of the present disclosure can utilize the output stabilization module 230 for improvement.

[0087] Specifically, in the subsequent time, when the first clock signal CLK5 changes from low to high, due to the parasitic capacitance Cgd between the control node Q and the first clock signal CLK5 of the second switch element M2, the control node Q will be coupled by the parasitic capacitance Cgd and generate noise. However, when the first timing signal V1 is at a high level, the fifth switch element M5 and the seventh switch element M7 are turned on, so that the control node QB1 is pulled high through the turned-on fifth switch element M5, and the node QB2 is pulled high through the turned-on seventh switch element M7. The node Q is pulled low by the turned-on eighth switch element M8, the gate drive signal Gn of the current stage output by the gate drive unit of the current stage is pulled low by the turned-on ninth switch element M9, and the transfer signal Zn of the current stage output by the gate drive unit of the current stage is pulled low by the turned-on tenth switch element M10.

[0088] It is noteworthy that in this embodiment, during the stable phase, the phases of the first timing signal V1 and the second timing signal V2 are always opposite, so that the voltages of the nodes QB1 and QB2 can alternately be high levels, thereby causing the eighth to tenth switching elements M8 to M10 and the fourteenth to sixteenth switching elements M14 to M16 to operate alternately, thereby ensuring the stability of the gate drive circuit while reducing the impact of threshold drift and ensuring the reliability of the gate drive circuit.

[0089] But with Figure 1 The difference in the working principle of the structure is that the input point voltage V–variable ≤ VGL of the eighteenth switching element M18, and the coupling effect of the first capacitor C1 can achieve a higher potential of the control node Q, thereby improving the output capacity of GIA. Specifically, when the output of the current-stage gate drive signal Gn ends and turns into the first low-voltage signal VGL, because the current-stage gate drive signal Gn is not connected to the first capacitor C1, when the current-stage gate drive signal Gn turns from the first high-voltage signal VGH to the first low-voltage signal VGL, the voltage of the control node Q will not be coupled down due to the presence of the first capacitor C1. Only the parasitic capacitance Cgd / Cgs of the second switching element M2 will have a coupling effect on the control node Q, so that the control node Q can still maintain a higher voltage during the pull-down stage, but the pull-down capability of the second switching element M2 can be increased, so that the pull-down time (Falling time) is further shortened. Figure 4b As shown, compared with the prior art Figure 1The pull-down capability of the gate drive signal of the current stage in the gate drive unit 100 structure of the embodiment and the gate drive signal of the current stage in the gate drive unit 200 structure of the embodiment is significantly accelerated. According to the actual simulation results, it can be seen that under the same load of the gate drive signal Gn of the current stage, the pull-down capability of the gate drive signal Gn of the current stage is improved, and the pull-down time can be reduced.

[0090] In an alternative embodiment, the input point of the eighteenth switch element M18 can be directly connected to the first low voltage signal VGL, such as Figure 5 As shown, similarly, when the gate drive signal Gn of this stage changes from the first high voltage signal VGH to the first low voltage signal VGL, the voltage of the control node Q will not be coupled down due to the presence of the first capacitor C1. Only the parasitic capacitance Cgd / Cgs of the second switch element M2 will have a coupling effect on the control node Q. In the pull-down phase, the control node Q can still maintain a relatively high voltage, while increasing the pull-down capability of the second switch element M2, thereby further shortening the pull-down time.

[0091] In order to further reduce power consumption and realize a low power consumption solution, in an alternative embodiment, the input point of the seventeenth switching element M17 can be directly connected to the gate drive signal Gn of the current stage, and the input point of the eighteenth switching element M18 can be directly connected to the first low voltage signal VGL. Figure 6 As shown, the power loss caused by the leakage of the seventeenth switching element M17 can be reduced.

[0092] Based on the same inventive concept, the present disclosure further provides a display device, comprising:

[0093] A panel including a two-dimensional pixel array consisting of a plurality of pixels, and a plurality of gate lines in a first direction and a plurality of data lines in a second direction connected to each pixel array;

[0094] A data driving circuit, used for providing image signals to the data lines;

[0095] The gate driving circuit is used to provide gate scanning signals to the gate lines.

[0096] In summary, the embodiments of the present disclosure provide a gate drive circuit and a display device, wherein the gate drive circuit includes a multi-stage gate drive unit 200. The drive signal generation module 210 in each stage of the gate drive unit 200 outputs a gate drive signal Gn of the current stage based on a clock signal, a previous-stage gate drive signal, a next-stage gate drive signal, and a voltage signal at a control node Q connected to a plurality of signal input terminals. The transfer signal generation module 220 outputs a transfer signal Zn of the current stage based on the voltage signal at the control node Q. The output stabilization module 230 is configured to clamp and control the voltage signal at the control node Q based on a first timing signal V1 or a second timing signal V2 to stabilize the gate drive signal Gn of the current stage and the transfer signal Zn of the current stage. The pull-down control module 240 is configured to maintain the voltage of the control node Q at a high potential during the pull-down phase of the gate drive signal Gn of the current stage to shorten the pull-down time of the gate drive signal Gn of the current stage. This effectively improves the output capability of the GIA circuit and reduces the gate pull-down time without increasing the size of the TFT, thereby reducing circuit noise and power consumption.

[0097] At the same time, the technical solution disclosed in the present invention can be applied to high-resolution display devices to improve their data transmission rate and response speed, as well as the design of dual-gate thin-film transistors, which can achieve precise control of current while improving product stability and reliability.

[0098] In addition, as the number of stages of the GIA circuit increases and the charging time of the gate drive signal of each row of transistors becomes shorter and shorter, the charging efficiency is guaranteed.

[0099] It should be noted that in the description of the present disclosure, it needs to be understood that the terms "upper", "lower", "inner", etc., which indicate orientation or positional relationships, are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the components or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0100] In addition, as used herein, the terms "comprises," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0101] Finally, it should be noted that the above embodiments are merely examples for the purpose of illustrating the present disclosure and are not intended to limit the embodiments. Those skilled in the art will readily appreciate that other variations or modifications based on the above descriptions are possible. It is not necessary and impossible to provide an exhaustive list of all embodiments. Obvious variations or modifications arising therefrom remain within the scope of protection of the present disclosure.

Claims

1. A gate driving circuit, comprising a plurality of gate driving units, each of which is used to drive a corresponding gate line on a display panel, wherein: Each stage of the gate driving unit comprises: A drive signal generating module, the drive signal generating module including a plurality of signal input terminals, outputting a current-stage gate drive signal according to a clock signal, a previous-stage gate drive signal, a subsequent-stage gate drive signal, and a voltage signal of a control node inputted by the plurality of signal input terminals; a transfer signal generating module, the transfer signal generating module being connected to the drive signal generating module and outputting a transfer signal of this stage according to the voltage signal of the control node; an output stabilization module, the output stabilization module being connected between the first timing signal terminal, the second timing signal terminal, and the control node, and clamping and controlling the voltage signal of the control node according to the first timing signal or the second timing signal to stabilize the gate drive signal of the current stage and the transfer signal of the current stage; A pull-down control module is connected between the control node and the output stabilization module, and maintains the voltage of the control node at a high potential during the pull-down phase of the current-stage gate drive signal to shorten the pull-down time of the current-stage gate drive signal.

2. The gate drive circuit according to claim 1, wherein: The plurality of signal input terminals include: A first signal input terminal, the first signal input terminal receiving the gate drive signal of the first three stages; A second signal input terminal, the second signal input terminal receiving the transmission signal of the first three stages; A third signal input terminal, the third signal input terminal receiving the gate drive signal of the last three stages; a fourth signal input terminal, the fourth signal input terminal receiving the first clock signal; A fifth signal input terminal is connected to the second clock signal.

3. The gate driving circuit according to claim 2, wherein: The driving signal generating module includes: A first switching element, a second switching element and a third switching element, wherein the first switching element and the third switching element are connected in series between the first signal input terminal and the fourth signal input terminal, the connection node between the first switching element and the third switching element is connected to the control terminal of the second switching element as the control node, the control terminal of the first switching element is connected to the second signal input terminal, the control terminal of the third switching element is connected to the third signal input terminal, the first terminal of the second switching element is connected to the fifth signal input terminal, and the second terminal of the second switching element provides the gate drive signal of this stage.

4. The gate driving circuit according to claim 3, wherein: The transmission signal generating module includes: A fourth switch element, wherein the control end of the fourth switch element is connected to the control node, the first end of the fourth switch element is connected to the fifth signal input end, and the second end of the fourth switch element provides the current stage transmission signal.

5. The gate driving circuit according to claim 4, wherein: The output stabilization module includes: a first output stabilization unit, connected between the first timing signal terminal and the control node, and clamping and controlling the voltage signal of the control node according to the first timing signal to stabilize the gate drive signal of the current stage and the transfer signal of the current stage; The second output stabilization unit is connected between the second timing signal terminal and the control node, and clamps and controls the voltage signal of the control node according to the second timing signal to stabilize the gate drive signal of this stage and the transfer signal of this stage.

6. The gate driving circuit according to claim 5, wherein: The first output stabilization unit includes: The fifth switching element, the sixth switching element, the seventh switching element, the eighth switching element, the ninth switching element and the tenth switching element, the first end and the control end of the fifth switching element, and the control end of the seventh switching element are commonly connected to the first timing signal end, the second end of the fifth switching element is connected to the control ends of the eighth switching element, the ninth switching element and the tenth switching element as the first connection node, the control end of the sixth switching element is connected to the control node, the second end of the sixth switching element is connected to the first connection node, the first end of the eighth switching element is connected to the control node, the first end of the ninth switching element is connected to the second end of the second switching element, and the first end of the tenth switching element is connected to the second end of the fourth switching element.

7. The gate driving circuit according to claim 6, wherein: The second output stabilization unit includes: The eleventh switching element, the twelfth switching element, the thirteenth switching element, the fourteenth switching element, the fifteenth switching element and the sixteenth switching element, the second end and the control end of the eleventh switching element and the control end of the thirteenth switching element are commonly connected to the second timing signal end, the first end of the eleventh switching element is connected to the control ends of the fourteenth switching element, the fifteenth switching element and the sixteenth switching element as the second connection node, the control end of the twelfth switching element is connected to the control node, the second end of the twelfth switching element and the second end of the seventh switching element are commonly connected to the second connection node, the first end of the twelfth switching element and the first end of the seventh switching element are commonly connected to the first end of the sixth switching element, the first end of the fourteenth switching element is connected to the The second end of the eighth switching element, and the connection node of the fourteenth switching element and the eighth switching element, the first end of the seventh switching element and the second end of the thirteenth switching element are commonly connected to the first low voltage signal end, the second end of the fourteenth switching element is connected to the control node, the first end of the fifteenth switching element is connected to the second end of the ninth switching element, the second end of the fifteenth switching element is connected to the second end of the second switching element, the first end of the sixteenth switching element is connected to the second end of the tenth switching element, the second end of the sixteenth switching element is connected to the second end of the fourth switching element, the connection node of the fifteenth switching element and the ninth switching element and the connection node of the sixteenth switching element and the tenth switching element are commonly connected to the first low voltage signal end.

8. The gate driving circuit according to claim 7, wherein: The pull-down control module includes: a first capacitor, a seventeenth switching element, an eighteenth switching element, a nineteenth switching element, and a twenty-first switching element; wherein the first end of the first capacitor is connected to the control node; the second end of the first capacitor is connected to the first end of the seventeenth switching element and the first end of the eighteenth switching element, respectively; the control end of the seventeenth switching element serves as a sixth signal input end, receiving the current stage transmission signal; the second end of the seventeenth switching element is connected to the first high voltage signal end; the control end of the eighteenth switching element serves as a seventh signal input end, receiving the gate drive signals of the first three stages; the second end of the eighteenth switching element is connected to the second low voltage signal end, receiving the first low voltage signal or a low-level signal less than the first low voltage signal; the control end of the nineteenth switching element is connected to the control end of the eighth switching element; the first end of the nineteenth switching element and the second end of the twentieth switching element are commonly connected to the second end of the first capacitor; the second end of the nineteenth switching element is connected to the first end of the twentieth switching element, and the control end of the twentieth switching element is connected to the control end of the fourteenth switching element.

9. The gate driving circuit according to claim 8, wherein: The first clock signal and the second clock signal have the same period, and both have a duty cycle of 50%.

10. A display device, wherein: include: A display panel comprising a two-dimensional pixel array consisting of a plurality of pixels, and a plurality of gate lines in a first direction and a plurality of data lines in a second direction connected to each pixel array; a data driving circuit, wherein the data driving circuit provides an image signal to the data line; The gate drive circuit according to any one of claims 1 to 9, wherein the gate drive circuit provides a gate scan signal to the gate line.

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