Control method and switching device

Abstract

The embodiment of the application provides a control method and an exchange device, relates to the field of IT technology, and the method comprises the following steps: a processing module can send test cells to an uplink management module of an exchange network, receive the test cells from a downlink management module of the exchange network, and extract the identification of an exchange network chip passed by the test cells, the link number of an uplink of the exchange network and / or the link number of a downlink of the exchange network from the received test cells, so that the fault detection of the internal hardware of the exchange network can be refined to the specified link of the exchange network, the detection accuracy of the hardware with faults is improved, and the detection period is shortened.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of IT, and particularly relate to a control method and a switching device. BACKGROUND

[0002] In the field of Internet, in order to solve the problem of a large number of connections between interface boards, the interface boards can be connected through a switch fabric chip (SC) between the interface boards, so that the interface boards only need to be connected with the switch fabric chip through a plurality of wires, and the intercommunication of any interface between the interface boards can be realized. The switch fabric chip can be used to establish a connection between an ingress interface and an egress interface, and complete the switching of data. The direction from the ingress interface to the switch fabric chip is referred to as uplink, and the direction from the switch fabric chip to the egress interface is referred to as downlink.

[0003] In order to realize the reliable and accurate forwarding of the switch fabric chip to the message, whether there is a fault in the hardware in the switch fabric can be detected. The detection period of the current detection method is relatively long, and the accuracy is relatively low. SUMMARY

[0004] In order to solve the above technical problems, the present application provides a control method and a switching device. In the method, the detection period of the message rewriting can be shortened, and the link of the switch fabric with the fault can be located.

[0005] In one possible implementation, the application provides a control method. The switching device comprises a first switching network management module, at least one switching network module, a second switching network management module, and a processing module. The first switching network management module is connected with an input port of the at least one switching network module, and the second switching network management module is connected with an output port of the at least one switching network module. The method comprises: the processing module periodically sends a first test cell to the first switching network management module; the processing module receives a second test cell from the second switching network management module, wherein the second test cell is used to provide a switching network identifier of the first switching network module through which the first test cell passes, and is used to provide a target link number, the target link number comprising at least one of an uplink number and a downlink number, wherein the uplink number is an uplink number of a first uplink through which the first test cell passes when inputting into the first switching network module, and the downlink number is a downlink number of a first downlink through which the first test cell passes when outputting from the first switching network module, wherein the at least one switching network module comprises the first switching network module; the processing module extracts the switching network identifier and the target link number from the second test cell; and the processing module controls a target link of the first switching network module indicated by the switching network identifier according to the first test cell and the second test cell, and the switching network identifier and the target link number, wherein the target link comprises at least one of the first uplink and the first downlink.

[0006] The processing module can comprise a CPU 101a for controlling the first switching network management module, and / or a CPU 101b for controlling the second switching network management module, and optionally further comprises a CPU 101c for controlling the switching network module.

[0007] The second test cell is the first test cell after the first test cell is received by the first switching network management module, and the first test cell is sequentially inputted into the first switching network module through the first uplink, and is outputted from the first switching network module through the first downlink to the second switching network management module.

[0008] Since the first test cell can be rewritten and / or lost after passing through each module, the first test cell received by the processing module from the second switching network management module is named as the second test cell.

[0009] The first switching network management module can be an uplink switching network manager, the second switching network management module can be a downlink switching network manager, the switching network module can be a switching network chip, and the processing module can be a processor (for example, a central processing unit).

[0010] The uplink number is a link number of an uplink through which the first test cell is transmitted from the first switch network management module to the first switch network module.

[0011] The downlink number is a link number of a downlink through which the first test cell is transmitted from the first switch network module to the second switch network management module.

[0012] The connection between the output port of the first switch network management module and the input port of the first switch network module can form an uplink, and there can be multiple uplinks between the first switch network management module and the first switch network module.

[0013] Similarly, the connection between the output port of the first switch network module and the input port of the second switch network management module can form a downlink, and there can be multiple downlinks between the first switch network module and the second switch network management module.

[0014] The processing module of the embodiment of the present application can locate the cell content rewriting or packet loss of the test cell to the uplink and / or downlink of the switch network module through which the test cell passes, by periodically sending test cells to the uplink switch network management module and receiving the test cells from the downlink switch network management module. The test cells received can carry the link number of the switch network module through which the test cell passes and the link number of the link (uplink and / or downlink) of the switch network module through which the test cell passes. In this way, the processing module can locate the cell content rewriting or packet loss of the test cell to the uplink and / or downlink of the switch network module through which the test cell passes, so that only the uplink and / or downlink of the switch network module needs to be controlled in a fine-grained manner, without the need to shut down the entire switch network module. In this way, the switch network chip and its link in which the fault exists in the switch network can be accurately located. In addition, the test cells sent by the processing module for detecting faults are sent to the uplink switch network management module, so that the test cells pass through fewer modules in the switch device, only the uplink and downlink switch network management modules and the switch network module, so that the detection period of the faulty chip can be shortened.

[0015] In a possible implementation, before the processing module receives the second test cell from the second switch network management module, the method further includes: the processing module sends first information indicating the uplink number of the first test cell to the first switch network management module; and the first switch network management module sends the received first test cell to the first switch network module through the first uplink indicated by the uplink number according to the first information.

[0016] The processing module can also send the uplink number of the uplink through which the test cell needs to pass to the first switching network management module when sending the test cell to the first switching network management module each time. In this way, the first switching network management module can send the received first test cell to the first switching network module through the first uplink indicated by the uplink number according to the indication of the processing module.

[0017] In a possible implementation, the method further comprises: the first switching network management module writes the uplink number into the first test cell based on the first information.

[0018] In the embodiment, the uplink number of the uplink through which the test cell passes can be written into the test cell by the uplink switching network management module.

[0019] In other embodiments, the uplink number can also be written into the test cell by the switching network module or the downlink switching network module through which the test cell passes.

[0020] In a possible implementation, after the first switching network management module sends the received first test cell to the first switching network module through the first uplink indicated by the uplink number according to the first information, the method further comprises: the first switching network module writes the switching network identifier of the first switching network module into the first test cell when determining that the cell type of the received first test cell is a test cell.

[0021] The switching network module can have the ability to identify the cell type and can write the switching network identifier of the switching network module into the cell when determining that the cell type of the received cell is a test cell.

[0022] In a possible implementation, the method further comprises: the first switching network module writes the uplink number of the first uplink through which the first test cell passes when the first test cell is input into the first switching network module into the first test cell when determining that the cell type of the received first test cell is a test cell.

[0023] In the embodiment, the uplink number of the uplink through which the first test cell passes from the first switching network management module to the first switching network module can be written into the first test cell received by the first switching network module.

[0024] In a possible implementation, the method further comprises: the first switching network module writing the downlink number of the first downlink required when the first test cell is output from the first switching network module, to the first test cell, when determining that the cell type of the received first test cell is a test cell.

[0025] The downlink required when the first test cell is output from the first switching network module to the second switching network management module can be a downlink automatically selected by the first switching network module from multiple downlinks by load balancing or other strategies, or can be a downlink indicated by the processing module (for example, indicated by the CPU 101c shown in the figure). Figure 2a The CPU 101c shown in the figure instructs the first switching network module, and the downlink required by the test cell is indicated in the form of a downlink number.

[0026] In a possible implementation, the method further comprises: the first switching network module outputting the first test cell to the second switching network management module through the first downlink.

[0027] In the embodiment, the first switching network module can output the first test cell received from the first switching network management module to the second switching network management module through the first downlink according to the automatically selected first downlink or the first downlink indicated by the processing module.

[0028] In a possible implementation, the second test cell is the first test cell received by the first switching network management module from the processing module, input to the first switching network module through the first uplink, and output from the first switching network module to the second switching network management module through the first downlink.

[0029] In a possible implementation, the processing module controls the target link of the first switching network module indicated by the switching network identifier according to the first test cell and the second test cell, and the switching network identifier and the target link number, comprising: the processing module updating the cell rewriting number associated with the switching network identifier and the target link number when determining that the cell content of the first test cell is different from that of the second test cell; and the processing module closing the target link of the first switching network module indicated by the switching network identifier when determining that the cell rewriting number is greater than a first preset threshold.

[0030] The processing module can determine whether the content of the two test cells has changed each time a second test cell is received after sending a first test cell periodically. If there is a change, it means that the first test cell sent this time has been rewritten by hardware, and the number of cell rewriting associated with the switching network identifier and the target link number extracted from the second test cell can be increased by one (or other numerical values, which are not limited here). In this way, when the processing module determines that the cell rewriting test associated with the switching network identifier, the uplink number and / or the downlink number is greater than the first preset threshold, it means that there is a high probability of cell rewriting in the uplink and / or downlink of the first switching network module indicated by the switching network identifier, thereby closing the uplink and / or downlink of the first switching network module.

[0031] In a possible implementation, the processing module controls the target link of the first switching network module indicated by the switching network identifier according to the first test cell and the second test cell, and the switching network identifier and the target link number, including: the processing module determines the packet loss rate of the first test cell according to the sending strategy of the first test cell and the number of received second test cells; the processing module closes the target link of the first switching network module indicated by the switching network identifier when it is determined that the packet loss rate is greater than a second preset threshold.

[0032] The sending strategy can include but is not limited to: the sending period of the test cell, the number of first test cells sent in each sending period, and information such as sending N (N is greater than 1, N is an integer) periods of the first test cell in total.

[0033] For example Figure 2a The second CPU 101b can determine the packet loss rate of the first test cell according to the number N of sending periods, the number of first test cells sent in each sending period, and the number of received second test cells. When the packet loss rate is greater than a second preset threshold, the first CPU 101a or the second CPU 101b can close at least one of the uplink or the downlink of the SC indicated by the switching network identifier.

[0034] The closed target link can be at least one of the links indicated by the target link number.

[0035] In one possible implementation, shutting down the target link of the first switching network module indicated by the switching network identifier includes: when the target link includes the first uplink, the processing module shuts down the output port of the first switching network management module corresponding to the first uplink; and / or, when the target link includes the first downlink, the processing module shuts down the input port of the second switching network management module corresponding to the first downlink.

[0036] When the target link, including the first uplink, is shut down, it can be done by Figure 2c The first CPU 101a shown controls the shutdown of the uplink output port of SMI 102 corresponding to the first uplink.

[0037] When the target link, including the first downlink, is shut down, it can be done by Figure 2c The second CPU 101b shown controls the shutdown of the downlink input port of SME 104 corresponding to the first downlink.

[0038] In one possible implementation, the target link is at least one of the links indicated by the target link number.

[0039] In one possible implementation, this application provides a switching device. The switching device includes a first switching network management module, at least one switching network module, a second switching network management module, and a processing module. The first switching network management module is connected to the input port of the at least one switching network module, and the second switching network management module is connected to the output port of the at least one switching network module. The processing module is configured to periodically send a first test cell to the first switching network management module. The processing module is configured to receive a second test cell from the second switching network management module, wherein the second test cell is used to provide the switching network identifier of the first switching network module through which the first test cell passes, and to provide a target link number, the target link number including at least one of an uplink number and a downlink number; wherein the uplink number is... The first test cell is input to the first switching network module, and the downlink number is the first uplink number traversed by the first uplink when the first test cell is output from the first switching network module; wherein, the at least one switching network module includes the first switching network module; the processing module is used to extract the switching network identifier and the target link number from the second test cell; the processing module is used to control the target link of the first switching network module indicated by the switching network identifier based on the first test cell and the second test cell, as well as the switching network identifier and the target link number, wherein the target link includes at least one of the first uplink and the first downlink.

[0040] In a possible implementation, before the processing module receives the second test cell from the second switch network management module, the method further comprises: the processing module sending first information indicating an uplink number of the first test cell to the first switch network management module; and the first switch network management module sending the received first test cell to the first switch network module through a first uplink indicated by the uplink number according to the first information.

[0041] In a possible implementation, the method further comprises: the first switch network management module writing the uplink number into the first test cell based on the first information.

[0042] In a possible implementation, after the first switch network management module sends the received first test cell to the first switch network module through a first uplink indicated by the uplink number according to the first information, the method further comprises: the first switch network module writing the switch network identifier of the first switch network module into the first test cell when determining that the cell type of the received first test cell is a test cell.

[0043] In a possible implementation, the method further comprises: the first switch network module writing the uplink number of the first uplink through which the first test cell is input into the first switch network module when determining that the cell type of the received first test cell is a test cell.

[0044] In a possible implementation, the method further comprises: the first switch network module writing the downlink number of the first downlink through which the first test cell is output from the first switch network module when determining that the cell type of the received first test cell is a test cell.

[0045] In a possible implementation, the method further comprises: the first switch network module outputting the first test cell to the second switch network management module through the first downlink.

[0046] In a possible implementation, the second test cell is the first test cell received by the first switch network management module from the processing module and input into the first switch network module through the first uplink, and output from the first switch network module to the second switch network management module through the first downlink.

[0047] In a possible implementation, the processing module controls the target link of the first switching network module indicated by the switching network identifier according to the first test cell and the second test cell, and the switching network identifier and the target link number, including: when the processing module determines that the cell contents of the first test cell and the second test cell are different, the processing module updates the cell rewriting times associated with the switching network identifier and the target link number; and when the processing module determines that the cell rewriting times are greater than a first preset threshold, the processing module closes the target link of the first switching network module indicated by the switching network identifier.

[0048] In a possible implementation, the processing module controls the target link of the first switching network module indicated by the switching network identifier according to the first test cell and the second test cell, and the switching network identifier and the target link number, including: the processing module determines the packet loss rate of the first test cell according to the sending strategy of the first test cell and the receiving quantity of the second test cell; and when the processing module determines that the packet loss rate is greater than a second preset threshold, the processing module closes the target link of the first switching network module indicated by the switching network identifier.

[0049] In a possible implementation, closing the target link of the first switching network module indicated by the switching network identifier includes: when the target link includes the first uplink, the processing module closes the output port of the first switching network management module corresponding to the first uplink; and / or, when the target link includes the first downlink, the processing module closes the input port of the second switching network management module corresponding to the first downlink.

[0050] In a possible implementation, the target link is at least one of the links indicated by the target link number.

[0051] The effects of the switching device in the above embodiments are similar to those of the control method in the above embodiments, which will not be repeated here.

[0052] In a possible implementation, the present application provides a control device. The control device includes one or more interface circuits and one or more processors; the interface circuit is used to receive a signal from a memory and send the signal to the processor, the signal including computer instructions stored in the memory; when the processor executes the computer instructions, the processor can implement the method in any of the above embodiments.

[0053] The effects of the control device in the above embodiments are similar to those of the control method in the above embodiments, which will not be repeated here.

[0054] In a possible implementation, the present application provides a computer readable storage medium. The computer readable storage medium stores a computer program, which, when executed on a computer or a processor, causes the computer or the processor to perform the method in any of the above embodiments.

[0055] The computer readable storage medium of the present embodiment has similar effects to the control method of the above embodiments, which will not be repeated here.

[0056] In a possible implementation, the present application provides a computer program product. The computer program product contains a software program, which, when executed by a computer or a processor, causes the method in any of the above embodiments to be performed.

[0057] The computer program product of the present embodiment has similar effects to the control method of the above embodiments, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0058] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0059] Figure 1a The system structure schematic diagram in the related art is exemplarily shown;

[0060] Figure 1b The hardware detection schematic diagram in the related art is exemplarily shown;

[0061] Figure 2a The system architecture schematic diagram is exemplarily shown;

[0062] Figure 2b The system architecture schematic diagram is exemplarily shown;

[0063] Figure 2c The system architecture schematic diagram is exemplarily shown;

[0064] Figure 3 The data processing process schematic diagram is exemplarily shown;

[0065] Figure 4 The structure schematic diagram of an apparatus provided by the embodiments of the present application is shown;

[0066] Figure 5 The structure schematic diagram of a chip provided by the embodiments of the present application is shown. DETAILED DESCRIPTION

[0067] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present application.

[0068] The term "and / or" in the present application is merely used to describe an association relationship of associated objects, and indicates that three relationships can exist, for example, A and / or B can represent three cases of existence of A alone, existence of A and B simultaneously, and existence of B alone.

[0069] The terms "first" and "second" and the like in the description and claims of the embodiments of the present application are used to distinguish different objects, and are not used to describe a specific order of the objects. For example, a first target object and a second target object are used to distinguish different target objects, and are not used to describe a specific order of the target objects.

[0070] In the embodiments of the present application, the words "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design presented as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or advantageous than other embodiments or design solutions. Rather, the use of "exemplary" or "for example" is intended to present concepts in a concrete manner.

[0071] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more. For example, a plurality of processing units means two or more processing units; a plurality of systems means two or more systems.

[0072] In the field of Internet, in order to solve the problem of a large number of connections between interface boards, the interface boards can be connected through a switch fabric chip (SC) between the interface boards. In this way, the interface boards only need to be connected with the switch fabric chip through a plurality of wires, so as to realize the intercommunication of any interface between the interface boards. The switch fabric chip can be used to establish a connection between an ingress interface and an egress interface, and complete the switching of data. The direction from the ingress interface to the switch fabric chip is referred to as uplink, and the direction from the switch fabric chip to the egress interface is referred to as downlink.

[0073] In order to realize reliable and accurate forwarding of the switch fabric chip to the message, whether the switch fabric chip modifies the received message can be detected. The related technology provides a detection method, as shown in Figure 1a and Figure 1b The framework diagram of the system to which the method is applied is shown.

[0074] As shown in Figure 1a and Figure 1b , the system can include a network processor (NP), an ingress switch fabric manager (SMI), an egress switch fabric manager (SME), and a plurality of switch fabric chips can be connected between the SMI and the SME, and here, switch fabric chip 1, switch fabric chip 2, and switch fabric chip 3 are exemplarily shown.

[0075] As shown in Figure 1a and Figure 1b , in order to detect the switch fabric chip in which the packet rewriting exists in the above-mentioned three switch fabric chips. The method can perform traversal detection on whether the packet rewriting exists in the switch fabric chip. Here, the detection on whether the packet rewriting exists in the switch fabric chip 2 is taken as an example to be described.

[0076] The CPU can insert the NP packet (here, test packet 1) to the network processor, the destination IP of the test packet 1 is the IP address of the switch fabric chip 2, and then the test packet 1 can pass through the network processor, the ingress switch fabric manager, and the forwarding flow of the switch fabric chip 2 to the egress switch fabric manager in turn. Since the test packet 1 sent by the CPU passes through a plurality of chips, the rewriting of the test packet 1 can occur, and therefore, the test packet 1 flowing into the egress switch fabric manager is named as test packet 2.

[0077] Then, the CPU can read the test packet 2 from the egress switch fabric manager, and when it is determined that the test packet 2 is different from the test packet 1, as shown in Figure 1b , the CPU can close the switch fabric chip 2, so that each link between the ingress switch fabric manager and the switch fabric chip 2 is closed (indicated by “x”), and each link between the egress switch fabric manager and the switch fabric chip 2 is also closed.

[0078] Similarly, the CPU can also send the test packet with the destination IP of the switch fabric chip 1 to detect whether the packet rewriting exists in the switch fabric chip 1, and send the test packet with the destination IP of the switch fabric chip 3 to detect whether the packet rewriting exists in the switch fabric chip 3, and the specific implementation process and the principle of the processing process of the above-mentioned detection on the packet rewriting of the switch fabric chip 2 are the same, and therefore, the description is not repeated here.

[0079] In the above method, the test packet needs to pass through multiple chips, including the network processor, uplink switching network manager, switching network chip, and downlink switching network manager. It cannot accurately determine whether the packet rewriting was caused by a specific switching network chip; it could also be caused by other chips the test packet passes through. Therefore, this method has low accuracy in identifying switching network chips where packet rewriting is occurring. Furthermore, because the test packet passes through many chips, the detection cycle for switching network chips where packet rewriting is occurring is long and has significant delays. Therefore, changing the detection cycle will have a significant impact on the system.

[0080] Furthermore, this method identifies faulty hardware at a coarse level, limited to the switching chip. When it's determined that the switching chip may be subject to packet rewriting, it's considered faulty, and the faulty network board (here, the switching chip) is located. This can lead to issues such as... Figure 1b The shutdown of the entire switching chip, as shown, shuts down all uplinks and downlinks of that switching chip.

[0081] In addition, after detecting a switching chip with message rewriting, this method requires the CPU to isolate the input and output terminals of the switching chip, resulting in low efficiency of centralized management of the switching chip and high requirements for the software reliability of the detection method.

[0082] Furthermore, this method has a long detection cycle for unloaded links and cannot determine the real-time packet modification rate.

[0083] To address the numerous problems existing in related detection methods, this application provides a method capable of quickly identifying whether a switching network chip has packet tampering and / or packet loss, and detecting designated links of the switching network chip with packet tampering and / or packet loss, thus eliminating the need to shut down the entire switching network chip; only the faulty designated links need to be isolated. Furthermore, this method involves fewer chips through which the test cells pass, shortening the detection cycle for the switching network chip and its links with packet tampering.

[0084] Figure 2a to Figure 2c The diagram illustrates the system architecture of this application as an example.

[0085] like Figure 2a As shown, the switching device 100 may include an uplink line processing unit (LPU) 301, a switch fabric unit (SFU) 303, and a downlink line processing unit (LPU) 302. The SFU 303 is connected between the uplink LPU 301 and the downlink LPU 302.

[0086] The switching device 100 can be a switch or router or other device used for packet forwarding, and there are no restrictions here.

[0087] The uplink LPU301 may include a first central processing unit (CPU) 101a and an uplink switching network manager (SMI) 102 interconnected with each other. The first CPU 101a can control the SMI 102.

[0088] The downlink LPU 301 may include a second central processing unit 101b and a downlink switching network manager (SME) 104 interconnected. The second CPU 101b can control the SME 104.

[0089] SFU303 may include at least one switching network chip (SC), SC103 is shown here.

[0090] Multiple switching network chips can be connected between SMI102 and SME104, and a switching network chip 103 is shown here as an example.

[0091] In addition, CPU101a, CPU101b, and CPU101c are physically connected to each other.

[0092] In addition, there is a physical connection between SMI102 and SC103, and a physical connection between SC103 and SME104.

[0093] like Figure 2c As shown, SMI102 may include an upstream input port ingress (IPI) 201, an upstream buffer manage ingress (BMI) 202, and an upstream output port ingress (OPI) 203, which are physically connected in sequence. SME104 may include a downstream input port egress (IPE) 401, a downstream buffer manage egress (BME) 402, and a downstream output port egress (OPE) 403, which are physically connected in sequence.

[0094] For example, the SMI102 has 16 uplink output ports 203, the SME104 has 16 downlink input ports 401, and the SC has 4 uplink ports and 4 downlink ports. Each of the 4 uplink output ports 203 of the SMI102 can be physically connected to the 4 uplink ports of an SC, and each of the 4 downlink input ports 401 of the SME104 can be physically connected to the 4 downlink ports of an SC.

[0095] Thus, as Figure 2a to Figure 2cAs shown, SMI 102 and SC 103 can have 4 uplinks based on 4 physical connections, respectively uplink 1 to uplink 4; similarly, SC 103 and SME 104 have 4 downlinks based on 4 physical connections, respectively downlink 1 to downlink 4.

[0096] For Figure 2a The connection structure of other SCs not shown in FIG. 1 between SMI 102 and SME 104 is similar to that of SC 103, which will not be described here.

[0097] It should be understood that the present application does not limit the number of uplinks between SMI 102 and SC 103, and the number of downlinks between SC 103 and SME 104.

[0098] The data processing process of switching device 100 shown in FIG. 1 will be described below in combination with Figure 3 . Figure 2a to Figure 2c The data processing process of switching device 100 shown in FIG. 1 will be described below in combination with

[0099] As shown in FIG. 1, CPU 101 of the present application can include Figure 3 As shown in FIG. 1, CPU 101 of the present application can include Figure 2a to Figure 2c first CPU 101a, second CPU 101b, and optionally third CPU 101c. Wherein, CPU 101 can run the target program of the present application to execute the method of the present application, the process of which can include the following steps:

[0100] S201a, CPU 101 periodically sends test cells to SMI 102.

[0101] Wherein, the cell is a fixed-length message, and the cell is composed of a cell header and a cell content.

[0102] For example, the types of cells of the present application can be divided into test class cells and non-test class cells.

[0103] The test cell of the present application belongs to the test class cell, and the data structure of the test class cell is the same as that of the non-test class cell (which can be referred to as "data cell"), which is also composed of a cell header of a specific length and a cell content of a specific length. There is no difference between the test class cell and the non-test class cell in data structure (or format).

[0104] The function of the test cell can be to determine which switching network chip in switching device 100 and which link of the switching network chip has failed, such as cell rewriting or cell packet loss failure, etc. This embodiment takes cell rewriting as an example to illustrate, which is used to identify the switching network chip and its link that have failed in switching device 100. The data cell is used to execute the service cell.

[0105] The cell header of the test cell of the present application can include information indicating the cell type.

[0106] For example, the cell header of the test cell of the present application can carry a cell type identifier indicating that the cell type of the test cell is a test class cell (e.g. represented by type A), while the cell header of a data cell can not carry the cell type identifier indicating type A, or can carry a cell type identifier indicating that the cell type of the cell is a non-test class cell (e.g. type B). In this way, the method of the present application can distinguish test class cells and non-test class cells through the cell header of the cell.

[0107] The first CPU 101a can generate test cells and periodically send the test cells to the SMI 102.

[0108] When generating the test cell, the first CPU 101a can fill a specific code (e.g. 01 code) in the payload of the test cell. The specific code can be a pre-set code or a randomly set code, which is not limited here.

[0109] In addition, the first CPU 101a sends the test cell without affecting the reception and forwarding of data cells by the switching device 100 of the present application, and the test cell of the present application does not affect the normal service flow, and the test cell can be sent online.

[0110] In addition, the sending period of the test cell described above is configurable. For example, when the switching device 100 has a low load (e.g. a low packet sending amount of data cells, etc., which is not limited in detail), the sending period of the test cell can be automatically reduced to support automatic stress testing under the condition of low load of the switching device 100, and to ensure that the hardware with cell rewriting can be quickly discovered. For another example, the first CPU 101a can also flexibly adjust the sending period of the test cell based on the real-time packet loss rate of the test cell, to accelerate the identification speed of the chip with fault in the switching device 100.

[0111] In the present embodiment, the first CPU 101a and the second CPU 101b can determine the sending strategy of the test cell (e.g. sending period, number of test cells sent in each sending period, etc.), the cell content of the test cell, the link number of the uplink and / or downlink that the test cell needs to pass through, the evaluation strategy for determining the hardware fault in the switching device 100 by using the test cell, etc. through negotiation.

[0112] For example, before sending the test cell, the first CPU 101a can inform the second CPU 101b of the following content: send a test cell to the uplink 1 of the SC 103 every second, and the cell content of the test cell is 1111.

[0113] Of course, in other examples, the cell content of each cell sent can be different in order to detect the same link of the same SC, and this is not a restriction here.

[0114] S201b, CPU101 sends information indicating the uplink number of the test cell to SMI102.

[0115] S201a and S201b can be executed together in one step or separately, without restriction.

[0116] To Figure 2a to Figure 2c Taking SC103 as an example, there are 4 uplinks between SMI102 and SC103, namely uplink 1 to uplink 4. Each uplink has a link number that can identify the uplink. In order to detect whether cell rewriting has occurred on a certain uplink of SC103, the first CPU101a can periodically send test cells to SMI102 for a certain uplink of SC103 to be tested.

[0117] For example, to detect uplink 1 of SC103, the first CPU101a can periodically send test cells to SMI102, and each time it sends a test cell to SMI102, it also sends the link number of the uplink that the test cell will pass through (e.g., the link number of uplink 1). In this process, the content of the test cells sent periodically by the first CPU101a for detecting uplink 1 can be the same or different, which is not restricted here.

[0118] Similarly, when other uplinks of SC103 need to be detected, the first CPU101a can periodically send test cells related to the corresponding uplink number to SMI102, and also send the uplink number related to the test cell to SMI102.

[0119] When detecting different links (e.g., different uplinks), the period of the test cells sent by the first CPU 101a can be the same or different, and there is no restriction here.

[0120] There are four links between SMI102 and SC103. In order to test each link, the first CPU101a can periodically send test cells for each uplink by executing the target program of this application. The principle of the process is similar and will not be described in detail here.

[0121] In other embodiments, the first CPU 101a can also not construct the test cell, but periodically instructs the SMI 102 to construct the test cell. In this way, the SMI 102 can generate the test cell of the test type according to the instruction of the CPU 101, and the cell content includes a specific code, and the link number of the uplink through which the test cell instructed by the first CPU 101a needs to pass is written into the test cell constructed by the SMI 102.

[0122] In other embodiments, after S201a and S201b, optionally, S202, the SMI 102 can write the uplink number into the test cell. In the above S201b, the first CPU 101a instructs the information of the link number of the uplink through which the test cell needs to pass (uplink number), and then the SMI 102 can write the uplink number instructed by the first CPU 101a into the test cell.

[0123] In the embodiments of the above S201a and S201b, the uplink number can be written into the cell header of the test cell, so that the SME 104 can directly compare the cell content of the received test cell with the cell content of the test cell notified by the SEI 102 to detect whether the test cell has been rewritten, thereby improving the detection efficiency. Figure 3

[0124] In other embodiments, the uplink number can also be written into the cell content of the test cell, for example, a field of a specified size can be reserved in the cell content for writing the uplink number.

[0125] S203, the SMI 102 sends the test cell to the SC 103 through the uplink 1 indicated by the uplink number.

[0126] As shown in the above S203, for example, the uplink number related to the test cell 1 is the link number of the uplink 1. Figure 2c

[0127] As shown in the above S203, for example, the uplink number related to the test cell 1 is the link number of the uplink 1. Figure 2c

[0128] Optionally, the uplink cache manager 202 can write the uplink number into the test cell.

[0129] Then, the uplink cache manager 202 can send the cached test cell 1 to a certain uplink output port 203 corresponding to the uplink 1 according to the instruction of the uplink 1, so as to send the test cell 1 to the SC 103 in the SFU 303 through the uplink 1. ​​​

[0130] S201a to S203 are processes in which the first CPU 101a executes the target program of the present application to cause the first CPU 101a to perform the corresponding operation, and the first CPU 101a instructs the SMI 102 to perform the corresponding operation.

[0131] S204, the SC 103 identifies the cell type of the test cell as a test cell.

[0132] The SC 103 can identify the cell header (carrying the cell type identifier indicating the cell type) of the received test cell to determine whether the received cell is a test cell or a non-test cell (e.g., a data cell).

[0133] For example, when the SC 103 determines that the cell header of the test cell carries a cell type identifier indicating that the cell type is a test cell, it means that the test cell received from the uplink 1 is a test cell, and S205 and S206 are executed.

[0134] The SC 103 supports the identification function of the cell type in hardware and can execute S205 and S206 for test cells without the need for the third CPU 101c to control the SC 103 to execute the operations of S204 to S206.

[0135] S205, the SC 103 assigns the test cell to the downlink 1.

[0136] In this embodiment, the SC 103 can automatically assign the downlink to the test cell received from the uplink 1 according to load balancing and other strategies, for example, the assigned downlink is downlink 1.

[0137] In other embodiments, the downlink through which the test cell is output from the SC 103 can also be specified by the target program of the present application, so that, as shown in Figure 2c The third CPU 101c can be physically connected to the SC 103, and the third CPU 101c can send the downlink number of the downlink 1 through which the test cell 1 needs to pass to the SC 103 by running the target program of the present application, so that the SC 103 can perform the downlink number writing operation in the following S206 according to the indicated downlink number.

[0138] S206, the SC 103 can write the uplink number, the corresponding downlink number and the SC identifier into the test cell.

[0139] As shown in Figure 2c When the SC 103 determines that the received test cell 1 is a test cell, the SC identifier of the SC 103 can be written into the test cell 1.

[0140] In addition, SC103 can also write the uplink number of uplink 1 when the test cell 1 is input to SC103, and the downlink number of downlink 1 when it is output from SC103 (e.g., the downlink number automatically determined by SC103, or the downlink number indicated by the third CPU101c) into the test cell 1.

[0141] When SC103 receives test cell 1 from SMI102, it can determine which uplink the test cell 1 was received from, and thus write the uplink number of the uplink 1 that the test cell 1 passed through into the received test cell 1.

[0142] In this embodiment, SC103 can write the uplink number that the test cell 1 passes through, the downlink number of the downlink that will be passed through here, and the SC identifier of the SC103 that it passes through into the test cell 1.

[0143] Regarding the writing position of the uplink number, downlink number, and SC identifier of SC103 in test cell 1, it can be the cell header or cell content (for example, specifying multiple specific fields to be used to write the SC identifier, uplink number, and downlink number respectively), there is no restriction here.

[0144] In this embodiment, the example is taken that SC103 writes the uplink number of uplink 1, the downlink number of downlink 1, and the SC identifier of SC103 that the test cell 1 passes through into the test cell 1. In other embodiments, SC103 can write its SC identifier into the test cell 1 when it determines that the test cell 1 is a test class message. At least one piece of information, such as the uplink number and downlink number that the test cell 1 passes through, can also be written into the test cell 1 by SMI102 and / or SME104.

[0145] For example, such as Figure 2a to Figure 2c The first CPU 101a shown can instruct SMI 102 on the uplink number and optionally the downlink number of the test cell 1. Under the control of the first CPU 101a, SMI 101 can write the uplink number and downlink number into the test cell 1 received from the first CPU 101a. Then, through the uplink 1 indicated by the uplink number, the test cell 1 is sent to SC103 in SFU 303.

[0146] For example, such as Figure 2a to Figure 2cThe first CPU 101a sends the uplink number of the uplink through which the test cell 1 passes to the second CPU 101b in the downlink SFU 302, so that the second CPU 101b can determine the uplink number of the uplink through which the test cell 2 received from the SME 104 passes.

[0147] The SC 103 sends the test cell to the SME 104 through the downlink 1 in S207.

[0148] In which, as shown in the figure, the SC 103 can send the test cell 1 to the SME 104 through the automatically selected downlink 1 or the downlink 1 indicated by the third CPU 101c. Figure 2c

[0149] The test cell 1 in which the SC identifier of the SC 103 and the uplink number of the uplink through which it passes are written is sent by the SC 103 to the downlink input port 401 of the SME 104 through the downlink 1, and is buffered at the downlink buffer manager 402 from the downlink input port 401, and the test cell 1 buffered at the downlink buffer manager 402 is referred to as the test cell 2, because the test cell 1 can be rewritten in content after passing through the SMI 102, the uplink 1, the SC 103, the downlink 1 and the SME 104 after being sent from the first CPU 101a, wherein in the embodiment, the uplink number, the downlink number and the SC identifier are written in the cell header of the test cell 1, and the cell content is not changed.

[0150] Alternatively, in other embodiments, when at least one of the uplink number, the downlink number and the SC identifier is written in the cell content of the test cell 1, the information is also written in the specified field of the test cell 1, and as shown in Figure 2a to Figure 2c When the second CPU 101b determines whether the cell content of the test cell 1 is rewritten, it also detects whether the cell content is rewritten except for the specified field in the cell content.

[0151] As shown in Figure 2a to Figure 2c When the link number of the downlink through which the test cell 1 passes is written in the test cell 1 by the SME 104, the SME 104 can receive the test cell 1 sent by the SC 103 from the downlink 1 in this step, so as to directly determine that the downlink through which the test cell 1 passes is the downlink 1, and determine the link number of the downlink 1, so as to write the downlink number of the downlink 1 in the test cell 1 received by the SME 104.

[0152] Optionally, when the test cell is output from the SC 103 to the SME 104, there can be a certain time delay (for example, 100 milliseconds).

[0153] ​Thus, the method of the present application is acceptable for detecting the delay performance of SC message rewriting, and the delay is low.

[0154] S208, the CPU 101 receives the test cell from the SME 104.

[0155] As Figure 2a to Figure 2c , the SME 104 can send the test cell 2 cached by the downlink cache manager 402 to the second CPU 101b through the downlink output port 403, so that the second CPU 101b can receive the test cell 2.

[0156] Here, the test cell 2 carries the SC identifier of the SC 103 it passes through, as well as the link number of the uplink and the downlink of the SC 103 it passes through.

[0157] S209, the CPU 101 determines that the cell content of the sent test cell is different from the received test cell.

[0158] Here, the cell is a fixed-length message, and the length of the message is not fixed. In order to reduce the signaling overhead on the hardware, the cell is used as the data basis for detecting whether the message rewriting of the SC occurs. Thus, in the process from the first CPU 101a sending the test cell 1 to the SMI 102 to the test cell output from the SME 104 to the second CPU 101b, the second CPU 101b only needs to determine whether the cell content of the test cell 2 read from the recovery position (here, the downlink cache manager 402) of the test cell 2 is the cell content notified by the first CPU 101a to the second CPU 101b before the first CPU 101a periodically sends the test cell 1, so as to determine whether the test cell sent by the first CPU 101a is rewritten when passing through the SC, without the need to detect the start address and the end address of the cell to determine whether the length of the message has changed. Figure 2c Figure 2c As

[0159] As Figure 2c shown, when the second CPU 101b determines that the cell content of the test cell 1 sent by the first CPU 101a is different from the cell content of the test cell 2 received by the second CPU 101b, the second CPU 101b can perform S210.

[0160] Alternatively, in other embodiments, the second CPU 101b can also send the received test cell 2 to the first CPU 101a to make the first CPU 101a perform S209 to S211, and the principle is similar.

[0161] S210, the CPU 101 extracts the uplink and downlink numbers and the SC identifier from the received test cell.

[0162] As​Figure 2b As shown, the second CPU 101b can extract the uplink number, downlink number and SC identifier from the received test cell 2.

[0163] S211, the CPU 101 adds one to the cell rewriting number associated with the uplink number and downlink number and SC identifier.

[0164] Since the test cell 1 has its cell content (e.g. the specific encoding mentioned above) rewritten after passing through the SC 103, the second CPU 101b can add one to the cell rewriting number associated with the uplink 1, downlink 1 and SC 103 that the test cell 1 has passed through.

[0165] On the contrary, if the test cell 1 has not changed its cell content after passing through the SC 103, the payload of the test cell 2 is the same as the payload of the test cell 1 sent by the first CPU 101a to the SMI 102, then there is no need to add one to the cell rewriting number mentioned above.

[0166] S212, when the CPU 101 determines that the cell rewriting number is greater than a preset threshold, the SMI 102 is controlled to close the uplink.

[0167] S213, when the CPU 101 determines that the cell rewriting number is greater than a preset threshold, the SME 104 is controlled to close the downlink.

[0168] For example, the preset threshold is 2, or 3 or other thresholds, which can be flexibly adjusted according to actual needs.

[0169] Since the cell rewriting number is not only associated with the SC, but also associated with the uplink number and downlink number of the SC, when the second CPU 101b determines that the cell rewriting number associated with a certain uplink number and a certain downlink number of a certain SC is greater than 2, it can be determined that the probability of message rewriting of the uplink and downlink of the SC is relatively high, and the second CPU 101b can close the downlink 1 corresponding to the downlink number of the SMI 104, so that the data cells and test cells input into the switching device 100 are no longer output from the above downlink 1 of the SC 103.

[0170] In addition, the second CPU 102b can also notify the first CPU 101a to close the uplink (here, the uplink 1) corresponding to the above certain uplink number. Then the first CPU 101a can control to close the uplink 1 of the SMI 102, so that the data cells and test cells input into the switching device 100 are no longer input from the above uplink 1 of the SC 103.

[0171] For example, as Figure 2c and Figure 2bAs shown, the 4 uplinks between the SMI 102 and the SC 103 can be lines connected through the respective 4 interfaces, and similarly, the 4 downlinks between the SC 103 and the SME 104 can be lines connected through the respective 4 interfaces. Then when closing an uplink 1, the closing of the uplink 1 between the uplink output port 203 of the SMI 102 and the input port of the SC 103 can be realized by controlling the closing of the uplink output port 203 of the SMI 102, and similarly, the closing of a downlink 1 can be realized by controlling the closing of the downlink input port 401 of the SME 104.

[0172] Then when the first CPU 101a closes the uplink 1 of the SMI 102, the first CPU 101a can control the closing of the uplink output port 203 of the SMI 102 corresponding to the uplink 1 according to the uplink number notified by the second CPU 101b, so as to realize the closing of the uplink 1 between the SMI 102 and the SC 103.

[0173] Then when the second CPU 101b closes the downlink 1 of the SME 104, the second CPU 101b can control the closing of the downlink input port 401 of the SME 104 corresponding to the downlink 1 according to the downlink number extracted from the test cell 2 received, so as to realize the closing of the downlink 1 between the SC 103 and the SME 104.

[0174] Thus, as shown, the data cells input to the switching device 100, or the test cells input to the SMI 102 from the first CPU 101a, are no longer input from the uplink 1 between the SMI 102 and the SC 103, and are no longer output from the downlink 1 between the SC 103 and the SME 104, so as to realize the effect of closing (indicated by X) the uplink 1 and the downlink 1 of the SC 103, without causing the whole network board of the SC 103 to be isolated, and without causing all the uplink and downlink of the switching network chip 2 to be closed, as shown, so as to ensure the high reliability and availability of the SC. Figure 1b Figure 2a to Figure 2c

[0175] In the above embodiment, the second CPU 101b performs the above S209 to S211, and in other embodiments, the second CPU 101b can also send the test cell 2 received from the SME 104 to the first CPU 101a, and the first CPU 101a performs the S209 to S211, and the principle is similar, which will not be described here.

[0176] ​​In addition, in the above embodiment, the evaluation strategy for determining that the SC and its link have a fault (to close the corresponding link) is that the number of times of rewriting the test cells is greater than a preset threshold. In other embodiments, the evaluation strategy for determining that the SC and its link have a fault can also be that the packet loss rate of the test cells is counted, and when it is determined that the packet loss rate is greater than a packet loss rate threshold, the corresponding uplink and / or downlink of the corresponding SC is closed.

[0177] For example, Figure 2a to Figure 2c The first CPU 101a in the first SC 101 can notify the second CPU 101b of the sending strategy of the test cells. For example, the sending strategy is that one test cell is sent every 1 s on the uplink 1 (or all the uplinks send), and the sending is completed within 30 s. Then, under normal circumstances, the second CPU 101b should receive one test cell passing through the uplink 1 from the SME 104 every 1 s, and the second CPU 101b can count the number of test cells passing through the uplink 1 received within 30 s, so as to determine the packet loss rate.

[0178] For example, the second CPU 101b only receives 10 test cells passing through the uplink 1 within 30 s, which indicates that the packet loss rate of the test cells passing through the uplink 1 is 2 / 3, and the packet loss rate is greater than a packet loss rate threshold (for example, 50%, which can be flexibly configured according to actual needs). Then, the second CPU 101b can notify the first CPU 101a to close the uplink 1 of the SC 103.

[0179] In some embodiments, in order to accelerate the detection efficiency of the SC and its link fault, the method can also flexibly adjust the sending strategy of the first CPU 101a to the test cells according to the real-time packet loss rate (or cell rewriting rate) of the test cells. Wherein, the cell rewriting rate = the ratio of the number of times of rewriting the test cells to the number of sent test cells.

[0180] For example, the packet loss rate is taken as an example to illustrate, and the principle is similar when the parameter is the cell rewriting rate, which is not described here.

[0181] In the above embodiment, the second CPU 101b can extract the SC identifier, the uplink number and the downlink number from the test cell 2. In some embodiments, the test cell 2 can carry the SC identifier of the SC through which the test cell 1 sent by the first CPU 101a passes, and at least one of the uplink number and the downlink number of the uplink and the downlink of the SC through which the test cell 1 passes. When the CPU in the switching device 100 determines that there is a faulty link through the evaluation strategy of the hardware fault, the CPU can only perform the closing operation on the link corresponding to the link number carried in the test cell 2.

[0182] In addition, in the above embodiment, the second CPU 101b can extract the SC identifier, the uplink number, and the downlink number from the test cell 2. In some embodiments, the test cell 2 can carry the SC identifier of the SC through which the test cell 1 sent by the first CPU 101a passes, and at least one of the uplink number and the downlink number of the uplink and the downlink of the SC through which the test cell 1 passes. When the CPU in the switching device 100 determines that there is a faulty link through the evaluation strategy of the hardware fault, the CPU can only perform the closing operation on the link corresponding to the link number carried in the test cell 2.

[0183] In addition, in the above embodiment, the second CPU 101b can extract the SC identifier, the uplink number, and the downlink number from the test cell 2. In some embodiments, the test cell 2 can carry the SC identifier of the SC through which the test cell 1 sent by the first CPU 101a passes, and at least one of the uplink number and the downlink number of the uplink and the downlink of the SC through which the test cell 1 passes. When the CPU in the switching device 100 determines that there is a faulty link through the evaluation strategy of the hardware fault, the CPU can only perform the closing operation on the link corresponding to the link number carried in the test cell 2.

[0184] The above technical solution of the present application uses the SMI of the switching network to send the test cell, without sending the test cell through the NP. In this way, the number of chips through which the test cell passes can be reduced, the detection period and the delay of the switching network chip can be reduced, and the detection accuracy of whether the switching network chip has packet rewriting can be improved.

[0185] Further, the method of the present application can quickly find the specific SC of the rewritten message and the specific link number (including the cell input link and the cell output link) of the SC, and uses the method of closing the problematic link for processing, which has no effect on the traffic of other links of the SC and the traffic of other SCs, and has little effect on the bandwidth of the switching network. In addition, the method of the present application can periodically send test cells of the switching network by a software program to realize the periodic detection of the switching network in the switching device 100, which can reduce the impact on the system.

[0186] Further, the number of test cells sent by the CPU 101 can be obtained, and whether the test cells sent each time are rewritten can also be determined. In this way, the CPU 101 can determine the rewriting rate of the test cells on a certain uplink of the currently tested SC in real time based on whether the cell content of the periodically sent test cells and the received corresponding test cells are the same.

[0187] Figure 2a to Figure 2c The system framework structure diagram is shown for example. It should be understood that, Figure 2a to Figure 2c The system shown is only an example, and the system of the present application can have more or fewer components than those shown in the figure, can combine two or more components, or can have a different component configuration. Figure 2a to Figure 2c The various components shown in the figure can be implemented in hardware, software, or a combination of hardware and software, including one or more signal processing and / or application specific integrated circuits.

[0188] It should be understood that the system of the present application Figure 3 and Figure 2a to Figure 2c Objects with the same reference numerals represent the same objects, and have the same functions and effects, so the above description of the objects with the same reference numerals is not repeated.

[0189] The above Figure 2a to Figure 2c The components between the components are shown with one-way arrows, and in actual applications, there can be bidirectional interaction between different components connected by lines. Here, only the flow of the method of the present application is taken as an example to describe the data processing process of the system. In other embodiments, there can also be reverse data interaction, because the uplink and the downlink are defined with respect to the transmission direction of the cells, and here there is no limitation. Figure 4 In other embodiments, there can also be reverse data interaction, because the uplink and the downlink are defined with respect to the transmission direction of the cells, and here there is no limitation.

[0190] In a possible implementation, the application provides a switching device. The switching device comprises a first switching network management module, at least one switching network module, a second switching network management module, and a processing module. The first switching network management module is connected with an input port of the at least one switching network module, and the second switching network management module is connected with an output port of the at least one switching network module. The processing module is configured to periodically send a first test cell to the first switching network management module. The processing module is configured to receive a second test cell from the second switching network management module, wherein the second test cell is configured to provide a switching network identifier of a first switching network module through which the first test cell passes, and to provide a target link number, the target link number comprising at least one of an uplink number and a downlink number. The uplink number is an uplink number of a first uplink through which the first test cell passes when the first test cell is input to the first switching network module, and the downlink number is a downlink number of a first downlink through which the first test cell passes when the first test cell is output from the first switching network module. The at least one switching network module comprises the first switching network module. The processing module is configured to extract the switching network identifier and the target link number from the second test cell. The processing module is configured to control a target link of the first switching network module indicated by the switching network identifier according to the first test cell and the second test cell, and according to the switching network identifier and the target link number, wherein the target link comprises at least one of the first uplink and the first downlink.

[0191] In a possible implementation, before the processing module receives the second test cell from the second switching network management module, the method further comprises: the processing module sends first information indicating the uplink number of the first test cell to the first switching network management module; and the first switching network management module sends the received first test cell to the first switching network module through the first uplink indicated by the uplink number according to the first information.

[0192] In a possible implementation, the method further comprises: the first switching network management module writes the uplink number into the first test cell based on the first information.

[0193] In a possible implementation, after the first switching network management module sends the received first test cell to the first switching network module through the first uplink indicated by the uplink number according to the first information, the method further comprises: the first switching network module writes the switching network identifier of the first switching network module into the first test cell when it is determined that the cell type of the received first test cell is a test cell.

[0194] In a possible implementation, the method further comprises: the first switching network module writes the uplink number of the first uplink through which the first test cell is input to the first switching network module when the first test cell is determined to be a test type cell into the first test cell.

[0195] In a possible implementation, the method further comprises: the first switching network module writes the downlink number of the first downlink through which the first test cell is output from the first switching network module when the first test cell is determined to be a test type cell into the first test cell.

[0196] In a possible implementation, the method further comprises: the first switching network module outputs the first test cell to the second switching network management module through the first downlink.

[0197] In a possible implementation, the second test cell is the first test cell received by the first switching network management module from the processing module and input to the first switching network module through the first uplink and output from the first switching network module to the second switching network management module through the first downlink.

[0198] In a possible implementation, the processing module controls the target link of the first switching network module indicated by the switching network identifier according to the first test cell and the second test cell and the switching network identifier and the target link number, comprising: the processing module updates the number of cell rewriting associated with the switching network identifier and the target link number when the cell content of the first test cell is determined to be different from the second test cell; the processing module closes the target link of the first switching network module indicated by the switching network identifier when the number of cell rewriting is determined to be greater than a first preset threshold.

[0199] In a possible implementation, the processing module controls the target link of the first switching network module indicated by the switching network identifier according to the first test cell and the second test cell and the switching network identifier and the target link number, comprising: the processing module determines the packet loss rate of the first test cell according to the sending strategy of the first test cell and the number of receptions of the second test cell; the processing module closes the target link of the first switching network module indicated by the switching network identifier when the packet loss rate is determined to be greater than a second preset threshold.

[0200] In a possible implementation, the processing module closes the target link of the first switching network module indicated by the switching network identifier, including: when the target link includes the first uplink, the processing module closes the output port of the first switching network management module corresponding to the first uplink; and / or, when the target link includes the first downlink, the processing module closes the input port of the second switching network management module corresponding to the first downlink.

[0201] In a possible implementation, the target link is at least one of the links indicated by the target link number.

[0202] The effects and implementation manners of the switching device in each of the above embodiments are similar to the effects of the method in each of the above embodiments, and thus are not described here.

[0203] The following describes an apparatus provided by an embodiment of the present application. As shown in Figure 4 the apparatus 500 can include a processor 501, a transceiver 505, and optionally further include a memory 502.

[0204] The transceiver 505 can be referred to as a transceiving unit, a transceiver, or a transceiving circuit, etc., and is configured to implement a transceiving function. The transceiver 505 can include a receiver and a transmitter. The receiver can be referred to as a receiver or a receiving circuit, etc., and is configured to implement a receiving function. The transmitter can be referred to as a transmitter or a transmitting circuit, etc., and is configured to implement a transmitting function. Figure 4 Figure 4 The memory 502 can store computer programs or software codes or instructions 504, which can also be referred to as firmware. The processor 501 can implement the control method provided by each of the embodiments of the present application by running the computer programs or software codes or instructions 503 therein, or by calling the computer programs or software codes or instructions 504 stored in the memory 502. The processor 501 can be a central processing unit (CPU), and the memory 502 can be, for example, a read-only memory (ROM) or a random access memory (RAM).

[0205] The transceiver 505 can be referred to as a transceiving unit, a transceiver, or a transceiving circuit, etc., and is configured to implement a transceiving function. The transceiver 505 can include a receiver and a transmitter. The receiver can be referred to as a receiver or a receiving circuit, etc., and is configured to implement a receiving function. The transmitter can be referred to as a transmitter or a transmitting circuit, etc., and is configured to implement a transmitting function.

[0206] The memory 502 can store computer programs or software codes or instructions 504, which can also be referred to as firmware. The processor 501 can implement the control method provided by each of the embodiments of the present application by running the computer programs or software codes or instructions 503 therein, or by calling the computer programs or software codes or instructions 504 stored in the memory 502. The processor 501 can be a central processing unit (CPU), and the memory 502 can be, for example, a read-only memory (ROM) or a random access memory (RAM).

[0207] The processor 501 and the transceiver 505 described in the present application can be implemented on an integrated circuit (IC), an analog IC, a radio frequency integrated circuit (RFIC), a mixed signal IC, an application specific integrated circuit (ASIC), a printed circuit board (PCB), an electronic device, etc.

[0208] The apparatus 500 described above can further include an antenna 506. The modules included in the apparatus 500 are only exemplary, and the present application does not limit the same.

[0209] Exemplarily, the structure of the control apparatus can not be limited by Figure 5 . The control apparatus can be a standalone device or can be part of a larger device. For example, the implementation form of the control apparatus can be:

[0210] (1) a standalone integrated circuit (IC), or a chip, or a chip system or subsystem; (2) a set of one or more ICs, optionally including storage components for storing data, instructions; (3) a module that can be embedded in other devices; (4) a vehicle-mounted device, etc.; (5) others, etc.

[0211] For the case where the implementation form of the control apparatus is a chip or a chip system, the structure of the chip can be referred to the structure of the chip shown in Figure 5 . ​ The chip shown in ​ includes a processor 601 and an interface 602. The number of the processor 601 can be one or more, and the number of the interface 602 can be multiple. Optionally, the chip or the chip system can include a memory 603.

[0212] All the related contents of each step involved in the above method embodiments can be referred to the function description of the corresponding function module, and will not be repeated here.

[0213] Based on the same technical concept, the present application further provides a computer readable storage medium, which stores a computer program. The computer program includes at least one code, which can be executed by a computer to control the computer to implement the above method embodiments.

[0214] Based on the same technical concept, the present application further provides a computer program, which, when executed, implements the above method embodiments.

[0215] The program can be stored in whole or in part on a storage medium which is packaged together with the processor. Alternatively, the program can be stored in whole or in part on a storage medium which is not packaged together with the processor.

[0216] Based on the same technical concept, the embodiment of the present application further provides a chip comprising a processor. The processor can implement the method embodiment described above.

[0217] The steps of the method or algorithm described in connection with the embodiments disclosed herein can be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module can reside in RAM, flash memory, ROM, EPROM, EEPROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium can be integral to the processor. The processor and the storage medium can reside in an ASIC.

[0218] Those skilled in the art should clearly understand that, in one or more of the examples described above, the functions described in the embodiments of the present application can be implemented by hardware, software, firmware, or any combination thereof. When implemented by software, these functions can be stored in a computer readable medium or transmitted as one or more instructions or codes on a computer readable medium. The computer readable medium includes computer storage medium and communication medium, wherein the communication medium includes any medium that facilitates the transfer of computer programs from one place to another. The storage medium can be any available medium accessible by a general purpose or special purpose computer.

[0219] The embodiments of the present application are described above in conjunction with the drawings, but the present application is not limited to the specific embodiments described above, which are merely illustrative and not restrictive. Those skilled in the art can make many modifications to the embodiments of the present application without departing from the spirit and scope of the present application and the claims, and all such modifications are intended to be within the scope of the present application.

Claims

1. A control method characterized by, The switching device comprises a first switching network management module, at least one switching network module, a second switching network management module, and a processing module. The first switching network management module is connected with an input port of the at least one switching network module. The second switching network management module is connected with an output port of the at least one switching network module. The method comprises the following steps: The processing module periodically sends a first test cell to the first switching network management module; The processing module receives a second test cell from the second switching network management module. The second test cell is used to provide a switching network identifier of the first switching network module through which the first test cell passes, and is used to provide a target link number. The target link number comprises at least one of an uplink number and a downlink number. The uplink number is an uplink number of a first uplink through which the first test cell passes when the first test cell is input to the first switching network module. The downlink number is a downlink number of a first downlink through which the first test cell passes when the first test cell is output from the first switching network module. The at least one switching network module comprises the first switching network module. The processing module extracts the switching network identifier and the target link number from the second test cell. The processing module controls a target link of the first switching network module indicated by the switching network identifier according to the first test cell and the second test cell, and the switching network identifier and the target link number. The target link comprises at least one of the first uplink and the first downlink.

2. The method of claim 1, wherein, Before the processing module receives the second test cell from the second switching network management module, the method further comprises the following steps: The processing module sends first information indicating the uplink number of the first test cell to the first switching network management module. The first switching network management module sends the received first test cell to the first switching network module through the first uplink indicated by the uplink number according to the first information.

3. The method of claim 2, wherein, The method further comprises the following steps: The first switching network management module writes the uplink number into the first test cell based on the first information.

4. The method of claim 2, wherein, After the first switching network management module sends the received first test cell to the first switching network module through the first uplink indicated by the uplink number according to the first information, the method further comprises the following steps: The first switching network module writes the switching network identifier of the first switching network module into the first test cell when it is determined that the cell type of the received first test cell is a test cell.

5. The method of claim 4, wherein, The method further comprises the following steps: The first switching network module writes the uplink number of the first uplink through which the first test cell passes when it is input to the first switching network module into the first test cell when it is determined that the cell type of the received first test cell is a test cell.

6. The method according to claim 4 or 5, characterized in that, The method further comprises the following steps: The first switching network module writes the downlink number of the first downlink that the first test cell needs to pass through when being output from the first switching network module into the first test cell when determining that the cell type of the received first test cell is a test cell.

7. The method according to any one of claims 4 to 6, characterized in that, The method further comprises: The first switching network module outputs the first test cell to the second switching network management module through the first downlink.

8. The method according to any one of claims 1 to 7, characterized in that, The second test cell is a first test cell received by the first switching network management module from the processing module and input to the first switching network module through the first uplink and output to the second switching network management module from the first switching network module through the first downlink.

9. The method according to any one of claims 1 to 8, characterized in that, The processing module controls the target link of the first switching network module indicated by the switching network identifier according to the first test cell and the second test cell and the switching network identifier and the target link number, including: The processing module updates the number of cell rewriting associated with the switching network identifier and the target link number when determining that the cell content of the first test cell is different from that of the second test cell; The processing module closes the target link of the first switching network module indicated by the switching network identifier when determining that the number of cell rewriting is greater than a first preset threshold.

10. The method according to any one of claims 1 to 9, characterized in that, The processing module controls the target link of the first switching network module indicated by the switching network identifier according to the first test cell and the second test cell and the switching network identifier and the target link number, including: The processing module determines the packet loss rate of the first test cell according to the sending strategy of the first test cell and the number of receptions of the second test cell; The processing module closes the target link of the first switching network module indicated by the switching network identifier when determining that the packet loss rate is greater than a second preset threshold.

11. The method according to claim 9 or 10, characterized in that, The closing of the target link of the first switching network module indicated by the switching network identifier comprises: When the target link includes the first uplink, the processing module closes the output port of the first switching network management module corresponding to the first uplink; and / or, When the target link includes the first downlink, the processing module closes the input port of the second switching network management module corresponding to the first downlink.

12. The method according to any one of claims 1 to 11, characterized in that, The target link is at least one of the links indicated by the target link number.

13. A switching device, characterized by The switching device comprises a first switching network management module, at least one switching network module, a second switching network management module, and a processing module, the input port of the at least one switching network module is connected with the first switching network management module, and the output port of the at least one switching network module is connected with the second switching network management module; The processing module is configured to periodically send a first test cell to the first switching network management module; The processing module is configured to receive a second test cell from the second switching network management module, wherein the second test cell is configured to provide a switching network identifier of the first switching network module through which the first test cell passes, and to provide a target link number, the target link number including at least one of an uplink number and a downlink number; wherein the uplink number is an uplink number of a first uplink through which the first test cell passes when input to the first switching network module, and the downlink number is a downlink number of a first downlink through which the first test cell passes when output from the first switching network module; wherein the at least one switching network module includes the first switching network module; The processing module is configured to extract the switching network identifier and the target link number from the second test cell; The processing module is configured to control a target link of the first switching network module indicated by the switching network identifier according to the first test cell and the second test cell, and the switching network identifier and the target link number, wherein the target link includes at least one of the first uplink and the first downlink.

14. A computer-readable storage medium, characterized in that, A computer program is included, when the computer program is executed on a computer or a processor, the computer or the processor is caused to execute the method of any one of claims 1 to 12.

15. A control device characterized by comprising: One or more interface circuits and one or more processors are included; the interface circuit is configured to receive a signal from a memory and send the signal to the processor, the signal including computer instructions stored in the memory; when the processor executes the computer instructions, the processor is configured to execute the method of any one of claims 1 to 12.

16. A computer program product, characterised in that, The computer program product includes a software program, when the software program is executed by a computer or a processor, the steps of the method of any one of claims 1 to 12 are executed.

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